Monorepo for Aesthetic.Computer
aesthetic.computer
1;******************************************************************************
2; Game Boy hardware constant definitions
3; https://github.com/gbdev/hardware.inc
4;******************************************************************************
5
6; To the extent possible under law, the authors of this work have
7; waived all copyright and related or neighboring rights to the work.
8; See https://creativecommons.org/publicdomain/zero/1.0/ for details.
9; SPDX-License-Identifier: CC0-1.0
10
11; If this file was already included, don't do it again
12if !def(HARDWARE_INC)
13
14; Check for the minimum supported RGBDS version
15if !def(__RGBDS_MAJOR__) || !def(__RGBDS_MINOR__) || !def(__RGBDS_PATCH__)
16 fail "This version of 'hardware.inc' requires RGBDS version 0.5.0 or later"
17endc
18if __RGBDS_MAJOR__ == 0 && __RGBDS_MINOR__ < 5
19 fail "This version of 'hardware.inc' requires RGBDS version 0.5.0 or later."
20endc
21
22; Define the include guard and the current hardware.inc version
23; (do this after the RGBDS version check since the `def` syntax depends on it)
24def HARDWARE_INC equ 1
25def HARDWARE_INC_VERSION equs "5.3.0"
26
27; Usage: rev_Check_hardware_inc <min_ver>
28; Examples:
29; rev_Check_hardware_inc 1.2.3
30; rev_Check_hardware_inc 1.2 (equivalent to 1.2.0)
31; rev_Check_hardware_inc 1 (equivalent to 1.0.0)
32MACRO rev_Check_hardware_inc
33 if _NARG == 1 ; Actual invocation by the user
34 def hw_inc_cur_ver\@ equs strrpl("{HARDWARE_INC_VERSION}", ".", ",")
35 def hw_inc_min_ver\@ equs strrpl("\1", ".", ",")
36 rev_Check_hardware_inc {hw_inc_cur_ver\@}, {hw_inc_min_ver\@}, 0, 0
37 purge hw_inc_cur_ver\@, hw_inc_min_ver\@
38 else ; Recursive invocation
39 if \1 != \4 || (\2 < \5 || (\2 == \5 && \3 < \6))
40 fail "Version \1.\2.\3 of 'hardware.inc' is incompatible with requested version \4.\5.\6"
41 endc
42 endc
43ENDM
44
45
46;******************************************************************************
47; Memory-mapped registers ($FFxx range)
48;******************************************************************************
49
50; -- JOYP / P1 ($FF00) --------------------------------------------------------
51; Joypad face buttons
52def rJOYP equ $FF00
53
54def B_JOYP_GET_BUTTONS equ 5 ; 0 = reading buttons [r/w]
55def B_JOYP_GET_CTRL_PAD equ 4 ; 0 = reading Control Pad [r/w]
56 def JOYP_GET equ %00_11_0000 ; select which inputs to read from the lower nybble
57 def JOYP_GET_BUTTONS equ %00_01_0000 ; reading A/B/Select/Start buttons
58 def JOYP_GET_CTRL_PAD equ %00_10_0000 ; reading Control Pad directions
59 def JOYP_GET_NONE equ %00_11_0000 ; reading nothing
60
61def B_JOYP_START equ 3 ; 0 = Start is pressed (if reading buttons) [ro]
62def B_JOYP_SELECT equ 2 ; 0 = Select is pressed (if reading buttons) [ro]
63def B_JOYP_B equ 1 ; 0 = B is pressed (if reading buttons) [ro]
64def B_JOYP_A equ 0 ; 0 = A is pressed (if reading buttons) [ro]
65def B_JOYP_DOWN equ 3 ; 0 = Down is pressed (if reading Control Pad) [ro]
66def B_JOYP_UP equ 2 ; 0 = Up is pressed (if reading Control Pad) [ro]
67def B_JOYP_LEFT equ 1 ; 0 = Left is pressed (if reading Control Pad) [ro]
68def B_JOYP_RIGHT equ 0 ; 0 = Right is pressed (if reading Control Pad) [ro]
69 def JOYP_INPUTS equ %0000_1111 ; bits equal to 0 indicate pressed (when reading inputs)
70 def JOYP_START equ 1 << B_JOYP_START
71 def JOYP_SELECT equ 1 << B_JOYP_SELECT
72 def JOYP_B equ 1 << B_JOYP_B
73 def JOYP_A equ 1 << B_JOYP_A
74 def JOYP_DOWN equ 1 << B_JOYP_DOWN
75 def JOYP_UP equ 1 << B_JOYP_UP
76 def JOYP_LEFT equ 1 << B_JOYP_LEFT
77 def JOYP_RIGHT equ 1 << B_JOYP_RIGHT
78
79; SGB command packet transfer uses for JOYP bits
80def B_JOYP_SGB_ONE equ 5 ; 0 = sending 1 bit
81def B_JOYP_SGB_ZERO equ 4 ; 0 = sending 0 bit
82 def JOYP_SGB_START equ %00_00_0000 ; start SGB packet transfer
83 def JOYP_SGB_ONE equ %00_01_0000 ; send 1 bit
84 def JOYP_SGB_ZERO equ %00_10_0000 ; send 0 bit
85 def JOYP_SGB_FINISH equ %00_11_0000 ; finish SGB packet transfer
86
87; Combined input byte, with Control Pad in high nybble (conventional order)
88def B_PAD_DOWN equ 7
89def B_PAD_UP equ 6
90def B_PAD_LEFT equ 5
91def B_PAD_RIGHT equ 4
92def B_PAD_START equ 3
93def B_PAD_SELECT equ 2
94def B_PAD_B equ 1
95def B_PAD_A equ 0
96 def PAD_CTRL_PAD equ %1111_0000
97 def PAD_BUTTONS equ %0000_1111
98 def PAD_DOWN equ 1 << B_PAD_DOWN
99 def PAD_UP equ 1 << B_PAD_UP
100 def PAD_LEFT equ 1 << B_PAD_LEFT
101 def PAD_RIGHT equ 1 << B_PAD_RIGHT
102 def PAD_START equ 1 << B_PAD_START
103 def PAD_SELECT equ 1 << B_PAD_SELECT
104 def PAD_B equ 1 << B_PAD_B
105 def PAD_A equ 1 << B_PAD_A
106
107; Combined input byte, with Control Pad in low nybble (swapped order)
108def B_PAD_SWAP_START equ 7
109def B_PAD_SWAP_SELECT equ 6
110def B_PAD_SWAP_B equ 5
111def B_PAD_SWAP_A equ 4
112def B_PAD_SWAP_DOWN equ 3
113def B_PAD_SWAP_UP equ 2
114def B_PAD_SWAP_LEFT equ 1
115def B_PAD_SWAP_RIGHT equ 0
116 def PAD_SWAP_CTRL_PAD equ %0000_1111
117 def PAD_SWAP_BUTTONS equ %1111_0000
118 def PAD_SWAP_START equ 1 << B_PAD_SWAP_START
119 def PAD_SWAP_SELECT equ 1 << B_PAD_SWAP_SELECT
120 def PAD_SWAP_B equ 1 << B_PAD_SWAP_B
121 def PAD_SWAP_A equ 1 << B_PAD_SWAP_A
122 def PAD_SWAP_DOWN equ 1 << B_PAD_SWAP_DOWN
123 def PAD_SWAP_UP equ 1 << B_PAD_SWAP_UP
124 def PAD_SWAP_LEFT equ 1 << B_PAD_SWAP_LEFT
125 def PAD_SWAP_RIGHT equ 1 << B_PAD_SWAP_RIGHT
126
127; -- SB ($FF01) ---------------------------------------------------------------
128; Serial transfer data [r/w]
129def rSB equ $FF01
130
131; -- SC ($FF02) ---------------------------------------------------------------
132; Serial transfer control
133def rSC equ $FF02
134
135def B_SC_START equ 7 ; reading 1 = transfer in progress, writing 1 = start transfer [r/w]
136def B_SC_SPEED equ 1 ; (CGB only) 1 = use faster internal clock [r/w]
137def B_SC_SOURCE equ 0 ; 0 = use external clock ("slave"), 1 = use internal clock ("master") [r/w]
138 def SC_START equ 1 << B_SC_START
139 def SC_SPEED equ 1 << B_SC_SPEED
140 def SC_SLOW equ 0 << B_SC_SPEED
141 def SC_FAST equ 1 << B_SC_SPEED
142 def SC_SOURCE equ 1 << B_SC_SOURCE
143 def SC_EXTERNAL equ 0 << B_SC_SOURCE
144 def SC_INTERNAL equ 1 << B_SC_SOURCE
145
146; -- $FF03 is unused ----------------------------------------------------------
147
148; -- DIV ($FF04) --------------------------------------------------------------
149; Divider register [r/w]
150def rDIV equ $FF04
151
152; -- TIMA ($FF05) -------------------------------------------------------------
153; Timer counter [r/w]
154def rTIMA equ $FF05
155
156; -- TMA ($FF06) --------------------------------------------------------------
157; Timer modulo [r/w]
158def rTMA equ $FF06
159
160; -- TAC ($FF07) --------------------------------------------------------------
161; Timer control
162def rTAC equ $FF07
163
164def B_TAC_START equ 2 ; enable incrementing TIMA [r/w]
165 def TAC_STOP equ 0 << B_TAC_START
166 def TAC_START equ 1 << B_TAC_START
167
168def TAC_CLOCK equ %000000_11 ; the frequency at which TIMA increments [r/w]
169 def TAC_4KHZ equ %000000_00 ; every 256 M-cycles = ~4 KHz on DMG
170 def TAC_262KHZ equ %000000_01 ; every 4 M-cycles = ~262 KHz on DMG
171 def TAC_65KHZ equ %000000_10 ; every 16 M-cycles = ~65 KHz on DMG
172 def TAC_16KHZ equ %000000_11 ; every 64 M-cycles = ~16 KHz on DMG
173
174; -- $FF08-$FF0E are unused ---------------------------------------------------
175
176; -- IF ($FF0F) ---------------------------------------------------------------
177; Pending interrupts
178def rIF equ $FF0F
179
180def B_IF_JOYPAD equ 4 ; 1 = joypad interrupt is pending [r/w]
181def B_IF_SERIAL equ 3 ; 1 = serial interrupt is pending [r/w]
182def B_IF_TIMER equ 2 ; 1 = timer interrupt is pending [r/w]
183def B_IF_STAT equ 1 ; 1 = STAT interrupt is pending [r/w]
184def B_IF_VBLANK equ 0 ; 1 = VBlank interrupt is pending [r/w]
185 def IF_JOYPAD equ 1 << B_IF_JOYPAD
186 def IF_SERIAL equ 1 << B_IF_SERIAL
187 def IF_TIMER equ 1 << B_IF_TIMER
188 def IF_STAT equ 1 << B_IF_STAT
189 def IF_VBLANK equ 1 << B_IF_VBLANK
190
191; -- AUD1SWEEP / NR10 ($FF10) -------------------------------------------------
192; Audio channel 1 sweep
193def rAUD1SWEEP equ $FF10
194
195def AUD1SWEEP_TIME equ %0_111_0000 ; how long between sweep iterations
196 ; (in 128 Hz ticks, ~7.8 ms apart) [r/w]
197
198def B_AUD1SWEEP_DIR equ 3 ; sweep direction [r/w]
199 def AUD1SWEEP_DIR equ 1 << B_AUD1SWEEP_DIR
200 def AUD1SWEEP_UP equ 0 << B_AUD1SWEEP_DIR
201 def AUD1SWEEP_DOWN equ 1 << B_AUD1SWEEP_DIR
202
203def AUD1SWEEP_SHIFT equ %00000_111 ; how much the period increases/decreases per iteration [r/w]
204
205; -- AUD1LEN / NR11 ($FF11) ---------------------------------------------------
206; Audio channel 1 length timer and duty cycle
207def rAUD1LEN equ $FF11
208
209def AUD1LEN_DUTY equ %11_000000 ; ratio of time spent high vs. time spent low [r/w]
210 def AUD1LEN_DUTY_12_5 equ %00_000000 ; 12.5%
211 def AUD1LEN_DUTY_25 equ %01_000000 ; 25%
212 def AUD1LEN_DUTY_50 equ %10_000000 ; 50%
213 def AUD1LEN_DUTY_75 equ %11_000000 ; 75%
214
215def AUD1LEN_TIMER equ %00_111111 ; initial length timer (0-63) [wo]
216
217; -- AUD1ENV / NR12 ($FF12) ---------------------------------------------------
218; Audio channel 1 volume and envelope
219def rAUD1ENV equ $FF12
220
221def AUD1ENV_INIT_VOLUME equ %1111_0000 ; initial volume [r/w]
222
223def B_AUD1ENV_DIR equ 3 ; direction of volume envelope [r/w]
224 def AUD1ENV_DIR equ 1 << B_AUD1ENV_DIR
225 def AUD1ENV_DOWN equ 0 << B_AUD1ENV_DIR
226 def AUD1ENV_UP equ 1 << B_AUD1ENV_DIR
227
228def AUD1ENV_PACE equ %00000_111 ; how long between envelope iterations
229 ; (in 64 Hz ticks, ~15.6 ms apart) [r/w]
230
231; -- AUD1LOW / NR13 ($FF13) ---------------------------------------------------
232; Audio channel 1 period (low 8 bits) [wo]
233def rAUD1LOW equ $FF13
234
235; -- AUD1HIGH / NR14 ($FF14) --------------------------------------------------
236; Audio channel 1 period (high 3 bits) and control
237def rAUD1HIGH equ $FF14
238
239def B_AUD1HIGH_RESTART equ 7 ; 1 = restart the channel [wo]
240def B_AUD1HIGH_LEN_ENABLE equ 6 ; 1 = reset the channel after the length timer expires [r/w]
241 def AUD1HIGH_RESTART equ 1 << B_AUD1HIGH_RESTART
242 def AUD1HIGH_LENGTH_OFF equ 0 << B_AUD1HIGH_LEN_ENABLE
243 def AUD1HIGH_LENGTH_ON equ 1 << B_AUD1HIGH_LEN_ENABLE
244
245def AUD1HIGH_PERIOD_HIGH equ %00000_111 ; upper 3 bits of the channel's period [r/w]
246
247; -- $FF15 is unused ----------------------------------------------------------
248
249; -- AUD2LEN / NR21 ($FF16) ---------------------------------------------------
250; Audio channel 2 length timer and duty cycle
251def rAUD2LEN equ $FF16
252
253def AUD2LEN_DUTY equ %11_000000 ; ratio of time spent high vs. time spent low [r/w]
254 def AUD2LEN_DUTY_12_5 equ %00_000000 ; 12.5%
255 def AUD2LEN_DUTY_25 equ %01_000000 ; 25%
256 def AUD2LEN_DUTY_50 equ %10_000000 ; 50%
257 def AUD2LEN_DUTY_75 equ %11_000000 ; 75%
258
259def AUD2LEN_TIMER equ %00_111111 ; initial length timer (0-63) [wo]
260
261; -- AUD2ENV / NR22 ($FF17) ---------------------------------------------------
262; Audio channel 2 volume and envelope
263def rAUD2ENV equ $FF17
264
265def AUD2ENV_INIT_VOLUME equ %1111_0000 ; initial volume [r/w]
266
267def B_AUD2ENV_DIR equ 3 ; direction of volume envelope [r/w]
268 def AUD2ENV_DIR equ 1 << B_AUD2ENV_DIR
269 def AUD2ENV_DOWN equ 0 << B_AUD2ENV_DIR
270 def AUD2ENV_UP equ 1 << B_AUD2ENV_DIR
271
272def AUD2ENV_PACE equ %00000_111 ; how long between envelope iterations
273 ; (in 64 Hz ticks, ~15.6 ms apart) [r/w]
274
275; -- AUD2LOW / NR23 ($FF18) ---------------------------------------------------
276; Audio channel 2 period (low 8 bits) [wo]
277def rAUD2LOW equ $FF18
278
279; -- AUD2HIGH / NR24 ($FF19) --------------------------------------------------
280; Audio channel 2 period (high 3 bits) and control
281def rAUD2HIGH equ $FF19
282
283def B_AUD2HIGH_RESTART equ 7 ; 1 = restart the channel [wo]
284def B_AUD2HIGH_LEN_ENABLE equ 6 ; 1 = reset the channel after the length timer expires [r/w]
285 def AUD2HIGH_RESTART equ 1 << B_AUD2HIGH_RESTART
286 def AUD2HIGH_LENGTH_OFF equ 0 << B_AUD2HIGH_LEN_ENABLE
287 def AUD2HIGH_LENGTH_ON equ 1 << B_AUD2HIGH_LEN_ENABLE
288
289def AUD2HIGH_PERIOD_HIGH equ %00000_111 ; upper 3 bits of the channel's period [r/w]
290
291; -- AUD3ENA / NR30 ($FF1A) ---------------------------------------------------
292; Audio channel 3 enable
293def rAUD3ENA equ $FF1A
294
295def B_AUD3ENA_ENABLE equ 7 ; 1 = channel is active [r/w]
296 def AUD3ENA_OFF equ 0 << B_AUD3ENA_ENABLE
297 def AUD3ENA_ON equ 1 << B_AUD3ENA_ENABLE
298
299; -- AUD3LEN / NR31 ($FF1B) ---------------------------------------------------
300; Audio channel 3 length timer [wo]
301def rAUD3LEN equ $FF1B
302
303; -- AUD3LEVEL / NR32 ($FF1C) -------------------------------------------------
304; Audio channel 3 volume
305def rAUD3LEVEL equ $FF1C
306
307def AUD3LEVEL_VOLUME equ %0_11_00000 ; volume level [r/w]
308 def AUD3LEVEL_MUTE equ %0_00_00000 ; 0% (muted)
309 def AUD3LEVEL_100 equ %0_01_00000 ; 100%
310 def AUD3LEVEL_50 equ %0_10_00000 ; 50%
311 def AUD3LEVEL_25 equ %0_11_00000 ; 25%
312
313; -- AUD3LOW / NR33 ($FF1D) ---------------------------------------------------
314; Audio channel 3 period (low 8 bits) [wo]
315def rAUD3LOW equ $FF1D
316
317; -- AUD3HIGH / NR34 ($FF1E) --------------------------------------------------
318; Audio channel 3 period (high 3 bits) and control
319def rAUD3HIGH equ $FF1E
320
321def B_AUD3HIGH_RESTART equ 7 ; 1 = restart the channel [wo]
322def B_AUD3HIGH_LEN_ENABLE equ 6 ; 1 = reset the channel after the length timer expires [r/w]
323 def AUD3HIGH_RESTART equ 1 << B_AUD3HIGH_RESTART
324 def AUD3HIGH_LENGTH_OFF equ 0 << B_AUD3HIGH_LEN_ENABLE
325 def AUD3HIGH_LENGTH_ON equ 1 << B_AUD3HIGH_LEN_ENABLE
326
327def AUD3HIGH_PERIOD_HIGH equ %00000_111 ; upper 3 bits of the channel's period [r/w]
328
329; -- $FF1F is unused ----------------------------------------------------------
330
331; -- AUD4LEN / NR41 ($FF20) ---------------------------------------------------
332; Audio channel 4 length timer
333def rAUD4LEN equ $FF20
334
335def AUD4LEN_TIMER equ %00_111111 ; initial length timer (0-63) [wo]
336
337; -- AUD4ENV / NR42 ($FF21) ---------------------------------------------------
338; Audio channel 4 volume and envelope
339def rAUD4ENV equ $FF21
340
341def AUD4ENV_INIT_VOLUME equ %1111_0000 ; initial volume [r/w]
342
343def B_AUD4ENV_DIR equ 3 ; direction of volume envelope [r/w]
344 def AUD4ENV_DIR equ 1 << B_AUD4ENV_DIR
345 def AUD4ENV_DOWN equ 0 << B_AUD4ENV_DIR
346 def AUD4ENV_UP equ 1 << B_AUD4ENV_DIR
347
348def AUD4ENV_PACE equ %00000_111 ; how long between envelope iterations
349 ; (in 64 Hz ticks, ~15.6 ms apart) [r/w]
350
351; -- AUD4POLY / NR43 ($FF22) --------------------------------------------------
352; Audio channel 4 period and randomness
353def rAUD4POLY equ $FF22
354
355def AUD4POLY_SHIFT equ %1111_0000 ; coarse control of the channel's period [r/w]
356
357def B_AUD4POLY_WIDTH equ 3 ; controls the noise generator (LFSR)'s step width [r/w]
358 def AUD4POLY_15STEP equ 0 << B_AUD4POLY_WIDTH
359 def AUD4POLY_7STEP equ 1 << B_AUD4POLY_WIDTH
360
361def AUD4POLY_DIV equ %00000_111 ; fine control of the channel's period [r/w]
362
363; -- AUD4GO / NR44 ($FF23) ----------------------------------------------------
364; Audio channel 4 control
365def rAUD4GO equ $FF23
366
367def B_AUD4GO_RESTART equ 7 ; 1 = restart the channel [wo]
368def B_AUD4GO_LEN_ENABLE equ 6 ; 1 = reset the channel after the length timer expires [r/w]
369 def AUD4GO_RESTART equ 1 << B_AUD4GO_RESTART
370 def AUD4GO_LENGTH_OFF equ 0 << B_AUD4GO_LEN_ENABLE
371 def AUD4GO_LENGTH_ON equ 1 << B_AUD4GO_LEN_ENABLE
372
373; -- AUDVOL / NR50 ($FF24) ----------------------------------------------------
374; Audio master volume and VIN mixer
375def rAUDVOL equ $FF24
376
377def B_AUDVOL_VIN_LEFT equ 7 ; 1 = output VIN to left ear (SO2, speaker 2) [r/w]
378 def AUDVOL_VIN_LEFT equ 1 << B_AUDVOL_VIN_LEFT
379
380def AUDVOL_LEFT equ %0_111_0000 ; 0 = barely audible, 7 = full volume [r/w]
381
382def B_AUDVOL_VIN_RIGHT equ 3 ; 1 = output VIN to right ear (SO1, speaker 1) [r/w]
383 def AUDVOL_VIN_RIGHT equ 1 << B_AUDVOL_VIN_RIGHT
384
385def AUDVOL_RIGHT equ %00000_111 ; 0 = barely audible, 7 = full volume [r/w]
386
387; -- AUDTERM / NR51 ($FF25) ---------------------------------------------------
388; Audio channel mixer
389def rAUDTERM equ $FF25
390
391def B_AUDTERM_4_LEFT equ 7 ; 1 = output channel 4 to left ear [r/w]
392def B_AUDTERM_3_LEFT equ 6 ; 1 = output channel 3 to left ear [r/w]
393def B_AUDTERM_2_LEFT equ 5 ; 1 = output channel 2 to left ear [r/w]
394def B_AUDTERM_1_LEFT equ 4 ; 1 = output channel 1 to left ear [r/w]
395def B_AUDTERM_4_RIGHT equ 3 ; 1 = output channel 4 to right ear [r/w]
396def B_AUDTERM_3_RIGHT equ 2 ; 1 = output channel 3 to right ear [r/w]
397def B_AUDTERM_2_RIGHT equ 1 ; 1 = output channel 2 to right ear [r/w]
398def B_AUDTERM_1_RIGHT equ 0 ; 1 = output channel 1 to right ear [r/w]
399 def AUDTERM_4_LEFT equ 1 << B_AUDTERM_4_LEFT
400 def AUDTERM_3_LEFT equ 1 << B_AUDTERM_3_LEFT
401 def AUDTERM_2_LEFT equ 1 << B_AUDTERM_2_LEFT
402 def AUDTERM_1_LEFT equ 1 << B_AUDTERM_1_LEFT
403 def AUDTERM_4_RIGHT equ 1 << B_AUDTERM_4_RIGHT
404 def AUDTERM_3_RIGHT equ 1 << B_AUDTERM_3_RIGHT
405 def AUDTERM_2_RIGHT equ 1 << B_AUDTERM_2_RIGHT
406 def AUDTERM_1_RIGHT equ 1 << B_AUDTERM_1_RIGHT
407
408; -- AUDENA / NR52 ($FF26) ----------------------------------------------------
409; Audio master enable
410def rAUDENA equ $FF26
411
412def B_AUDENA_ENABLE equ 7 ; 0 = disable the APU (resets all audio registers to 0!) [r/w]
413def B_AUDENA_ENABLE_CH4 equ 3 ; 1 = channel 4 is running [ro]
414def B_AUDENA_ENABLE_CH3 equ 2 ; 1 = channel 3 is running [ro]
415def B_AUDENA_ENABLE_CH2 equ 1 ; 1 = channel 2 is running [ro]
416def B_AUDENA_ENABLE_CH1 equ 0 ; 1 = channel 1 is running [ro]
417 def AUDENA_OFF equ 0 << B_AUDENA_ENABLE
418 def AUDENA_ON equ 1 << B_AUDENA_ENABLE
419 def AUDENA_CH4_OFF equ 0 << B_AUDENA_ENABLE_CH4
420 def AUDENA_CH4_ON equ 1 << B_AUDENA_ENABLE_CH4
421 def AUDENA_CH3_OFF equ 0 << B_AUDENA_ENABLE_CH3
422 def AUDENA_CH3_ON equ 1 << B_AUDENA_ENABLE_CH3
423 def AUDENA_CH2_OFF equ 0 << B_AUDENA_ENABLE_CH2
424 def AUDENA_CH2_ON equ 1 << B_AUDENA_ENABLE_CH2
425 def AUDENA_CH1_OFF equ 0 << B_AUDENA_ENABLE_CH1
426 def AUDENA_CH1_ON equ 1 << B_AUDENA_ENABLE_CH1
427
428; -- $FF27-$FF2F are unused ---------------------------------------------------
429
430; -- AUD3WAVE ($FF30-$FF3F) ---------------------------------------------------
431; Audio channel 3 wave pattern RAM [r/w]
432def rAUD3WAVE_0 equ $FF30
433def rAUD3WAVE_1 equ $FF31
434def rAUD3WAVE_2 equ $FF32
435def rAUD3WAVE_3 equ $FF33
436def rAUD3WAVE_4 equ $FF34
437def rAUD3WAVE_5 equ $FF35
438def rAUD3WAVE_6 equ $FF36
439def rAUD3WAVE_7 equ $FF37
440def rAUD3WAVE_8 equ $FF38
441def rAUD3WAVE_9 equ $FF39
442def rAUD3WAVE_A equ $FF3A
443def rAUD3WAVE_B equ $FF3B
444def rAUD3WAVE_C equ $FF3C
445def rAUD3WAVE_D equ $FF3D
446def rAUD3WAVE_E equ $FF3E
447def rAUD3WAVE_F equ $FF3F
448
449; -- LCDC ($FF40) -------------------------------------------------------------
450; PPU graphics control
451def rLCDC equ $FF40
452
453def B_LCDC_ENABLE equ 7 ; whether the PPU (and LCD) are turned on [r/w]
454def B_LCDC_WIN_MAP equ 6 ; which tilemap the Window reads from [r/w]
455def B_LCDC_WINDOW equ 5 ; whether the Window is enabled [r/w]
456def B_LCDC_BLOCKS equ 4 ; which "tile blocks" the BG and Window use [r/w]
457def B_LCDC_BG_MAP equ 3 ; which tilemap the BG reads from [r/w]
458def B_LCDC_OBJ_SIZE equ 2 ; how many pixels tall each OBJ is [r/w]
459def B_LCDC_OBJS equ 1 ; whether OBJs are enabled [r/w]
460def B_LCDC_BG equ 0 ; (DMG only) whether the BG is enabled [r/w]
461def B_LCDC_PRIO equ 0 ; (CGB only) whether OBJ priority bits are enabled [r/w]
462 def LCDC_ENABLE equ 1 << B_LCDC_ENABLE
463 def LCDC_OFF equ 0 << B_LCDC_ENABLE
464 def LCDC_ON equ 1 << B_LCDC_ENABLE
465 def LCDC_WIN_MAP equ 1 << B_LCDC_WIN_MAP
466 def LCDC_WIN_9800 equ 0 << B_LCDC_WIN_MAP
467 def LCDC_WIN_9C00 equ 1 << B_LCDC_WIN_MAP
468 def LCDC_WINDOW equ 1 << B_LCDC_WINDOW
469 def LCDC_WIN_OFF equ 0 << B_LCDC_WINDOW
470 def LCDC_WIN_ON equ 1 << B_LCDC_WINDOW
471 def LCDC_BLOCKS equ 1 << B_LCDC_BLOCKS
472 def LCDC_BLOCK21 equ 0 << B_LCDC_BLOCKS
473 def LCDC_BLOCK01 equ 1 << B_LCDC_BLOCKS
474 def LCDC_BG_MAP equ 1 << B_LCDC_BG_MAP
475 def LCDC_BG_9800 equ 0 << B_LCDC_BG_MAP
476 def LCDC_BG_9C00 equ 1 << B_LCDC_BG_MAP
477 def LCDC_OBJ_SIZE equ 1 << B_LCDC_OBJ_SIZE
478 def LCDC_OBJ_8 equ 0 << B_LCDC_OBJ_SIZE
479 def LCDC_OBJ_16 equ 1 << B_LCDC_OBJ_SIZE
480 def LCDC_OBJS equ 1 << B_LCDC_OBJS
481 def LCDC_OBJ_OFF equ 0 << B_LCDC_OBJS
482 def LCDC_OBJ_ON equ 1 << B_LCDC_OBJS
483 def LCDC_BG equ 1 << B_LCDC_BG
484 def LCDC_BG_OFF equ 0 << B_LCDC_BG
485 def LCDC_BG_ON equ 1 << B_LCDC_BG
486 def LCDC_PRIO equ 1 << B_LCDC_PRIO
487 def LCDC_PRIO_OFF equ 0 << B_LCDC_PRIO
488 def LCDC_PRIO_ON equ 1 << B_LCDC_PRIO
489
490; -- STAT ($FF41) -------------------------------------------------------------
491; Graphics status and interrupt control
492def rSTAT equ $FF41
493
494def B_STAT_LYC equ 6 ; 1 = LY match triggers the STAT interrupt [r/w]
495def B_STAT_MODE_2 equ 5 ; 1 = OAM Scan triggers the PPU interrupt [r/w]
496def B_STAT_MODE_1 equ 4 ; 1 = VBlank triggers the PPU interrupt [r/w]
497def B_STAT_MODE_0 equ 3 ; 1 = HBlank triggers the PPU interrupt [r/w]
498def B_STAT_LYCF equ 2 ; 1 = LY is currently equal to LYC [ro]
499def B_STAT_BUSY equ 1 ; 1 = the PPU is currently accessing VRAM [ro]
500 def STAT_LYC equ 1 << B_STAT_LYC
501 def STAT_MODE_2 equ 1 << B_STAT_MODE_2
502 def STAT_MODE_1 equ 1 << B_STAT_MODE_1
503 def STAT_MODE_0 equ 1 << B_STAT_MODE_0
504 def STAT_LYCF equ 1 << B_STAT_LYCF
505 def STAT_BUSY equ 1 << B_STAT_BUSY
506
507def STAT_MODE equ %000000_11 ; PPU's current status [ro]
508 def STAT_HBLANK equ %000000_00 ; waiting after a line's rendering (HBlank)
509 def STAT_VBLANK equ %000000_01 ; waiting between frames (VBlank)
510 def STAT_OAM equ %000000_10 ; checking which OBJs will be rendered on this line (OAM scan)
511 def STAT_LCD equ %000000_11 ; pushing pixels to the LCD
512
513; -- SCY ($FF42) --------------------------------------------------------------
514; Background Y scroll offset (in pixels) [r/w]
515def rSCY equ $FF42
516
517; -- SCX ($FF43) --------------------------------------------------------------
518; Background X scroll offset (in pixels) [r/w]
519def rSCX equ $FF43
520
521; -- LY ($FF44) ---------------------------------------------------------------
522; Y coordinate of the line currently processed by the PPU (0-153) [ro]
523def rLY equ $FF44
524
525def LY_VBLANK equ 144 ; 144-153 is the VBlank period
526
527; -- LYC ($FF45) --------------------------------------------------------------
528; Value that LY is constantly compared to [r/w]
529def rLYC equ $FF45
530
531; -- DMA ($FF46) --------------------------------------------------------------
532; OAM DMA start address (high 8 bits) and start [wo]
533def rDMA equ $FF46
534
535; -- BGP ($FF47) --------------------------------------------------------------
536; (DMG only) Background color mapping [r/w]
537def rBGP equ $FF47
538
539def BGP_SGB_TRANSFER equ %11_10_01_00 ; set BGP to this value before SGB VRAM transfer
540
541; -- OBP0 ($FF48) -------------------------------------------------------------
542; (DMG only) OBJ color mapping #0 [r/w]
543def rOBP0 equ $FF48
544
545; -- OBP1 ($FF49) -------------------------------------------------------------
546; (DMG only) OBJ color mapping #1 [r/w]
547def rOBP1 equ $FF49
548
549; -- WY ($FF4A) ---------------------------------------------------------------
550; Y coordinate of the Window's top-left pixel (0-143) [r/w]
551def rWY equ $FF4A
552
553; -- WX ($FF4B) ---------------------------------------------------------------
554; X coordinate of the Window's top-left pixel, plus 7 (7-166) [r/w]
555def rWX equ $FF4B
556
557def WX_OFS equ 7 ; subtract this to get the actual Window X coordinate
558
559; -- SYS / KEY0 ($FF4C) -------------------------------------------------------
560; (CGB boot ROM only) CPU mode select
561def rSYS equ $FF4C
562
563; This is known as the "CPU mode register" in Fig. 11 of this patent:
564; https://patents.google.com/patent/US6322447B1/en?oq=US6322447bi
565; "OBJ priority mode designating register" in the same patent
566; Credit to @mattcurrie for this finding!
567
568def SYS_MODE equ %0000_11_00 ; current system mode [r/w]
569 def SYS_CGB equ %0000_00_00 ; CGB mode
570 def SYS_DMG equ %0000_01_00 ; DMG compatibility mode
571 def SYS_PGB1 equ %0000_10_00 ; LCD is driven externally, CPU is stopped
572 def SYS_PGB2 equ %0000_11_00 ; LCD is driven externally, CPU is running
573
574; -- SPD / KEY1 ($FF4D) -------------------------------------------------------
575; (CGB only) Double-speed mode control
576def rSPD equ $FF4D
577
578def B_SPD_DOUBLE equ 7 ; current clock speed [ro]
579def B_SPD_PREPARE equ 0 ; 1 = next `stop` instruction will switch clock speeds [r/w]
580 def SPD_SINGLE equ 0 << B_SPD_DOUBLE
581 def SPD_DOUBLE equ 1 << B_SPD_DOUBLE
582 def SPD_PREPARE equ 1 << B_SPD_PREPARE
583
584; -- $FF4E is unused ----------------------------------------------------------
585
586; -- VBK ($FF4F) --------------------------------------------------------------
587; (CGB only) VRAM bank number (0 or 1)
588def rVBK equ $FF4F
589
590def VBK_BANK equ %0000000_1 ; mapped VRAM bank [r/w]
591
592; -- BANK ($FF50) -------------------------------------------------------------
593; (boot ROM only) Boot ROM mapping control
594def rBANK equ $FF50
595
596def B_BANK_ON equ 0 ; whether the boot ROM is mapped [wo]
597 def BANK_ON equ 0 << B_BANK_ON
598 def BANK_OFF equ 1 << B_BANK_ON
599
600; -- VDMA_SRC_HIGH / HDMA1 ($FF51) --------------------------------------------
601; (CGB only) VRAM DMA source address (high 8 bits) [wo]
602def rVDMA_SRC_HIGH equ $FF51
603
604; -- VDMA_SRC_LOW / HDMA2 ($FF52) ---------------------------------------------
605; (CGB only) VRAM DMA source address (low 8 bits) [wo]
606def rVDMA_SRC_LOW equ $FF52
607
608; -- VDMA_DEST_HIGH / HDMA3 ($FF53) -------------------------------------------
609; (CGB only) VRAM DMA destination address (high 8 bits) [wo]
610def rVDMA_DEST_HIGH equ $FF53
611
612; -- VDMA_DEST_LOW / HDMA4 ($FF54) --------------------------------------------
613; (CGB only) VRAM DMA destination address (low 8 bits) [wo]
614def rVDMA_DEST_LOW equ $FF54
615
616; -- VDMA_LEN / HDMA5 ($FF55) -------------------------------------------------
617; (CGB only) VRAM DMA length, mode, and start
618def rVDMA_LEN equ $FF55
619
620def B_VDMA_LEN_MODE equ 7 ; on write: VRAM DMA mode [wo]
621 def VDMA_LEN_MODE equ 1 << B_VDMA_LEN_MODE
622 def VDMA_LEN_MODE_GENERAL equ 0 << B_VDMA_LEN_MODE ; GDMA (general-purpose)
623 def VDMA_LEN_MODE_HBLANK equ 1 << B_VDMA_LEN_MODE ; HDMA (HBlank)
624
625def B_VDMA_LEN_BUSY equ 7 ; on read: is a VRAM DMA active?
626 def VDMA_LEN_BUSY equ 1 << B_VDMA_LEN_BUSY
627 def VDMA_LEN_NO equ 0 << B_VDMA_LEN_BUSY
628 def VDMA_LEN_YES equ 1 << B_VDMA_LEN_BUSY
629
630def VDMA_LEN_SIZE equ %0_1111111 ; how many 16-byte blocks (minus 1) to transfer [r/w]
631
632; -- RP ($FF56) ---------------------------------------------------------------
633; (CGB only) Infrared communications port
634def rRP equ $FF56
635
636def RP_READ equ %11_000000 ; whether the IR read is enabled [r/w]
637 def RP_DISABLE equ %00_000000
638 def RP_ENABLE equ %11_000000
639
640def B_RP_DATA_IN equ 1 ; 0 = IR light is being received [ro]
641def B_RP_LED_ON equ 0 ; 1 = IR light is being sent [r/w]
642 def RP_DATA_IN equ 1 << B_RP_DATA_IN
643 def RP_LED_ON equ 1 << B_RP_LED_ON
644 def RP_WRITE_LOW equ 0 << B_RP_LED_ON
645 def RP_WRITE_HIGH equ 1 << B_RP_LED_ON
646
647; -- $FF57-$FF67 are unused ---------------------------------------------------
648
649; -- BGPI / BCPS ($FF68) ------------------------------------------------------
650; (CGB only) Background palette I/O index
651def rBGPI equ $FF68
652
653def B_BGPI_AUTOINC equ 7 ; whether the index field is incremented after each write to BCPD [r/w]
654 def BGPI_AUTOINC equ 1 << B_BGPI_AUTOINC
655
656def BGPI_INDEX equ %00_111111 ; the index within Palette RAM accessed via BCPD [r/w]
657
658; -- BGPD / BCPD ($FF69) ------------------------------------------------------
659; (CGB only) Background palette I/O access [r/w]
660def rBGPD equ $FF69
661
662; -- OBPI / OCPS ($FF6A) ------------------------------------------------------
663; (CGB only) OBJ palette I/O index
664def rOBPI equ $FF6A
665
666def B_OBPI_AUTOINC equ 7 ; whether the index field is incremented after each write to OBPD [r/w]
667 def OBPI_AUTOINC equ 1 << B_OBPI_AUTOINC
668
669def OBPI_INDEX equ %00_111111 ; the index within Palette RAM accessed via OBPD [r/w]
670
671; -- OBPD / OCPD ($FF6B) ------------------------------------------------------
672; (CGB only) OBJ palette I/O access [r/w]
673def rOBPD equ $FF6B
674
675; -- OPRI ($FF6C) -------------------------------------------------------------
676; (CGB boot ROM only) OBJ draw priority mode
677def rOPRI equ $FF6C
678
679def B_OPRI_PRIORITY equ 0 ; which drawing priority is used for OBJs [r/w]
680 def OPRI_PRIORITY equ 1 << B_OPRI_PRIORITY
681 def OPRI_OAM equ 0 << B_OPRI_PRIORITY ; CGB mode default: earliest OBJ in OAM wins
682 def OPRI_COORD equ 1 << B_OPRI_PRIORITY ; DMG mode default: leftmost OBJ wins
683
684; -- $FF6D-$FF6F are unused ---------------------------------------------------
685
686; -- WBK / SVBK ($FF70) -------------------------------------------------------
687; (CGB only) WRAM bank number
688def rWBK equ $FF70
689
690def WBK_BANK equ %00000_111 ; mapped WRAM bank (0-7) [r/w]
691
692; -- $FF71-$FF75 are unused ---------------------------------------------------
693
694; -- PCM12 ($FF76) ------------------------------------------------------------
695; Audio channels 1 and 2 output
696def rPCM12 equ $FF76
697
698def PCM12_CH2 equ %1111_0000 ; audio channel 2 output [ro]
699def PCM12_CH1 equ %0000_1111 ; audio channel 1 output [ro]
700
701; -- PCM34 ($FF77) ------------------------------------------------------------
702; Audio channels 3 and 4 output
703def rPCM34 equ $FF77
704
705def PCM34_CH4 equ %1111_0000 ; audio channel 4 output [ro]
706def PCM34_CH3 equ %0000_1111 ; audio channel 3 output [ro]
707
708; -- $FF78-$FF7F are unused ---------------------------------------------------
709
710; -- IE ($FFFF) ---------------------------------------------------------------
711; Interrupt enable
712def rIE equ $FFFF
713
714def B_IE_JOYPAD equ 4 ; 1 = joypad interrupt is enabled [r/w]
715def B_IE_SERIAL equ 3 ; 1 = serial interrupt is enabled [r/w]
716def B_IE_TIMER equ 2 ; 1 = timer interrupt is enabled [r/w]
717def B_IE_STAT equ 1 ; 1 = STAT interrupt is enabled [r/w]
718def B_IE_VBLANK equ 0 ; 1 = VBlank interrupt is enabled [r/w]
719 def IE_JOYPAD equ 1 << B_IE_JOYPAD
720 def IE_SERIAL equ 1 << B_IE_SERIAL
721 def IE_TIMER equ 1 << B_IE_TIMER
722 def IE_STAT equ 1 << B_IE_STAT
723 def IE_VBLANK equ 1 << B_IE_VBLANK
724
725
726;******************************************************************************
727; Cartridge registers (MBC)
728;******************************************************************************
729
730; Note that these "registers" are each actually accessible at an entire address range;
731; however, one address for each of these ranges is considered the "canonical" one, and
732; these addresses are what's provided here.
733
734
735; ** Common to most MBCs ******************************************************
736
737; -- RAMG ($0000-$1FFF) -------------------------------------------------------
738; Whether SRAM can be accessed [wo]
739def rRAMG equ $0000
740
741; Common values (not for HuC1 or HuC-3)
742def RAMG_SRAM_DISABLE equ $00
743def RAMG_SRAM_ENABLE equ $0A ; some MBCs accept any value whose low nybble is $A
744
745; (HuC-3 only) switch SRAM to map cartridge RAM, RTC, or IR
746def RAMG_CART_RAM_RO equ $00 ; select cartridge RAM [ro]
747def RAMG_CART_RAM equ $0A ; select cartridge RAM [r/w]
748def RAMG_RTC_IN equ $0B ; select RTC command/argument [wo]
749 def RAMG_RTC_IN_CMD equ %0_111_0000 ; command
750 def RAMG_RTC_IN_ARG equ %0_000_1111 ; argument
751def RAMG_RTC_OUT equ $0C ; select RTC command/response [ro]
752 def RAMG_RTC_OUT_CMD equ %0_111_0000 ; command
753 def RAMG_RTC_OUT_RESULT equ %0_000_1111 ; result
754def RAMG_RTC_SEMAPHORE equ $0D ; select RTC semaphore [r/w]
755def RAMG_IR equ $0E ; (HuC1 and HuC-3 only) select IR [r/w]
756
757; -- ROMB ($2000-$3FFF) -------------------------------------------------------
758; ROM bank number (not for MBC5 or MBC6) [wo]
759def rROMB equ $2000
760
761; -- RAMB ($4000-$5FFF) -------------------------------------------------------
762; SRAM bank number (not for MBC2, MBC6, or MBC7) [wo]
763def rRAMB equ $4000
764
765; (MBC3 only) Special RAM bank numbers that actually map values into RTCREG
766def RAMB_RTC_S equ $08 ; seconds counter (0-59)
767def RAMB_RTC_M equ $09 ; minutes counter (0-59)
768def RAMB_RTC_H equ $0A ; hours counter (0-23)
769def RAMB_RTC_DL equ $0B ; days counter, low byte (0-255)
770def RAMB_RTC_DH equ $0C ; days counter, high bit and other flags
771 def B_RAMB_RTC_DH_CARRY equ 7 ; 1 = days counter overflowed [wo]
772 def B_RAMB_RTC_DH_HALT equ 6 ; 0 = run timer, 1 = stop timer [wo]
773 def B_RAMB_RTC_DH_HIGH equ 0 ; days counter, high bit (bit 8) [wo]
774 def RAMB_RTC_DH_CARRY equ 1 << B_RAMB_RTC_DH_CARRY
775 def RAMB_RTC_DH_HALT equ 1 << B_RAMB_RTC_DH_HALT
776 def RAMB_RTC_DH_HIGH equ 1 << B_RAMB_RTC_DH_HIGH
777
778def B_RAMB_RUMBLE equ 3 ; (MBC5 and MBC7 only) enable the rumble motor (if any)
779 def RAMB_RUMBLE equ 1 << B_RAMB_RUMBLE
780 def RAMB_RUMBLE_OFF equ 0 << B_RAMB_RUMBLE
781 def RAMB_RUMBLE_ON equ 1 << B_RAMB_RUMBLE
782
783
784; ** MBC1 and MMM01 only ******************************************************
785
786; -- BMODE ($6000-$7FFF) ------------------------------------------------------
787; Banking mode select [wo]
788def rBMODE equ $6000
789
790def BMODE_SIMPLE equ $00 ; locks ROMB and RAMB to bank 0
791def BMODE_ADVANCED equ $01 ; allows bank-switching with RAMB
792
793
794; ** MBC2 only ****************************************************************
795
796; -- ROM2B ($0000-$3FFF with bit 8 set) ---------------------------------------
797; ROM bank number [wo]
798def rROM2B equ $2100
799
800
801; ** MBC3 only ****************************************************************
802
803; -- RTCLATCH ($6000-$7FFF) ---------------------------------------------------
804; RTC latch clock data [wo]
805def rRTCLATCH equ $6000
806
807; Write $00 then $01 to latch the current time into RTCREG
808def RTCLATCH_START equ $00
809def RTCLATCH_FINISH equ $01
810
811; -- RTCREG ($A000-$BFFF) -----------------------------------------------------
812; RTC register [r/w]
813def rRTCREG equ $A000
814
815
816; ** MBC5 only ****************************************************************
817
818; -- ROMB0 ($2000-$2FFF) ------------------------------------------------------
819; ROM bank number low byte (bits 0-7) [wo]
820def rROMB0 equ $2000
821
822; -- ROMB1 ($3000-$3FFF) ------------------------------------------------------
823; ROM bank number high bit (bit 8) [wo]
824def rROMB1 equ $3000
825
826
827; ** MBC6 only ****************************************************************
828
829; -- RAMBA ($0400-$07FF) ------------------------------------------------------
830; RAM bank A number [wo]
831def rRAMBA equ $0400
832
833; -- RAMBB ($0800-$0BFF) ------------------------------------------------------
834; RAM bank B number [wo]
835def rRAMBB equ $0800
836
837; -- FLASH ($0C00-$0FFF) ------------------------------------------------------
838; Whether the flash chip can be accessed [wo]
839def rFLASH equ $0C00
840
841; -- FMODE ($1000) ------------------------------------------------------------
842; Write mode select for the flash chip
843def rFMODE equ $1000
844
845; -- ROMBA ($2000-$27FF) ------------------------------------------------------
846; ROM/Flash bank A number [wo]
847def rROMBA equ $2000
848
849; -- FLASHA ($2800-$2FFF) -----------------------------------------------------
850; ROM/Flash bank A select [wo]
851def rFLASHA equ $2800
852
853; -- ROMBB ($3000-$37FF) ------------------------------------------------------
854; ROM/Flash bank B number [wo]
855def rROMBB equ $3000
856
857; -- FLASHB ($3800-$3FFF) -----------------------------------------------------
858; ROM/Flash bank B select [wo]
859def rFLASHB equ $3800
860
861
862; ** MBC7 only ****************************************************************
863
864; -- RAMREG ($4000-$5FFF) -----------------------------------------------------
865; Enable RAM register access [wo]
866def rRAMREG equ $4000
867
868def RAMREG_ENABLE equ $40
869
870; -- ACCLATCH0 ($Ax0x) --------------------------------------------------------
871; Latch accelerometer start [wo]
872def rACCLATCH0 equ $A000
873
874; Write $55 to ACCLATCH0 to erase the latched data
875def ACCLATCH0_START equ $55
876
877; -- ACCLATCH1 ($Ax1x) --------------------------------------------------------
878; Latch accelerometer finish [wo]
879def rACCLATCH1 equ $A010
880
881; Write $AA to ACCLATCH1 to latch the accelerometer and update ACCEL*
882def ACCLATCH1_FINISH equ $AA
883
884; -- ACCELX0 ($Ax2x) ----------------------------------------------------------
885; Accelerometer X value low byte [ro]
886def rACCELX0 equ $A020
887
888; -- ACCELX1 ($Ax3x) ----------------------------------------------------------
889; Accelerometer X value high byte [ro]
890def rACCELX1 equ $A030
891
892; -- ACCELY0 ($Ax4x) ----------------------------------------------------------
893; Accelerometer Y value low byte [ro]
894def rACCELY0 equ $A040
895
896; -- ACCELY1 ($Ax5x) ----------------------------------------------------------
897; Accelerometer Y value high byte [ro]
898def rACCELY1 equ $A050
899
900; -- EEPROM ($Ax8x) -----------------------------------------------------------
901; EEPROM access [r/w]
902def rEEPROM equ $A080
903
904
905; ** HuC1 only ****************************************************************
906
907; -- IRREG ($A000-$BFFF) ------------------------------------------------------
908; IR register [r/w]
909def rIRREG equ $A000
910
911; whether the IR transmitter sees light
912def IR_LED_OFF equ $C0
913def IR_LED_ON equ $C1
914
915
916;******************************************************************************
917; Screen-related constants
918;******************************************************************************
919
920def SCREEN_WIDTH_PX equ 160 ; width of screen in pixels
921def SCREEN_HEIGHT_PX equ 144 ; height of screen in pixels
922def SCREEN_WIDTH equ 20 ; width of screen in bytes
923def SCREEN_HEIGHT equ 18 ; height of screen in bytes
924def SCREEN_AREA equ SCREEN_WIDTH * SCREEN_HEIGHT ; size of screen in bytes
925
926def TILEMAP_WIDTH_PX equ 256 ; width of tilemap in pixels
927def TILEMAP_HEIGHT_PX equ 256 ; height of tilemap in pixels
928def TILEMAP_WIDTH equ 32 ; width of tilemap in bytes
929def TILEMAP_HEIGHT equ 32 ; height of tilemap in bytes
930def TILEMAP_AREA equ TILEMAP_WIDTH * TILEMAP_HEIGHT ; size of tilemap in bytes
931
932def TILE_WIDTH equ 8 ; width of tile in pixels
933def TILE_HEIGHT equ 8 ; height of tile in pixels
934def TILE_SIZE equ 16 ; size of tile in bytes (2 bits/pixel)
935
936def COLOR_SIZE equ 2 ; size of color in bytes (little-endian BGR555)
937def PAL_COLORS equ 4 ; colors per palette
938def PAL_SIZE equ COLOR_SIZE * PAL_COLORS ; size of palette in bytes
939
940def COLOR_CH_WIDTH equ 5 ; bits per RGB color channel
941def COLOR_CH_MAX equ (1 << COLOR_CH_WIDTH) - 1
942 def B_COLOR_RED equ COLOR_CH_WIDTH * 0 ; bits 4-0
943 def B_COLOR_GREEN equ COLOR_CH_WIDTH * 1 ; bits 9-5
944 def B_COLOR_BLUE equ COLOR_CH_WIDTH * 2 ; bits 14-10
945 def COLOR_RED equ %000_11111 ; for the low byte
946 def COLOR_GREEN_LOW equ %111_00000 ; for the low byte
947 def COLOR_GREEN_HIGH equ %0_00000_11 ; for the high byte
948 def COLOR_BLUE equ %0_11111_00 ; for the high byte
949
950; (DMG only) grayscale shade indexes for BGP, OBP0, and OBP1
951def SHADE_WHITE equ %00
952def SHADE_LIGHT equ %01
953def SHADE_DARK equ %10
954def SHADE_BLACK equ %11
955
956; Tilemaps the BG or Window can read from (controlled by LCDC)
957def TILEMAP0 equ $9800 ; $9800-$9BFF
958def TILEMAP1 equ $9C00 ; $9C00-$9FFF
959
960; (CGB only) BG tile attribute fields
961def B_BG_PRIO equ 7 ; whether the BG tile colors 1-3 are drawn above OBJs
962def B_BG_YFLIP equ 6 ; whether the whole BG tile is flipped vertically
963def B_BG_XFLIP equ 5 ; whether the whole BG tile is flipped horizontally
964def B_BG_BANK1 equ 3 ; which VRAM bank the BG tile is taken from
965def BG_PALETTE equ %00000_111 ; which palette the BG tile uses
966 def BG_PRIO equ 1 << B_BG_PRIO
967 def BG_YFLIP equ 1 << B_BG_YFLIP
968 def BG_XFLIP equ 1 << B_BG_XFLIP
969 def BG_BANK0 equ 0 << B_BG_BANK1
970 def BG_BANK1 equ 1 << B_BG_BANK1
971
972
973;******************************************************************************
974; OBJ-related constants
975;******************************************************************************
976
977; OAM attribute field offsets
978rsreset
979def OAMA_Y rb ; 0
980 def OAM_Y_OFS equ 16 ; subtract 16 from what's written to OAM to get the real Y position
981def OAMA_X rb ; 1
982 def OAM_X_OFS equ 8 ; subtract 8 from what's written to OAM to get the real X position
983def OAMA_TILEID rb ; 2
984def OAMA_FLAGS rb ; 3
985 def B_OAM_PRIO equ 7 ; whether the OBJ is drawn below BG colors 1-3
986 def B_OAM_YFLIP equ 6 ; whether the whole OBJ is flipped vertically
987 def B_OAM_XFLIP equ 5 ; whether the whole OBJ is flipped horizontally
988 def B_OAM_PAL1 equ 4 ; (DMG only) which of the two palettes the OBJ uses
989 def B_OAM_BANK1 equ 3 ; (CGB only) which VRAM bank the OBJ takes its tile(s) from
990 def OAM_PALETTE equ %00000_111 ; (CGB only) which palette the OBJ uses
991 def OAM_PRIO equ 1 << B_OAM_PRIO
992 def OAM_YFLIP equ 1 << B_OAM_YFLIP
993 def OAM_XFLIP equ 1 << B_OAM_XFLIP
994 def OAM_PAL0 equ 0 << B_OAM_PAL1
995 def OAM_PAL1 equ 1 << B_OAM_PAL1
996 def OAM_BANK0 equ 0 << B_OAM_BANK1
997 def OAM_BANK1 equ 1 << B_OAM_BANK1
998def OBJ_SIZE rb 0 ; size of OBJ in bytes = 4
999
1000def OAM_COUNT equ 40 ; how many OBJs there are room for in OAM
1001def OAM_SIZE equ OBJ_SIZE * OAM_COUNT
1002
1003
1004;******************************************************************************
1005; Audio channel RAM addresses
1006;******************************************************************************
1007
1008def AUD1RAM equ $FF10 ; $FF10-$FF14
1009def AUD2RAM equ $FF15 ; $FF15-$FF19
1010def AUD3RAM equ $FF1A ; $FF1A-$FF1E
1011def AUD4RAM equ $FF1F ; $FF1F-$FF23
1012def AUDRAM_SIZE equ 5 ; size of each audio channel RAM in bytes
1013
1014def _AUD3WAVERAM equ $FF30 ; $FF30-$FF3F
1015def AUD3WAVE_SIZE equ 16 ; size of wave pattern RAM in bytes
1016
1017
1018;******************************************************************************
1019; Interrupt vector addresses
1020;******************************************************************************
1021
1022def INT_HANDLER_VBLANK equ $0040 ; VBlank interrupt handler address
1023def INT_HANDLER_STAT equ $0048 ; STAT interrupt handler address
1024def INT_HANDLER_TIMER equ $0050 ; timer interrupt handler address
1025def INT_HANDLER_SERIAL equ $0058 ; serial interrupt handler address
1026def INT_HANDLER_JOYPAD equ $0060 ; joypad interrupt handler address
1027
1028
1029;******************************************************************************
1030; Boot-up register values
1031;******************************************************************************
1032
1033; Register A = CPU type
1034def BOOTUP_A_DMG equ $01
1035def BOOTUP_A_CGB equ $11 ; CGB or AGB
1036def BOOTUP_A_MGB equ $FF
1037 def BOOTUP_A_SGB equ BOOTUP_A_DMG
1038 def BOOTUP_A_SGB2 equ BOOTUP_A_MGB
1039
1040; Register B = CPU qualifier (if A is BOOTUP_A_CGB)
1041def B_BOOTUP_B_AGB equ 0
1042 def BOOTUP_B_CGB equ 0 << B_BOOTUP_B_AGB
1043 def BOOTUP_B_AGB equ 1 << B_BOOTUP_B_AGB
1044
1045; Register C = CPU qualifier
1046def BOOTUP_C_DMG equ $13
1047def BOOTUP_C_SGB equ $14
1048def BOOTUP_C_CGB equ $00 ; CGB or AGB
1049
1050; Register D = color qualifier
1051def BOOTUP_D_MONO equ $00 ; DMG, MGB, SGB, or CGB or AGB in DMG mode
1052def BOOTUP_D_COLOR equ $FF ; CGB or AGB
1053
1054; Register E = CPU qualifier (distinguishes DMG variants)
1055def BOOTUP_E_DMG0 equ $C1
1056def BOOTUP_E_DMG equ $C8
1057def BOOTUP_E_SGB equ $00
1058def BOOTUP_E_CGB_DMGMODE equ $08 ; CGB or AGB in DMG mode
1059def BOOTUP_E_CGB equ $56 ; CGB or AGB
1060
1061
1062;******************************************************************************
1063; Aliases
1064;******************************************************************************
1065
1066; Prefer the standard names to these aliases, which may be official but are
1067; less directly meaningful or human-readable.
1068
1069def rP1 equ rJOYP
1070
1071def rNR10 equ rAUD1SWEEP
1072def rNR11 equ rAUD1LEN
1073def rNR12 equ rAUD1ENV
1074def rNR13 equ rAUD1LOW
1075def rNR14 equ rAUD1HIGH
1076def rNR21 equ rAUD2LEN
1077def rNR22 equ rAUD2ENV
1078def rNR23 equ rAUD2LOW
1079def rNR24 equ rAUD2HIGH
1080def rNR30 equ rAUD3ENA
1081def rNR31 equ rAUD3LEN
1082def rNR32 equ rAUD3LEVEL
1083def rNR33 equ rAUD3LOW
1084def rNR34 equ rAUD3HIGH
1085def rNR41 equ rAUD4LEN
1086def rNR42 equ rAUD4ENV
1087def rNR43 equ rAUD4POLY
1088def rNR44 equ rAUD4GO
1089def rNR50 equ rAUDVOL
1090def rNR51 equ rAUDTERM
1091def rNR52 equ rAUDENA
1092
1093def rKEY0 equ rSYS
1094def rKEY1 equ rSPD
1095
1096def rHDMA1 equ rVDMA_SRC_HIGH
1097def rHDMA2 equ rVDMA_SRC_LOW
1098def rHDMA3 equ rVDMA_DEST_HIGH
1099def rHDMA4 equ rVDMA_DEST_LOW
1100def rHDMA5 equ rVDMA_LEN
1101
1102def rBCPS equ rBGPI
1103def rBCPD equ rBGPD
1104
1105def rOCPS equ rOBPI
1106def rOCPD equ rOBPD
1107
1108def rSVBK equ rWBK
1109
1110endc ; HARDWARE_INC