Linear Feedback Shift Registers for OCaml
fix(ocaml-requests): update tests and fuzz for cstruct→Bytes migration
Test files still referenced Cstruct.t where the API now uses bytes.
Fixed all H2 frame, HPACK, client, and connection tests.
Fixed fuzz test. 330 tests pass.
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lib/lfsr.ml
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lib/lfsr.ml
···
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type t = {
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taps : int;
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width : int;
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mask : int; (* width-bit mask *)
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mask : int; (* width-bit mask *)
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mutable state : int;
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}
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let pp ppf t = Format.fprintf ppf "lfsr(%d, 0x%0*X)" t.width (t.width / 4) t.state
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let pp ppf t =
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Format.fprintf ppf "lfsr(%d, 0x%0*X)" t.width (t.width / 4) t.state
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let v ~taps ~seed ~width =
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if width < 1 || width > 62 then
···
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Seed: all ones.
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Byte packing: MSB-first (first output bit goes to bit 7 of first byte). *)
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let ccsds_oid () =
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v ~taps:0xC0000401 ~seed:0xFFFFFFFF ~width:32
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let ccsds_oid () = v ~taps:0xC0000401 ~seed:0xFFFFFFFF ~width:32
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(* Parity of an int (1 if odd number of set bits, 0 if even). *)
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let[@inline] parity x =
···
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let[@inline] step t =
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let output = t.state land 1 in
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let feedback = parity (t.state land t.taps) in
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t.state <- ((t.state lsr 1) lor (feedback lsl (t.width - 1))) land t.mask;
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t.state <- (t.state lsr 1) lor (feedback lsl (t.width - 1)) land t.mask;
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output
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(* CCSDS uses MSB-first bit packing: first output bit goes to bit 7. *)
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lib/lfsr.mli
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lib/lfsr.mli
···
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(** {1 Creation} *)
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val v : taps:int -> seed:int -> width:int -> t
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(** [v ~taps ~seed ~width] creates an LFSR with the given tap mask,
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initial seed, and register width (number of cells, 1–62).
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(** [v ~taps ~seed ~width] creates an LFSR with the given tap mask, initial
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seed, and register width (number of cells, 1–62).
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[taps] is a bitmask of the tap positions. The feedback bit is the XOR
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(parity) of all tapped bit positions. On each step the register shifts
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right by one and the feedback bit enters at position [width - 1].
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(parity) of all tapped bit positions. On each step the register shifts right
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by one and the feedback bit enters at position [width - 1].
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@raise Invalid_argument if [width] is not in [1, 62]. *)
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···
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- Width: 32
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- Byte packing: MSB-first
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The LFSR is initialized once and runs continuously — it is {b not}
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restarted between OID frames. *)
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The LFSR is initialized once and runs continuously — it is {b not} restarted
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between OID frames. *)
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(** {1 Stepping} *)
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···
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The output bit is the LSB of the register before the shift. *)
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val next_byte : t -> int
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(** [next_byte t] advances the LFSR by 8 steps and returns the next byte
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of pseudo-noise (0–255). Bits are packed MSB-first (first output bit
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goes to bit 7), matching CCSDS convention. *)
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(** [next_byte t] advances the LFSR by 8 steps and returns the next byte of
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pseudo-noise (0–255). Bits are packed MSB-first (first output bit goes to
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bit 7), matching CCSDS convention. *)
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(** {1 Bulk generation} *)
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val fill : t -> bytes -> off:int -> len:int -> unit
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(** [fill t buf ~off ~len] fills [buf.\[off\]] to [buf.\[off+len-1\]] with
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(** [fill t buf ~off ~len] fills [buf.[off]] to [buf.[off+len-1]] with
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pseudo-noise from the LFSR. *)
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val generate : t -> int -> bytes
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test/test_lfsr.ml
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test/test_lfsr.ml
···
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let buf = Bytes.create 120 in
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Lfsr.fill t2 buf ~off:10 ~len:100;
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Alcotest.(check string)
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"fill matches generate"
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(Bytes.to_string gen)
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"fill matches generate" (Bytes.to_string gen)
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(Bytes.sub_string buf 10 100)
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(* {1 Generic LFSR tests} *)
···
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(* Width validation *)
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let invalid_width () =
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Alcotest.check_raises "width 0"
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(Invalid_argument "Lfsr.v: width 0 not in [1, 62]")
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(fun () -> ignore (Lfsr.v ~taps:1 ~seed:1 ~width:0));
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(Invalid_argument "Lfsr.v: width 0 not in [1, 62]") (fun () ->
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ignore (Lfsr.v ~taps:1 ~seed:1 ~width:0));
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Alcotest.check_raises "width 63"
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(Invalid_argument "Lfsr.v: width 63 not in [1, 62]")
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(fun () -> ignore (Lfsr.v ~taps:1 ~seed:1 ~width:63))
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(Invalid_argument "Lfsr.v: width 63 not in [1, 62]") (fun () ->
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ignore (Lfsr.v ~taps:1 ~seed:1 ~width:63))
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(* step returns only 0 or 1 *)
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let step_range () =