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1/* amdgpu_drm.h -- Public header for the amdgpu driver -*- linux-c -*-
2 *
3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
5 * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * Copyright 2014 Advanced Micro Devices, Inc.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
24 * OTHER DEALINGS IN THE SOFTWARE.
25 *
26 * Authors:
27 * Kevin E. Martin <martin@valinux.com>
28 * Gareth Hughes <gareth@valinux.com>
29 * Keith Whitwell <keith@tungstengraphics.com>
30 */
31
32#ifndef __AMDGPU_DRM_H__
33#define __AMDGPU_DRM_H__
34
35#include "drm.h"
36
37#if defined(__cplusplus)
38extern "C" {
39#endif
40
41#define DRM_AMDGPU_GEM_CREATE 0x00
42#define DRM_AMDGPU_GEM_MMAP 0x01
43#define DRM_AMDGPU_CTX 0x02
44#define DRM_AMDGPU_BO_LIST 0x03
45#define DRM_AMDGPU_CS 0x04
46#define DRM_AMDGPU_INFO 0x05
47#define DRM_AMDGPU_GEM_METADATA 0x06
48#define DRM_AMDGPU_GEM_WAIT_IDLE 0x07
49#define DRM_AMDGPU_GEM_VA 0x08
50#define DRM_AMDGPU_WAIT_CS 0x09
51#define DRM_AMDGPU_GEM_OP 0x10
52#define DRM_AMDGPU_GEM_USERPTR 0x11
53#define DRM_AMDGPU_WAIT_FENCES 0x12
54#define DRM_AMDGPU_VM 0x13
55#define DRM_AMDGPU_FENCE_TO_HANDLE 0x14
56#define DRM_AMDGPU_SCHED 0x15
57#define DRM_AMDGPU_USERQ 0x16
58#define DRM_AMDGPU_USERQ_SIGNAL 0x17
59#define DRM_AMDGPU_USERQ_WAIT 0x18
60
61#define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create)
62#define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap)
63#define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx)
64#define DRM_IOCTL_AMDGPU_BO_LIST DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list)
65#define DRM_IOCTL_AMDGPU_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs)
66#define DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info)
67#define DRM_IOCTL_AMDGPU_GEM_METADATA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata)
68#define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle)
69#define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va)
70#define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs)
71#define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op)
72#define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr)
73#define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences)
74#define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm)
75#define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle)
76#define DRM_IOCTL_AMDGPU_SCHED DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched)
77#define DRM_IOCTL_AMDGPU_USERQ DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ, union drm_amdgpu_userq)
78#define DRM_IOCTL_AMDGPU_USERQ_SIGNAL DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ_SIGNAL, struct drm_amdgpu_userq_signal)
79#define DRM_IOCTL_AMDGPU_USERQ_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ_WAIT, struct drm_amdgpu_userq_wait)
80
81/**
82 * DOC: memory domains
83 *
84 * %AMDGPU_GEM_DOMAIN_CPU System memory that is not GPU accessible.
85 * Memory in this pool could be swapped out to disk if there is pressure.
86 *
87 * %AMDGPU_GEM_DOMAIN_GTT GPU accessible system memory, mapped into the
88 * GPU's virtual address space via gart. Gart memory linearizes non-contiguous
89 * pages of system memory, allows GPU access system memory in a linearized
90 * fashion.
91 *
92 * %AMDGPU_GEM_DOMAIN_VRAM Local video memory. For APUs, it is memory
93 * carved out by the BIOS.
94 *
95 * %AMDGPU_GEM_DOMAIN_GDS Global on-chip data storage used to share data
96 * across shader threads.
97 *
98 * %AMDGPU_GEM_DOMAIN_GWS Global wave sync, used to synchronize the
99 * execution of all the waves on a device.
100 *
101 * %AMDGPU_GEM_DOMAIN_OA Ordered append, used by 3D or Compute engines
102 * for appending data.
103 *
104 * %AMDGPU_GEM_DOMAIN_DOORBELL Doorbell. It is an MMIO region for
105 * signalling user mode queues.
106 */
107#define AMDGPU_GEM_DOMAIN_CPU 0x1
108#define AMDGPU_GEM_DOMAIN_GTT 0x2
109#define AMDGPU_GEM_DOMAIN_VRAM 0x4
110#define AMDGPU_GEM_DOMAIN_GDS 0x8
111#define AMDGPU_GEM_DOMAIN_GWS 0x10
112#define AMDGPU_GEM_DOMAIN_OA 0x20
113#define AMDGPU_GEM_DOMAIN_DOORBELL 0x40
114#define AMDGPU_GEM_DOMAIN_MASK (AMDGPU_GEM_DOMAIN_CPU | \
115 AMDGPU_GEM_DOMAIN_GTT | \
116 AMDGPU_GEM_DOMAIN_VRAM | \
117 AMDGPU_GEM_DOMAIN_GDS | \
118 AMDGPU_GEM_DOMAIN_GWS | \
119 AMDGPU_GEM_DOMAIN_OA | \
120 AMDGPU_GEM_DOMAIN_DOORBELL)
121
122/* Flag that CPU access will be required for the case of VRAM domain */
123#define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0)
124/* Flag that CPU access will not work, this VRAM domain is invisible */
125#define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1)
126/* Flag that USWC attributes should be used for GTT */
127#define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2)
128/* Flag that the memory should be in VRAM and cleared */
129#define AMDGPU_GEM_CREATE_VRAM_CLEARED (1 << 3)
130/* Flag that allocating the BO should use linear VRAM */
131#define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5)
132/* Flag that BO is always valid in this VM */
133#define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID (1 << 6)
134/* Flag that BO sharing will be explicitly synchronized */
135#define AMDGPU_GEM_CREATE_EXPLICIT_SYNC (1 << 7)
136/* Flag that indicates allocating MQD gart on GFX9, where the mtype
137 * for the second page onward should be set to NC. It should never
138 * be used by user space applications.
139 */
140#define AMDGPU_GEM_CREATE_CP_MQD_GFX9 (1 << 8)
141/* Flag that BO may contain sensitive data that must be wiped before
142 * releasing the memory
143 */
144#define AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE (1 << 9)
145/* Flag that BO will be encrypted and that the TMZ bit should be
146 * set in the PTEs when mapping this buffer via GPUVM or
147 * accessing it with various hw blocks
148 */
149#define AMDGPU_GEM_CREATE_ENCRYPTED (1 << 10)
150/* Flag that BO will be used only in preemptible context, which does
151 * not require GTT memory accounting
152 */
153#define AMDGPU_GEM_CREATE_PREEMPTIBLE (1 << 11)
154/* Flag that BO can be discarded under memory pressure without keeping the
155 * content.
156 */
157#define AMDGPU_GEM_CREATE_DISCARDABLE (1 << 12)
158/* Flag that BO is shared coherently between multiple devices or CPU threads.
159 * May depend on GPU instructions to flush caches to system scope explicitly.
160 *
161 * This influences the choice of MTYPE in the PTEs on GFXv9 and later GPUs and
162 * may override the MTYPE selected in AMDGPU_VA_OP_MAP.
163 */
164#define AMDGPU_GEM_CREATE_COHERENT (1 << 13)
165/* Flag that BO should not be cached by GPU. Coherent without having to flush
166 * GPU caches explicitly
167 *
168 * This influences the choice of MTYPE in the PTEs on GFXv9 and later GPUs and
169 * may override the MTYPE selected in AMDGPU_VA_OP_MAP.
170 */
171#define AMDGPU_GEM_CREATE_UNCACHED (1 << 14)
172/* Flag that BO should be coherent across devices when using device-level
173 * atomics. May depend on GPU instructions to flush caches to device scope
174 * explicitly, promoting them to system scope automatically.
175 *
176 * This influences the choice of MTYPE in the PTEs on GFXv9 and later GPUs and
177 * may override the MTYPE selected in AMDGPU_VA_OP_MAP.
178 */
179#define AMDGPU_GEM_CREATE_EXT_COHERENT (1 << 15)
180/* Set PTE.D and recompress during GTT->VRAM moves according to TILING flags. */
181#define AMDGPU_GEM_CREATE_GFX12_DCC (1 << 16)
182
183struct drm_amdgpu_gem_create_in {
184 /** the requested memory size */
185 __u64 bo_size;
186 /** physical start_addr alignment in bytes for some HW requirements */
187 __u64 alignment;
188 /** the requested memory domains */
189 __u64 domains;
190 /** allocation flags */
191 __u64 domain_flags;
192};
193
194struct drm_amdgpu_gem_create_out {
195 /** returned GEM object handle */
196 __u32 handle;
197 __u32 _pad;
198};
199
200union drm_amdgpu_gem_create {
201 struct drm_amdgpu_gem_create_in in;
202 struct drm_amdgpu_gem_create_out out;
203};
204
205/** Opcode to create new residency list. */
206#define AMDGPU_BO_LIST_OP_CREATE 0
207/** Opcode to destroy previously created residency list */
208#define AMDGPU_BO_LIST_OP_DESTROY 1
209/** Opcode to update resource information in the list */
210#define AMDGPU_BO_LIST_OP_UPDATE 2
211
212struct drm_amdgpu_bo_list_in {
213 /** Type of operation */
214 __u32 operation;
215 /** Handle of list or 0 if we want to create one */
216 __u32 list_handle;
217 /** Number of BOs in list */
218 __u32 bo_number;
219 /** Size of each element describing BO */
220 __u32 bo_info_size;
221 /** Pointer to array describing BOs */
222 __u64 bo_info_ptr;
223};
224
225struct drm_amdgpu_bo_list_entry {
226 /** Handle of BO */
227 __u32 bo_handle;
228 /** New (if specified) BO priority to be used during migration */
229 __u32 bo_priority;
230};
231
232struct drm_amdgpu_bo_list_out {
233 /** Handle of resource list */
234 __u32 list_handle;
235 __u32 _pad;
236};
237
238union drm_amdgpu_bo_list {
239 struct drm_amdgpu_bo_list_in in;
240 struct drm_amdgpu_bo_list_out out;
241};
242
243/* context related */
244#define AMDGPU_CTX_OP_ALLOC_CTX 1
245#define AMDGPU_CTX_OP_FREE_CTX 2
246#define AMDGPU_CTX_OP_QUERY_STATE 3
247#define AMDGPU_CTX_OP_QUERY_STATE2 4
248#define AMDGPU_CTX_OP_GET_STABLE_PSTATE 5
249#define AMDGPU_CTX_OP_SET_STABLE_PSTATE 6
250
251/* GPU reset status */
252#define AMDGPU_CTX_NO_RESET 0
253/* this the context caused it */
254#define AMDGPU_CTX_GUILTY_RESET 1
255/* some other context caused it */
256#define AMDGPU_CTX_INNOCENT_RESET 2
257/* unknown cause */
258#define AMDGPU_CTX_UNKNOWN_RESET 3
259
260/* indicate gpu reset occurred after ctx created */
261#define AMDGPU_CTX_QUERY2_FLAGS_RESET (1<<0)
262/* indicate vram lost occurred after ctx created */
263#define AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST (1<<1)
264/* indicate some job from this context once cause gpu hang */
265#define AMDGPU_CTX_QUERY2_FLAGS_GUILTY (1<<2)
266/* indicate some errors are detected by RAS */
267#define AMDGPU_CTX_QUERY2_FLAGS_RAS_CE (1<<3)
268#define AMDGPU_CTX_QUERY2_FLAGS_RAS_UE (1<<4)
269/* indicate that the reset hasn't completed yet */
270#define AMDGPU_CTX_QUERY2_FLAGS_RESET_IN_PROGRESS (1<<5)
271
272/* Context priority level */
273#define AMDGPU_CTX_PRIORITY_UNSET -2048
274#define AMDGPU_CTX_PRIORITY_VERY_LOW -1023
275#define AMDGPU_CTX_PRIORITY_LOW -512
276#define AMDGPU_CTX_PRIORITY_NORMAL 0
277/*
278 * When used in struct drm_amdgpu_ctx_in, a priority above NORMAL requires
279 * CAP_SYS_NICE or DRM_MASTER
280*/
281#define AMDGPU_CTX_PRIORITY_HIGH 512
282#define AMDGPU_CTX_PRIORITY_VERY_HIGH 1023
283
284/* select a stable profiling pstate for perfmon tools */
285#define AMDGPU_CTX_STABLE_PSTATE_FLAGS_MASK 0xf
286#define AMDGPU_CTX_STABLE_PSTATE_NONE 0
287#define AMDGPU_CTX_STABLE_PSTATE_STANDARD 1
288#define AMDGPU_CTX_STABLE_PSTATE_MIN_SCLK 2
289#define AMDGPU_CTX_STABLE_PSTATE_MIN_MCLK 3
290#define AMDGPU_CTX_STABLE_PSTATE_PEAK 4
291
292struct drm_amdgpu_ctx_in {
293 /** AMDGPU_CTX_OP_* */
294 __u32 op;
295 /** Flags */
296 __u32 flags;
297 __u32 ctx_id;
298 /** AMDGPU_CTX_PRIORITY_* */
299 __s32 priority;
300};
301
302union drm_amdgpu_ctx_out {
303 struct {
304 __u32 ctx_id;
305 __u32 _pad;
306 } alloc;
307
308 struct {
309 /** For future use, no flags defined so far */
310 __u64 flags;
311 /** Number of resets caused by this context so far. */
312 __u32 hangs;
313 /** Reset status since the last call of the ioctl. */
314 __u32 reset_status;
315 } state;
316
317 struct {
318 __u32 flags;
319 __u32 _pad;
320 } pstate;
321};
322
323union drm_amdgpu_ctx {
324 struct drm_amdgpu_ctx_in in;
325 union drm_amdgpu_ctx_out out;
326};
327
328/* user queue IOCTL operations */
329#define AMDGPU_USERQ_OP_CREATE 1
330#define AMDGPU_USERQ_OP_FREE 2
331
332/*
333 * This structure is a container to pass input configuration
334 * info for all supported userqueue related operations.
335 * For operation AMDGPU_USERQ_OP_CREATE: user is expected
336 * to set all fields, excep the parameter 'queue_id'.
337 * For operation AMDGPU_USERQ_OP_FREE: the only input parameter expected
338 * to be set is 'queue_id', eveything else is ignored.
339 */
340struct drm_amdgpu_userq_in {
341 /** AMDGPU_USERQ_OP_* */
342 __u32 op;
343 /** Queue id passed for operation USERQ_OP_FREE */
344 __u32 queue_id;
345 /** the target GPU engine to execute workload (AMDGPU_HW_IP_*) */
346 __u32 ip_type;
347 /**
348 * @doorbell_handle: the handle of doorbell GEM object
349 * associated to this userqueue client.
350 */
351 __u32 doorbell_handle;
352 /**
353 * @doorbell_offset: 32-bit offset of the doorbell in the doorbell bo.
354 * Kernel will generate absolute doorbell offset using doorbell_handle
355 * and doorbell_offset in the doorbell bo.
356 */
357 __u32 doorbell_offset;
358 __u32 _pad;
359 /**
360 * @queue_va: Virtual address of the GPU memory which holds the queue
361 * object. The queue holds the workload packets.
362 */
363 __u64 queue_va;
364 /**
365 * @queue_size: Size of the queue in bytes, this needs to be 256-byte
366 * aligned.
367 */
368 __u64 queue_size;
369 /**
370 * @rptr_va : Virtual address of the GPU memory which holds the ring RPTR.
371 * This object must be at least 8 byte in size and aligned to 8-byte offset.
372 */
373 __u64 rptr_va;
374 /**
375 * @wptr_va : Virtual address of the GPU memory which holds the ring WPTR.
376 * This object must be at least 8 byte in size and aligned to 8-byte offset.
377 *
378 * Queue, RPTR and WPTR can come from the same object, as long as the size
379 * and alignment related requirements are met.
380 */
381 __u64 wptr_va;
382 /**
383 * @mqd: MQD (memory queue descriptor) is a set of parameters which allow
384 * the GPU to uniquely define and identify a usermode queue.
385 *
386 * MQD data can be of different size for different GPU IP/engine and
387 * their respective versions/revisions, so this points to a __u64 *
388 * which holds IP specific MQD of this usermode queue.
389 */
390 __u64 mqd;
391 /**
392 * @size: size of MQD data in bytes, it must match the MQD structure
393 * size of the respective engine/revision defined in UAPI for ex, for
394 * gfx11 workloads, size = sizeof(drm_amdgpu_userq_mqd_gfx11).
395 */
396 __u64 mqd_size;
397};
398
399/* The structure to carry output of userqueue ops */
400struct drm_amdgpu_userq_out {
401 /**
402 * For operation AMDGPU_USERQ_OP_CREATE: This field contains a unique
403 * queue ID to represent the newly created userqueue in the system, otherwise
404 * it should be ignored.
405 */
406 __u32 queue_id;
407 __u32 _pad;
408};
409
410union drm_amdgpu_userq {
411 struct drm_amdgpu_userq_in in;
412 struct drm_amdgpu_userq_out out;
413};
414
415/* GFX V11 IP specific MQD parameters */
416struct drm_amdgpu_userq_mqd_gfx11 {
417 /**
418 * @shadow_va: Virtual address of the GPU memory to hold the shadow buffer.
419 * Use AMDGPU_INFO_IOCTL to find the exact size of the object.
420 */
421 __u64 shadow_va;
422 /**
423 * @csa_va: Virtual address of the GPU memory to hold the CSA buffer.
424 * Use AMDGPU_INFO_IOCTL to find the exact size of the object.
425 */
426 __u64 csa_va;
427};
428
429/* GFX V11 SDMA IP specific MQD parameters */
430struct drm_amdgpu_userq_mqd_sdma_gfx11 {
431 /**
432 * @csa_va: Virtual address of the GPU memory to hold the CSA buffer.
433 * This must be a from a separate GPU object, and use AMDGPU_INFO IOCTL
434 * to get the size.
435 */
436 __u64 csa_va;
437};
438
439/* GFX V11 Compute IP specific MQD parameters */
440struct drm_amdgpu_userq_mqd_compute_gfx11 {
441 /**
442 * @eop_va: Virtual address of the GPU memory to hold the EOP buffer.
443 * This must be a from a separate GPU object, and use AMDGPU_INFO IOCTL
444 * to get the size.
445 */
446 __u64 eop_va;
447};
448
449/* userq signal/wait ioctl */
450struct drm_amdgpu_userq_signal {
451 /**
452 * @queue_id: Queue handle used by the userq fence creation function
453 * to retrieve the WPTR.
454 */
455 __u32 queue_id;
456 __u32 pad;
457 /**
458 * @syncobj_handles: The list of syncobj handles submitted by the user queue
459 * job to be signaled.
460 */
461 __u64 syncobj_handles;
462 /**
463 * @num_syncobj_handles: A count that represents the number of syncobj handles in
464 * @syncobj_handles.
465 */
466 __u64 num_syncobj_handles;
467 /**
468 * @bo_read_handles: The list of BO handles that the submitted user queue job
469 * is using for read only. This will update BO fences in the kernel.
470 */
471 __u64 bo_read_handles;
472 /**
473 * @bo_write_handles: The list of BO handles that the submitted user queue job
474 * is using for write only. This will update BO fences in the kernel.
475 */
476 __u64 bo_write_handles;
477 /**
478 * @num_bo_read_handles: A count that represents the number of read BO handles in
479 * @bo_read_handles.
480 */
481 __u32 num_bo_read_handles;
482 /**
483 * @num_bo_write_handles: A count that represents the number of write BO handles in
484 * @bo_write_handles.
485 */
486 __u32 num_bo_write_handles;
487
488};
489
490struct drm_amdgpu_userq_fence_info {
491 /**
492 * @va: A gpu address allocated for each queue which stores the
493 * read pointer (RPTR) value.
494 */
495 __u64 va;
496 /**
497 * @value: A 64 bit value represents the write pointer (WPTR) of the
498 * queue commands which compared with the RPTR value to signal the
499 * fences.
500 */
501 __u64 value;
502};
503
504struct drm_amdgpu_userq_wait {
505 /**
506 * @syncobj_handles: The list of syncobj handles submitted by the user queue
507 * job to get the va/value pairs.
508 */
509 __u64 syncobj_handles;
510 /**
511 * @syncobj_timeline_handles: The list of timeline syncobj handles submitted by
512 * the user queue job to get the va/value pairs at given @syncobj_timeline_points.
513 */
514 __u64 syncobj_timeline_handles;
515 /**
516 * @syncobj_timeline_points: The list of timeline syncobj points submitted by the
517 * user queue job for the corresponding @syncobj_timeline_handles.
518 */
519 __u64 syncobj_timeline_points;
520 /**
521 * @bo_read_handles: The list of read BO handles submitted by the user queue
522 * job to get the va/value pairs.
523 */
524 __u64 bo_read_handles;
525 /**
526 * @bo_write_handles: The list of write BO handles submitted by the user queue
527 * job to get the va/value pairs.
528 */
529 __u64 bo_write_handles;
530 /**
531 * @num_syncobj_timeline_handles: A count that represents the number of timeline
532 * syncobj handles in @syncobj_timeline_handles.
533 */
534 __u16 num_syncobj_timeline_handles;
535 /**
536 * @num_fences: This field can be used both as input and output. As input it defines
537 * the maximum number of fences that can be returned and as output it will specify
538 * how many fences were actually returned from the ioctl.
539 */
540 __u16 num_fences;
541 /**
542 * @num_syncobj_handles: A count that represents the number of syncobj handles in
543 * @syncobj_handles.
544 */
545 __u32 num_syncobj_handles;
546 /**
547 * @num_bo_read_handles: A count that represents the number of read BO handles in
548 * @bo_read_handles.
549 */
550 __u32 num_bo_read_handles;
551 /**
552 * @num_bo_write_handles: A count that represents the number of write BO handles in
553 * @bo_write_handles.
554 */
555 __u32 num_bo_write_handles;
556 /**
557 * @out_fences: The field is a return value from the ioctl containing the list of
558 * address/value pairs to wait for.
559 */
560 __u64 out_fences;
561};
562
563/* vm ioctl */
564#define AMDGPU_VM_OP_RESERVE_VMID 1
565#define AMDGPU_VM_OP_UNRESERVE_VMID 2
566
567struct drm_amdgpu_vm_in {
568 /** AMDGPU_VM_OP_* */
569 __u32 op;
570 __u32 flags;
571};
572
573struct drm_amdgpu_vm_out {
574 /** For future use, no flags defined so far */
575 __u64 flags;
576};
577
578union drm_amdgpu_vm {
579 struct drm_amdgpu_vm_in in;
580 struct drm_amdgpu_vm_out out;
581};
582
583/* sched ioctl */
584#define AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE 1
585#define AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE 2
586
587struct drm_amdgpu_sched_in {
588 /* AMDGPU_SCHED_OP_* */
589 __u32 op;
590 __u32 fd;
591 /** AMDGPU_CTX_PRIORITY_* */
592 __s32 priority;
593 __u32 ctx_id;
594};
595
596union drm_amdgpu_sched {
597 struct drm_amdgpu_sched_in in;
598};
599
600/*
601 * This is not a reliable API and you should expect it to fail for any
602 * number of reasons and have fallback path that do not use userptr to
603 * perform any operation.
604 */
605#define AMDGPU_GEM_USERPTR_READONLY (1 << 0)
606#define AMDGPU_GEM_USERPTR_ANONONLY (1 << 1)
607#define AMDGPU_GEM_USERPTR_VALIDATE (1 << 2)
608#define AMDGPU_GEM_USERPTR_REGISTER (1 << 3)
609
610struct drm_amdgpu_gem_userptr {
611 __u64 addr;
612 __u64 size;
613 /* AMDGPU_GEM_USERPTR_* */
614 __u32 flags;
615 /* Resulting GEM handle */
616 __u32 handle;
617};
618
619/* SI-CI-VI: */
620/* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */
621#define AMDGPU_TILING_ARRAY_MODE_SHIFT 0
622#define AMDGPU_TILING_ARRAY_MODE_MASK 0xf
623#define AMDGPU_TILING_PIPE_CONFIG_SHIFT 4
624#define AMDGPU_TILING_PIPE_CONFIG_MASK 0x1f
625#define AMDGPU_TILING_TILE_SPLIT_SHIFT 9
626#define AMDGPU_TILING_TILE_SPLIT_MASK 0x7
627#define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT 12
628#define AMDGPU_TILING_MICRO_TILE_MODE_MASK 0x7
629#define AMDGPU_TILING_BANK_WIDTH_SHIFT 15
630#define AMDGPU_TILING_BANK_WIDTH_MASK 0x3
631#define AMDGPU_TILING_BANK_HEIGHT_SHIFT 17
632#define AMDGPU_TILING_BANK_HEIGHT_MASK 0x3
633#define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT 19
634#define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK 0x3
635#define AMDGPU_TILING_NUM_BANKS_SHIFT 21
636#define AMDGPU_TILING_NUM_BANKS_MASK 0x3
637
638/* GFX9 - GFX11: */
639#define AMDGPU_TILING_SWIZZLE_MODE_SHIFT 0
640#define AMDGPU_TILING_SWIZZLE_MODE_MASK 0x1f
641#define AMDGPU_TILING_DCC_OFFSET_256B_SHIFT 5
642#define AMDGPU_TILING_DCC_OFFSET_256B_MASK 0xFFFFFF
643#define AMDGPU_TILING_DCC_PITCH_MAX_SHIFT 29
644#define AMDGPU_TILING_DCC_PITCH_MAX_MASK 0x3FFF
645#define AMDGPU_TILING_DCC_INDEPENDENT_64B_SHIFT 43
646#define AMDGPU_TILING_DCC_INDEPENDENT_64B_MASK 0x1
647#define AMDGPU_TILING_DCC_INDEPENDENT_128B_SHIFT 44
648#define AMDGPU_TILING_DCC_INDEPENDENT_128B_MASK 0x1
649#define AMDGPU_TILING_SCANOUT_SHIFT 63
650#define AMDGPU_TILING_SCANOUT_MASK 0x1
651
652/* GFX12 and later: */
653#define AMDGPU_TILING_GFX12_SWIZZLE_MODE_SHIFT 0
654#define AMDGPU_TILING_GFX12_SWIZZLE_MODE_MASK 0x7
655/* These are DCC recompression settings for memory management: */
656#define AMDGPU_TILING_GFX12_DCC_MAX_COMPRESSED_BLOCK_SHIFT 3
657#define AMDGPU_TILING_GFX12_DCC_MAX_COMPRESSED_BLOCK_MASK 0x3 /* 0:64B, 1:128B, 2:256B */
658#define AMDGPU_TILING_GFX12_DCC_NUMBER_TYPE_SHIFT 5
659#define AMDGPU_TILING_GFX12_DCC_NUMBER_TYPE_MASK 0x7 /* CB_COLOR0_INFO.NUMBER_TYPE */
660#define AMDGPU_TILING_GFX12_DCC_DATA_FORMAT_SHIFT 8
661#define AMDGPU_TILING_GFX12_DCC_DATA_FORMAT_MASK 0x3f /* [0:4]:CB_COLOR0_INFO.FORMAT, [5]:MM */
662/* When clearing the buffer or moving it from VRAM to GTT, don't compress and set DCC metadata
663 * to uncompressed. Set when parts of an allocation bypass DCC and read raw data. */
664#define AMDGPU_TILING_GFX12_DCC_WRITE_COMPRESS_DISABLE_SHIFT 14
665#define AMDGPU_TILING_GFX12_DCC_WRITE_COMPRESS_DISABLE_MASK 0x1
666/* bit gap */
667#define AMDGPU_TILING_GFX12_SCANOUT_SHIFT 63
668#define AMDGPU_TILING_GFX12_SCANOUT_MASK 0x1
669
670/* Set/Get helpers for tiling flags. */
671#define AMDGPU_TILING_SET(field, value) \
672 (((__u64)(value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT)
673#define AMDGPU_TILING_GET(value, field) \
674 (((__u64)(value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK)
675
676#define AMDGPU_GEM_METADATA_OP_SET_METADATA 1
677#define AMDGPU_GEM_METADATA_OP_GET_METADATA 2
678
679/** The same structure is shared for input/output */
680struct drm_amdgpu_gem_metadata {
681 /** GEM Object handle */
682 __u32 handle;
683 /** Do we want get or set metadata */
684 __u32 op;
685 struct {
686 /** For future use, no flags defined so far */
687 __u64 flags;
688 /** family specific tiling info */
689 __u64 tiling_info;
690 __u32 data_size_bytes;
691 __u32 data[64];
692 } data;
693};
694
695struct drm_amdgpu_gem_mmap_in {
696 /** the GEM object handle */
697 __u32 handle;
698 __u32 _pad;
699};
700
701struct drm_amdgpu_gem_mmap_out {
702 /** mmap offset from the vma offset manager */
703 __u64 addr_ptr;
704};
705
706union drm_amdgpu_gem_mmap {
707 struct drm_amdgpu_gem_mmap_in in;
708 struct drm_amdgpu_gem_mmap_out out;
709};
710
711struct drm_amdgpu_gem_wait_idle_in {
712 /** GEM object handle */
713 __u32 handle;
714 /** For future use, no flags defined so far */
715 __u32 flags;
716 /** Absolute timeout to wait */
717 __u64 timeout;
718};
719
720struct drm_amdgpu_gem_wait_idle_out {
721 /** BO status: 0 - BO is idle, 1 - BO is busy */
722 __u32 status;
723 /** Returned current memory domain */
724 __u32 domain;
725};
726
727union drm_amdgpu_gem_wait_idle {
728 struct drm_amdgpu_gem_wait_idle_in in;
729 struct drm_amdgpu_gem_wait_idle_out out;
730};
731
732struct drm_amdgpu_wait_cs_in {
733 /* Command submission handle
734 * handle equals 0 means none to wait for
735 * handle equals ~0ull means wait for the latest sequence number
736 */
737 __u64 handle;
738 /** Absolute timeout to wait */
739 __u64 timeout;
740 __u32 ip_type;
741 __u32 ip_instance;
742 __u32 ring;
743 __u32 ctx_id;
744};
745
746struct drm_amdgpu_wait_cs_out {
747 /** CS status: 0 - CS completed, 1 - CS still busy */
748 __u64 status;
749};
750
751union drm_amdgpu_wait_cs {
752 struct drm_amdgpu_wait_cs_in in;
753 struct drm_amdgpu_wait_cs_out out;
754};
755
756struct drm_amdgpu_fence {
757 __u32 ctx_id;
758 __u32 ip_type;
759 __u32 ip_instance;
760 __u32 ring;
761 __u64 seq_no;
762};
763
764struct drm_amdgpu_wait_fences_in {
765 /** This points to uint64_t * which points to fences */
766 __u64 fences;
767 __u32 fence_count;
768 __u32 wait_all;
769 __u64 timeout_ns;
770};
771
772struct drm_amdgpu_wait_fences_out {
773 __u32 status;
774 __u32 first_signaled;
775};
776
777union drm_amdgpu_wait_fences {
778 struct drm_amdgpu_wait_fences_in in;
779 struct drm_amdgpu_wait_fences_out out;
780};
781
782#define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0
783#define AMDGPU_GEM_OP_SET_PLACEMENT 1
784
785/* Sets or returns a value associated with a buffer. */
786struct drm_amdgpu_gem_op {
787 /** GEM object handle */
788 __u32 handle;
789 /** AMDGPU_GEM_OP_* */
790 __u32 op;
791 /** Input or return value */
792 __u64 value;
793};
794
795#define AMDGPU_VA_OP_MAP 1
796#define AMDGPU_VA_OP_UNMAP 2
797#define AMDGPU_VA_OP_CLEAR 3
798#define AMDGPU_VA_OP_REPLACE 4
799
800/* Delay the page table update till the next CS */
801#define AMDGPU_VM_DELAY_UPDATE (1 << 0)
802
803/* Mapping flags */
804/* readable mapping */
805#define AMDGPU_VM_PAGE_READABLE (1 << 1)
806/* writable mapping */
807#define AMDGPU_VM_PAGE_WRITEABLE (1 << 2)
808/* executable mapping, new for VI */
809#define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3)
810/* partially resident texture */
811#define AMDGPU_VM_PAGE_PRT (1 << 4)
812/* MTYPE flags use bit 5 to 8 */
813#define AMDGPU_VM_MTYPE_MASK (0xf << 5)
814/* Default MTYPE. Pre-AI must use this. Recommended for newer ASICs. */
815#define AMDGPU_VM_MTYPE_DEFAULT (0 << 5)
816/* Use Non Coherent MTYPE instead of default MTYPE */
817#define AMDGPU_VM_MTYPE_NC (1 << 5)
818/* Use Write Combine MTYPE instead of default MTYPE */
819#define AMDGPU_VM_MTYPE_WC (2 << 5)
820/* Use Cache Coherent MTYPE instead of default MTYPE */
821#define AMDGPU_VM_MTYPE_CC (3 << 5)
822/* Use UnCached MTYPE instead of default MTYPE */
823#define AMDGPU_VM_MTYPE_UC (4 << 5)
824/* Use Read Write MTYPE instead of default MTYPE */
825#define AMDGPU_VM_MTYPE_RW (5 << 5)
826/* don't allocate MALL */
827#define AMDGPU_VM_PAGE_NOALLOC (1 << 9)
828
829struct drm_amdgpu_gem_va {
830 /** GEM object handle */
831 __u32 handle;
832 __u32 _pad;
833 /** AMDGPU_VA_OP_* */
834 __u32 operation;
835 /** AMDGPU_VM_PAGE_* */
836 __u32 flags;
837 /** va address to assign . Must be correctly aligned.*/
838 __u64 va_address;
839 /** Specify offset inside of BO to assign. Must be correctly aligned.*/
840 __u64 offset_in_bo;
841 /** Specify mapping size. Must be correctly aligned. */
842 __u64 map_size;
843 /**
844 * vm_timeline_point is a sequence number used to add new timeline point.
845 */
846 __u64 vm_timeline_point;
847 /**
848 * The vm page table update fence is installed in given vm_timeline_syncobj_out
849 * at vm_timeline_point.
850 */
851 __u32 vm_timeline_syncobj_out;
852 /** the number of syncobj handles in @input_fence_syncobj_handles */
853 __u32 num_syncobj_handles;
854 /** Array of sync object handle to wait for given input fences */
855 __u64 input_fence_syncobj_handles;
856};
857
858#define AMDGPU_HW_IP_GFX 0
859#define AMDGPU_HW_IP_COMPUTE 1
860#define AMDGPU_HW_IP_DMA 2
861#define AMDGPU_HW_IP_UVD 3
862#define AMDGPU_HW_IP_VCE 4
863#define AMDGPU_HW_IP_UVD_ENC 5
864#define AMDGPU_HW_IP_VCN_DEC 6
865/*
866 * From VCN4, AMDGPU_HW_IP_VCN_ENC is re-used to support
867 * both encoding and decoding jobs.
868 */
869#define AMDGPU_HW_IP_VCN_ENC 7
870#define AMDGPU_HW_IP_VCN_JPEG 8
871#define AMDGPU_HW_IP_VPE 9
872#define AMDGPU_HW_IP_NUM 10
873
874#define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1
875
876#define AMDGPU_CHUNK_ID_IB 0x01
877#define AMDGPU_CHUNK_ID_FENCE 0x02
878#define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03
879#define AMDGPU_CHUNK_ID_SYNCOBJ_IN 0x04
880#define AMDGPU_CHUNK_ID_SYNCOBJ_OUT 0x05
881#define AMDGPU_CHUNK_ID_BO_HANDLES 0x06
882#define AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 0x07
883#define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT 0x08
884#define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL 0x09
885#define AMDGPU_CHUNK_ID_CP_GFX_SHADOW 0x0a
886
887struct drm_amdgpu_cs_chunk {
888 __u32 chunk_id;
889 __u32 length_dw;
890 __u64 chunk_data;
891};
892
893struct drm_amdgpu_cs_in {
894 /** Rendering context id */
895 __u32 ctx_id;
896 /** Handle of resource list associated with CS */
897 __u32 bo_list_handle;
898 __u32 num_chunks;
899 __u32 flags;
900 /** this points to __u64 * which point to cs chunks */
901 __u64 chunks;
902};
903
904struct drm_amdgpu_cs_out {
905 __u64 handle;
906};
907
908union drm_amdgpu_cs {
909 struct drm_amdgpu_cs_in in;
910 struct drm_amdgpu_cs_out out;
911};
912
913/* Specify flags to be used for IB */
914
915/* This IB should be submitted to CE */
916#define AMDGPU_IB_FLAG_CE (1<<0)
917
918/* Preamble flag, which means the IB could be dropped if no context switch */
919#define AMDGPU_IB_FLAG_PREAMBLE (1<<1)
920
921/* Preempt flag, IB should set Pre_enb bit if PREEMPT flag detected */
922#define AMDGPU_IB_FLAG_PREEMPT (1<<2)
923
924/* The IB fence should do the L2 writeback but not invalidate any shader
925 * caches (L2/vL1/sL1/I$). */
926#define AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE (1 << 3)
927
928/* Set GDS_COMPUTE_MAX_WAVE_ID = DEFAULT before PACKET3_INDIRECT_BUFFER.
929 * This will reset wave ID counters for the IB.
930 */
931#define AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID (1 << 4)
932
933/* Flag the IB as secure (TMZ)
934 */
935#define AMDGPU_IB_FLAGS_SECURE (1 << 5)
936
937/* Tell KMD to flush and invalidate caches
938 */
939#define AMDGPU_IB_FLAG_EMIT_MEM_SYNC (1 << 6)
940
941struct drm_amdgpu_cs_chunk_ib {
942 __u32 _pad;
943 /** AMDGPU_IB_FLAG_* */
944 __u32 flags;
945 /** Virtual address to begin IB execution */
946 __u64 va_start;
947 /** Size of submission */
948 __u32 ib_bytes;
949 /** HW IP to submit to */
950 __u32 ip_type;
951 /** HW IP index of the same type to submit to */
952 __u32 ip_instance;
953 /** Ring index to submit to */
954 __u32 ring;
955};
956
957struct drm_amdgpu_cs_chunk_dep {
958 __u32 ip_type;
959 __u32 ip_instance;
960 __u32 ring;
961 __u32 ctx_id;
962 __u64 handle;
963};
964
965struct drm_amdgpu_cs_chunk_fence {
966 __u32 handle;
967 __u32 offset;
968};
969
970struct drm_amdgpu_cs_chunk_sem {
971 __u32 handle;
972};
973
974struct drm_amdgpu_cs_chunk_syncobj {
975 __u32 handle;
976 __u32 flags;
977 __u64 point;
978};
979
980#define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ 0
981#define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD 1
982#define AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD 2
983
984union drm_amdgpu_fence_to_handle {
985 struct {
986 struct drm_amdgpu_fence fence;
987 __u32 what;
988 __u32 pad;
989 } in;
990 struct {
991 __u32 handle;
992 } out;
993};
994
995struct drm_amdgpu_cs_chunk_data {
996 union {
997 struct drm_amdgpu_cs_chunk_ib ib_data;
998 struct drm_amdgpu_cs_chunk_fence fence_data;
999 };
1000};
1001
1002#define AMDGPU_CS_CHUNK_CP_GFX_SHADOW_FLAGS_INIT_SHADOW 0x1
1003
1004struct drm_amdgpu_cs_chunk_cp_gfx_shadow {
1005 __u64 shadow_va;
1006 __u64 csa_va;
1007 __u64 gds_va;
1008 __u64 flags;
1009};
1010
1011/*
1012 * Query h/w info: Flag that this is integrated (a.h.a. fusion) GPU
1013 *
1014 */
1015#define AMDGPU_IDS_FLAGS_FUSION 0x1
1016#define AMDGPU_IDS_FLAGS_PREEMPTION 0x2
1017#define AMDGPU_IDS_FLAGS_TMZ 0x4
1018#define AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD 0x8
1019
1020/*
1021 * Query h/w info: Flag identifying VF/PF/PT mode
1022 *
1023 */
1024#define AMDGPU_IDS_FLAGS_MODE_MASK 0x300
1025#define AMDGPU_IDS_FLAGS_MODE_SHIFT 0x8
1026#define AMDGPU_IDS_FLAGS_MODE_PF 0x0
1027#define AMDGPU_IDS_FLAGS_MODE_VF 0x1
1028#define AMDGPU_IDS_FLAGS_MODE_PT 0x2
1029
1030/* indicate if acceleration can be working */
1031#define AMDGPU_INFO_ACCEL_WORKING 0x00
1032/* get the crtc_id from the mode object id? */
1033#define AMDGPU_INFO_CRTC_FROM_ID 0x01
1034/* query hw IP info */
1035#define AMDGPU_INFO_HW_IP_INFO 0x02
1036/* query hw IP instance count for the specified type */
1037#define AMDGPU_INFO_HW_IP_COUNT 0x03
1038/* timestamp for GL_ARB_timer_query */
1039#define AMDGPU_INFO_TIMESTAMP 0x05
1040/* Query the firmware version */
1041#define AMDGPU_INFO_FW_VERSION 0x0e
1042 /* Subquery id: Query VCE firmware version */
1043 #define AMDGPU_INFO_FW_VCE 0x1
1044 /* Subquery id: Query UVD firmware version */
1045 #define AMDGPU_INFO_FW_UVD 0x2
1046 /* Subquery id: Query GMC firmware version */
1047 #define AMDGPU_INFO_FW_GMC 0x03
1048 /* Subquery id: Query GFX ME firmware version */
1049 #define AMDGPU_INFO_FW_GFX_ME 0x04
1050 /* Subquery id: Query GFX PFP firmware version */
1051 #define AMDGPU_INFO_FW_GFX_PFP 0x05
1052 /* Subquery id: Query GFX CE firmware version */
1053 #define AMDGPU_INFO_FW_GFX_CE 0x06
1054 /* Subquery id: Query GFX RLC firmware version */
1055 #define AMDGPU_INFO_FW_GFX_RLC 0x07
1056 /* Subquery id: Query GFX MEC firmware version */
1057 #define AMDGPU_INFO_FW_GFX_MEC 0x08
1058 /* Subquery id: Query SMC firmware version */
1059 #define AMDGPU_INFO_FW_SMC 0x0a
1060 /* Subquery id: Query SDMA firmware version */
1061 #define AMDGPU_INFO_FW_SDMA 0x0b
1062 /* Subquery id: Query PSP SOS firmware version */
1063 #define AMDGPU_INFO_FW_SOS 0x0c
1064 /* Subquery id: Query PSP ASD firmware version */
1065 #define AMDGPU_INFO_FW_ASD 0x0d
1066 /* Subquery id: Query VCN firmware version */
1067 #define AMDGPU_INFO_FW_VCN 0x0e
1068 /* Subquery id: Query GFX RLC SRLC firmware version */
1069 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL 0x0f
1070 /* Subquery id: Query GFX RLC SRLG firmware version */
1071 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM 0x10
1072 /* Subquery id: Query GFX RLC SRLS firmware version */
1073 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM 0x11
1074 /* Subquery id: Query DMCU firmware version */
1075 #define AMDGPU_INFO_FW_DMCU 0x12
1076 #define AMDGPU_INFO_FW_TA 0x13
1077 /* Subquery id: Query DMCUB firmware version */
1078 #define AMDGPU_INFO_FW_DMCUB 0x14
1079 /* Subquery id: Query TOC firmware version */
1080 #define AMDGPU_INFO_FW_TOC 0x15
1081 /* Subquery id: Query CAP firmware version */
1082 #define AMDGPU_INFO_FW_CAP 0x16
1083 /* Subquery id: Query GFX RLCP firmware version */
1084 #define AMDGPU_INFO_FW_GFX_RLCP 0x17
1085 /* Subquery id: Query GFX RLCV firmware version */
1086 #define AMDGPU_INFO_FW_GFX_RLCV 0x18
1087 /* Subquery id: Query MES_KIQ firmware version */
1088 #define AMDGPU_INFO_FW_MES_KIQ 0x19
1089 /* Subquery id: Query MES firmware version */
1090 #define AMDGPU_INFO_FW_MES 0x1a
1091 /* Subquery id: Query IMU firmware version */
1092 #define AMDGPU_INFO_FW_IMU 0x1b
1093 /* Subquery id: Query VPE firmware version */
1094 #define AMDGPU_INFO_FW_VPE 0x1c
1095
1096/* number of bytes moved for TTM migration */
1097#define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f
1098/* the used VRAM size */
1099#define AMDGPU_INFO_VRAM_USAGE 0x10
1100/* the used GTT size */
1101#define AMDGPU_INFO_GTT_USAGE 0x11
1102/* Information about GDS, etc. resource configuration */
1103#define AMDGPU_INFO_GDS_CONFIG 0x13
1104/* Query information about VRAM and GTT domains */
1105#define AMDGPU_INFO_VRAM_GTT 0x14
1106/* Query information about register in MMR address space*/
1107#define AMDGPU_INFO_READ_MMR_REG 0x15
1108/* Query information about device: rev id, family, etc. */
1109#define AMDGPU_INFO_DEV_INFO 0x16
1110/* visible vram usage */
1111#define AMDGPU_INFO_VIS_VRAM_USAGE 0x17
1112/* number of TTM buffer evictions */
1113#define AMDGPU_INFO_NUM_EVICTIONS 0x18
1114/* Query memory about VRAM and GTT domains */
1115#define AMDGPU_INFO_MEMORY 0x19
1116/* Query vce clock table */
1117#define AMDGPU_INFO_VCE_CLOCK_TABLE 0x1A
1118/* Query vbios related information */
1119#define AMDGPU_INFO_VBIOS 0x1B
1120 /* Subquery id: Query vbios size */
1121 #define AMDGPU_INFO_VBIOS_SIZE 0x1
1122 /* Subquery id: Query vbios image */
1123 #define AMDGPU_INFO_VBIOS_IMAGE 0x2
1124 /* Subquery id: Query vbios info */
1125 #define AMDGPU_INFO_VBIOS_INFO 0x3
1126/* Query UVD handles */
1127#define AMDGPU_INFO_NUM_HANDLES 0x1C
1128/* Query sensor related information */
1129#define AMDGPU_INFO_SENSOR 0x1D
1130 /* Subquery id: Query GPU shader clock */
1131 #define AMDGPU_INFO_SENSOR_GFX_SCLK 0x1
1132 /* Subquery id: Query GPU memory clock */
1133 #define AMDGPU_INFO_SENSOR_GFX_MCLK 0x2
1134 /* Subquery id: Query GPU temperature */
1135 #define AMDGPU_INFO_SENSOR_GPU_TEMP 0x3
1136 /* Subquery id: Query GPU load */
1137 #define AMDGPU_INFO_SENSOR_GPU_LOAD 0x4
1138 /* Subquery id: Query average GPU power */
1139 #define AMDGPU_INFO_SENSOR_GPU_AVG_POWER 0x5
1140 /* Subquery id: Query northbridge voltage */
1141 #define AMDGPU_INFO_SENSOR_VDDNB 0x6
1142 /* Subquery id: Query graphics voltage */
1143 #define AMDGPU_INFO_SENSOR_VDDGFX 0x7
1144 /* Subquery id: Query GPU stable pstate shader clock */
1145 #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK 0x8
1146 /* Subquery id: Query GPU stable pstate memory clock */
1147 #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK 0x9
1148 /* Subquery id: Query GPU peak pstate shader clock */
1149 #define AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_SCLK 0xa
1150 /* Subquery id: Query GPU peak pstate memory clock */
1151 #define AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_MCLK 0xb
1152 /* Subquery id: Query input GPU power */
1153 #define AMDGPU_INFO_SENSOR_GPU_INPUT_POWER 0xc
1154/* Number of VRAM page faults on CPU access. */
1155#define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E
1156#define AMDGPU_INFO_VRAM_LOST_COUNTER 0x1F
1157/* query ras mask of enabled features*/
1158#define AMDGPU_INFO_RAS_ENABLED_FEATURES 0x20
1159/* RAS MASK: UMC (VRAM) */
1160#define AMDGPU_INFO_RAS_ENABLED_UMC (1 << 0)
1161/* RAS MASK: SDMA */
1162#define AMDGPU_INFO_RAS_ENABLED_SDMA (1 << 1)
1163/* RAS MASK: GFX */
1164#define AMDGPU_INFO_RAS_ENABLED_GFX (1 << 2)
1165/* RAS MASK: MMHUB */
1166#define AMDGPU_INFO_RAS_ENABLED_MMHUB (1 << 3)
1167/* RAS MASK: ATHUB */
1168#define AMDGPU_INFO_RAS_ENABLED_ATHUB (1 << 4)
1169/* RAS MASK: PCIE */
1170#define AMDGPU_INFO_RAS_ENABLED_PCIE (1 << 5)
1171/* RAS MASK: HDP */
1172#define AMDGPU_INFO_RAS_ENABLED_HDP (1 << 6)
1173/* RAS MASK: XGMI */
1174#define AMDGPU_INFO_RAS_ENABLED_XGMI (1 << 7)
1175/* RAS MASK: DF */
1176#define AMDGPU_INFO_RAS_ENABLED_DF (1 << 8)
1177/* RAS MASK: SMN */
1178#define AMDGPU_INFO_RAS_ENABLED_SMN (1 << 9)
1179/* RAS MASK: SEM */
1180#define AMDGPU_INFO_RAS_ENABLED_SEM (1 << 10)
1181/* RAS MASK: MP0 */
1182#define AMDGPU_INFO_RAS_ENABLED_MP0 (1 << 11)
1183/* RAS MASK: MP1 */
1184#define AMDGPU_INFO_RAS_ENABLED_MP1 (1 << 12)
1185/* RAS MASK: FUSE */
1186#define AMDGPU_INFO_RAS_ENABLED_FUSE (1 << 13)
1187/* query video encode/decode caps */
1188#define AMDGPU_INFO_VIDEO_CAPS 0x21
1189 /* Subquery id: Decode */
1190 #define AMDGPU_INFO_VIDEO_CAPS_DECODE 0
1191 /* Subquery id: Encode */
1192 #define AMDGPU_INFO_VIDEO_CAPS_ENCODE 1
1193/* Query the max number of IBs per gang per submission */
1194#define AMDGPU_INFO_MAX_IBS 0x22
1195/* query last page fault info */
1196#define AMDGPU_INFO_GPUVM_FAULT 0x23
1197/* query FW object size and alignment */
1198#define AMDGPU_INFO_UQ_FW_AREAS 0x24
1199
1200#define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0
1201#define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff
1202#define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8
1203#define AMDGPU_INFO_MMR_SH_INDEX_MASK 0xff
1204
1205struct drm_amdgpu_query_fw {
1206 /** AMDGPU_INFO_FW_* */
1207 __u32 fw_type;
1208 /**
1209 * Index of the IP if there are more IPs of
1210 * the same type.
1211 */
1212 __u32 ip_instance;
1213 /**
1214 * Index of the engine. Whether this is used depends
1215 * on the firmware type. (e.g. MEC, SDMA)
1216 */
1217 __u32 index;
1218 __u32 _pad;
1219};
1220
1221/* Input structure for the INFO ioctl */
1222struct drm_amdgpu_info {
1223 /* Where the return value will be stored */
1224 __u64 return_pointer;
1225 /* The size of the return value. Just like "size" in "snprintf",
1226 * it limits how many bytes the kernel can write. */
1227 __u32 return_size;
1228 /* The query request id. */
1229 __u32 query;
1230
1231 union {
1232 struct {
1233 __u32 id;
1234 __u32 _pad;
1235 } mode_crtc;
1236
1237 struct {
1238 /** AMDGPU_HW_IP_* */
1239 __u32 type;
1240 /**
1241 * Index of the IP if there are more IPs of the same
1242 * type. Ignored by AMDGPU_INFO_HW_IP_COUNT.
1243 */
1244 __u32 ip_instance;
1245 } query_hw_ip;
1246
1247 struct {
1248 __u32 dword_offset;
1249 /** number of registers to read */
1250 __u32 count;
1251 __u32 instance;
1252 /** For future use, no flags defined so far */
1253 __u32 flags;
1254 } read_mmr_reg;
1255
1256 struct drm_amdgpu_query_fw query_fw;
1257
1258 struct {
1259 __u32 type;
1260 __u32 offset;
1261 } vbios_info;
1262
1263 struct {
1264 __u32 type;
1265 } sensor_info;
1266
1267 struct {
1268 __u32 type;
1269 } video_cap;
1270 };
1271};
1272
1273struct drm_amdgpu_info_gds {
1274 /** GDS GFX partition size */
1275 __u32 gds_gfx_partition_size;
1276 /** GDS compute partition size */
1277 __u32 compute_partition_size;
1278 /** total GDS memory size */
1279 __u32 gds_total_size;
1280 /** GWS size per GFX partition */
1281 __u32 gws_per_gfx_partition;
1282 /** GSW size per compute partition */
1283 __u32 gws_per_compute_partition;
1284 /** OA size per GFX partition */
1285 __u32 oa_per_gfx_partition;
1286 /** OA size per compute partition */
1287 __u32 oa_per_compute_partition;
1288 __u32 _pad;
1289};
1290
1291struct drm_amdgpu_info_vram_gtt {
1292 __u64 vram_size;
1293 __u64 vram_cpu_accessible_size;
1294 __u64 gtt_size;
1295};
1296
1297struct drm_amdgpu_heap_info {
1298 /** max. physical memory */
1299 __u64 total_heap_size;
1300
1301 /** Theoretical max. available memory in the given heap */
1302 __u64 usable_heap_size;
1303
1304 /**
1305 * Number of bytes allocated in the heap. This includes all processes
1306 * and private allocations in the kernel. It changes when new buffers
1307 * are allocated, freed, and moved. It cannot be larger than
1308 * heap_size.
1309 */
1310 __u64 heap_usage;
1311
1312 /**
1313 * Theoretical possible max. size of buffer which
1314 * could be allocated in the given heap
1315 */
1316 __u64 max_allocation;
1317};
1318
1319struct drm_amdgpu_memory_info {
1320 struct drm_amdgpu_heap_info vram;
1321 struct drm_amdgpu_heap_info cpu_accessible_vram;
1322 struct drm_amdgpu_heap_info gtt;
1323};
1324
1325struct drm_amdgpu_info_firmware {
1326 __u32 ver;
1327 __u32 feature;
1328};
1329
1330struct drm_amdgpu_info_vbios {
1331 __u8 name[64];
1332 __u8 vbios_pn[64];
1333 __u32 version;
1334 __u32 pad;
1335 __u8 vbios_ver_str[32];
1336 __u8 date[32];
1337};
1338
1339#define AMDGPU_VRAM_TYPE_UNKNOWN 0
1340#define AMDGPU_VRAM_TYPE_GDDR1 1
1341#define AMDGPU_VRAM_TYPE_DDR2 2
1342#define AMDGPU_VRAM_TYPE_GDDR3 3
1343#define AMDGPU_VRAM_TYPE_GDDR4 4
1344#define AMDGPU_VRAM_TYPE_GDDR5 5
1345#define AMDGPU_VRAM_TYPE_HBM 6
1346#define AMDGPU_VRAM_TYPE_DDR3 7
1347#define AMDGPU_VRAM_TYPE_DDR4 8
1348#define AMDGPU_VRAM_TYPE_GDDR6 9
1349#define AMDGPU_VRAM_TYPE_DDR5 10
1350#define AMDGPU_VRAM_TYPE_LPDDR4 11
1351#define AMDGPU_VRAM_TYPE_LPDDR5 12
1352
1353struct drm_amdgpu_info_device {
1354 /** PCI Device ID */
1355 __u32 device_id;
1356 /** Internal chip revision: A0, A1, etc.) */
1357 __u32 chip_rev;
1358 __u32 external_rev;
1359 /** Revision id in PCI Config space */
1360 __u32 pci_rev;
1361 __u32 family;
1362 __u32 num_shader_engines;
1363 __u32 num_shader_arrays_per_engine;
1364 /* in KHz */
1365 __u32 gpu_counter_freq;
1366 __u64 max_engine_clock;
1367 __u64 max_memory_clock;
1368 /* cu information */
1369 __u32 cu_active_number;
1370 /* NOTE: cu_ao_mask is INVALID, DON'T use it */
1371 __u32 cu_ao_mask;
1372 __u32 cu_bitmap[4][4];
1373 /** Render backend pipe mask. One render backend is CB+DB. */
1374 __u32 enabled_rb_pipes_mask;
1375 __u32 num_rb_pipes;
1376 __u32 num_hw_gfx_contexts;
1377 /* PCIe version (the smaller of the GPU and the CPU/motherboard) */
1378 __u32 pcie_gen;
1379 __u64 ids_flags;
1380 /** Starting virtual address for UMDs. */
1381 __u64 virtual_address_offset;
1382 /** The maximum virtual address */
1383 __u64 virtual_address_max;
1384 /** Required alignment of virtual addresses. */
1385 __u32 virtual_address_alignment;
1386 /** Page table entry - fragment size */
1387 __u32 pte_fragment_size;
1388 __u32 gart_page_size;
1389 /** constant engine ram size*/
1390 __u32 ce_ram_size;
1391 /** video memory type info*/
1392 __u32 vram_type;
1393 /** video memory bit width*/
1394 __u32 vram_bit_width;
1395 /* vce harvesting instance */
1396 __u32 vce_harvest_config;
1397 /* gfx double offchip LDS buffers */
1398 __u32 gc_double_offchip_lds_buf;
1399 /* NGG Primitive Buffer */
1400 __u64 prim_buf_gpu_addr;
1401 /* NGG Position Buffer */
1402 __u64 pos_buf_gpu_addr;
1403 /* NGG Control Sideband */
1404 __u64 cntl_sb_buf_gpu_addr;
1405 /* NGG Parameter Cache */
1406 __u64 param_buf_gpu_addr;
1407 __u32 prim_buf_size;
1408 __u32 pos_buf_size;
1409 __u32 cntl_sb_buf_size;
1410 __u32 param_buf_size;
1411 /* wavefront size*/
1412 __u32 wave_front_size;
1413 /* shader visible vgprs*/
1414 __u32 num_shader_visible_vgprs;
1415 /* CU per shader array*/
1416 __u32 num_cu_per_sh;
1417 /* number of tcc blocks*/
1418 __u32 num_tcc_blocks;
1419 /* gs vgt table depth*/
1420 __u32 gs_vgt_table_depth;
1421 /* gs primitive buffer depth*/
1422 __u32 gs_prim_buffer_depth;
1423 /* max gs wavefront per vgt*/
1424 __u32 max_gs_waves_per_vgt;
1425 /* PCIe number of lanes (the smaller of the GPU and the CPU/motherboard) */
1426 __u32 pcie_num_lanes;
1427 /* always on cu bitmap */
1428 __u32 cu_ao_bitmap[4][4];
1429 /** Starting high virtual address for UMDs. */
1430 __u64 high_va_offset;
1431 /** The maximum high virtual address */
1432 __u64 high_va_max;
1433 /* gfx10 pa_sc_tile_steering_override */
1434 __u32 pa_sc_tile_steering_override;
1435 /* disabled TCCs */
1436 __u64 tcc_disabled_mask;
1437 __u64 min_engine_clock;
1438 __u64 min_memory_clock;
1439 /* The following fields are only set on gfx11+, older chips set 0. */
1440 __u32 tcp_cache_size; /* AKA GL0, VMEM cache */
1441 __u32 num_sqc_per_wgp;
1442 __u32 sqc_data_cache_size; /* AKA SMEM cache */
1443 __u32 sqc_inst_cache_size;
1444 __u32 gl1c_cache_size;
1445 __u32 gl2c_cache_size;
1446 __u64 mall_size; /* AKA infinity cache */
1447 /* high 32 bits of the rb pipes mask */
1448 __u32 enabled_rb_pipes_mask_hi;
1449 /* shadow area size for gfx11 */
1450 __u32 shadow_size;
1451 /* shadow area base virtual alignment for gfx11 */
1452 __u32 shadow_alignment;
1453 /* context save area size for gfx11 */
1454 __u32 csa_size;
1455 /* context save area base virtual alignment for gfx11 */
1456 __u32 csa_alignment;
1457};
1458
1459struct drm_amdgpu_info_hw_ip {
1460 /** Version of h/w IP */
1461 __u32 hw_ip_version_major;
1462 __u32 hw_ip_version_minor;
1463 /** Capabilities */
1464 __u64 capabilities_flags;
1465 /** command buffer address start alignment*/
1466 __u32 ib_start_alignment;
1467 /** command buffer size alignment*/
1468 __u32 ib_size_alignment;
1469 /** Bitmask of available rings. Bit 0 means ring 0, etc. */
1470 __u32 available_rings;
1471 /** version info: bits 23:16 major, 15:8 minor, 7:0 revision */
1472 __u32 ip_discovery_version;
1473};
1474
1475/* GFX metadata BO sizes and alignment info (in bytes) */
1476struct drm_amdgpu_info_uq_fw_areas_gfx {
1477 /* shadow area size */
1478 __u32 shadow_size;
1479 /* shadow area base virtual mem alignment */
1480 __u32 shadow_alignment;
1481 /* context save area size */
1482 __u32 csa_size;
1483 /* context save area base virtual mem alignment */
1484 __u32 csa_alignment;
1485};
1486
1487/* IP specific metadata related information used in the
1488 * subquery AMDGPU_INFO_UQ_FW_AREAS
1489 */
1490struct drm_amdgpu_info_uq_fw_areas {
1491 union {
1492 struct drm_amdgpu_info_uq_fw_areas_gfx gfx;
1493 };
1494};
1495
1496struct drm_amdgpu_info_num_handles {
1497 /** Max handles as supported by firmware for UVD */
1498 __u32 uvd_max_handles;
1499 /** Handles currently in use for UVD */
1500 __u32 uvd_used_handles;
1501};
1502
1503#define AMDGPU_VCE_CLOCK_TABLE_ENTRIES 6
1504
1505struct drm_amdgpu_info_vce_clock_table_entry {
1506 /** System clock */
1507 __u32 sclk;
1508 /** Memory clock */
1509 __u32 mclk;
1510 /** VCE clock */
1511 __u32 eclk;
1512 __u32 pad;
1513};
1514
1515struct drm_amdgpu_info_vce_clock_table {
1516 struct drm_amdgpu_info_vce_clock_table_entry entries[AMDGPU_VCE_CLOCK_TABLE_ENTRIES];
1517 __u32 num_valid_entries;
1518 __u32 pad;
1519};
1520
1521/* query video encode/decode caps */
1522#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2 0
1523#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4 1
1524#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1 2
1525#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC 3
1526#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC 4
1527#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG 5
1528#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9 6
1529#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1 7
1530#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_COUNT 8
1531
1532struct drm_amdgpu_info_video_codec_info {
1533 __u32 valid;
1534 __u32 max_width;
1535 __u32 max_height;
1536 __u32 max_pixels_per_frame;
1537 __u32 max_level;
1538 __u32 pad;
1539};
1540
1541struct drm_amdgpu_info_video_caps {
1542 struct drm_amdgpu_info_video_codec_info codec_info[AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_COUNT];
1543};
1544
1545#define AMDGPU_VMHUB_TYPE_MASK 0xff
1546#define AMDGPU_VMHUB_TYPE_SHIFT 0
1547#define AMDGPU_VMHUB_TYPE_GFX 0
1548#define AMDGPU_VMHUB_TYPE_MM0 1
1549#define AMDGPU_VMHUB_TYPE_MM1 2
1550#define AMDGPU_VMHUB_IDX_MASK 0xff00
1551#define AMDGPU_VMHUB_IDX_SHIFT 8
1552
1553struct drm_amdgpu_info_gpuvm_fault {
1554 __u64 addr;
1555 __u32 status;
1556 __u32 vmhub;
1557};
1558
1559/*
1560 * Supported GPU families
1561 */
1562#define AMDGPU_FAMILY_UNKNOWN 0
1563#define AMDGPU_FAMILY_SI 110 /* Hainan, Oland, Verde, Pitcairn, Tahiti */
1564#define AMDGPU_FAMILY_CI 120 /* Bonaire, Hawaii */
1565#define AMDGPU_FAMILY_KV 125 /* Kaveri, Kabini, Mullins */
1566#define AMDGPU_FAMILY_VI 130 /* Iceland, Tonga */
1567#define AMDGPU_FAMILY_CZ 135 /* Carrizo, Stoney */
1568#define AMDGPU_FAMILY_AI 141 /* Vega10 */
1569#define AMDGPU_FAMILY_RV 142 /* Raven */
1570#define AMDGPU_FAMILY_NV 143 /* Navi10 */
1571#define AMDGPU_FAMILY_VGH 144 /* Van Gogh */
1572#define AMDGPU_FAMILY_GC_11_0_0 145 /* GC 11.0.0 */
1573#define AMDGPU_FAMILY_YC 146 /* Yellow Carp */
1574#define AMDGPU_FAMILY_GC_11_0_1 148 /* GC 11.0.1 */
1575#define AMDGPU_FAMILY_GC_10_3_6 149 /* GC 10.3.6 */
1576#define AMDGPU_FAMILY_GC_10_3_7 151 /* GC 10.3.7 */
1577#define AMDGPU_FAMILY_GC_11_5_0 150 /* GC 11.5.0 */
1578#define AMDGPU_FAMILY_GC_12_0_0 152 /* GC 12.0.0 */
1579
1580#if defined(__cplusplus)
1581}
1582#endif
1583
1584#endif