Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/* SPDX-License-Identifier: MIT */
2/* Copyright © 2026 Intel Corporation */
3
4#ifndef _INTEL_PCODE_REGS_H_
5#define _INTEL_PCODE_REGS_H_
6
7#define GEN6_PCODE_MAILBOX _MMIO(0x138124)
8#define GEN6_PCODE_READY (1 << 31)
9#define GEN6_PCODE_MB_PARAM2 REG_GENMASK(23, 16)
10#define GEN6_PCODE_MB_PARAM1 REG_GENMASK(15, 8)
11#define GEN6_PCODE_MB_COMMAND REG_GENMASK(7, 0)
12#define GEN6_PCODE_ERROR_MASK 0xFF
13#define GEN6_PCODE_SUCCESS 0x0
14#define GEN6_PCODE_ILLEGAL_CMD 0x1
15#define GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x2
16#define GEN6_PCODE_TIMEOUT 0x3
17#define GEN6_PCODE_UNIMPLEMENTED_CMD 0xFF
18#define GEN7_PCODE_TIMEOUT 0x2
19#define GEN7_PCODE_ILLEGAL_DATA 0x3
20#define GEN11_PCODE_ILLEGAL_SUBCOMMAND 0x4
21#define GEN11_PCODE_LOCKED 0x6
22#define GEN11_PCODE_REJECTED 0x11
23#define GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10
24#define GEN6_PCODE_WRITE_RC6VIDS 0x4
25#define GEN6_PCODE_READ_RC6VIDS 0x5
26#define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5)
27#define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245)
28#define BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ 0x18
29#define GEN9_PCODE_READ_MEM_LATENCY 0x6
30#define GEN9_MEM_LATENCY_LEVEL_3_7_MASK REG_GENMASK(31, 24)
31#define GEN9_MEM_LATENCY_LEVEL_2_6_MASK REG_GENMASK(23, 16)
32#define GEN9_MEM_LATENCY_LEVEL_1_5_MASK REG_GENMASK(15, 8)
33#define GEN9_MEM_LATENCY_LEVEL_0_4_MASK REG_GENMASK(7, 0)
34#define SKL_PCODE_LOAD_HDCP_KEYS 0x5
35#define SKL_PCODE_CDCLK_CONTROL 0x7
36#define SKL_CDCLK_PREPARE_FOR_CHANGE 0x3
37#define SKL_CDCLK_READY_FOR_CHANGE 0x1
38#define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8
39#define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9
40#define GEN6_READ_OC_PARAMS 0xc
41#define ICL_PCODE_MEM_SUBSYSYSTEM_INFO 0xd
42#define ICL_PCODE_MEM_SS_READ_GLOBAL_INFO (0x0 << 8)
43#define ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point) (((point) << 16) | (0x1 << 8))
44#define ADL_PCODE_MEM_SS_READ_PSF_GV_INFO ((0) | (0x2 << 8))
45#define DISPLAY_TO_PCODE_CDCLK_MAX 0x28D
46#define DISPLAY_TO_PCODE_VOLTAGE_MASK REG_GENMASK(1, 0)
47#define DISPLAY_TO_PCODE_VOLTAGE_MAX DISPLAY_TO_PCODE_VOLTAGE_MASK
48#define DISPLAY_TO_PCODE_CDCLK_VALID REG_BIT(27)
49#define DISPLAY_TO_PCODE_PIPE_COUNT_VALID REG_BIT(31)
50#define DISPLAY_TO_PCODE_CDCLK_MASK REG_GENMASK(25, 16)
51#define DISPLAY_TO_PCODE_PIPE_COUNT_MASK REG_GENMASK(30, 28)
52#define DISPLAY_TO_PCODE_CDCLK(x) REG_FIELD_PREP(DISPLAY_TO_PCODE_CDCLK_MASK, (x))
53#define DISPLAY_TO_PCODE_PIPE_COUNT(x) REG_FIELD_PREP(DISPLAY_TO_PCODE_PIPE_COUNT_MASK, (x))
54#define DISPLAY_TO_PCODE_VOLTAGE(x) REG_FIELD_PREP(DISPLAY_TO_PCODE_VOLTAGE_MASK, (x))
55#define DISPLAY_TO_PCODE_UPDATE_MASK(cdclk, num_pipes, voltage_level) \
56 ((DISPLAY_TO_PCODE_CDCLK(cdclk)) | \
57 (DISPLAY_TO_PCODE_PIPE_COUNT(num_pipes)) | \
58 (DISPLAY_TO_PCODE_VOLTAGE(voltage_level)))
59#define ICL_PCODE_SAGV_DE_MEM_SS_CONFIG 0xe
60#define ICL_PCODE_REP_QGV_MASK REG_GENMASK(1, 0)
61#define ICL_PCODE_REP_QGV_SAFE REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 0)
62#define ICL_PCODE_REP_QGV_POLL REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 1)
63#define ICL_PCODE_REP_QGV_REJECTED REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 2)
64#define ADLS_PCODE_REP_PSF_MASK REG_GENMASK(3, 2)
65#define ADLS_PCODE_REP_PSF_SAFE REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 0)
66#define ADLS_PCODE_REP_PSF_POLL REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 1)
67#define ADLS_PCODE_REP_PSF_REJECTED REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 2)
68#define ICL_PCODE_REQ_QGV_PT_MASK REG_GENMASK(7, 0)
69#define ICL_PCODE_REQ_QGV_PT(x) REG_FIELD_PREP(ICL_PCODE_REQ_QGV_PT_MASK, (x))
70#define ADLS_PCODE_REQ_PSF_PT_MASK REG_GENMASK(10, 8)
71#define ADLS_PCODE_REQ_PSF_PT(x) REG_FIELD_PREP(ADLS_PCODE_REQ_PSF_PT_MASK, (x))
72#define GEN6_PCODE_READ_D_COMP 0x10
73#define GEN6_PCODE_WRITE_D_COMP 0x11
74#define ICL_PCODE_EXIT_TCCOLD 0x12
75#define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17
76#define DISPLAY_IPS_CONTROL 0x19
77#define TGL_PCODE_TCCOLD 0x26
78#define TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED REG_BIT(0)
79#define TGL_PCODE_EXIT_TCCOLD_DATA_L_BLOCK_REQ 0
80#define TGL_PCODE_EXIT_TCCOLD_DATA_L_UNBLOCK_REQ REG_BIT(0)
81/* See also IPS_CTL */
82#define IPS_PCODE_CONTROL (1 << 30)
83#define HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL 0x1A
84#define GEN9_PCODE_SAGV_CONTROL 0x21
85#define GEN9_SAGV_DISABLE 0x0
86#define GEN9_SAGV_IS_DISABLED 0x1
87#define GEN9_SAGV_ENABLE 0x3
88#define DG1_PCODE_STATUS 0x7E
89#define DG1_UNCORE_GET_INIT_STATUS 0x0
90#define DG1_UNCORE_INIT_STATUS_COMPLETE 0x1
91#define PCODE_POWER_SETUP 0x7C
92#define POWER_SETUP_SUBCOMMAND_READ_I1 0x4
93#define POWER_SETUP_SUBCOMMAND_WRITE_I1 0x5
94#define POWER_SETUP_I1_WATTS REG_BIT(31)
95#define POWER_SETUP_I1_SHIFT 6 /* 10.6 fixed point format */
96#define POWER_SETUP_I1_DATA_MASK REG_GENMASK(15, 0)
97#define POWER_SETUP_SUBCOMMAND_G8_ENABLE 0x6
98#define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US 0x23
99#define XEHP_PCODE_FREQUENCY_CONFIG 0x6e /* pvc */
100/* XEHP_PCODE_FREQUENCY_CONFIG sub-commands (param1) */
101#define PCODE_MBOX_FC_SC_READ_FUSED_P0 0x0
102#define PCODE_MBOX_FC_SC_READ_FUSED_PN 0x1
103/* PCODE_MBOX_DOMAIN_* - mailbox domain IDs */
104/* XEHP_PCODE_FREQUENCY_CONFIG param2 */
105#define PCODE_MBOX_DOMAIN_NONE 0x0
106#define PCODE_MBOX_DOMAIN_MEDIAFF 0x3
107
108#endif