Linux kernel mirror (for testing)
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linux
1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef _LINUX_PGTABLE_H
3#define _LINUX_PGTABLE_H
4
5#include <linux/pfn.h>
6#include <asm/pgtable.h>
7
8#define PMD_ORDER (PMD_SHIFT - PAGE_SHIFT)
9#define PUD_ORDER (PUD_SHIFT - PAGE_SHIFT)
10
11#ifndef __ASSEMBLY__
12#ifdef CONFIG_MMU
13
14#include <linux/mm_types.h>
15#include <linux/bug.h>
16#include <linux/errno.h>
17#include <asm-generic/pgtable_uffd.h>
18#include <linux/page_table_check.h>
19
20#if 5 - defined(__PAGETABLE_P4D_FOLDED) - defined(__PAGETABLE_PUD_FOLDED) - \
21 defined(__PAGETABLE_PMD_FOLDED) != CONFIG_PGTABLE_LEVELS
22#error CONFIG_PGTABLE_LEVELS is not consistent with __PAGETABLE_{P4D,PUD,PMD}_FOLDED
23#endif
24
25/*
26 * This defines the generic helper for accessing PMD page
27 * table page. Although platforms can still override this
28 * via their respective <asm/pgtable.h>.
29 */
30#ifndef pmd_pgtable
31#define pmd_pgtable(pmd) pmd_page(pmd)
32#endif
33
34#define pmd_folio(pmd) page_folio(pmd_page(pmd))
35
36/*
37 * A page table page can be thought of an array like this: pXd_t[PTRS_PER_PxD]
38 *
39 * The pXx_index() functions return the index of the entry in the page
40 * table page which would control the given virtual address
41 *
42 * As these functions may be used by the same code for different levels of
43 * the page table folding, they are always available, regardless of
44 * CONFIG_PGTABLE_LEVELS value. For the folded levels they simply return 0
45 * because in such cases PTRS_PER_PxD equals 1.
46 */
47
48static inline unsigned long pte_index(unsigned long address)
49{
50 return (address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1);
51}
52
53#ifndef pmd_index
54static inline unsigned long pmd_index(unsigned long address)
55{
56 return (address >> PMD_SHIFT) & (PTRS_PER_PMD - 1);
57}
58#define pmd_index pmd_index
59#endif
60
61#ifndef pud_index
62static inline unsigned long pud_index(unsigned long address)
63{
64 return (address >> PUD_SHIFT) & (PTRS_PER_PUD - 1);
65}
66#define pud_index pud_index
67#endif
68
69#ifndef pgd_index
70/* Must be a compile-time constant, so implement it as a macro */
71#define pgd_index(a) (((a) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1))
72#endif
73
74#ifndef kernel_pte_init
75static inline void kernel_pte_init(void *addr)
76{
77}
78#define kernel_pte_init kernel_pte_init
79#endif
80
81#ifndef pmd_init
82static inline void pmd_init(void *addr)
83{
84}
85#define pmd_init pmd_init
86#endif
87
88#ifndef pud_init
89static inline void pud_init(void *addr)
90{
91}
92#define pud_init pud_init
93#endif
94
95#ifndef pte_offset_kernel
96static inline pte_t *pte_offset_kernel(pmd_t *pmd, unsigned long address)
97{
98 return (pte_t *)pmd_page_vaddr(*pmd) + pte_index(address);
99}
100#define pte_offset_kernel pte_offset_kernel
101#endif
102
103#ifdef CONFIG_HIGHPTE
104#define __pte_map(pmd, address) \
105 ((pte_t *)kmap_local_page(pmd_page(*(pmd))) + pte_index((address)))
106#define pte_unmap(pte) do { \
107 kunmap_local((pte)); \
108 rcu_read_unlock(); \
109} while (0)
110#else
111static inline pte_t *__pte_map(pmd_t *pmd, unsigned long address)
112{
113 return pte_offset_kernel(pmd, address);
114}
115static inline void pte_unmap(pte_t *pte)
116{
117 rcu_read_unlock();
118}
119#endif
120
121void pte_free_defer(struct mm_struct *mm, pgtable_t pgtable);
122
123/* Find an entry in the second-level page table.. */
124#ifndef pmd_offset
125static inline pmd_t *pmd_offset(pud_t *pud, unsigned long address)
126{
127 return pud_pgtable(*pud) + pmd_index(address);
128}
129#define pmd_offset pmd_offset
130#endif
131
132#ifndef pud_offset
133static inline pud_t *pud_offset(p4d_t *p4d, unsigned long address)
134{
135 return p4d_pgtable(*p4d) + pud_index(address);
136}
137#define pud_offset pud_offset
138#endif
139
140static inline pgd_t *pgd_offset_pgd(pgd_t *pgd, unsigned long address)
141{
142 return (pgd + pgd_index(address));
143};
144
145/*
146 * a shortcut to get a pgd_t in a given mm
147 */
148#ifndef pgd_offset
149#define pgd_offset(mm, address) pgd_offset_pgd((mm)->pgd, (address))
150#endif
151
152/*
153 * a shortcut which implies the use of the kernel's pgd, instead
154 * of a process's
155 */
156#define pgd_offset_k(address) pgd_offset(&init_mm, (address))
157
158/*
159 * In many cases it is known that a virtual address is mapped at PMD or PTE
160 * level, so instead of traversing all the page table levels, we can get a
161 * pointer to the PMD entry in user or kernel page table or translate a virtual
162 * address to the pointer in the PTE in the kernel page tables with simple
163 * helpers.
164 */
165static inline pmd_t *pmd_off(struct mm_struct *mm, unsigned long va)
166{
167 return pmd_offset(pud_offset(p4d_offset(pgd_offset(mm, va), va), va), va);
168}
169
170static inline pmd_t *pmd_off_k(unsigned long va)
171{
172 return pmd_offset(pud_offset(p4d_offset(pgd_offset_k(va), va), va), va);
173}
174
175static inline pte_t *virt_to_kpte(unsigned long vaddr)
176{
177 pmd_t *pmd = pmd_off_k(vaddr);
178
179 return pmd_none(*pmd) ? NULL : pte_offset_kernel(pmd, vaddr);
180}
181
182#ifndef pmd_young
183static inline int pmd_young(pmd_t pmd)
184{
185 return 0;
186}
187#endif
188
189#ifndef pmd_dirty
190static inline int pmd_dirty(pmd_t pmd)
191{
192 return 0;
193}
194#endif
195
196/*
197 * A facility to provide lazy MMU batching. This allows PTE updates and
198 * page invalidations to be delayed until a call to leave lazy MMU mode
199 * is issued. Some architectures may benefit from doing this, and it is
200 * beneficial for both shadow and direct mode hypervisors, which may batch
201 * the PTE updates which happen during this window. Note that using this
202 * interface requires that read hazards be removed from the code. A read
203 * hazard could result in the direct mode hypervisor case, since the actual
204 * write to the page tables may not yet have taken place, so reads though
205 * a raw PTE pointer after it has been modified are not guaranteed to be
206 * up to date.
207 *
208 * In the general case, no lock is guaranteed to be held between entry and exit
209 * of the lazy mode. (In practice, for user PTE updates, the appropriate page
210 * table lock(s) are held, but for kernel PTE updates, no lock is held).
211 * The implementation must therefore assume preemption may be enabled upon
212 * entry to the mode and cpu migration is possible; it must take steps to be
213 * robust against this. An implementation may handle this by disabling
214 * preemption, as a consequence generic code may not sleep while the lazy MMU
215 * mode is active.
216 *
217 * The mode is disabled in interrupt context and calls to the lazy_mmu API have
218 * no effect.
219 *
220 * The lazy MMU mode is enabled for a given block of code using:
221 *
222 * lazy_mmu_mode_enable();
223 * <code>
224 * lazy_mmu_mode_disable();
225 *
226 * Nesting is permitted: <code> may itself use an enable()/disable() pair.
227 * A nested call to enable() has no functional effect; however disable() causes
228 * any batched architectural state to be flushed regardless of nesting. After a
229 * call to disable(), the caller can therefore rely on all previous page table
230 * modifications to have taken effect, but the lazy MMU mode may still be
231 * enabled.
232 *
233 * In certain cases, it may be desirable to temporarily pause the lazy MMU mode.
234 * This can be done using:
235 *
236 * lazy_mmu_mode_pause();
237 * <code>
238 * lazy_mmu_mode_resume();
239 *
240 * pause() ensures that the mode is exited regardless of the nesting level;
241 * resume() re-enters the mode at the same nesting level. Any call to the
242 * lazy_mmu_mode_* API between those two calls has no effect. In particular,
243 * this means that pause()/resume() pairs may nest.
244 *
245 * is_lazy_mmu_mode_active() can be used to check whether the lazy MMU mode is
246 * currently enabled.
247 */
248#ifdef CONFIG_ARCH_HAS_LAZY_MMU_MODE
249/**
250 * lazy_mmu_mode_enable() - Enable the lazy MMU mode.
251 *
252 * Enters a new lazy MMU mode section; if the mode was not already enabled,
253 * enables it and calls arch_enter_lazy_mmu_mode().
254 *
255 * Must be paired with a call to lazy_mmu_mode_disable().
256 *
257 * Has no effect if called:
258 * - While paused - see lazy_mmu_mode_pause()
259 * - In interrupt context
260 */
261static inline void lazy_mmu_mode_enable(void)
262{
263 struct lazy_mmu_state *state = ¤t->lazy_mmu_state;
264
265 if (in_interrupt() || state->pause_count > 0)
266 return;
267
268 VM_WARN_ON_ONCE(state->enable_count == U8_MAX);
269
270 if (state->enable_count++ == 0)
271 arch_enter_lazy_mmu_mode();
272}
273
274/**
275 * lazy_mmu_mode_disable() - Disable the lazy MMU mode.
276 *
277 * Exits the current lazy MMU mode section. If it is the outermost section,
278 * disables the mode and calls arch_leave_lazy_mmu_mode(). Otherwise (nested
279 * section), calls arch_flush_lazy_mmu_mode().
280 *
281 * Must match a call to lazy_mmu_mode_enable().
282 *
283 * Has no effect if called:
284 * - While paused - see lazy_mmu_mode_pause()
285 * - In interrupt context
286 */
287static inline void lazy_mmu_mode_disable(void)
288{
289 struct lazy_mmu_state *state = ¤t->lazy_mmu_state;
290
291 if (in_interrupt() || state->pause_count > 0)
292 return;
293
294 VM_WARN_ON_ONCE(state->enable_count == 0);
295
296 if (--state->enable_count == 0)
297 arch_leave_lazy_mmu_mode();
298 else /* Exiting a nested section */
299 arch_flush_lazy_mmu_mode();
300
301}
302
303/**
304 * lazy_mmu_mode_pause() - Pause the lazy MMU mode.
305 *
306 * Pauses the lazy MMU mode; if it is currently active, disables it and calls
307 * arch_leave_lazy_mmu_mode().
308 *
309 * Must be paired with a call to lazy_mmu_mode_resume(). Calls to the
310 * lazy_mmu_mode_* API have no effect until the matching resume() call.
311 *
312 * Has no effect if called:
313 * - While paused (inside another pause()/resume() pair)
314 * - In interrupt context
315 */
316static inline void lazy_mmu_mode_pause(void)
317{
318 struct lazy_mmu_state *state = ¤t->lazy_mmu_state;
319
320 if (in_interrupt())
321 return;
322
323 VM_WARN_ON_ONCE(state->pause_count == U8_MAX);
324
325 if (state->pause_count++ == 0 && state->enable_count > 0)
326 arch_leave_lazy_mmu_mode();
327}
328
329/**
330 * lazy_mmu_mode_resume() - Resume the lazy MMU mode.
331 *
332 * Resumes the lazy MMU mode; if it was active at the point where the matching
333 * call to lazy_mmu_mode_pause() was made, re-enables it and calls
334 * arch_enter_lazy_mmu_mode().
335 *
336 * Must match a call to lazy_mmu_mode_pause().
337 *
338 * Has no effect if called:
339 * - While paused (inside another pause()/resume() pair)
340 * - In interrupt context
341 */
342static inline void lazy_mmu_mode_resume(void)
343{
344 struct lazy_mmu_state *state = ¤t->lazy_mmu_state;
345
346 if (in_interrupt())
347 return;
348
349 VM_WARN_ON_ONCE(state->pause_count == 0);
350
351 if (--state->pause_count == 0 && state->enable_count > 0)
352 arch_enter_lazy_mmu_mode();
353}
354#else
355static inline void lazy_mmu_mode_enable(void) {}
356static inline void lazy_mmu_mode_disable(void) {}
357static inline void lazy_mmu_mode_pause(void) {}
358static inline void lazy_mmu_mode_resume(void) {}
359#endif
360
361#ifndef pte_batch_hint
362/**
363 * pte_batch_hint - Number of pages that can be added to batch without scanning.
364 * @ptep: Page table pointer for the entry.
365 * @pte: Page table entry.
366 *
367 * Some architectures know that a set of contiguous ptes all map the same
368 * contiguous memory with the same permissions. In this case, it can provide a
369 * hint to aid pte batching without the core code needing to scan every pte.
370 *
371 * An architecture implementation may ignore the PTE accessed state. Further,
372 * the dirty state must apply atomically to all the PTEs described by the hint.
373 *
374 * May be overridden by the architecture, else pte_batch_hint is always 1.
375 */
376static inline unsigned int pte_batch_hint(pte_t *ptep, pte_t pte)
377{
378 return 1;
379}
380#endif
381
382#ifndef pte_advance_pfn
383static inline pte_t pte_advance_pfn(pte_t pte, unsigned long nr)
384{
385 return __pte(pte_val(pte) + (nr << PFN_PTE_SHIFT));
386}
387#endif
388
389#define pte_next_pfn(pte) pte_advance_pfn(pte, 1)
390
391#ifndef set_ptes
392/**
393 * set_ptes - Map consecutive pages to a contiguous range of addresses.
394 * @mm: Address space to map the pages into.
395 * @addr: Address to map the first page at.
396 * @ptep: Page table pointer for the first entry.
397 * @pte: Page table entry for the first page.
398 * @nr: Number of pages to map.
399 *
400 * When nr==1, initial state of pte may be present or not present, and new state
401 * may be present or not present. When nr>1, initial state of all ptes must be
402 * not present, and new state must be present.
403 *
404 * May be overridden by the architecture, or the architecture can define
405 * set_pte() and PFN_PTE_SHIFT.
406 *
407 * Context: The caller holds the page table lock. The pages all belong
408 * to the same folio. The PTEs are all in the same PMD.
409 */
410static inline void set_ptes(struct mm_struct *mm, unsigned long addr,
411 pte_t *ptep, pte_t pte, unsigned int nr)
412{
413 page_table_check_ptes_set(mm, addr, ptep, pte, nr);
414
415 for (;;) {
416 set_pte(ptep, pte);
417 if (--nr == 0)
418 break;
419 ptep++;
420 pte = pte_next_pfn(pte);
421 }
422}
423#endif
424#define set_pte_at(mm, addr, ptep, pte) set_ptes(mm, addr, ptep, pte, 1)
425
426#ifndef __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
427extern int ptep_set_access_flags(struct vm_area_struct *vma,
428 unsigned long address, pte_t *ptep,
429 pte_t entry, int dirty);
430#endif
431
432#ifndef __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS
433#ifdef CONFIG_TRANSPARENT_HUGEPAGE
434extern int pmdp_set_access_flags(struct vm_area_struct *vma,
435 unsigned long address, pmd_t *pmdp,
436 pmd_t entry, int dirty);
437extern int pudp_set_access_flags(struct vm_area_struct *vma,
438 unsigned long address, pud_t *pudp,
439 pud_t entry, int dirty);
440#else
441static inline int pmdp_set_access_flags(struct vm_area_struct *vma,
442 unsigned long address, pmd_t *pmdp,
443 pmd_t entry, int dirty)
444{
445 BUILD_BUG();
446 return 0;
447}
448static inline int pudp_set_access_flags(struct vm_area_struct *vma,
449 unsigned long address, pud_t *pudp,
450 pud_t entry, int dirty)
451{
452 BUILD_BUG();
453 return 0;
454}
455#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
456#endif
457
458#ifndef ptep_get
459static inline pte_t ptep_get(pte_t *ptep)
460{
461 return READ_ONCE(*ptep);
462}
463#endif
464
465#ifndef pmdp_get
466static inline pmd_t pmdp_get(pmd_t *pmdp)
467{
468 return READ_ONCE(*pmdp);
469}
470#endif
471
472#ifndef pudp_get
473static inline pud_t pudp_get(pud_t *pudp)
474{
475 return READ_ONCE(*pudp);
476}
477#endif
478
479#ifndef p4dp_get
480static inline p4d_t p4dp_get(p4d_t *p4dp)
481{
482 return READ_ONCE(*p4dp);
483}
484#endif
485
486#ifndef pgdp_get
487static inline pgd_t pgdp_get(pgd_t *pgdp)
488{
489 return READ_ONCE(*pgdp);
490}
491#endif
492
493#ifndef __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
494static inline int ptep_test_and_clear_young(struct vm_area_struct *vma,
495 unsigned long address,
496 pte_t *ptep)
497{
498 pte_t pte = ptep_get(ptep);
499 int r = 1;
500 if (!pte_young(pte))
501 r = 0;
502 else
503 set_pte_at(vma->vm_mm, address, ptep, pte_mkold(pte));
504 return r;
505}
506#endif
507
508#ifndef __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG
509#if defined(CONFIG_TRANSPARENT_HUGEPAGE) || defined(CONFIG_ARCH_HAS_NONLEAF_PMD_YOUNG)
510static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma,
511 unsigned long address,
512 pmd_t *pmdp)
513{
514 pmd_t pmd = *pmdp;
515 int r = 1;
516 if (!pmd_young(pmd))
517 r = 0;
518 else
519 set_pmd_at(vma->vm_mm, address, pmdp, pmd_mkold(pmd));
520 return r;
521}
522#else
523static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma,
524 unsigned long address,
525 pmd_t *pmdp)
526{
527 BUILD_BUG();
528 return 0;
529}
530#endif /* CONFIG_TRANSPARENT_HUGEPAGE || CONFIG_ARCH_HAS_NONLEAF_PMD_YOUNG */
531#endif
532
533#ifndef __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH
534int ptep_clear_flush_young(struct vm_area_struct *vma,
535 unsigned long address, pte_t *ptep);
536#endif
537
538#ifndef __HAVE_ARCH_PMDP_CLEAR_YOUNG_FLUSH
539#ifdef CONFIG_TRANSPARENT_HUGEPAGE
540extern int pmdp_clear_flush_young(struct vm_area_struct *vma,
541 unsigned long address, pmd_t *pmdp);
542#else
543/*
544 * Despite relevant to THP only, this API is called from generic rmap code
545 * under PageTransHuge(), hence needs a dummy implementation for !THP
546 */
547static inline int pmdp_clear_flush_young(struct vm_area_struct *vma,
548 unsigned long address, pmd_t *pmdp)
549{
550 BUILD_BUG();
551 return 0;
552}
553#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
554#endif
555
556#ifndef arch_has_hw_nonleaf_pmd_young
557/*
558 * Return whether the accessed bit in non-leaf PMD entries is supported on the
559 * local CPU.
560 */
561static inline bool arch_has_hw_nonleaf_pmd_young(void)
562{
563 return IS_ENABLED(CONFIG_ARCH_HAS_NONLEAF_PMD_YOUNG);
564}
565#endif
566
567#ifndef arch_has_hw_pte_young
568/*
569 * Return whether the accessed bit is supported on the local CPU.
570 *
571 * This stub assumes accessing through an old PTE triggers a page fault.
572 * Architectures that automatically set the access bit should overwrite it.
573 */
574static inline bool arch_has_hw_pte_young(void)
575{
576 return IS_ENABLED(CONFIG_ARCH_HAS_HW_PTE_YOUNG);
577}
578#endif
579
580#ifndef exec_folio_order
581/*
582 * Returns preferred minimum folio order for executable file-backed memory. Must
583 * be in range [0, PMD_ORDER). Default to order-0.
584 */
585static inline unsigned int exec_folio_order(void)
586{
587 return 0;
588}
589#endif
590
591#ifndef arch_check_zapped_pte
592static inline void arch_check_zapped_pte(struct vm_area_struct *vma,
593 pte_t pte)
594{
595}
596#endif
597
598#ifndef arch_check_zapped_pmd
599static inline void arch_check_zapped_pmd(struct vm_area_struct *vma,
600 pmd_t pmd)
601{
602}
603#endif
604
605#ifndef arch_check_zapped_pud
606static inline void arch_check_zapped_pud(struct vm_area_struct *vma, pud_t pud)
607{
608}
609#endif
610
611#ifndef __HAVE_ARCH_PTEP_GET_AND_CLEAR
612static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
613 unsigned long address,
614 pte_t *ptep)
615{
616 pte_t pte = ptep_get(ptep);
617 pte_clear(mm, address, ptep);
618 page_table_check_pte_clear(mm, address, pte);
619 return pte;
620}
621#endif
622
623#ifndef clear_young_dirty_ptes
624/**
625 * clear_young_dirty_ptes - Mark PTEs that map consecutive pages of the
626 * same folio as old/clean.
627 * @mm: Address space the pages are mapped into.
628 * @addr: Address the first page is mapped at.
629 * @ptep: Page table pointer for the first entry.
630 * @nr: Number of entries to mark old/clean.
631 * @flags: Flags to modify the PTE batch semantics.
632 *
633 * May be overridden by the architecture; otherwise, implemented by
634 * get_and_clear/modify/set for each pte in the range.
635 *
636 * Note that PTE bits in the PTE range besides the PFN can differ. For example,
637 * some PTEs might be write-protected.
638 *
639 * Context: The caller holds the page table lock. The PTEs map consecutive
640 * pages that belong to the same folio. The PTEs are all in the same PMD.
641 */
642static inline void clear_young_dirty_ptes(struct vm_area_struct *vma,
643 unsigned long addr, pte_t *ptep,
644 unsigned int nr, cydp_t flags)
645{
646 pte_t pte;
647
648 for (;;) {
649 if (flags == CYDP_CLEAR_YOUNG)
650 ptep_test_and_clear_young(vma, addr, ptep);
651 else {
652 pte = ptep_get_and_clear(vma->vm_mm, addr, ptep);
653 if (flags & CYDP_CLEAR_YOUNG)
654 pte = pte_mkold(pte);
655 if (flags & CYDP_CLEAR_DIRTY)
656 pte = pte_mkclean(pte);
657 set_pte_at(vma->vm_mm, addr, ptep, pte);
658 }
659 if (--nr == 0)
660 break;
661 ptep++;
662 addr += PAGE_SIZE;
663 }
664}
665#endif
666
667static inline void ptep_clear(struct mm_struct *mm, unsigned long addr,
668 pte_t *ptep)
669{
670 pte_t pte = ptep_get(ptep);
671
672 pte_clear(mm, addr, ptep);
673 /*
674 * No need for ptep_get_and_clear(): page table check doesn't care about
675 * any bits that could have been set by HW concurrently.
676 */
677 page_table_check_pte_clear(mm, addr, pte);
678}
679
680#ifdef CONFIG_GUP_GET_PXX_LOW_HIGH
681/*
682 * For walking the pagetables without holding any locks. Some architectures
683 * (eg x86-32 PAE) cannot load the entries atomically without using expensive
684 * instructions. We are guaranteed that a PTE will only either go from not
685 * present to present, or present to not present -- it will not switch to a
686 * completely different present page without a TLB flush inbetween; which we
687 * are blocking by holding interrupts off.
688 *
689 * Setting ptes from not present to present goes:
690 *
691 * ptep->pte_high = h;
692 * smp_wmb();
693 * ptep->pte_low = l;
694 *
695 * And present to not present goes:
696 *
697 * ptep->pte_low = 0;
698 * smp_wmb();
699 * ptep->pte_high = 0;
700 *
701 * We must ensure here that the load of pte_low sees 'l' IFF pte_high sees 'h'.
702 * We load pte_high *after* loading pte_low, which ensures we don't see an older
703 * value of pte_high. *Then* we recheck pte_low, which ensures that we haven't
704 * picked up a changed pte high. We might have gotten rubbish values from
705 * pte_low and pte_high, but we are guaranteed that pte_low will not have the
706 * present bit set *unless* it is 'l'. Because get_user_pages_fast() only
707 * operates on present ptes we're safe.
708 */
709static inline pte_t ptep_get_lockless(pte_t *ptep)
710{
711 pte_t pte;
712
713 do {
714 pte.pte_low = ptep->pte_low;
715 smp_rmb();
716 pte.pte_high = ptep->pte_high;
717 smp_rmb();
718 } while (unlikely(pte.pte_low != ptep->pte_low));
719
720 return pte;
721}
722#define ptep_get_lockless ptep_get_lockless
723
724#if CONFIG_PGTABLE_LEVELS > 2
725static inline pmd_t pmdp_get_lockless(pmd_t *pmdp)
726{
727 pmd_t pmd;
728
729 do {
730 pmd.pmd_low = pmdp->pmd_low;
731 smp_rmb();
732 pmd.pmd_high = pmdp->pmd_high;
733 smp_rmb();
734 } while (unlikely(pmd.pmd_low != pmdp->pmd_low));
735
736 return pmd;
737}
738#define pmdp_get_lockless pmdp_get_lockless
739#define pmdp_get_lockless_sync() tlb_remove_table_sync_one()
740#endif /* CONFIG_PGTABLE_LEVELS > 2 */
741#endif /* CONFIG_GUP_GET_PXX_LOW_HIGH */
742
743/*
744 * We require that the PTE can be read atomically.
745 */
746#ifndef ptep_get_lockless
747static inline pte_t ptep_get_lockless(pte_t *ptep)
748{
749 return ptep_get(ptep);
750}
751#endif
752
753#ifndef pmdp_get_lockless
754static inline pmd_t pmdp_get_lockless(pmd_t *pmdp)
755{
756 return pmdp_get(pmdp);
757}
758static inline void pmdp_get_lockless_sync(void)
759{
760}
761#endif
762
763#ifdef CONFIG_TRANSPARENT_HUGEPAGE
764#ifndef __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR
765static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm,
766 unsigned long address,
767 pmd_t *pmdp)
768{
769 pmd_t pmd = *pmdp;
770
771 pmd_clear(pmdp);
772 page_table_check_pmd_clear(mm, address, pmd);
773
774 return pmd;
775}
776#endif /* __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR */
777#ifndef __HAVE_ARCH_PUDP_HUGE_GET_AND_CLEAR
778static inline pud_t pudp_huge_get_and_clear(struct mm_struct *mm,
779 unsigned long address,
780 pud_t *pudp)
781{
782 pud_t pud = *pudp;
783
784 pud_clear(pudp);
785 page_table_check_pud_clear(mm, address, pud);
786
787 return pud;
788}
789#endif /* __HAVE_ARCH_PUDP_HUGE_GET_AND_CLEAR */
790#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
791
792#ifdef CONFIG_TRANSPARENT_HUGEPAGE
793#ifndef __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR_FULL
794static inline pmd_t pmdp_huge_get_and_clear_full(struct vm_area_struct *vma,
795 unsigned long address, pmd_t *pmdp,
796 int full)
797{
798 return pmdp_huge_get_and_clear(vma->vm_mm, address, pmdp);
799}
800#endif
801
802#ifndef __HAVE_ARCH_PUDP_HUGE_GET_AND_CLEAR_FULL
803static inline pud_t pudp_huge_get_and_clear_full(struct vm_area_struct *vma,
804 unsigned long address, pud_t *pudp,
805 int full)
806{
807 return pudp_huge_get_and_clear(vma->vm_mm, address, pudp);
808}
809#endif
810#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
811
812#ifndef __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL
813static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm,
814 unsigned long address, pte_t *ptep,
815 int full)
816{
817 return ptep_get_and_clear(mm, address, ptep);
818}
819#endif
820
821#ifndef get_and_clear_full_ptes
822/**
823 * get_and_clear_full_ptes - Clear present PTEs that map consecutive pages of
824 * the same folio, collecting dirty/accessed bits.
825 * @mm: Address space the pages are mapped into.
826 * @addr: Address the first page is mapped at.
827 * @ptep: Page table pointer for the first entry.
828 * @nr: Number of entries to clear.
829 * @full: Whether we are clearing a full mm.
830 *
831 * May be overridden by the architecture; otherwise, implemented as a simple
832 * loop over ptep_get_and_clear_full(), merging dirty/accessed bits into the
833 * returned PTE.
834 *
835 * Note that PTE bits in the PTE range besides the PFN can differ. For example,
836 * some PTEs might be write-protected.
837 *
838 * Context: The caller holds the page table lock. The PTEs map consecutive
839 * pages that belong to the same folio. The PTEs are all in the same PMD.
840 */
841static inline pte_t get_and_clear_full_ptes(struct mm_struct *mm,
842 unsigned long addr, pte_t *ptep, unsigned int nr, int full)
843{
844 pte_t pte, tmp_pte;
845
846 pte = ptep_get_and_clear_full(mm, addr, ptep, full);
847 while (--nr) {
848 ptep++;
849 addr += PAGE_SIZE;
850 tmp_pte = ptep_get_and_clear_full(mm, addr, ptep, full);
851 if (pte_dirty(tmp_pte))
852 pte = pte_mkdirty(pte);
853 if (pte_young(tmp_pte))
854 pte = pte_mkyoung(pte);
855 }
856 return pte;
857}
858#endif
859
860/**
861 * get_and_clear_ptes - Clear present PTEs that map consecutive pages of
862 * the same folio, collecting dirty/accessed bits.
863 * @mm: Address space the pages are mapped into.
864 * @addr: Address the first page is mapped at.
865 * @ptep: Page table pointer for the first entry.
866 * @nr: Number of entries to clear.
867 *
868 * Use this instead of get_and_clear_full_ptes() if it is known that we don't
869 * need to clear the full mm, which is mostly the case.
870 *
871 * Note that PTE bits in the PTE range besides the PFN can differ. For example,
872 * some PTEs might be write-protected.
873 *
874 * Context: The caller holds the page table lock. The PTEs map consecutive
875 * pages that belong to the same folio. The PTEs are all in the same PMD.
876 */
877static inline pte_t get_and_clear_ptes(struct mm_struct *mm, unsigned long addr,
878 pte_t *ptep, unsigned int nr)
879{
880 return get_and_clear_full_ptes(mm, addr, ptep, nr, 0);
881}
882
883#ifndef clear_full_ptes
884/**
885 * clear_full_ptes - Clear present PTEs that map consecutive pages of the same
886 * folio.
887 * @mm: Address space the pages are mapped into.
888 * @addr: Address the first page is mapped at.
889 * @ptep: Page table pointer for the first entry.
890 * @nr: Number of entries to clear.
891 * @full: Whether we are clearing a full mm.
892 *
893 * May be overridden by the architecture; otherwise, implemented as a simple
894 * loop over ptep_get_and_clear_full().
895 *
896 * Note that PTE bits in the PTE range besides the PFN can differ. For example,
897 * some PTEs might be write-protected.
898 *
899 * Context: The caller holds the page table lock. The PTEs map consecutive
900 * pages that belong to the same folio. The PTEs are all in the same PMD.
901 */
902static inline void clear_full_ptes(struct mm_struct *mm, unsigned long addr,
903 pte_t *ptep, unsigned int nr, int full)
904{
905 for (;;) {
906 ptep_get_and_clear_full(mm, addr, ptep, full);
907 if (--nr == 0)
908 break;
909 ptep++;
910 addr += PAGE_SIZE;
911 }
912}
913#endif
914
915/**
916 * clear_ptes - Clear present PTEs that map consecutive pages of the same folio.
917 * @mm: Address space the pages are mapped into.
918 * @addr: Address the first page is mapped at.
919 * @ptep: Page table pointer for the first entry.
920 * @nr: Number of entries to clear.
921 *
922 * Use this instead of clear_full_ptes() if it is known that we don't need to
923 * clear the full mm, which is mostly the case.
924 *
925 * Note that PTE bits in the PTE range besides the PFN can differ. For example,
926 * some PTEs might be write-protected.
927 *
928 * Context: The caller holds the page table lock. The PTEs map consecutive
929 * pages that belong to the same folio. The PTEs are all in the same PMD.
930 */
931static inline void clear_ptes(struct mm_struct *mm, unsigned long addr,
932 pte_t *ptep, unsigned int nr)
933{
934 clear_full_ptes(mm, addr, ptep, nr, 0);
935}
936
937/*
938 * If two threads concurrently fault at the same page, the thread that
939 * won the race updates the PTE and its local TLB/Cache. The other thread
940 * gives up, simply does nothing, and continues; on architectures where
941 * software can update TLB, local TLB can be updated here to avoid next page
942 * fault. This function updates TLB only, do nothing with cache or others.
943 * It is the difference with function update_mmu_cache.
944 */
945#ifndef update_mmu_tlb_range
946static inline void update_mmu_tlb_range(struct vm_area_struct *vma,
947 unsigned long address, pte_t *ptep, unsigned int nr)
948{
949}
950#endif
951
952static inline void update_mmu_tlb(struct vm_area_struct *vma,
953 unsigned long address, pte_t *ptep)
954{
955 update_mmu_tlb_range(vma, address, ptep, 1);
956}
957
958/*
959 * Some architectures may be able to avoid expensive synchronization
960 * primitives when modifications are made to PTE's which are already
961 * not present, or in the process of an address space destruction.
962 */
963#ifndef __HAVE_ARCH_PTE_CLEAR_NOT_PRESENT_FULL
964static inline void pte_clear_not_present_full(struct mm_struct *mm,
965 unsigned long address,
966 pte_t *ptep,
967 int full)
968{
969 pte_clear(mm, address, ptep);
970}
971#endif
972
973#ifndef clear_not_present_full_ptes
974/**
975 * clear_not_present_full_ptes - Clear multiple not present PTEs which are
976 * consecutive in the pgtable.
977 * @mm: Address space the ptes represent.
978 * @addr: Address of the first pte.
979 * @ptep: Page table pointer for the first entry.
980 * @nr: Number of entries to clear.
981 * @full: Whether we are clearing a full mm.
982 *
983 * May be overridden by the architecture; otherwise, implemented as a simple
984 * loop over pte_clear_not_present_full().
985 *
986 * Context: The caller holds the page table lock. The PTEs are all not present.
987 * The PTEs are all in the same PMD.
988 */
989static inline void clear_not_present_full_ptes(struct mm_struct *mm,
990 unsigned long addr, pte_t *ptep, unsigned int nr, int full)
991{
992 for (;;) {
993 pte_clear_not_present_full(mm, addr, ptep, full);
994 if (--nr == 0)
995 break;
996 ptep++;
997 addr += PAGE_SIZE;
998 }
999}
1000#endif
1001
1002#ifndef __HAVE_ARCH_PTEP_CLEAR_FLUSH
1003extern pte_t ptep_clear_flush(struct vm_area_struct *vma,
1004 unsigned long address,
1005 pte_t *ptep);
1006#endif
1007
1008#ifndef __HAVE_ARCH_PMDP_HUGE_CLEAR_FLUSH
1009extern pmd_t pmdp_huge_clear_flush(struct vm_area_struct *vma,
1010 unsigned long address,
1011 pmd_t *pmdp);
1012extern pud_t pudp_huge_clear_flush(struct vm_area_struct *vma,
1013 unsigned long address,
1014 pud_t *pudp);
1015#endif
1016
1017#ifndef pte_mkwrite
1018static inline pte_t pte_mkwrite(pte_t pte, struct vm_area_struct *vma)
1019{
1020 return pte_mkwrite_novma(pte);
1021}
1022#endif
1023
1024#if defined(CONFIG_ARCH_WANT_PMD_MKWRITE) && !defined(pmd_mkwrite)
1025static inline pmd_t pmd_mkwrite(pmd_t pmd, struct vm_area_struct *vma)
1026{
1027 return pmd_mkwrite_novma(pmd);
1028}
1029#endif
1030
1031#ifndef __HAVE_ARCH_PTEP_SET_WRPROTECT
1032struct mm_struct;
1033static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long address, pte_t *ptep)
1034{
1035 pte_t old_pte = ptep_get(ptep);
1036 set_pte_at(mm, address, ptep, pte_wrprotect(old_pte));
1037}
1038#endif
1039
1040#ifndef wrprotect_ptes
1041/**
1042 * wrprotect_ptes - Write-protect PTEs that map consecutive pages of the same
1043 * folio.
1044 * @mm: Address space the pages are mapped into.
1045 * @addr: Address the first page is mapped at.
1046 * @ptep: Page table pointer for the first entry.
1047 * @nr: Number of entries to write-protect.
1048 *
1049 * May be overridden by the architecture; otherwise, implemented as a simple
1050 * loop over ptep_set_wrprotect().
1051 *
1052 * Note that PTE bits in the PTE range besides the PFN can differ. For example,
1053 * some PTEs might be write-protected.
1054 *
1055 * Context: The caller holds the page table lock. The PTEs map consecutive
1056 * pages that belong to the same folio. The PTEs are all in the same PMD.
1057 */
1058static inline void wrprotect_ptes(struct mm_struct *mm, unsigned long addr,
1059 pte_t *ptep, unsigned int nr)
1060{
1061 for (;;) {
1062 ptep_set_wrprotect(mm, addr, ptep);
1063 if (--nr == 0)
1064 break;
1065 ptep++;
1066 addr += PAGE_SIZE;
1067 }
1068}
1069#endif
1070
1071#ifndef clear_flush_young_ptes
1072/**
1073 * clear_flush_young_ptes - Mark PTEs that map consecutive pages of the same
1074 * folio as old and flush the TLB.
1075 * @vma: The virtual memory area the pages are mapped into.
1076 * @addr: Address the first page is mapped at.
1077 * @ptep: Page table pointer for the first entry.
1078 * @nr: Number of entries to clear access bit.
1079 *
1080 * May be overridden by the architecture; otherwise, implemented as a simple
1081 * loop over ptep_clear_flush_young().
1082 *
1083 * Note that PTE bits in the PTE range besides the PFN can differ. For example,
1084 * some PTEs might be write-protected.
1085 *
1086 * Context: The caller holds the page table lock. The PTEs map consecutive
1087 * pages that belong to the same folio. The PTEs are all in the same PMD.
1088 */
1089static inline int clear_flush_young_ptes(struct vm_area_struct *vma,
1090 unsigned long addr, pte_t *ptep, unsigned int nr)
1091{
1092 int young = 0;
1093
1094 for (;;) {
1095 young |= ptep_clear_flush_young(vma, addr, ptep);
1096 if (--nr == 0)
1097 break;
1098 ptep++;
1099 addr += PAGE_SIZE;
1100 }
1101
1102 return young;
1103}
1104#endif
1105
1106/*
1107 * On some architectures hardware does not set page access bit when accessing
1108 * memory page, it is responsibility of software setting this bit. It brings
1109 * out extra page fault penalty to track page access bit. For optimization page
1110 * access bit can be set during all page fault flow on these arches.
1111 * To be differentiate with macro pte_mkyoung, this macro is used on platforms
1112 * where software maintains page access bit.
1113 */
1114#ifndef pte_sw_mkyoung
1115static inline pte_t pte_sw_mkyoung(pte_t pte)
1116{
1117 return pte;
1118}
1119#define pte_sw_mkyoung pte_sw_mkyoung
1120#endif
1121
1122#ifndef __HAVE_ARCH_PMDP_SET_WRPROTECT
1123#ifdef CONFIG_TRANSPARENT_HUGEPAGE
1124static inline void pmdp_set_wrprotect(struct mm_struct *mm,
1125 unsigned long address, pmd_t *pmdp)
1126{
1127 pmd_t old_pmd = *pmdp;
1128 set_pmd_at(mm, address, pmdp, pmd_wrprotect(old_pmd));
1129}
1130#else
1131static inline void pmdp_set_wrprotect(struct mm_struct *mm,
1132 unsigned long address, pmd_t *pmdp)
1133{
1134 BUILD_BUG();
1135}
1136#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
1137#endif
1138#ifndef __HAVE_ARCH_PUDP_SET_WRPROTECT
1139#ifdef CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD
1140#ifdef CONFIG_TRANSPARENT_HUGEPAGE
1141static inline void pudp_set_wrprotect(struct mm_struct *mm,
1142 unsigned long address, pud_t *pudp)
1143{
1144 pud_t old_pud = *pudp;
1145
1146 set_pud_at(mm, address, pudp, pud_wrprotect(old_pud));
1147}
1148#else
1149static inline void pudp_set_wrprotect(struct mm_struct *mm,
1150 unsigned long address, pud_t *pudp)
1151{
1152 BUILD_BUG();
1153}
1154#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
1155#endif /* CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD */
1156#endif
1157
1158#ifndef pmdp_collapse_flush
1159#ifdef CONFIG_TRANSPARENT_HUGEPAGE
1160extern pmd_t pmdp_collapse_flush(struct vm_area_struct *vma,
1161 unsigned long address, pmd_t *pmdp);
1162#else
1163static inline pmd_t pmdp_collapse_flush(struct vm_area_struct *vma,
1164 unsigned long address,
1165 pmd_t *pmdp)
1166{
1167 BUILD_BUG();
1168 return *pmdp;
1169}
1170#define pmdp_collapse_flush pmdp_collapse_flush
1171#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
1172#endif
1173
1174#ifndef __HAVE_ARCH_PGTABLE_DEPOSIT
1175extern void pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp,
1176 pgtable_t pgtable);
1177#endif
1178
1179#ifndef __HAVE_ARCH_PGTABLE_WITHDRAW
1180extern pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp);
1181#endif
1182
1183#ifndef arch_needs_pgtable_deposit
1184#define arch_needs_pgtable_deposit() (false)
1185#endif
1186
1187#ifdef CONFIG_TRANSPARENT_HUGEPAGE
1188/*
1189 * This is an implementation of pmdp_establish() that is only suitable for an
1190 * architecture that doesn't have hardware dirty/accessed bits. In this case we
1191 * can't race with CPU which sets these bits and non-atomic approach is fine.
1192 */
1193static inline pmd_t generic_pmdp_establish(struct vm_area_struct *vma,
1194 unsigned long address, pmd_t *pmdp, pmd_t pmd)
1195{
1196 pmd_t old_pmd = *pmdp;
1197 set_pmd_at(vma->vm_mm, address, pmdp, pmd);
1198 return old_pmd;
1199}
1200#endif
1201
1202#ifndef __HAVE_ARCH_PMDP_INVALIDATE
1203extern pmd_t pmdp_invalidate(struct vm_area_struct *vma, unsigned long address,
1204 pmd_t *pmdp);
1205#endif
1206
1207#ifndef __HAVE_ARCH_PMDP_INVALIDATE_AD
1208
1209/*
1210 * pmdp_invalidate_ad() invalidates the PMD while changing a transparent
1211 * hugepage mapping in the page tables. This function is similar to
1212 * pmdp_invalidate(), but should only be used if the access and dirty bits would
1213 * not be cleared by the software in the new PMD value. The function ensures
1214 * that hardware changes of the access and dirty bits updates would not be lost.
1215 *
1216 * Doing so can allow in certain architectures to avoid a TLB flush in most
1217 * cases. Yet, another TLB flush might be necessary later if the PMD update
1218 * itself requires such flush (e.g., if protection was set to be stricter). Yet,
1219 * even when a TLB flush is needed because of the update, the caller may be able
1220 * to batch these TLB flushing operations, so fewer TLB flush operations are
1221 * needed.
1222 */
1223extern pmd_t pmdp_invalidate_ad(struct vm_area_struct *vma,
1224 unsigned long address, pmd_t *pmdp);
1225#endif
1226
1227#ifndef __HAVE_ARCH_PTE_SAME
1228static inline int pte_same(pte_t pte_a, pte_t pte_b)
1229{
1230 return pte_val(pte_a) == pte_val(pte_b);
1231}
1232#endif
1233
1234#ifndef __HAVE_ARCH_PTE_UNUSED
1235/*
1236 * Some architectures provide facilities to virtualization guests
1237 * so that they can flag allocated pages as unused. This allows the
1238 * host to transparently reclaim unused pages. This function returns
1239 * whether the pte's page is unused.
1240 */
1241static inline int pte_unused(pte_t pte)
1242{
1243 return 0;
1244}
1245#endif
1246
1247#ifndef pte_access_permitted
1248#define pte_access_permitted(pte, write) \
1249 (pte_present(pte) && (!(write) || pte_write(pte)))
1250#endif
1251
1252#ifndef pmd_access_permitted
1253#define pmd_access_permitted(pmd, write) \
1254 (pmd_present(pmd) && (!(write) || pmd_write(pmd)))
1255#endif
1256
1257#ifndef pud_access_permitted
1258#define pud_access_permitted(pud, write) \
1259 (pud_present(pud) && (!(write) || pud_write(pud)))
1260#endif
1261
1262#ifndef p4d_access_permitted
1263#define p4d_access_permitted(p4d, write) \
1264 (p4d_present(p4d) && (!(write) || p4d_write(p4d)))
1265#endif
1266
1267#ifndef pgd_access_permitted
1268#define pgd_access_permitted(pgd, write) \
1269 (pgd_present(pgd) && (!(write) || pgd_write(pgd)))
1270#endif
1271
1272#ifndef __HAVE_ARCH_PMD_SAME
1273static inline int pmd_same(pmd_t pmd_a, pmd_t pmd_b)
1274{
1275 return pmd_val(pmd_a) == pmd_val(pmd_b);
1276}
1277#endif
1278
1279#ifndef pud_same
1280static inline int pud_same(pud_t pud_a, pud_t pud_b)
1281{
1282 return pud_val(pud_a) == pud_val(pud_b);
1283}
1284#define pud_same pud_same
1285#endif
1286
1287#ifndef __HAVE_ARCH_P4D_SAME
1288static inline int p4d_same(p4d_t p4d_a, p4d_t p4d_b)
1289{
1290 return p4d_val(p4d_a) == p4d_val(p4d_b);
1291}
1292#endif
1293
1294#ifndef __HAVE_ARCH_PGD_SAME
1295static inline int pgd_same(pgd_t pgd_a, pgd_t pgd_b)
1296{
1297 return pgd_val(pgd_a) == pgd_val(pgd_b);
1298}
1299#endif
1300
1301#ifndef __HAVE_ARCH_DO_SWAP_PAGE
1302static inline void arch_do_swap_page_nr(struct mm_struct *mm,
1303 struct vm_area_struct *vma,
1304 unsigned long addr,
1305 pte_t pte, pte_t oldpte,
1306 int nr)
1307{
1308
1309}
1310#else
1311/*
1312 * Some architectures support metadata associated with a page. When a
1313 * page is being swapped out, this metadata must be saved so it can be
1314 * restored when the page is swapped back in. SPARC M7 and newer
1315 * processors support an ADI (Application Data Integrity) tag for the
1316 * page as metadata for the page. arch_do_swap_page() can restore this
1317 * metadata when a page is swapped back in.
1318 */
1319static inline void arch_do_swap_page_nr(struct mm_struct *mm,
1320 struct vm_area_struct *vma,
1321 unsigned long addr,
1322 pte_t pte, pte_t oldpte,
1323 int nr)
1324{
1325 for (int i = 0; i < nr; i++) {
1326 arch_do_swap_page(vma->vm_mm, vma, addr + i * PAGE_SIZE,
1327 pte_advance_pfn(pte, i),
1328 pte_advance_pfn(oldpte, i));
1329 }
1330}
1331#endif
1332
1333#ifndef __HAVE_ARCH_UNMAP_ONE
1334/*
1335 * Some architectures support metadata associated with a page. When a
1336 * page is being swapped out, this metadata must be saved so it can be
1337 * restored when the page is swapped back in. SPARC M7 and newer
1338 * processors support an ADI (Application Data Integrity) tag for the
1339 * page as metadata for the page. arch_unmap_one() can save this
1340 * metadata on a swap-out of a page.
1341 */
1342static inline int arch_unmap_one(struct mm_struct *mm,
1343 struct vm_area_struct *vma,
1344 unsigned long addr,
1345 pte_t orig_pte)
1346{
1347 return 0;
1348}
1349#endif
1350
1351/*
1352 * Allow architectures to preserve additional metadata associated with
1353 * swapped-out pages. The corresponding __HAVE_ARCH_SWAP_* macros and function
1354 * prototypes must be defined in the arch-specific asm/pgtable.h file.
1355 */
1356#ifndef __HAVE_ARCH_PREPARE_TO_SWAP
1357static inline int arch_prepare_to_swap(struct folio *folio)
1358{
1359 return 0;
1360}
1361#endif
1362
1363#ifndef __HAVE_ARCH_SWAP_INVALIDATE
1364static inline void arch_swap_invalidate_page(int type, pgoff_t offset)
1365{
1366}
1367
1368static inline void arch_swap_invalidate_area(int type)
1369{
1370}
1371#endif
1372
1373#ifndef __HAVE_ARCH_SWAP_RESTORE
1374static inline void arch_swap_restore(swp_entry_t entry, struct folio *folio)
1375{
1376}
1377#endif
1378
1379#ifndef __HAVE_ARCH_MOVE_PTE
1380#define move_pte(pte, old_addr, new_addr) (pte)
1381#endif
1382
1383#ifndef pte_accessible
1384# define pte_accessible(mm, pte) ((void)(pte), 1)
1385#endif
1386
1387#ifndef flush_tlb_fix_spurious_fault
1388#define flush_tlb_fix_spurious_fault(vma, address, ptep) flush_tlb_page(vma, address)
1389#endif
1390
1391#ifndef flush_tlb_fix_spurious_fault_pmd
1392#define flush_tlb_fix_spurious_fault_pmd(vma, address, pmdp) do { } while (0)
1393#endif
1394
1395/*
1396 * When walking page tables, get the address of the next boundary,
1397 * or the end address of the range if that comes earlier. Although no
1398 * vma end wraps to 0, rounded up __boundary may wrap to 0 throughout.
1399 */
1400
1401#define pgd_addr_end(addr, end) \
1402({ unsigned long __boundary = ((addr) + PGDIR_SIZE) & PGDIR_MASK; \
1403 (__boundary - 1 < (end) - 1)? __boundary: (end); \
1404})
1405
1406#ifndef p4d_addr_end
1407#define p4d_addr_end(addr, end) \
1408({ unsigned long __boundary = ((addr) + P4D_SIZE) & P4D_MASK; \
1409 (__boundary - 1 < (end) - 1)? __boundary: (end); \
1410})
1411#endif
1412
1413#ifndef pud_addr_end
1414#define pud_addr_end(addr, end) \
1415({ unsigned long __boundary = ((addr) + PUD_SIZE) & PUD_MASK; \
1416 (__boundary - 1 < (end) - 1)? __boundary: (end); \
1417})
1418#endif
1419
1420#ifndef pmd_addr_end
1421#define pmd_addr_end(addr, end) \
1422({ unsigned long __boundary = ((addr) + PMD_SIZE) & PMD_MASK; \
1423 (__boundary - 1 < (end) - 1)? __boundary: (end); \
1424})
1425#endif
1426
1427/*
1428 * When walking page tables, we usually want to skip any p?d_none entries;
1429 * and any p?d_bad entries - reporting the error before resetting to none.
1430 * Do the tests inline, but report and clear the bad entry in mm/memory.c.
1431 */
1432void pgd_clear_bad(pgd_t *);
1433
1434#ifndef __PAGETABLE_P4D_FOLDED
1435void p4d_clear_bad(p4d_t *);
1436#else
1437#define p4d_clear_bad(p4d) do { } while (0)
1438#endif
1439
1440#ifndef __PAGETABLE_PUD_FOLDED
1441void pud_clear_bad(pud_t *);
1442#else
1443#define pud_clear_bad(p4d) do { } while (0)
1444#endif
1445
1446void pmd_clear_bad(pmd_t *);
1447
1448static inline int pgd_none_or_clear_bad(pgd_t *pgd)
1449{
1450 if (pgd_none(*pgd))
1451 return 1;
1452 if (unlikely(pgd_bad(*pgd))) {
1453 pgd_clear_bad(pgd);
1454 return 1;
1455 }
1456 return 0;
1457}
1458
1459static inline int p4d_none_or_clear_bad(p4d_t *p4d)
1460{
1461 if (p4d_none(*p4d))
1462 return 1;
1463 if (unlikely(p4d_bad(*p4d))) {
1464 p4d_clear_bad(p4d);
1465 return 1;
1466 }
1467 return 0;
1468}
1469
1470static inline int pud_none_or_clear_bad(pud_t *pud)
1471{
1472 if (pud_none(*pud))
1473 return 1;
1474 if (unlikely(pud_bad(*pud))) {
1475 pud_clear_bad(pud);
1476 return 1;
1477 }
1478 return 0;
1479}
1480
1481static inline int pmd_none_or_clear_bad(pmd_t *pmd)
1482{
1483 if (pmd_none(*pmd))
1484 return 1;
1485 if (unlikely(pmd_bad(*pmd))) {
1486 pmd_clear_bad(pmd);
1487 return 1;
1488 }
1489 return 0;
1490}
1491
1492static inline pte_t __ptep_modify_prot_start(struct vm_area_struct *vma,
1493 unsigned long addr,
1494 pte_t *ptep)
1495{
1496 /*
1497 * Get the current pte state, but zero it out to make it
1498 * non-present, preventing the hardware from asynchronously
1499 * updating it.
1500 */
1501 return ptep_get_and_clear(vma->vm_mm, addr, ptep);
1502}
1503
1504static inline void __ptep_modify_prot_commit(struct vm_area_struct *vma,
1505 unsigned long addr,
1506 pte_t *ptep, pte_t pte)
1507{
1508 /*
1509 * The pte is non-present, so there's no hardware state to
1510 * preserve.
1511 */
1512 set_pte_at(vma->vm_mm, addr, ptep, pte);
1513}
1514
1515#ifndef __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION
1516/*
1517 * Start a pte protection read-modify-write transaction, which
1518 * protects against asynchronous hardware modifications to the pte.
1519 * The intention is not to prevent the hardware from making pte
1520 * updates, but to prevent any updates it may make from being lost.
1521 *
1522 * This does not protect against other software modifications of the
1523 * pte; the appropriate pte lock must be held over the transaction.
1524 *
1525 * Note that this interface is intended to be batchable, meaning that
1526 * ptep_modify_prot_commit may not actually update the pte, but merely
1527 * queue the update to be done at some later time. The update must be
1528 * actually committed before the pte lock is released, however.
1529 */
1530static inline pte_t ptep_modify_prot_start(struct vm_area_struct *vma,
1531 unsigned long addr,
1532 pte_t *ptep)
1533{
1534 return __ptep_modify_prot_start(vma, addr, ptep);
1535}
1536
1537/*
1538 * Commit an update to a pte, leaving any hardware-controlled bits in
1539 * the PTE unmodified. The pte returned from ptep_modify_prot_start() may
1540 * additionally have young and/or dirty bits set where previously they were not,
1541 * so the updated pte may have these additional changes.
1542 */
1543static inline void ptep_modify_prot_commit(struct vm_area_struct *vma,
1544 unsigned long addr,
1545 pte_t *ptep, pte_t old_pte, pte_t pte)
1546{
1547 __ptep_modify_prot_commit(vma, addr, ptep, pte);
1548}
1549#endif /* __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION */
1550
1551/**
1552 * modify_prot_start_ptes - Start a pte protection read-modify-write transaction
1553 * over a batch of ptes, which protects against asynchronous hardware
1554 * modifications to the ptes. The intention is not to prevent the hardware from
1555 * making pte updates, but to prevent any updates it may make from being lost.
1556 * Please see the comment above ptep_modify_prot_start() for full description.
1557 *
1558 * @vma: The virtual memory area the pages are mapped into.
1559 * @addr: Address the first page is mapped at.
1560 * @ptep: Page table pointer for the first entry.
1561 * @nr: Number of entries.
1562 *
1563 * May be overridden by the architecture; otherwise, implemented as a simple
1564 * loop over ptep_modify_prot_start(), collecting the a/d bits from each pte
1565 * in the batch.
1566 *
1567 * Note that PTE bits in the PTE batch besides the PFN can differ.
1568 *
1569 * Context: The caller holds the page table lock. The PTEs map consecutive
1570 * pages that belong to the same folio. All other PTE bits must be identical for
1571 * all PTEs in the batch except for young and dirty bits. The PTEs are all in
1572 * the same PMD.
1573 */
1574#ifndef modify_prot_start_ptes
1575static inline pte_t modify_prot_start_ptes(struct vm_area_struct *vma,
1576 unsigned long addr, pte_t *ptep, unsigned int nr)
1577{
1578 pte_t pte, tmp_pte;
1579
1580 pte = ptep_modify_prot_start(vma, addr, ptep);
1581 while (--nr) {
1582 ptep++;
1583 addr += PAGE_SIZE;
1584 tmp_pte = ptep_modify_prot_start(vma, addr, ptep);
1585 if (pte_dirty(tmp_pte))
1586 pte = pte_mkdirty(pte);
1587 if (pte_young(tmp_pte))
1588 pte = pte_mkyoung(pte);
1589 }
1590 return pte;
1591}
1592#endif
1593
1594/**
1595 * modify_prot_commit_ptes - Commit an update to a batch of ptes, leaving any
1596 * hardware-controlled bits in the PTE unmodified.
1597 *
1598 * @vma: The virtual memory area the pages are mapped into.
1599 * @addr: Address the first page is mapped at.
1600 * @ptep: Page table pointer for the first entry.
1601 * @old_pte: Old page table entry (for the first entry) which is now cleared.
1602 * @pte: New page table entry to be set.
1603 * @nr: Number of entries.
1604 *
1605 * May be overridden by the architecture; otherwise, implemented as a simple
1606 * loop over ptep_modify_prot_commit().
1607 *
1608 * Context: The caller holds the page table lock. The PTEs are all in the same
1609 * PMD. On exit, the set ptes in the batch map the same folio. The ptes set by
1610 * ptep_modify_prot_start() may additionally have young and/or dirty bits set
1611 * where previously they were not, so the updated ptes may have these
1612 * additional changes.
1613 */
1614#ifndef modify_prot_commit_ptes
1615static inline void modify_prot_commit_ptes(struct vm_area_struct *vma, unsigned long addr,
1616 pte_t *ptep, pte_t old_pte, pte_t pte, unsigned int nr)
1617{
1618 int i;
1619
1620 for (i = 0; i < nr; ++i, ++ptep, addr += PAGE_SIZE) {
1621 ptep_modify_prot_commit(vma, addr, ptep, old_pte, pte);
1622
1623 /* Advance PFN only, set same prot */
1624 old_pte = pte_next_pfn(old_pte);
1625 pte = pte_next_pfn(pte);
1626 }
1627}
1628#endif
1629
1630/*
1631 * Architectures can set this mask to a combination of PGTBL_P?D_MODIFIED values
1632 * and let generic vmalloc, ioremap and page table update code know when
1633 * arch_sync_kernel_mappings() needs to be called.
1634 */
1635#ifndef ARCH_PAGE_TABLE_SYNC_MASK
1636#define ARCH_PAGE_TABLE_SYNC_MASK 0
1637#endif
1638
1639/*
1640 * There is no default implementation for arch_sync_kernel_mappings(). It is
1641 * relied upon the compiler to optimize calls out if ARCH_PAGE_TABLE_SYNC_MASK
1642 * is 0.
1643 */
1644void arch_sync_kernel_mappings(unsigned long start, unsigned long end);
1645
1646#endif /* CONFIG_MMU */
1647
1648/*
1649 * On almost all architectures and configurations, 0 can be used as the
1650 * upper ceiling to free_pgtables(): on many architectures it has the same
1651 * effect as using TASK_SIZE. However, there is one configuration which
1652 * must impose a more careful limit, to avoid freeing kernel pgtables.
1653 */
1654#ifndef USER_PGTABLES_CEILING
1655#define USER_PGTABLES_CEILING 0UL
1656#endif
1657
1658/*
1659 * This defines the first usable user address. Platforms
1660 * can override its value with custom FIRST_USER_ADDRESS
1661 * defined in their respective <asm/pgtable.h>.
1662 */
1663#ifndef FIRST_USER_ADDRESS
1664#define FIRST_USER_ADDRESS 0UL
1665#endif
1666
1667/*
1668 * No-op macros that just return the current protection value. Defined here
1669 * because these macros can be used even if CONFIG_MMU is not defined.
1670 */
1671
1672#ifndef pgprot_nx
1673#define pgprot_nx(prot) (prot)
1674#endif
1675
1676#ifndef pgprot_noncached
1677#define pgprot_noncached(prot) (prot)
1678#endif
1679
1680#ifndef pgprot_writecombine
1681#define pgprot_writecombine pgprot_noncached
1682#endif
1683
1684#ifndef pgprot_writethrough
1685#define pgprot_writethrough pgprot_noncached
1686#endif
1687
1688#ifndef pgprot_device
1689#define pgprot_device pgprot_noncached
1690#endif
1691
1692#ifndef pgprot_mhp
1693#define pgprot_mhp(prot) (prot)
1694#endif
1695
1696#ifdef CONFIG_MMU
1697#ifndef pgprot_modify
1698#define pgprot_modify pgprot_modify
1699static inline pgprot_t pgprot_modify(pgprot_t oldprot, pgprot_t newprot)
1700{
1701 if (pgprot_val(oldprot) == pgprot_val(pgprot_noncached(oldprot)))
1702 newprot = pgprot_noncached(newprot);
1703 if (pgprot_val(oldprot) == pgprot_val(pgprot_writecombine(oldprot)))
1704 newprot = pgprot_writecombine(newprot);
1705 if (pgprot_val(oldprot) == pgprot_val(pgprot_device(oldprot)))
1706 newprot = pgprot_device(newprot);
1707 return newprot;
1708}
1709#endif
1710#endif /* CONFIG_MMU */
1711
1712#ifndef pgprot_encrypted
1713#define pgprot_encrypted(prot) (prot)
1714#endif
1715
1716#ifndef pgprot_decrypted
1717#define pgprot_decrypted(prot) (prot)
1718#endif
1719
1720/*
1721 * A facility to provide batching of the reload of page tables and
1722 * other process state with the actual context switch code for
1723 * paravirtualized guests. By convention, only one of the batched
1724 * update (lazy) modes (CPU, MMU) should be active at any given time,
1725 * entry should never be nested, and entry and exits should always be
1726 * paired. This is for sanity of maintaining and reasoning about the
1727 * kernel code. In this case, the exit (end of the context switch) is
1728 * in architecture-specific code, and so doesn't need a generic
1729 * definition.
1730 */
1731#ifndef __HAVE_ARCH_START_CONTEXT_SWITCH
1732#define arch_start_context_switch(prev) do {} while (0)
1733#endif
1734
1735/*
1736 * Some platforms can customize the PTE soft-dirty bit making it unavailable
1737 * even if the architecture provides the resource.
1738 * Adding this API allows architectures to add their own checks for the
1739 * devices on which the kernel is running.
1740 * Note: When overriding it, please make sure the CONFIG_MEM_SOFT_DIRTY
1741 * is part of this macro.
1742 */
1743#ifndef pgtable_supports_soft_dirty
1744#define pgtable_supports_soft_dirty() IS_ENABLED(CONFIG_MEM_SOFT_DIRTY)
1745#endif
1746
1747#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
1748#ifndef CONFIG_ARCH_ENABLE_THP_MIGRATION
1749static inline pmd_t pmd_swp_mksoft_dirty(pmd_t pmd)
1750{
1751 return pmd;
1752}
1753
1754static inline int pmd_swp_soft_dirty(pmd_t pmd)
1755{
1756 return 0;
1757}
1758
1759static inline pmd_t pmd_swp_clear_soft_dirty(pmd_t pmd)
1760{
1761 return pmd;
1762}
1763#endif
1764#else /* !CONFIG_HAVE_ARCH_SOFT_DIRTY */
1765static inline int pte_soft_dirty(pte_t pte)
1766{
1767 return 0;
1768}
1769
1770static inline int pmd_soft_dirty(pmd_t pmd)
1771{
1772 return 0;
1773}
1774
1775static inline pte_t pte_mksoft_dirty(pte_t pte)
1776{
1777 return pte;
1778}
1779
1780static inline pmd_t pmd_mksoft_dirty(pmd_t pmd)
1781{
1782 return pmd;
1783}
1784
1785static inline pte_t pte_clear_soft_dirty(pte_t pte)
1786{
1787 return pte;
1788}
1789
1790static inline pmd_t pmd_clear_soft_dirty(pmd_t pmd)
1791{
1792 return pmd;
1793}
1794
1795static inline pte_t pte_swp_mksoft_dirty(pte_t pte)
1796{
1797 return pte;
1798}
1799
1800static inline int pte_swp_soft_dirty(pte_t pte)
1801{
1802 return 0;
1803}
1804
1805static inline pte_t pte_swp_clear_soft_dirty(pte_t pte)
1806{
1807 return pte;
1808}
1809
1810static inline pmd_t pmd_swp_mksoft_dirty(pmd_t pmd)
1811{
1812 return pmd;
1813}
1814
1815static inline int pmd_swp_soft_dirty(pmd_t pmd)
1816{
1817 return 0;
1818}
1819
1820static inline pmd_t pmd_swp_clear_soft_dirty(pmd_t pmd)
1821{
1822 return pmd;
1823}
1824#endif
1825
1826#ifndef __HAVE_PFNMAP_TRACKING
1827/*
1828 * Interfaces that can be used by architecture code to keep track of
1829 * memory type of pfn mappings specified by the remap_pfn_range,
1830 * vmf_insert_pfn.
1831 */
1832
1833static inline int pfnmap_setup_cachemode(unsigned long pfn, unsigned long size,
1834 pgprot_t *prot)
1835{
1836 return 0;
1837}
1838
1839static inline int pfnmap_track(unsigned long pfn, unsigned long size,
1840 pgprot_t *prot)
1841{
1842 return 0;
1843}
1844
1845static inline void pfnmap_untrack(unsigned long pfn, unsigned long size)
1846{
1847}
1848#else
1849/**
1850 * pfnmap_setup_cachemode - setup the cachemode in the pgprot for a pfn range
1851 * @pfn: the start of the pfn range
1852 * @size: the size of the pfn range in bytes
1853 * @prot: the pgprot to modify
1854 *
1855 * Lookup the cachemode for the pfn range starting at @pfn with the size
1856 * @size and store it in @prot, leaving other data in @prot unchanged.
1857 *
1858 * This allows for a hardware implementation to have fine-grained control of
1859 * memory cache behavior at page level granularity. Without a hardware
1860 * implementation, this function does nothing.
1861 *
1862 * Currently there is only one implementation for this - x86 Page Attribute
1863 * Table (PAT). See Documentation/arch/x86/pat.rst for more details.
1864 *
1865 * This function can fail if the pfn range spans pfns that require differing
1866 * cachemodes. If the pfn range was previously verified to have a single
1867 * cachemode, it is sufficient to query only a single pfn. The assumption is
1868 * that this is the case for drivers using the vmf_insert_pfn*() interface.
1869 *
1870 * Returns 0 on success and -EINVAL on error.
1871 */
1872int pfnmap_setup_cachemode(unsigned long pfn, unsigned long size,
1873 pgprot_t *prot);
1874
1875/**
1876 * pfnmap_track - track a pfn range
1877 * @pfn: the start of the pfn range
1878 * @size: the size of the pfn range in bytes
1879 * @prot: the pgprot to track
1880 *
1881 * Requested the pfn range to be 'tracked' by a hardware implementation and
1882 * setup the cachemode in @prot similar to pfnmap_setup_cachemode().
1883 *
1884 * This allows for fine-grained control of memory cache behaviour at page
1885 * level granularity. Tracking memory this way is persisted across VMA splits
1886 * (VMA merging does not apply for VM_PFNMAP).
1887 *
1888 * Currently, there is only one implementation for this - x86 Page Attribute
1889 * Table (PAT). See Documentation/arch/x86/pat.rst for more details.
1890 *
1891 * Returns 0 on success and -EINVAL on error.
1892 */
1893int pfnmap_track(unsigned long pfn, unsigned long size, pgprot_t *prot);
1894
1895/**
1896 * pfnmap_untrack - untrack a pfn range
1897 * @pfn: the start of the pfn range
1898 * @size: the size of the pfn range in bytes
1899 *
1900 * Untrack a pfn range previously tracked through pfnmap_track().
1901 */
1902void pfnmap_untrack(unsigned long pfn, unsigned long size);
1903#endif
1904
1905/**
1906 * pfnmap_setup_cachemode_pfn - setup the cachemode in the pgprot for a pfn
1907 * @pfn: the pfn
1908 * @prot: the pgprot to modify
1909 *
1910 * Lookup the cachemode for @pfn and store it in @prot, leaving other
1911 * data in @prot unchanged.
1912 *
1913 * See pfnmap_setup_cachemode() for details.
1914 */
1915static inline void pfnmap_setup_cachemode_pfn(unsigned long pfn, pgprot_t *prot)
1916{
1917 pfnmap_setup_cachemode(pfn, PAGE_SIZE, prot);
1918}
1919
1920#ifdef CONFIG_MMU
1921#ifdef __HAVE_COLOR_ZERO_PAGE
1922static inline int is_zero_pfn(unsigned long pfn)
1923{
1924 extern unsigned long zero_pfn;
1925 unsigned long offset_from_zero_pfn = pfn - zero_pfn;
1926 return offset_from_zero_pfn <= (zero_page_mask >> PAGE_SHIFT);
1927}
1928
1929#define my_zero_pfn(addr) page_to_pfn(ZERO_PAGE(addr))
1930
1931#else
1932static inline int is_zero_pfn(unsigned long pfn)
1933{
1934 extern unsigned long zero_pfn;
1935 return pfn == zero_pfn;
1936}
1937
1938static inline unsigned long my_zero_pfn(unsigned long addr)
1939{
1940 extern unsigned long zero_pfn;
1941 return zero_pfn;
1942}
1943#endif
1944#else
1945static inline int is_zero_pfn(unsigned long pfn)
1946{
1947 return 0;
1948}
1949
1950static inline unsigned long my_zero_pfn(unsigned long addr)
1951{
1952 return 0;
1953}
1954#endif /* CONFIG_MMU */
1955
1956#ifdef CONFIG_MMU
1957
1958#ifndef CONFIG_TRANSPARENT_HUGEPAGE
1959static inline int pmd_trans_huge(pmd_t pmd)
1960{
1961 return 0;
1962}
1963#ifndef pmd_write
1964static inline int pmd_write(pmd_t pmd)
1965{
1966 BUG();
1967 return 0;
1968}
1969#endif /* pmd_write */
1970#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
1971
1972#ifndef pud_write
1973static inline int pud_write(pud_t pud)
1974{
1975 BUG();
1976 return 0;
1977}
1978#endif /* pud_write */
1979
1980#if !defined(CONFIG_TRANSPARENT_HUGEPAGE) || \
1981 !defined(CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD)
1982static inline int pud_trans_huge(pud_t pud)
1983{
1984 return 0;
1985}
1986#endif
1987
1988static inline int pud_trans_unstable(pud_t *pud)
1989{
1990#if defined(CONFIG_TRANSPARENT_HUGEPAGE) && \
1991 defined(CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD)
1992 pud_t pudval = READ_ONCE(*pud);
1993
1994 if (pud_none(pudval) || pud_trans_huge(pudval))
1995 return 1;
1996 if (unlikely(pud_bad(pudval))) {
1997 pud_clear_bad(pud);
1998 return 1;
1999 }
2000#endif
2001 return 0;
2002}
2003
2004#ifndef CONFIG_NUMA_BALANCING
2005/*
2006 * In an inaccessible (PROT_NONE) VMA, pte_protnone() may indicate "yes". It is
2007 * perfectly valid to indicate "no" in that case, which is why our default
2008 * implementation defaults to "always no".
2009 *
2010 * In an accessible VMA, however, pte_protnone() reliably indicates PROT_NONE
2011 * page protection due to NUMA hinting. NUMA hinting faults only apply in
2012 * accessible VMAs.
2013 *
2014 * So, to reliably identify PROT_NONE PTEs that require a NUMA hinting fault,
2015 * looking at the VMA accessibility is sufficient.
2016 */
2017static inline int pte_protnone(pte_t pte)
2018{
2019 return 0;
2020}
2021
2022static inline int pmd_protnone(pmd_t pmd)
2023{
2024 return 0;
2025}
2026#endif /* CONFIG_NUMA_BALANCING */
2027
2028#endif /* CONFIG_MMU */
2029
2030#ifdef CONFIG_HAVE_ARCH_HUGE_VMAP
2031
2032#ifndef __PAGETABLE_P4D_FOLDED
2033int p4d_set_huge(p4d_t *p4d, phys_addr_t addr, pgprot_t prot);
2034void p4d_clear_huge(p4d_t *p4d);
2035#else
2036static inline int p4d_set_huge(p4d_t *p4d, phys_addr_t addr, pgprot_t prot)
2037{
2038 return 0;
2039}
2040static inline void p4d_clear_huge(p4d_t *p4d) { }
2041#endif /* !__PAGETABLE_P4D_FOLDED */
2042
2043int pud_set_huge(pud_t *pud, phys_addr_t addr, pgprot_t prot);
2044int pmd_set_huge(pmd_t *pmd, phys_addr_t addr, pgprot_t prot);
2045int pud_clear_huge(pud_t *pud);
2046int pmd_clear_huge(pmd_t *pmd);
2047int p4d_free_pud_page(p4d_t *p4d, unsigned long addr);
2048int pud_free_pmd_page(pud_t *pud, unsigned long addr);
2049int pmd_free_pte_page(pmd_t *pmd, unsigned long addr);
2050#else /* !CONFIG_HAVE_ARCH_HUGE_VMAP */
2051static inline int p4d_set_huge(p4d_t *p4d, phys_addr_t addr, pgprot_t prot)
2052{
2053 return 0;
2054}
2055static inline int pud_set_huge(pud_t *pud, phys_addr_t addr, pgprot_t prot)
2056{
2057 return 0;
2058}
2059static inline int pmd_set_huge(pmd_t *pmd, phys_addr_t addr, pgprot_t prot)
2060{
2061 return 0;
2062}
2063static inline void p4d_clear_huge(p4d_t *p4d) { }
2064static inline int pud_clear_huge(pud_t *pud)
2065{
2066 return 0;
2067}
2068static inline int pmd_clear_huge(pmd_t *pmd)
2069{
2070 return 0;
2071}
2072static inline int p4d_free_pud_page(p4d_t *p4d, unsigned long addr)
2073{
2074 return 0;
2075}
2076static inline int pud_free_pmd_page(pud_t *pud, unsigned long addr)
2077{
2078 return 0;
2079}
2080static inline int pmd_free_pte_page(pmd_t *pmd, unsigned long addr)
2081{
2082 return 0;
2083}
2084#endif /* CONFIG_HAVE_ARCH_HUGE_VMAP */
2085
2086#ifndef __HAVE_ARCH_FLUSH_PMD_TLB_RANGE
2087#ifdef CONFIG_TRANSPARENT_HUGEPAGE
2088/*
2089 * ARCHes with special requirements for evicting THP backing TLB entries can
2090 * implement this. Otherwise also, it can help optimize normal TLB flush in
2091 * THP regime. Stock flush_tlb_range() typically has optimization to nuke the
2092 * entire TLB if flush span is greater than a threshold, which will
2093 * likely be true for a single huge page. Thus a single THP flush will
2094 * invalidate the entire TLB which is not desirable.
2095 * e.g. see arch/arc: flush_pmd_tlb_range
2096 */
2097#define flush_pmd_tlb_range(vma, addr, end) flush_tlb_range(vma, addr, end)
2098#define flush_pud_tlb_range(vma, addr, end) flush_tlb_range(vma, addr, end)
2099#else
2100#define flush_pmd_tlb_range(vma, addr, end) BUILD_BUG()
2101#define flush_pud_tlb_range(vma, addr, end) BUILD_BUG()
2102#endif
2103#endif
2104
2105struct file;
2106int phys_mem_access_prot_allowed(struct file *file, unsigned long pfn,
2107 unsigned long size, pgprot_t *vma_prot);
2108
2109#ifndef CONFIG_X86_ESPFIX64
2110static inline void init_espfix_bsp(void) { }
2111#endif
2112
2113extern void __init pgtable_cache_init(void);
2114
2115#ifndef __HAVE_ARCH_PFN_MODIFY_ALLOWED
2116static inline bool pfn_modify_allowed(unsigned long pfn, pgprot_t prot)
2117{
2118 return true;
2119}
2120
2121static inline bool arch_has_pfn_modify_check(void)
2122{
2123 return false;
2124}
2125#endif /* !_HAVE_ARCH_PFN_MODIFY_ALLOWED */
2126
2127/*
2128 * Architecture PAGE_KERNEL_* fallbacks
2129 *
2130 * Some architectures don't define certain PAGE_KERNEL_* flags. This is either
2131 * because they really don't support them, or the port needs to be updated to
2132 * reflect the required functionality. Below are a set of relatively safe
2133 * fallbacks, as best effort, which we can count on in lieu of the architectures
2134 * not defining them on their own yet.
2135 */
2136
2137#ifndef PAGE_KERNEL_RO
2138# define PAGE_KERNEL_RO PAGE_KERNEL
2139#endif
2140
2141#ifndef PAGE_KERNEL_EXEC
2142# define PAGE_KERNEL_EXEC PAGE_KERNEL
2143#endif
2144
2145/*
2146 * Page Table Modification bits for pgtbl_mod_mask.
2147 *
2148 * These are used by the p?d_alloc_track*() and p*d_populate_kernel()
2149 * functions in the generic vmalloc, ioremap and page table update code
2150 * to track at which page-table levels entries have been modified.
2151 * Based on that the code can better decide when page table changes need
2152 * to be synchronized to other page-tables in the system.
2153 */
2154#define __PGTBL_PGD_MODIFIED 0
2155#define __PGTBL_P4D_MODIFIED 1
2156#define __PGTBL_PUD_MODIFIED 2
2157#define __PGTBL_PMD_MODIFIED 3
2158#define __PGTBL_PTE_MODIFIED 4
2159
2160#define PGTBL_PGD_MODIFIED BIT(__PGTBL_PGD_MODIFIED)
2161#define PGTBL_P4D_MODIFIED BIT(__PGTBL_P4D_MODIFIED)
2162#define PGTBL_PUD_MODIFIED BIT(__PGTBL_PUD_MODIFIED)
2163#define PGTBL_PMD_MODIFIED BIT(__PGTBL_PMD_MODIFIED)
2164#define PGTBL_PTE_MODIFIED BIT(__PGTBL_PTE_MODIFIED)
2165
2166/* Page-Table Modification Mask */
2167typedef unsigned int pgtbl_mod_mask;
2168
2169enum pgtable_level {
2170 PGTABLE_LEVEL_PTE = 0,
2171 PGTABLE_LEVEL_PMD,
2172 PGTABLE_LEVEL_PUD,
2173 PGTABLE_LEVEL_P4D,
2174 PGTABLE_LEVEL_PGD,
2175};
2176
2177static inline const char *pgtable_level_to_str(enum pgtable_level level)
2178{
2179 switch (level) {
2180 case PGTABLE_LEVEL_PTE:
2181 return "pte";
2182 case PGTABLE_LEVEL_PMD:
2183 return "pmd";
2184 case PGTABLE_LEVEL_PUD:
2185 return "pud";
2186 case PGTABLE_LEVEL_P4D:
2187 return "p4d";
2188 case PGTABLE_LEVEL_PGD:
2189 return "pgd";
2190 default:
2191 return "unknown";
2192 }
2193}
2194
2195#endif /* !__ASSEMBLY__ */
2196
2197#if !defined(MAX_POSSIBLE_PHYSMEM_BITS) && !defined(CONFIG_64BIT)
2198#ifdef CONFIG_PHYS_ADDR_T_64BIT
2199/*
2200 * ZSMALLOC needs to know the highest PFN on 32-bit architectures
2201 * with physical address space extension, but falls back to
2202 * BITS_PER_LONG otherwise.
2203 */
2204#error Missing MAX_POSSIBLE_PHYSMEM_BITS definition
2205#else
2206#define MAX_POSSIBLE_PHYSMEM_BITS 32
2207#endif
2208#endif
2209
2210#ifndef has_transparent_hugepage
2211#define has_transparent_hugepage() IS_BUILTIN(CONFIG_TRANSPARENT_HUGEPAGE)
2212#endif
2213
2214#ifndef has_transparent_pud_hugepage
2215#define has_transparent_pud_hugepage() IS_BUILTIN(CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD)
2216#endif
2217/*
2218 * On some architectures it depends on the mm if the p4d/pud or pmd
2219 * layer of the page table hierarchy is folded or not.
2220 */
2221#ifndef mm_p4d_folded
2222#define mm_p4d_folded(mm) __is_defined(__PAGETABLE_P4D_FOLDED)
2223#endif
2224
2225#ifndef mm_pud_folded
2226#define mm_pud_folded(mm) __is_defined(__PAGETABLE_PUD_FOLDED)
2227#endif
2228
2229#ifndef mm_pmd_folded
2230#define mm_pmd_folded(mm) __is_defined(__PAGETABLE_PMD_FOLDED)
2231#endif
2232
2233#ifndef p4d_offset_lockless
2234#define p4d_offset_lockless(pgdp, pgd, address) p4d_offset(&(pgd), address)
2235#endif
2236#ifndef pud_offset_lockless
2237#define pud_offset_lockless(p4dp, p4d, address) pud_offset(&(p4d), address)
2238#endif
2239#ifndef pmd_offset_lockless
2240#define pmd_offset_lockless(pudp, pud, address) pmd_offset(&(pud), address)
2241#endif
2242
2243/*
2244 * pXd_leaf() is the API to check whether a pgtable entry is a huge page
2245 * mapping. It should work globally across all archs, without any
2246 * dependency on CONFIG_* options. For architectures that do not support
2247 * huge mappings on specific levels, below fallbacks will be used.
2248 *
2249 * A leaf pgtable entry should always imply the following:
2250 *
2251 * - It is a "present" entry. IOW, before using this API, please check it
2252 * with pXd_present() first. NOTE: it may not always mean the "present
2253 * bit" is set. For example, PROT_NONE entries are always "present".
2254 *
2255 * - It should _never_ be a swap entry of any type. Above "present" check
2256 * should have guarded this, but let's be crystal clear on this.
2257 *
2258 * - It should contain a huge PFN, which points to a huge page larger than
2259 * PAGE_SIZE of the platform. The PFN format isn't important here.
2260 *
2261 * - It should cover all kinds of huge mappings (i.e. pXd_trans_huge()
2262 * or hugetlb mappings).
2263 */
2264#ifndef pgd_leaf
2265#define pgd_leaf(x) false
2266#endif
2267#ifndef p4d_leaf
2268#define p4d_leaf(x) false
2269#endif
2270#ifndef pud_leaf
2271#define pud_leaf(x) false
2272#endif
2273#ifndef pmd_leaf
2274#define pmd_leaf(x) false
2275#endif
2276
2277#ifndef pgd_leaf_size
2278#define pgd_leaf_size(x) (1ULL << PGDIR_SHIFT)
2279#endif
2280#ifndef p4d_leaf_size
2281#define p4d_leaf_size(x) P4D_SIZE
2282#endif
2283#ifndef pud_leaf_size
2284#define pud_leaf_size(x) PUD_SIZE
2285#endif
2286#ifndef pmd_leaf_size
2287#define pmd_leaf_size(x) PMD_SIZE
2288#endif
2289#ifndef __pte_leaf_size
2290#ifndef pte_leaf_size
2291#define pte_leaf_size(x) PAGE_SIZE
2292#endif
2293#define __pte_leaf_size(x,y) pte_leaf_size(y)
2294#endif
2295
2296/*
2297 * We always define pmd_pfn for all archs as it's used in lots of generic
2298 * code. Now it happens too for pud_pfn (and can happen for larger
2299 * mappings too in the future; we're not there yet). Instead of defining
2300 * it for all archs (like pmd_pfn), provide a fallback.
2301 *
2302 * Note that returning 0 here means any arch that didn't define this can
2303 * get severely wrong when it hits a real pud leaf. It's arch's
2304 * responsibility to properly define it when a huge pud is possible.
2305 */
2306#ifndef pud_pfn
2307#define pud_pfn(x) 0
2308#endif
2309
2310/*
2311 * Some architectures have MMUs that are configurable or selectable at boot
2312 * time. These lead to variable PTRS_PER_x. For statically allocated arrays it
2313 * helps to have a static maximum value.
2314 */
2315
2316#ifndef MAX_PTRS_PER_PTE
2317#define MAX_PTRS_PER_PTE PTRS_PER_PTE
2318#endif
2319
2320#ifndef MAX_PTRS_PER_PMD
2321#define MAX_PTRS_PER_PMD PTRS_PER_PMD
2322#endif
2323
2324#ifndef MAX_PTRS_PER_PUD
2325#define MAX_PTRS_PER_PUD PTRS_PER_PUD
2326#endif
2327
2328#ifndef MAX_PTRS_PER_P4D
2329#define MAX_PTRS_PER_P4D PTRS_PER_P4D
2330#endif
2331
2332#ifndef pte_pgprot
2333#define pte_pgprot(x) ((pgprot_t) {0})
2334#endif
2335
2336#ifndef pmd_pgprot
2337#define pmd_pgprot(x) ((pgprot_t) {0})
2338#endif
2339
2340#ifndef pud_pgprot
2341#define pud_pgprot(x) ((pgprot_t) {0})
2342#endif
2343
2344/* description of effects of mapping type and prot in current implementation.
2345 * this is due to the limited x86 page protection hardware. The expected
2346 * behavior is in parens:
2347 *
2348 * map_type prot
2349 * PROT_NONE PROT_READ PROT_WRITE PROT_EXEC
2350 * MAP_SHARED r: (no) no r: (yes) yes r: (no) yes r: (no) yes
2351 * w: (no) no w: (no) no w: (yes) yes w: (no) no
2352 * x: (no) no x: (no) yes x: (no) yes x: (yes) yes
2353 *
2354 * MAP_PRIVATE r: (no) no r: (yes) yes r: (no) yes r: (no) yes
2355 * w: (no) no w: (no) no w: (copy) copy w: (no) no
2356 * x: (no) no x: (no) yes x: (no) yes x: (yes) yes
2357 *
2358 * On arm64, PROT_EXEC has the following behaviour for both MAP_SHARED and
2359 * MAP_PRIVATE (with Enhanced PAN supported):
2360 * r: (no) no
2361 * w: (no) no
2362 * x: (yes) yes
2363 */
2364#define DECLARE_VM_GET_PAGE_PROT \
2365pgprot_t vm_get_page_prot(vm_flags_t vm_flags) \
2366{ \
2367 return protection_map[vm_flags & \
2368 (VM_READ | VM_WRITE | VM_EXEC | VM_SHARED)]; \
2369} \
2370EXPORT_SYMBOL(vm_get_page_prot);
2371
2372#endif /* _LINUX_PGTABLE_H */