Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/* SPDX-License-Identifier: GPL-2.0 */
2
3#ifndef __LINUX_GPIO_GENERIC_H
4#define __LINUX_GPIO_GENERIC_H
5
6#include <linux/bits.h>
7#include <linux/bug.h>
8#include <linux/cleanup.h>
9#include <linux/container_of.h>
10#include <linux/errno.h>
11#include <linux/spinlock.h>
12#include <linux/types.h>
13
14#include <linux/gpio/driver.h>
15
16struct device;
17
18#define GPIO_GENERIC_BIG_ENDIAN BIT(0)
19#define GPIO_GENERIC_UNREADABLE_REG_SET BIT(1) /* reg_set is unreadable */
20#define GPIO_GENERIC_UNREADABLE_REG_DIR BIT(2) /* reg_dir is unreadable */
21#define GPIO_GENERIC_BIG_ENDIAN_BYTE_ORDER BIT(3)
22#define GPIO_GENERIC_READ_OUTPUT_REG_SET BIT(4) /* reg_set stores output value */
23#define GPIO_GENERIC_NO_OUTPUT BIT(5) /* only input */
24#define GPIO_GENERIC_NO_SET_ON_INPUT BIT(6)
25#define GPIO_GENERIC_PINCTRL_BACKEND BIT(7) /* Call pinctrl direction setters */
26#define GPIO_GENERIC_NO_INPUT BIT(8) /* only output */
27
28/**
29 * struct gpio_generic_chip_config - Generic GPIO chip configuration data
30 * @dev: Parent device of the new GPIO chip (compulsory).
31 * @sz: Size (width) of the MMIO registers in bytes, typically 1, 2 or 4.
32 * @dat: MMIO address for the register to READ the value of the GPIO lines, it
33 * is expected that a 1 in the corresponding bit in this register means
34 * the line is asserted.
35 * @set: MMIO address for the register to SET the value of the GPIO lines, it
36 * is expected that we write the line with 1 in this register to drive
37 * the GPIO line high.
38 * @clr: MMIO address for the register to CLEAR the value of the GPIO lines,
39 * it is expected that we write the line with 1 in this register to
40 * drive the GPIO line low. It is allowed to leave this address as NULL,
41 * in that case the SET register will be assumed to also clear the GPIO
42 * lines, by actively writing the line with 0.
43 * @dirout: MMIO address for the register to set the line as OUTPUT. It is
44 * assumed that setting a line to 1 in this register will turn that
45 * line into an output line. Conversely, setting the line to 0 will
46 * turn that line into an input.
47 * @dirin: MMIO address for the register to set this line as INPUT. It is
48 * assumed that setting a line to 1 in this register will turn that
49 * line into an input line. Conversely, setting the line to 0 will
50 * turn that line into an output.
51 * @flags: Different flags that will affect the behaviour of the device, such
52 * as endianness etc.
53 */
54struct gpio_generic_chip_config {
55 struct device *dev;
56 unsigned long sz;
57 void __iomem *dat;
58 void __iomem *set;
59 void __iomem *clr;
60 void __iomem *dirout;
61 void __iomem *dirin;
62 unsigned long flags;
63};
64
65/**
66 * struct gpio_generic_chip - Generic GPIO chip implementation.
67 * @gc: The underlying struct gpio_chip object, implementing low-level GPIO
68 * chip routines.
69 * @read_reg: reader function for generic GPIO
70 * @write_reg: writer function for generic GPIO
71 * @be_bits: if the generic GPIO has big endian bit order (bit 31 is
72 * representing line 0, bit 30 is line 1 ... bit 0 is line 31) this
73 * is set to true by the generic GPIO core. It is for internal
74 * housekeeping only.
75 * @reg_dat: data (in) register for generic GPIO
76 * @reg_set: output set register (out=high) for generic GPIO
77 * @reg_clr: output clear register (out=low) for generic GPIO
78 * @reg_dir_out: direction out setting register for generic GPIO
79 * @reg_dir_in: direction in setting register for generic GPIO
80 * @dir_unreadable: indicates that the direction register(s) cannot be read and
81 * we need to rely on out internal state tracking.
82 * @pinctrl: the generic GPIO uses a pin control backend.
83 * @bits: number of register bits used for a generic GPIO
84 * i.e. <register width> * 8
85 * @lock: used to lock chip->sdata. Also, this is needed to keep
86 * shadowed and real data registers writes together.
87 * @sdata: shadowed data register for generic GPIO to clear/set bits safely.
88 * @sdir: shadowed direction register for generic GPIO to clear/set direction
89 * safely. A "1" in this word means the line is set as output.
90 */
91struct gpio_generic_chip {
92 struct gpio_chip gc;
93 unsigned long (*read_reg)(void __iomem *reg);
94 void (*write_reg)(void __iomem *reg, unsigned long data);
95 bool be_bits;
96 void __iomem *reg_dat;
97 void __iomem *reg_set;
98 void __iomem *reg_clr;
99 void __iomem *reg_dir_out;
100 void __iomem *reg_dir_in;
101 bool dir_unreadable;
102 bool pinctrl;
103 int bits;
104 raw_spinlock_t lock;
105 unsigned long sdata;
106 unsigned long sdir;
107};
108
109static inline struct gpio_generic_chip *
110to_gpio_generic_chip(struct gpio_chip *gc)
111{
112 return container_of(gc, struct gpio_generic_chip, gc);
113}
114
115int gpio_generic_chip_init(struct gpio_generic_chip *chip,
116 const struct gpio_generic_chip_config *cfg);
117
118/**
119 * gpio_generic_chip_set() - Set the GPIO line value of the generic GPIO chip.
120 * @chip: Generic GPIO chip to use.
121 * @offset: Hardware offset of the line to set.
122 * @value: New GPIO line value.
123 *
124 * Some modules using the generic GPIO chip, need to set line values in their
125 * direction setters but they don't have access to the gpio-mmio symbols so
126 * they use the function pointer in struct gpio_chip directly. This is not
127 * optimal and can lead to crashes at run-time in some instances. This wrapper
128 * provides a safe interface for users.
129 *
130 * Returns: 0 on success, negative error number of failure.
131 */
132static inline int
133gpio_generic_chip_set(struct gpio_generic_chip *chip, unsigned int offset,
134 int value)
135{
136 if (WARN_ON(!chip->gc.set))
137 return -EOPNOTSUPP;
138
139 return chip->gc.set(&chip->gc, offset, value);
140}
141
142/**
143 * gpio_generic_read_reg() - Read a register using the underlying callback.
144 * @chip: Generic GPIO chip to use.
145 * @reg: Register to read.
146 *
147 * Returns: value read from register.
148 */
149static inline unsigned long
150gpio_generic_read_reg(struct gpio_generic_chip *chip, void __iomem *reg)
151{
152 if (WARN_ON(!chip->read_reg))
153 return 0;
154
155 return chip->read_reg(reg);
156}
157
158/**
159 * gpio_generic_write_reg() - Write a register using the underlying callback.
160 * @chip: Generic GPIO chip to use.
161 * @reg: Register to write to.
162 * @val: New value to write.
163 */
164static inline void gpio_generic_write_reg(struct gpio_generic_chip *chip,
165 void __iomem *reg, unsigned long val)
166{
167 if (WARN_ON(!chip->write_reg))
168 return;
169
170 chip->write_reg(reg, val);
171}
172
173#define gpio_generic_chip_lock(gen_gc) \
174 raw_spin_lock(&(gen_gc)->lock)
175
176#define gpio_generic_chip_unlock(gen_gc) \
177 raw_spin_unlock(&(gen_gc)->lock)
178
179#define gpio_generic_chip_lock_irqsave(gen_gc, flags) \
180 raw_spin_lock_irqsave(&(gen_gc)->lock, flags)
181
182#define gpio_generic_chip_unlock_irqrestore(gen_gc, flags) \
183 raw_spin_unlock_irqrestore(&(gen_gc)->lock, flags)
184
185DEFINE_LOCK_GUARD_1(gpio_generic_lock,
186 struct gpio_generic_chip,
187 gpio_generic_chip_lock(_T->lock),
188 gpio_generic_chip_unlock(_T->lock))
189
190DEFINE_LOCK_GUARD_1(gpio_generic_lock_irqsave,
191 struct gpio_generic_chip,
192 gpio_generic_chip_lock_irqsave(_T->lock, _T->flags),
193 gpio_generic_chip_unlock_irqrestore(_T->lock, _T->flags),
194 unsigned long flags)
195
196#endif /* __LINUX_GPIO_GENERIC_H */