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1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com>
4 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
5 */
6#ifndef __LINUX_CLK_PROVIDER_H
7#define __LINUX_CLK_PROVIDER_H
8
9#include <linux/of.h>
10#include <linux/of_clk.h>
11
12/*
13 * flags used across common struct clk. these flags should only affect the
14 * top-level framework. custom flags for dealing with hardware specifics
15 * belong in struct clk_foo
16 *
17 * Please update clk_flags[] in drivers/clk/clk.c when making changes here!
18 */
19#define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */
20#define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */
21#define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */
22#define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */
23 /* unused */
24 /* unused */
25#define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */
26#define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
27#define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */
28#define CLK_RECALC_NEW_RATES BIT(9) /* recalc rates after notifications */
29#define CLK_SET_RATE_UNGATE BIT(10) /* clock needs to run to set rate */
30#define CLK_IS_CRITICAL BIT(11) /* do not gate, ever */
31/* parents need enable during gate/ungate, set rate and re-parent */
32#define CLK_OPS_PARENT_ENABLE BIT(12)
33/* duty cycle call may be forwarded to the parent clock */
34#define CLK_DUTY_CYCLE_PARENT BIT(13)
35
36struct clk;
37struct clk_hw;
38struct clk_core;
39struct dentry;
40
41/**
42 * struct clk_rate_request - Structure encoding the clk constraints that
43 * a clock user might require.
44 *
45 * Should be initialized by calling clk_hw_init_rate_request().
46 *
47 * @core: Pointer to the struct clk_core affected by this request
48 * @rate: Requested clock rate. This field will be adjusted by
49 * clock drivers according to hardware capabilities.
50 * @min_rate: Minimum rate imposed by clk users.
51 * @max_rate: Maximum rate imposed by clk users.
52 * @best_parent_rate: The best parent rate a parent can provide to fulfill the
53 * requested constraints.
54 * @best_parent_hw: The most appropriate parent clock that fulfills the
55 * requested constraints.
56 *
57 */
58struct clk_rate_request {
59 struct clk_core *core;
60 unsigned long rate;
61 unsigned long min_rate;
62 unsigned long max_rate;
63 unsigned long best_parent_rate;
64 struct clk_hw *best_parent_hw;
65};
66
67void clk_hw_init_rate_request(const struct clk_hw *hw,
68 struct clk_rate_request *req,
69 unsigned long rate);
70void clk_hw_forward_rate_request(const struct clk_hw *core,
71 const struct clk_rate_request *old_req,
72 const struct clk_hw *parent,
73 struct clk_rate_request *req,
74 unsigned long parent_rate);
75
76/**
77 * struct clk_duty - Structure encoding the duty cycle ratio of a clock
78 *
79 * @num: Numerator of the duty cycle ratio
80 * @den: Denominator of the duty cycle ratio
81 */
82struct clk_duty {
83 unsigned int num;
84 unsigned int den;
85};
86
87/**
88 * struct clk_ops - Callback operations for hardware clocks; these are to
89 * be provided by the clock implementation, and will be called by drivers
90 * through the clk_* api.
91 *
92 * @prepare: Prepare the clock for enabling. This must not return until
93 * the clock is fully prepared, and it's safe to call clk_enable.
94 * This callback is intended to allow clock implementations to
95 * do any initialisation that may sleep. Called with
96 * prepare_lock held.
97 *
98 * @unprepare: Release the clock from its prepared state. This will typically
99 * undo any work done in the @prepare callback. Called with
100 * prepare_lock held.
101 *
102 * @is_prepared: Queries the hardware to determine if the clock is prepared.
103 * This function is allowed to sleep. Optional, if this op is not
104 * set then the prepare count will be used.
105 *
106 * @unprepare_unused: Unprepare the clock atomically. Only called from
107 * clk_disable_unused for prepare clocks with special needs.
108 * Called with prepare mutex held. This function may sleep.
109 *
110 * @enable: Enable the clock atomically. This must not return until the
111 * clock is generating a valid clock signal, usable by consumer
112 * devices. Called with enable_lock held. This function must not
113 * sleep.
114 *
115 * @disable: Disable the clock atomically. Called with enable_lock held.
116 * This function must not sleep.
117 *
118 * @is_enabled: Queries the hardware to determine if the clock is enabled.
119 * This function must not sleep. Optional, if this op is not
120 * set then the enable count will be used.
121 *
122 * @disable_unused: Disable the clock atomically. Only called from
123 * clk_disable_unused for gate clocks with special needs.
124 * Called with enable_lock held. This function must not
125 * sleep.
126 *
127 * @save_context: Save the context of the clock in prepration for poweroff.
128 *
129 * @restore_context: Restore the context of the clock after a restoration
130 * of power.
131 *
132 * @recalc_rate: Recalculate the rate of this clock, by querying hardware. The
133 * parent rate is an input parameter. It is up to the caller to
134 * ensure that the prepare_mutex is held across this call. If the
135 * driver cannot figure out a rate for this clock, it must return
136 * 0. Returns the calculated rate. Optional, but recommended - if
137 * this op is not set then clock rate will be initialized to 0.
138 *
139 * @determine_rate: Given a target rate as input, returns the closest rate
140 * actually supported by the clock, and optionally the parent clock
141 * that should be used to provide the clock rate.
142 *
143 * @set_parent: Change the input source of this clock; for clocks with multiple
144 * possible parents specify a new parent by passing in the index
145 * as a u8 corresponding to the parent in either the .parent_names
146 * or .parents arrays. This function in affect translates an
147 * array index into the value programmed into the hardware.
148 * Returns 0 on success, -EERROR otherwise.
149 *
150 * @get_parent: Queries the hardware to determine the parent of a clock. The
151 * return value is a u8 which specifies the index corresponding to
152 * the parent clock. This index can be applied to either the
153 * .parent_names or .parents arrays. In short, this function
154 * translates the parent value read from hardware into an array
155 * index. Currently only called when the clock is initialized by
156 * __clk_init. This callback is mandatory for clocks with
157 * multiple parents. It is optional (and unnecessary) for clocks
158 * with 0 or 1 parents.
159 *
160 * @set_rate: Change the rate of this clock. The requested rate is specified
161 * by the second argument, which should typically be the return
162 * of .determine_rate call. The third argument gives the parent
163 * rate which is likely helpful for most .set_rate implementation.
164 * Returns 0 on success, -EERROR otherwise.
165 *
166 * @set_rate_and_parent: Change the rate and the parent of this clock. The
167 * requested rate is specified by the second argument, which
168 * should typically be the return of clk_round_rate() call. The
169 * third argument gives the parent rate which is likely helpful
170 * for most .set_rate_and_parent implementation. The fourth
171 * argument gives the parent index. This callback is optional (and
172 * unnecessary) for clocks with 0 or 1 parents as well as
173 * for clocks that can tolerate switching the rate and the parent
174 * separately via calls to .set_parent and .set_rate.
175 * Returns 0 on success, -EERROR otherwise.
176 *
177 * @recalc_accuracy: Recalculate the accuracy of this clock. The clock accuracy
178 * is expressed in ppb (parts per billion). The parent accuracy is
179 * an input parameter.
180 * Returns the calculated accuracy. Optional - if this op is not
181 * set then clock accuracy will be initialized to parent accuracy
182 * or 0 (perfect clock) if clock has no parent.
183 *
184 * @get_phase: Queries the hardware to get the current phase of a clock.
185 * Returned values are 0-359 degrees on success, negative
186 * error codes on failure.
187 *
188 * @set_phase: Shift the phase this clock signal in degrees specified
189 * by the second argument. Valid values for degrees are
190 * 0-359. Return 0 on success, otherwise -EERROR.
191 *
192 * @get_duty_cycle: Queries the hardware to get the current duty cycle ratio
193 * of a clock. Returned values denominator cannot be 0 and must be
194 * superior or equal to the numerator.
195 *
196 * @set_duty_cycle: Apply the duty cycle ratio to this clock signal specified by
197 * the numerator (2nd argurment) and denominator (3rd argument).
198 * Argument must be a valid ratio (denominator > 0
199 * and >= numerator) Return 0 on success, otherwise -EERROR.
200 *
201 * @init: Perform platform-specific initialization magic.
202 * This is not used by any of the basic clock types.
203 * This callback exist for HW which needs to perform some
204 * initialisation magic for CCF to get an accurate view of the
205 * clock. It may also be used dynamic resource allocation is
206 * required. It shall not used to deal with clock parameters,
207 * such as rate or parents.
208 * Returns 0 on success, -EERROR otherwise.
209 *
210 * @terminate: Free any resource allocated by init.
211 *
212 * @debug_init: Set up type-specific debugfs entries for this clock. This
213 * is called once, after the debugfs directory entry for this
214 * clock has been created. The dentry pointer representing that
215 * directory is provided as an argument. Called with
216 * prepare_lock held. Returns 0 on success, -EERROR otherwise.
217 *
218 *
219 * The clk_enable/clk_disable and clk_prepare/clk_unprepare pairs allow
220 * implementations to split any work between atomic (enable) and sleepable
221 * (prepare) contexts. If enabling a clock requires code that might sleep,
222 * this must be done in clk_prepare. Clock enable code that will never be
223 * called in a sleepable context may be implemented in clk_enable.
224 *
225 * Typically, drivers will call clk_prepare when a clock may be needed later
226 * (eg. when a device is opened), and clk_enable when the clock is actually
227 * required (eg. from an interrupt). Note that clk_prepare MUST have been
228 * called before clk_enable.
229 */
230struct clk_ops {
231 int (*prepare)(struct clk_hw *hw);
232 void (*unprepare)(struct clk_hw *hw);
233 int (*is_prepared)(struct clk_hw *hw);
234 void (*unprepare_unused)(struct clk_hw *hw);
235 int (*enable)(struct clk_hw *hw);
236 void (*disable)(struct clk_hw *hw);
237 int (*is_enabled)(struct clk_hw *hw);
238 void (*disable_unused)(struct clk_hw *hw);
239 int (*save_context)(struct clk_hw *hw);
240 void (*restore_context)(struct clk_hw *hw);
241 unsigned long (*recalc_rate)(struct clk_hw *hw,
242 unsigned long parent_rate);
243 int (*determine_rate)(struct clk_hw *hw,
244 struct clk_rate_request *req);
245 int (*set_parent)(struct clk_hw *hw, u8 index);
246 u8 (*get_parent)(struct clk_hw *hw);
247 int (*set_rate)(struct clk_hw *hw, unsigned long rate,
248 unsigned long parent_rate);
249 int (*set_rate_and_parent)(struct clk_hw *hw,
250 unsigned long rate,
251 unsigned long parent_rate, u8 index);
252 unsigned long (*recalc_accuracy)(struct clk_hw *hw,
253 unsigned long parent_accuracy);
254 int (*get_phase)(struct clk_hw *hw);
255 int (*set_phase)(struct clk_hw *hw, int degrees);
256 int (*get_duty_cycle)(struct clk_hw *hw,
257 struct clk_duty *duty);
258 int (*set_duty_cycle)(struct clk_hw *hw,
259 struct clk_duty *duty);
260 int (*init)(struct clk_hw *hw);
261 void (*terminate)(struct clk_hw *hw);
262 void (*debug_init)(struct clk_hw *hw, struct dentry *dentry);
263};
264
265/**
266 * struct clk_parent_data - clk parent information
267 * @hw: parent clk_hw pointer (used for clk providers with internal clks)
268 * @fw_name: parent name local to provider registering clk
269 * @name: globally unique parent name (used as a fallback)
270 * @index: parent index local to provider registering clk (if @fw_name absent)
271 */
272struct clk_parent_data {
273 const struct clk_hw *hw;
274 const char *fw_name;
275 const char *name;
276 int index;
277};
278
279/**
280 * struct clk_init_data - holds init data that's common to all clocks and is
281 * shared between the clock provider and the common clock framework.
282 *
283 * @name: clock name
284 * @ops: operations this clock supports
285 * @parent_names: array of string names for all possible parents
286 * @parent_data: array of parent data for all possible parents (when some
287 * parents are external to the clk controller)
288 * @parent_hws: array of pointers to all possible parents (when all parents
289 * are internal to the clk controller)
290 * @num_parents: number of possible parents
291 * @flags: framework-level hints and quirks
292 */
293struct clk_init_data {
294 const char *name;
295 const struct clk_ops *ops;
296 /* Only one of the following three should be assigned */
297 const char * const *parent_names;
298 const struct clk_parent_data *parent_data;
299 const struct clk_hw **parent_hws;
300 u8 num_parents;
301 unsigned long flags;
302};
303
304/**
305 * struct clk_hw - handle for traversing from a struct clk to its corresponding
306 * hardware-specific structure. struct clk_hw should be declared within struct
307 * clk_foo and then referenced by the struct clk instance that uses struct
308 * clk_foo's clk_ops
309 *
310 * @core: pointer to the struct clk_core instance that points back to this
311 * struct clk_hw instance
312 *
313 * @clk: pointer to the per-user struct clk instance that can be used to call
314 * into the clk API
315 *
316 * @init: pointer to struct clk_init_data that contains the init data shared
317 * with the common clock framework. This pointer will be set to NULL once
318 * a clk_register() variant is called on this clk_hw pointer.
319 */
320struct clk_hw {
321 struct clk_core *core;
322 struct clk *clk;
323 const struct clk_init_data *init;
324};
325
326/*
327 * DOC: Basic clock implementations common to many platforms
328 *
329 * Each basic clock hardware type is comprised of a structure describing the
330 * clock hardware, implementations of the relevant callbacks in struct clk_ops,
331 * unique flags for that hardware type, a registration function and an
332 * alternative macro for static initialization
333 */
334
335/**
336 * struct clk_fixed_rate - fixed-rate clock
337 * @hw: handle between common and hardware-specific interfaces
338 * @fixed_rate: constant frequency of clock
339 * @fixed_accuracy: constant accuracy of clock in ppb (parts per billion)
340 * @flags: hardware specific flags
341 *
342 * Flags:
343 * * CLK_FIXED_RATE_PARENT_ACCURACY - Use the accuracy of the parent clk
344 * instead of what's set in @fixed_accuracy.
345 */
346struct clk_fixed_rate {
347 struct clk_hw hw;
348 unsigned long fixed_rate;
349 unsigned long fixed_accuracy;
350 unsigned long flags;
351};
352
353#define CLK_FIXED_RATE_PARENT_ACCURACY BIT(0)
354
355extern const struct clk_ops clk_fixed_rate_ops;
356struct clk_hw *__clk_hw_register_fixed_rate(struct device *dev,
357 struct device_node *np, const char *name,
358 const char *parent_name, const struct clk_hw *parent_hw,
359 const struct clk_parent_data *parent_data, unsigned long flags,
360 unsigned long fixed_rate, unsigned long fixed_accuracy,
361 unsigned long clk_fixed_flags, bool devm);
362struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
363 const char *parent_name, unsigned long flags,
364 unsigned long fixed_rate);
365/**
366 * clk_hw_register_fixed_rate - register fixed-rate clock with the clock
367 * framework
368 * @dev: device that is registering this clock
369 * @name: name of this clock
370 * @parent_name: name of clock's parent
371 * @flags: framework-specific flags
372 * @fixed_rate: non-adjustable clock rate
373 */
374#define clk_hw_register_fixed_rate(dev, name, parent_name, flags, fixed_rate) \
375 __clk_hw_register_fixed_rate((dev), NULL, (name), (parent_name), NULL, \
376 NULL, (flags), (fixed_rate), 0, 0, false)
377
378/**
379 * devm_clk_hw_register_fixed_rate - register fixed-rate clock with the clock
380 * framework
381 * @dev: device that is registering this clock
382 * @name: name of this clock
383 * @parent_name: name of clock's parent
384 * @flags: framework-specific flags
385 * @fixed_rate: non-adjustable clock rate
386 */
387#define devm_clk_hw_register_fixed_rate(dev, name, parent_name, flags, fixed_rate) \
388 __clk_hw_register_fixed_rate((dev), NULL, (name), (parent_name), NULL, \
389 NULL, (flags), (fixed_rate), 0, 0, true)
390/**
391 * devm_clk_hw_register_fixed_rate_parent_data - register fixed-rate clock with
392 * the clock framework
393 * @dev: device that is registering this clock
394 * @name: name of this clock
395 * @parent_data: parent clk data
396 * @flags: framework-specific flags
397 * @fixed_rate: non-adjustable clock rate
398 */
399#define devm_clk_hw_register_fixed_rate_parent_data(dev, name, parent_data, flags, \
400 fixed_rate) \
401 __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, NULL, \
402 (parent_data), (flags), (fixed_rate), 0, \
403 0, true)
404/**
405 * clk_hw_register_fixed_rate_parent_hw - register fixed-rate clock with
406 * the clock framework
407 * @dev: device that is registering this clock
408 * @name: name of this clock
409 * @parent_hw: pointer to parent clk
410 * @flags: framework-specific flags
411 * @fixed_rate: non-adjustable clock rate
412 */
413#define clk_hw_register_fixed_rate_parent_hw(dev, name, parent_hw, flags, \
414 fixed_rate) \
415 __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, (parent_hw), \
416 NULL, (flags), (fixed_rate), 0, 0, false)
417/**
418 * clk_hw_register_fixed_rate_parent_data - register fixed-rate clock with
419 * the clock framework
420 * @dev: device that is registering this clock
421 * @name: name of this clock
422 * @parent_data: parent clk data
423 * @flags: framework-specific flags
424 * @fixed_rate: non-adjustable clock rate
425 */
426#define clk_hw_register_fixed_rate_parent_data(dev, name, parent_data, flags, \
427 fixed_rate) \
428 __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, NULL, \
429 (parent_data), (flags), (fixed_rate), 0, \
430 0, false)
431/**
432 * clk_hw_register_fixed_rate_with_accuracy - register fixed-rate clock with
433 * the clock framework
434 * @dev: device that is registering this clock
435 * @name: name of this clock
436 * @parent_name: name of clock's parent
437 * @flags: framework-specific flags
438 * @fixed_rate: non-adjustable clock rate
439 * @fixed_accuracy: non-adjustable clock accuracy
440 */
441#define clk_hw_register_fixed_rate_with_accuracy(dev, name, parent_name, \
442 flags, fixed_rate, \
443 fixed_accuracy) \
444 __clk_hw_register_fixed_rate((dev), NULL, (name), (parent_name), \
445 NULL, NULL, (flags), (fixed_rate), \
446 (fixed_accuracy), 0, false)
447/**
448 * clk_hw_register_fixed_rate_with_accuracy_parent_hw - register fixed-rate
449 * clock with the clock framework
450 * @dev: device that is registering this clock
451 * @name: name of this clock
452 * @parent_hw: pointer to parent clk
453 * @flags: framework-specific flags
454 * @fixed_rate: non-adjustable clock rate
455 * @fixed_accuracy: non-adjustable clock accuracy
456 */
457#define clk_hw_register_fixed_rate_with_accuracy_parent_hw(dev, name, \
458 parent_hw, flags, fixed_rate, fixed_accuracy) \
459 __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, (parent_hw), \
460 NULL, (flags), (fixed_rate), \
461 (fixed_accuracy), 0, false)
462/**
463 * clk_hw_register_fixed_rate_with_accuracy_parent_data - register fixed-rate
464 * clock with the clock framework
465 * @dev: device that is registering this clock
466 * @name: name of this clock
467 * @parent_data: name of clock's parent
468 * @flags: framework-specific flags
469 * @fixed_rate: non-adjustable clock rate
470 * @fixed_accuracy: non-adjustable clock accuracy
471 */
472#define clk_hw_register_fixed_rate_with_accuracy_parent_data(dev, name, \
473 parent_data, flags, fixed_rate, fixed_accuracy) \
474 __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, NULL, \
475 (parent_data), NULL, (flags), \
476 (fixed_rate), (fixed_accuracy), 0, false)
477/**
478 * clk_hw_register_fixed_rate_parent_accuracy - register fixed-rate clock with
479 * the clock framework
480 * @dev: device that is registering this clock
481 * @name: name of this clock
482 * @parent_data: name of clock's parent
483 * @flags: framework-specific flags
484 * @fixed_rate: non-adjustable clock rate
485 */
486#define clk_hw_register_fixed_rate_parent_accuracy(dev, name, parent_data, \
487 flags, fixed_rate) \
488 __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, NULL, \
489 (parent_data), (flags), (fixed_rate), 0, \
490 CLK_FIXED_RATE_PARENT_ACCURACY, false)
491
492void clk_unregister_fixed_rate(struct clk *clk);
493void clk_hw_unregister_fixed_rate(struct clk_hw *hw);
494
495void of_fixed_clk_setup(struct device_node *np);
496
497/**
498 * struct clk_gate - gating clock
499 *
500 * @hw: handle between common and hardware-specific interfaces
501 * @reg: register controlling gate
502 * @bit_idx: single bit controlling gate
503 * @flags: hardware-specific flags
504 * @lock: register lock
505 *
506 * Clock which can gate its output. Implements .enable & .disable
507 *
508 * Flags:
509 * CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to
510 * enable the clock. Setting this flag does the opposite: setting the bit
511 * disable the clock and clearing it enables the clock
512 * CLK_GATE_HIWORD_MASK - The gate settings are only in lower 16-bit
513 * of this register, and mask of gate bits are in higher 16-bit of this
514 * register. While setting the gate bits, higher 16-bit should also be
515 * updated to indicate changing gate bits.
516 * CLK_GATE_BIG_ENDIAN - by default little endian register accesses are used for
517 * the gate register. Setting this flag makes the register accesses big
518 * endian.
519 */
520struct clk_gate {
521 struct clk_hw hw;
522 void __iomem *reg;
523 u8 bit_idx;
524 u8 flags;
525 spinlock_t *lock;
526};
527
528#define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
529
530#define CLK_GATE_SET_TO_DISABLE BIT(0)
531#define CLK_GATE_HIWORD_MASK BIT(1)
532#define CLK_GATE_BIG_ENDIAN BIT(2)
533
534extern const struct clk_ops clk_gate_ops;
535struct clk_hw *__clk_hw_register_gate(struct device *dev,
536 struct device_node *np, const char *name,
537 const char *parent_name, const struct clk_hw *parent_hw,
538 const struct clk_parent_data *parent_data,
539 unsigned long flags,
540 void __iomem *reg, u8 bit_idx,
541 u8 clk_gate_flags, spinlock_t *lock);
542struct clk_hw *__devm_clk_hw_register_gate(struct device *dev,
543 struct device_node *np, const char *name,
544 const char *parent_name, const struct clk_hw *parent_hw,
545 const struct clk_parent_data *parent_data,
546 unsigned long flags,
547 void __iomem *reg, u8 bit_idx,
548 u8 clk_gate_flags, spinlock_t *lock);
549struct clk *clk_register_gate(struct device *dev, const char *name,
550 const char *parent_name, unsigned long flags,
551 void __iomem *reg, u8 bit_idx,
552 u8 clk_gate_flags, spinlock_t *lock);
553/**
554 * clk_hw_register_gate - register a gate clock with the clock framework
555 * @dev: device that is registering this clock
556 * @name: name of this clock
557 * @parent_name: name of this clock's parent
558 * @flags: framework-specific flags for this clock
559 * @reg: register address to control gating of this clock
560 * @bit_idx: which bit in the register controls gating of this clock
561 * @clk_gate_flags: gate-specific flags for this clock
562 * @lock: shared register lock for this clock
563 */
564#define clk_hw_register_gate(dev, name, parent_name, flags, reg, bit_idx, \
565 clk_gate_flags, lock) \
566 __clk_hw_register_gate((dev), NULL, (name), (parent_name), NULL, \
567 NULL, (flags), (reg), (bit_idx), \
568 (clk_gate_flags), (lock))
569/**
570 * clk_hw_register_gate_parent_hw - register a gate clock with the clock
571 * framework
572 * @dev: device that is registering this clock
573 * @name: name of this clock
574 * @parent_hw: pointer to parent clk
575 * @flags: framework-specific flags for this clock
576 * @reg: register address to control gating of this clock
577 * @bit_idx: which bit in the register controls gating of this clock
578 * @clk_gate_flags: gate-specific flags for this clock
579 * @lock: shared register lock for this clock
580 */
581#define clk_hw_register_gate_parent_hw(dev, name, parent_hw, flags, reg, \
582 bit_idx, clk_gate_flags, lock) \
583 __clk_hw_register_gate((dev), NULL, (name), NULL, (parent_hw), \
584 NULL, (flags), (reg), (bit_idx), \
585 (clk_gate_flags), (lock))
586/**
587 * clk_hw_register_gate_parent_data - register a gate clock with the clock
588 * framework
589 * @dev: device that is registering this clock
590 * @name: name of this clock
591 * @parent_data: parent clk data
592 * @flags: framework-specific flags for this clock
593 * @reg: register address to control gating of this clock
594 * @bit_idx: which bit in the register controls gating of this clock
595 * @clk_gate_flags: gate-specific flags for this clock
596 * @lock: shared register lock for this clock
597 */
598#define clk_hw_register_gate_parent_data(dev, name, parent_data, flags, reg, \
599 bit_idx, clk_gate_flags, lock) \
600 __clk_hw_register_gate((dev), NULL, (name), NULL, NULL, (parent_data), \
601 (flags), (reg), (bit_idx), \
602 (clk_gate_flags), (lock))
603/**
604 * devm_clk_hw_register_gate - register a gate clock with the clock framework
605 * @dev: device that is registering this clock
606 * @name: name of this clock
607 * @parent_name: name of this clock's parent
608 * @flags: framework-specific flags for this clock
609 * @reg: register address to control gating of this clock
610 * @bit_idx: which bit in the register controls gating of this clock
611 * @clk_gate_flags: gate-specific flags for this clock
612 * @lock: shared register lock for this clock
613 */
614#define devm_clk_hw_register_gate(dev, name, parent_name, flags, reg, bit_idx,\
615 clk_gate_flags, lock) \
616 __devm_clk_hw_register_gate((dev), NULL, (name), (parent_name), NULL, \
617 NULL, (flags), (reg), (bit_idx), \
618 (clk_gate_flags), (lock))
619/**
620 * devm_clk_hw_register_gate_parent_hw - register a gate clock with the clock
621 * framework
622 * @dev: device that is registering this clock
623 * @name: name of this clock
624 * @parent_hw: pointer to parent clk
625 * @flags: framework-specific flags for this clock
626 * @reg: register address to control gating of this clock
627 * @bit_idx: which bit in the register controls gating of this clock
628 * @clk_gate_flags: gate-specific flags for this clock
629 * @lock: shared register lock for this clock
630 */
631#define devm_clk_hw_register_gate_parent_hw(dev, name, parent_hw, flags, \
632 reg, bit_idx, clk_gate_flags, \
633 lock) \
634 __devm_clk_hw_register_gate((dev), NULL, (name), NULL, (parent_hw), \
635 NULL, (flags), (reg), (bit_idx), \
636 (clk_gate_flags), (lock))
637/**
638 * devm_clk_hw_register_gate_parent_data - register a gate clock with the
639 * clock framework
640 * @dev: device that is registering this clock
641 * @name: name of this clock
642 * @parent_data: parent clk data
643 * @flags: framework-specific flags for this clock
644 * @reg: register address to control gating of this clock
645 * @bit_idx: which bit in the register controls gating of this clock
646 * @clk_gate_flags: gate-specific flags for this clock
647 * @lock: shared register lock for this clock
648 */
649#define devm_clk_hw_register_gate_parent_data(dev, name, parent_data, flags, \
650 reg, bit_idx, clk_gate_flags, \
651 lock) \
652 __devm_clk_hw_register_gate((dev), NULL, (name), NULL, NULL, \
653 (parent_data), (flags), (reg), (bit_idx), \
654 (clk_gate_flags), (lock))
655
656void clk_unregister_gate(struct clk *clk);
657void clk_hw_unregister_gate(struct clk_hw *hw);
658int clk_gate_is_enabled(struct clk_hw *hw);
659
660struct clk_div_table {
661 unsigned int val;
662 unsigned int div;
663};
664
665/**
666 * struct clk_divider - adjustable divider clock
667 *
668 * @hw: handle between common and hardware-specific interfaces
669 * @reg: register containing the divider
670 * @shift: shift to the divider bit field
671 * @width: width of the divider bit field
672 * @table: array of value/divider pairs, last entry should have div = 0
673 * @lock: register lock
674 *
675 * Clock with an adjustable divider affecting its output frequency. Implements
676 * .recalc_rate, .set_rate and .determine_rate
677 *
678 * @flags:
679 * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the
680 * register plus one. If CLK_DIVIDER_ONE_BASED is set then the divider is
681 * the raw value read from the register, with the value of zero considered
682 * invalid, unless CLK_DIVIDER_ALLOW_ZERO is set.
683 * CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from
684 * the hardware register
685 * CLK_DIVIDER_ALLOW_ZERO - Allow zero divisors. For dividers which have
686 * CLK_DIVIDER_ONE_BASED set, it is possible to end up with a zero divisor.
687 * Some hardware implementations gracefully handle this case and allow a
688 * zero divisor by not modifying their input clock
689 * (divide by one / bypass).
690 * CLK_DIVIDER_HIWORD_MASK - The divider settings are only in lower 16-bit
691 * of this register, and mask of divider bits are in higher 16-bit of this
692 * register. While setting the divider bits, higher 16-bit should also be
693 * updated to indicate changing divider bits.
694 * CLK_DIVIDER_ROUND_CLOSEST - Makes the best calculated divider to be rounded
695 * to the closest integer instead of the up one.
696 * CLK_DIVIDER_READ_ONLY - The divider settings are preconfigured and should
697 * not be changed by the clock framework.
698 * CLK_DIVIDER_MAX_AT_ZERO - For dividers which are like CLK_DIVIDER_ONE_BASED
699 * except when the value read from the register is zero, the divisor is
700 * 2^width of the field.
701 * CLK_DIVIDER_BIG_ENDIAN - By default little endian register accesses are used
702 * for the divider register. Setting this flag makes the register accesses
703 * big endian.
704 * CLK_DIVIDER_EVEN_INTEGERS - clock divisor is 2, 4, 6, 8, 10, etc.
705 * Formula is 2 * (value read from hardware + 1).
706 */
707struct clk_divider {
708 struct clk_hw hw;
709 void __iomem *reg;
710 u8 shift;
711 u8 width;
712 u16 flags;
713 const struct clk_div_table *table;
714 spinlock_t *lock;
715};
716
717#define clk_div_mask(width) ((1 << (width)) - 1)
718#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
719
720#define CLK_DIVIDER_ONE_BASED BIT(0)
721#define CLK_DIVIDER_POWER_OF_TWO BIT(1)
722#define CLK_DIVIDER_ALLOW_ZERO BIT(2)
723#define CLK_DIVIDER_HIWORD_MASK BIT(3)
724#define CLK_DIVIDER_ROUND_CLOSEST BIT(4)
725#define CLK_DIVIDER_READ_ONLY BIT(5)
726#define CLK_DIVIDER_MAX_AT_ZERO BIT(6)
727#define CLK_DIVIDER_BIG_ENDIAN BIT(7)
728#define CLK_DIVIDER_EVEN_INTEGERS BIT(8)
729
730extern const struct clk_ops clk_divider_ops;
731extern const struct clk_ops clk_divider_ro_ops;
732
733unsigned long divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate,
734 unsigned int val, const struct clk_div_table *table,
735 unsigned long flags, unsigned long width);
736int divider_determine_rate(struct clk_hw *hw, struct clk_rate_request *req,
737 const struct clk_div_table *table, u8 width,
738 unsigned long flags);
739int divider_ro_determine_rate(struct clk_hw *hw, struct clk_rate_request *req,
740 const struct clk_div_table *table, u8 width,
741 unsigned long flags, unsigned int val);
742int divider_get_val(unsigned long rate, unsigned long parent_rate,
743 const struct clk_div_table *table, u8 width,
744 unsigned long flags);
745
746struct clk_hw *__clk_hw_register_divider(struct device *dev,
747 struct device_node *np, const char *name,
748 const char *parent_name, const struct clk_hw *parent_hw,
749 const struct clk_parent_data *parent_data, unsigned long flags,
750 void __iomem *reg, u8 shift, u8 width,
751 unsigned long clk_divider_flags,
752 const struct clk_div_table *table, spinlock_t *lock);
753struct clk_hw *__devm_clk_hw_register_divider(struct device *dev,
754 struct device_node *np, const char *name,
755 const char *parent_name, const struct clk_hw *parent_hw,
756 const struct clk_parent_data *parent_data, unsigned long flags,
757 void __iomem *reg, u8 shift, u8 width,
758 unsigned long clk_divider_flags,
759 const struct clk_div_table *table, spinlock_t *lock);
760struct clk *clk_register_divider_table(struct device *dev, const char *name,
761 const char *parent_name, unsigned long flags,
762 void __iomem *reg, u8 shift, u8 width,
763 unsigned long clk_divider_flags,
764 const struct clk_div_table *table, spinlock_t *lock);
765/**
766 * clk_register_divider - register a divider clock with the clock framework
767 * @dev: device registering this clock
768 * @name: name of this clock
769 * @parent_name: name of clock's parent
770 * @flags: framework-specific flags
771 * @reg: register address to adjust divider
772 * @shift: number of bits to shift the bitfield
773 * @width: width of the bitfield
774 * @clk_divider_flags: divider-specific flags for this clock
775 * @lock: shared register lock for this clock
776 */
777#define clk_register_divider(dev, name, parent_name, flags, reg, shift, width, \
778 clk_divider_flags, lock) \
779 clk_register_divider_table((dev), (name), (parent_name), (flags), \
780 (reg), (shift), (width), \
781 (clk_divider_flags), NULL, (lock))
782/**
783 * clk_hw_register_divider - register a divider clock with the clock framework
784 * @dev: device registering this clock
785 * @name: name of this clock
786 * @parent_name: name of clock's parent
787 * @flags: framework-specific flags
788 * @reg: register address to adjust divider
789 * @shift: number of bits to shift the bitfield
790 * @width: width of the bitfield
791 * @clk_divider_flags: divider-specific flags for this clock
792 * @lock: shared register lock for this clock
793 */
794#define clk_hw_register_divider(dev, name, parent_name, flags, reg, shift, \
795 width, clk_divider_flags, lock) \
796 __clk_hw_register_divider((dev), NULL, (name), (parent_name), NULL, \
797 NULL, (flags), (reg), (shift), (width), \
798 (clk_divider_flags), NULL, (lock))
799/**
800 * clk_hw_register_divider_parent_hw - register a divider clock with the clock
801 * framework
802 * @dev: device registering this clock
803 * @name: name of this clock
804 * @parent_hw: pointer to parent clk
805 * @flags: framework-specific flags
806 * @reg: register address to adjust divider
807 * @shift: number of bits to shift the bitfield
808 * @width: width of the bitfield
809 * @clk_divider_flags: divider-specific flags for this clock
810 * @lock: shared register lock for this clock
811 */
812#define clk_hw_register_divider_parent_hw(dev, name, parent_hw, flags, reg, \
813 shift, width, clk_divider_flags, \
814 lock) \
815 __clk_hw_register_divider((dev), NULL, (name), NULL, (parent_hw), \
816 NULL, (flags), (reg), (shift), (width), \
817 (clk_divider_flags), NULL, (lock))
818/**
819 * clk_hw_register_divider_parent_data - register a divider clock with the clock
820 * framework
821 * @dev: device registering this clock
822 * @name: name of this clock
823 * @parent_data: parent clk data
824 * @flags: framework-specific flags
825 * @reg: register address to adjust divider
826 * @shift: number of bits to shift the bitfield
827 * @width: width of the bitfield
828 * @clk_divider_flags: divider-specific flags for this clock
829 * @lock: shared register lock for this clock
830 */
831#define clk_hw_register_divider_parent_data(dev, name, parent_data, flags, \
832 reg, shift, width, \
833 clk_divider_flags, lock) \
834 __clk_hw_register_divider((dev), NULL, (name), NULL, NULL, \
835 (parent_data), (flags), (reg), (shift), \
836 (width), (clk_divider_flags), NULL, (lock))
837/**
838 * clk_hw_register_divider_table - register a table based divider clock with
839 * the clock framework
840 * @dev: device registering this clock
841 * @name: name of this clock
842 * @parent_name: name of clock's parent
843 * @flags: framework-specific flags
844 * @reg: register address to adjust divider
845 * @shift: number of bits to shift the bitfield
846 * @width: width of the bitfield
847 * @clk_divider_flags: divider-specific flags for this clock
848 * @table: array of divider/value pairs ending with a div set to 0
849 * @lock: shared register lock for this clock
850 */
851#define clk_hw_register_divider_table(dev, name, parent_name, flags, reg, \
852 shift, width, clk_divider_flags, table, \
853 lock) \
854 __clk_hw_register_divider((dev), NULL, (name), (parent_name), NULL, \
855 NULL, (flags), (reg), (shift), (width), \
856 (clk_divider_flags), (table), (lock))
857/**
858 * clk_hw_register_divider_table_parent_hw - register a table based divider
859 * clock with the clock framework
860 * @dev: device registering this clock
861 * @name: name of this clock
862 * @parent_hw: pointer to parent clk
863 * @flags: framework-specific flags
864 * @reg: register address to adjust divider
865 * @shift: number of bits to shift the bitfield
866 * @width: width of the bitfield
867 * @clk_divider_flags: divider-specific flags for this clock
868 * @table: array of divider/value pairs ending with a div set to 0
869 * @lock: shared register lock for this clock
870 */
871#define clk_hw_register_divider_table_parent_hw(dev, name, parent_hw, flags, \
872 reg, shift, width, \
873 clk_divider_flags, table, \
874 lock) \
875 __clk_hw_register_divider((dev), NULL, (name), NULL, (parent_hw), \
876 NULL, (flags), (reg), (shift), (width), \
877 (clk_divider_flags), (table), (lock))
878/**
879 * clk_hw_register_divider_table_parent_data - register a table based divider
880 * clock with the clock framework
881 * @dev: device registering this clock
882 * @name: name of this clock
883 * @parent_data: parent clk data
884 * @flags: framework-specific flags
885 * @reg: register address to adjust divider
886 * @shift: number of bits to shift the bitfield
887 * @width: width of the bitfield
888 * @clk_divider_flags: divider-specific flags for this clock
889 * @table: array of divider/value pairs ending with a div set to 0
890 * @lock: shared register lock for this clock
891 */
892#define clk_hw_register_divider_table_parent_data(dev, name, parent_data, \
893 flags, reg, shift, width, \
894 clk_divider_flags, table, \
895 lock) \
896 __clk_hw_register_divider((dev), NULL, (name), NULL, NULL, \
897 (parent_data), (flags), (reg), (shift), \
898 (width), (clk_divider_flags), (table), \
899 (lock))
900/**
901 * devm_clk_hw_register_divider - register a divider clock with the clock framework
902 * @dev: device registering this clock
903 * @name: name of this clock
904 * @parent_name: name of clock's parent
905 * @flags: framework-specific flags
906 * @reg: register address to adjust divider
907 * @shift: number of bits to shift the bitfield
908 * @width: width of the bitfield
909 * @clk_divider_flags: divider-specific flags for this clock
910 * @lock: shared register lock for this clock
911 */
912#define devm_clk_hw_register_divider(dev, name, parent_name, flags, reg, shift, \
913 width, clk_divider_flags, lock) \
914 __devm_clk_hw_register_divider((dev), NULL, (name), (parent_name), NULL, \
915 NULL, (flags), (reg), (shift), (width), \
916 (clk_divider_flags), NULL, (lock))
917/**
918 * devm_clk_hw_register_divider_parent_hw - register a divider clock with the clock framework
919 * @dev: device registering this clock
920 * @name: name of this clock
921 * @parent_hw: pointer to parent clk
922 * @flags: framework-specific flags
923 * @reg: register address to adjust divider
924 * @shift: number of bits to shift the bitfield
925 * @width: width of the bitfield
926 * @clk_divider_flags: divider-specific flags for this clock
927 * @lock: shared register lock for this clock
928 */
929#define devm_clk_hw_register_divider_parent_hw(dev, name, parent_hw, flags, \
930 reg, shift, width, \
931 clk_divider_flags, lock) \
932 __devm_clk_hw_register_divider((dev), NULL, (name), NULL, \
933 (parent_hw), NULL, (flags), (reg), \
934 (shift), (width), (clk_divider_flags), \
935 NULL, (lock))
936/**
937 * devm_clk_hw_register_divider_parent_data - register a divider clock with the
938 * clock framework
939 * @dev: device registering this clock
940 * @name: name of this clock
941 * @parent_data: parent clk data
942 * @flags: framework-specific flags
943 * @reg: register address to adjust divider
944 * @shift: number of bits to shift the bitfield
945 * @width: width of the bitfield
946 * @clk_divider_flags: divider-specific flags for this clock
947 * @lock: shared register lock for this clock
948 */
949#define devm_clk_hw_register_divider_parent_data(dev, name, parent_data, \
950 flags, reg, shift, width, \
951 clk_divider_flags, lock) \
952 __devm_clk_hw_register_divider((dev), NULL, (name), NULL, NULL, \
953 (parent_data), (flags), (reg), (shift), \
954 (width), (clk_divider_flags), NULL, \
955 (lock))
956/**
957 * devm_clk_hw_register_divider_table - register a table based divider clock
958 * with the clock framework (devres variant)
959 * @dev: device registering this clock
960 * @name: name of this clock
961 * @parent_name: name of clock's parent
962 * @flags: framework-specific flags
963 * @reg: register address to adjust divider
964 * @shift: number of bits to shift the bitfield
965 * @width: width of the bitfield
966 * @clk_divider_flags: divider-specific flags for this clock
967 * @table: array of divider/value pairs ending with a div set to 0
968 * @lock: shared register lock for this clock
969 */
970#define devm_clk_hw_register_divider_table(dev, name, parent_name, flags, \
971 reg, shift, width, \
972 clk_divider_flags, table, lock) \
973 __devm_clk_hw_register_divider((dev), NULL, (name), (parent_name), \
974 NULL, NULL, (flags), (reg), (shift), \
975 (width), (clk_divider_flags), (table), \
976 (lock))
977
978void clk_unregister_divider(struct clk *clk);
979void clk_hw_unregister_divider(struct clk_hw *hw);
980
981/**
982 * struct clk_mux - multiplexer clock
983 *
984 * @hw: handle between common and hardware-specific interfaces
985 * @reg: register controlling multiplexer
986 * @table: array of register values corresponding to the parent index
987 * @shift: shift to multiplexer bit field
988 * @mask: mask of mutliplexer bit field
989 * @flags: hardware-specific flags
990 * @lock: register lock
991 *
992 * Clock with multiple selectable parents. Implements .get_parent, .set_parent
993 * and .recalc_rate
994 *
995 * Flags:
996 * CLK_MUX_INDEX_ONE - register index starts at 1, not 0
997 * CLK_MUX_INDEX_BIT - register index is a single bit (power of two)
998 * CLK_MUX_HIWORD_MASK - The mux settings are only in lower 16-bit of this
999 * register, and mask of mux bits are in higher 16-bit of this register.
1000 * While setting the mux bits, higher 16-bit should also be updated to
1001 * indicate changing mux bits.
1002 * CLK_MUX_READ_ONLY - The mux registers can't be written, only read in the
1003 * .get_parent clk_op.
1004 * CLK_MUX_ROUND_CLOSEST - Use the parent rate that is closest to the desired
1005 * frequency.
1006 * CLK_MUX_BIG_ENDIAN - By default little endian register accesses are used for
1007 * the mux register. Setting this flag makes the register accesses big
1008 * endian.
1009 */
1010struct clk_mux {
1011 struct clk_hw hw;
1012 void __iomem *reg;
1013 const u32 *table;
1014 u32 mask;
1015 u8 shift;
1016 u8 flags;
1017 spinlock_t *lock;
1018};
1019
1020#define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw)
1021
1022#define CLK_MUX_INDEX_ONE BIT(0)
1023#define CLK_MUX_INDEX_BIT BIT(1)
1024#define CLK_MUX_HIWORD_MASK BIT(2)
1025#define CLK_MUX_READ_ONLY BIT(3) /* mux can't be changed */
1026#define CLK_MUX_ROUND_CLOSEST BIT(4)
1027#define CLK_MUX_BIG_ENDIAN BIT(5)
1028
1029extern const struct clk_ops clk_mux_ops;
1030extern const struct clk_ops clk_mux_ro_ops;
1031
1032struct clk_hw *__clk_hw_register_mux(struct device *dev, struct device_node *np,
1033 const char *name, u8 num_parents,
1034 const char * const *parent_names,
1035 const struct clk_hw **parent_hws,
1036 const struct clk_parent_data *parent_data,
1037 unsigned long flags, void __iomem *reg, u8 shift, u32 mask,
1038 u8 clk_mux_flags, const u32 *table, spinlock_t *lock);
1039struct clk_hw *__devm_clk_hw_register_mux(struct device *dev, struct device_node *np,
1040 const char *name, u8 num_parents,
1041 const char * const *parent_names,
1042 const struct clk_hw **parent_hws,
1043 const struct clk_parent_data *parent_data,
1044 unsigned long flags, void __iomem *reg, u8 shift, u32 mask,
1045 u8 clk_mux_flags, const u32 *table, spinlock_t *lock);
1046struct clk *clk_register_mux_table(struct device *dev, const char *name,
1047 const char * const *parent_names, u8 num_parents,
1048 unsigned long flags, void __iomem *reg, u8 shift, u32 mask,
1049 u8 clk_mux_flags, const u32 *table, spinlock_t *lock);
1050
1051#define clk_register_mux(dev, name, parent_names, num_parents, flags, reg, \
1052 shift, width, clk_mux_flags, lock) \
1053 clk_register_mux_table((dev), (name), (parent_names), (num_parents), \
1054 (flags), (reg), (shift), BIT((width)) - 1, \
1055 (clk_mux_flags), NULL, (lock))
1056#define clk_hw_register_mux_table(dev, name, parent_names, num_parents, \
1057 flags, reg, shift, mask, clk_mux_flags, \
1058 table, lock) \
1059 __clk_hw_register_mux((dev), NULL, (name), (num_parents), \
1060 (parent_names), NULL, NULL, (flags), (reg), \
1061 (shift), (mask), (clk_mux_flags), (table), \
1062 (lock))
1063#define clk_hw_register_mux_table_parent_data(dev, name, parent_data, \
1064 num_parents, flags, reg, shift, mask, \
1065 clk_mux_flags, table, lock) \
1066 __clk_hw_register_mux((dev), NULL, (name), (num_parents), \
1067 NULL, NULL, (parent_data), (flags), (reg), \
1068 (shift), (mask), (clk_mux_flags), (table), \
1069 (lock))
1070#define clk_hw_register_mux(dev, name, parent_names, num_parents, flags, reg, \
1071 shift, width, clk_mux_flags, lock) \
1072 __clk_hw_register_mux((dev), NULL, (name), (num_parents), \
1073 (parent_names), NULL, NULL, (flags), (reg), \
1074 (shift), BIT((width)) - 1, (clk_mux_flags), \
1075 NULL, (lock))
1076#define clk_hw_register_mux_hws(dev, name, parent_hws, num_parents, flags, \
1077 reg, shift, width, clk_mux_flags, lock) \
1078 __clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, \
1079 (parent_hws), NULL, (flags), (reg), (shift), \
1080 BIT((width)) - 1, (clk_mux_flags), NULL, (lock))
1081#define clk_hw_register_mux_parent_data(dev, name, parent_data, num_parents, \
1082 flags, reg, shift, width, \
1083 clk_mux_flags, lock) \
1084 __clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, NULL, \
1085 (parent_data), (flags), (reg), (shift), \
1086 BIT((width)) - 1, (clk_mux_flags), NULL, (lock))
1087#define clk_hw_register_mux_parent_data_table(dev, name, parent_data, \
1088 num_parents, flags, reg, shift, \
1089 width, clk_mux_flags, table, \
1090 lock) \
1091 __clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, NULL, \
1092 (parent_data), (flags), (reg), (shift), \
1093 BIT((width)) - 1, (clk_mux_flags), table, (lock))
1094#define devm_clk_hw_register_mux(dev, name, parent_names, num_parents, flags, reg, \
1095 shift, width, clk_mux_flags, lock) \
1096 __devm_clk_hw_register_mux((dev), NULL, (name), (num_parents), \
1097 (parent_names), NULL, NULL, (flags), (reg), \
1098 (shift), BIT((width)) - 1, (clk_mux_flags), \
1099 NULL, (lock))
1100#define devm_clk_hw_register_mux_parent_hws(dev, name, parent_hws, \
1101 num_parents, flags, reg, shift, \
1102 width, clk_mux_flags, lock) \
1103 __devm_clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, \
1104 (parent_hws), NULL, (flags), (reg), \
1105 (shift), BIT((width)) - 1, \
1106 (clk_mux_flags), NULL, (lock))
1107#define devm_clk_hw_register_mux_parent_data_table(dev, name, parent_data, \
1108 num_parents, flags, reg, shift, \
1109 width, clk_mux_flags, table, \
1110 lock) \
1111 __devm_clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, \
1112 NULL, (parent_data), (flags), (reg), (shift), \
1113 BIT((width)) - 1, (clk_mux_flags), table, (lock))
1114
1115int clk_mux_val_to_index(struct clk_hw *hw, const u32 *table, unsigned int flags,
1116 unsigned int val);
1117unsigned int clk_mux_index_to_val(const u32 *table, unsigned int flags, u8 index);
1118
1119void clk_unregister_mux(struct clk *clk);
1120void clk_hw_unregister_mux(struct clk_hw *hw);
1121
1122void of_fixed_factor_clk_setup(struct device_node *node);
1123
1124/**
1125 * struct clk_fixed_factor - fixed multiplier and divider clock
1126 *
1127 * @hw: handle between common and hardware-specific interfaces
1128 * @mult: multiplier
1129 * @div: divider
1130 * @acc: fixed accuracy in ppb
1131 * @flags: behavior modifying flags
1132 *
1133 * Clock with a fixed multiplier and divider. The output frequency is the
1134 * parent clock rate divided by div and multiplied by mult.
1135 * Implements .recalc_rate, .set_rate, .determine_rate and .recalc_accuracy
1136 *
1137 * Flags:
1138 * * CLK_FIXED_FACTOR_FIXED_ACCURACY - Use the value in @acc instead of the
1139 * parent clk accuracy.
1140 */
1141
1142struct clk_fixed_factor {
1143 struct clk_hw hw;
1144 unsigned int mult;
1145 unsigned int div;
1146 unsigned long acc;
1147 unsigned int flags;
1148};
1149
1150#define CLK_FIXED_FACTOR_FIXED_ACCURACY BIT(0)
1151
1152#define to_clk_fixed_factor(_hw) container_of(_hw, struct clk_fixed_factor, hw)
1153
1154extern const struct clk_ops clk_fixed_factor_ops;
1155struct clk *clk_register_fixed_factor(struct device *dev, const char *name,
1156 const char *parent_name, unsigned long flags,
1157 unsigned int mult, unsigned int div);
1158void clk_unregister_fixed_factor(struct clk *clk);
1159struct clk_hw *clk_hw_register_fixed_factor(struct device *dev,
1160 const char *name, const char *parent_name, unsigned long flags,
1161 unsigned int mult, unsigned int div);
1162struct clk_hw *clk_hw_register_fixed_factor_fwname(struct device *dev,
1163 struct device_node *np, const char *name, const char *fw_name,
1164 unsigned long flags, unsigned int mult, unsigned int div);
1165struct clk_hw *clk_hw_register_fixed_factor_with_accuracy_fwname(struct device *dev,
1166 struct device_node *np, const char *name, const char *fw_name,
1167 unsigned long flags, unsigned int mult, unsigned int div,
1168 unsigned long acc);
1169struct clk_hw *clk_hw_register_fixed_factor_index(struct device *dev,
1170 const char *name, unsigned int index, unsigned long flags,
1171 unsigned int mult, unsigned int div);
1172void clk_hw_unregister_fixed_factor(struct clk_hw *hw);
1173struct clk_hw *devm_clk_hw_register_fixed_factor(struct device *dev,
1174 const char *name, const char *parent_name, unsigned long flags,
1175 unsigned int mult, unsigned int div);
1176struct clk_hw *devm_clk_hw_register_fixed_factor_fwname(struct device *dev,
1177 struct device_node *np, const char *name, const char *fw_name,
1178 unsigned long flags, unsigned int mult, unsigned int div);
1179struct clk_hw *devm_clk_hw_register_fixed_factor_with_accuracy_fwname(struct device *dev,
1180 struct device_node *np, const char *name, const char *fw_name,
1181 unsigned long flags, unsigned int mult, unsigned int div,
1182 unsigned long acc);
1183struct clk_hw *devm_clk_hw_register_fixed_factor_index(struct device *dev,
1184 const char *name, unsigned int index, unsigned long flags,
1185 unsigned int mult, unsigned int div);
1186
1187struct clk_hw *devm_clk_hw_register_fixed_factor_parent_hw(struct device *dev,
1188 const char *name, const struct clk_hw *parent_hw,
1189 unsigned long flags, unsigned int mult, unsigned int div);
1190
1191struct clk_hw *clk_hw_register_fixed_factor_parent_hw(struct device *dev,
1192 const char *name, const struct clk_hw *parent_hw,
1193 unsigned long flags, unsigned int mult, unsigned int div);
1194/**
1195 * struct clk_fractional_divider - adjustable fractional divider clock
1196 *
1197 * @hw: handle between common and hardware-specific interfaces
1198 * @reg: register containing the divider
1199 * @mshift: shift to the numerator bit field
1200 * @mwidth: width of the numerator bit field
1201 * @nshift: shift to the denominator bit field
1202 * @nwidth: width of the denominator bit field
1203 * @approximation: clk driver's callback for calculating the divider clock
1204 * @lock: register lock
1205 *
1206 * Clock with adjustable fractional divider affecting its output frequency.
1207 *
1208 * @flags:
1209 * CLK_FRAC_DIVIDER_ZERO_BASED - by default the numerator and denominator
1210 * is the value read from the register. If CLK_FRAC_DIVIDER_ZERO_BASED
1211 * is set then the numerator and denominator are both the value read
1212 * plus one.
1213 * CLK_FRAC_DIVIDER_BIG_ENDIAN - By default little endian register accesses are
1214 * used for the divider register. Setting this flag makes the register
1215 * accesses big endian.
1216 * CLK_FRAC_DIVIDER_POWER_OF_TWO_PS - By default the resulting fraction might
1217 * be saturated and the caller will get quite far from the good enough
1218 * approximation. Instead the caller may require, by setting this flag,
1219 * to shift left by a few bits in case, when the asked one is quite small
1220 * to satisfy the desired range of denominator. It assumes that on the
1221 * caller's side the power-of-two capable prescaler exists.
1222 */
1223struct clk_fractional_divider {
1224 struct clk_hw hw;
1225 void __iomem *reg;
1226 u8 mshift;
1227 u8 mwidth;
1228 u8 nshift;
1229 u8 nwidth;
1230 u8 flags;
1231 void (*approximation)(struct clk_hw *hw,
1232 unsigned long rate, unsigned long *parent_rate,
1233 unsigned long *m, unsigned long *n);
1234 spinlock_t *lock;
1235};
1236
1237#define to_clk_fd(_hw) container_of(_hw, struct clk_fractional_divider, hw)
1238
1239#define CLK_FRAC_DIVIDER_ZERO_BASED BIT(0)
1240#define CLK_FRAC_DIVIDER_BIG_ENDIAN BIT(1)
1241#define CLK_FRAC_DIVIDER_POWER_OF_TWO_PS BIT(2)
1242
1243struct clk *clk_register_fractional_divider(struct device *dev,
1244 const char *name, const char *parent_name, unsigned long flags,
1245 void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth,
1246 u8 clk_divider_flags, spinlock_t *lock);
1247struct clk_hw *clk_hw_register_fractional_divider(struct device *dev,
1248 const char *name, const char *parent_name, unsigned long flags,
1249 void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth,
1250 u8 clk_divider_flags, spinlock_t *lock);
1251void clk_hw_unregister_fractional_divider(struct clk_hw *hw);
1252
1253/**
1254 * struct clk_multiplier - adjustable multiplier clock
1255 *
1256 * @hw: handle between common and hardware-specific interfaces
1257 * @reg: register containing the multiplier
1258 * @shift: shift to the multiplier bit field
1259 * @width: width of the multiplier bit field
1260 * @lock: register lock
1261 *
1262 * Clock with an adjustable multiplier affecting its output frequency.
1263 * Implements .recalc_rate, .set_rate and .determine_rate
1264 *
1265 * @flags:
1266 * CLK_MULTIPLIER_ZERO_BYPASS - By default, the multiplier is the value read
1267 * from the register, with 0 being a valid value effectively
1268 * zeroing the output clock rate. If CLK_MULTIPLIER_ZERO_BYPASS is
1269 * set, then a null multiplier will be considered as a bypass,
1270 * leaving the parent rate unmodified.
1271 * CLK_MULTIPLIER_ROUND_CLOSEST - Makes the best calculated divider to be
1272 * rounded to the closest integer instead of the down one.
1273 * CLK_MULTIPLIER_BIG_ENDIAN - By default little endian register accesses are
1274 * used for the multiplier register. Setting this flag makes the register
1275 * accesses big endian.
1276 */
1277struct clk_multiplier {
1278 struct clk_hw hw;
1279 void __iomem *reg;
1280 u8 shift;
1281 u8 width;
1282 u8 flags;
1283 spinlock_t *lock;
1284};
1285
1286#define to_clk_multiplier(_hw) container_of(_hw, struct clk_multiplier, hw)
1287
1288#define CLK_MULTIPLIER_ZERO_BYPASS BIT(0)
1289#define CLK_MULTIPLIER_ROUND_CLOSEST BIT(1)
1290#define CLK_MULTIPLIER_BIG_ENDIAN BIT(2)
1291
1292extern const struct clk_ops clk_multiplier_ops;
1293
1294/***
1295 * struct clk_composite - aggregate clock of mux, divider and gate clocks
1296 *
1297 * @hw: handle between common and hardware-specific interfaces
1298 * @mux_hw: handle between composite and hardware-specific mux clock
1299 * @rate_hw: handle between composite and hardware-specific rate clock
1300 * @gate_hw: handle between composite and hardware-specific gate clock
1301 * @mux_ops: clock ops for mux
1302 * @rate_ops: clock ops for rate
1303 * @gate_ops: clock ops for gate
1304 */
1305struct clk_composite {
1306 struct clk_hw hw;
1307 struct clk_ops ops;
1308
1309 struct clk_hw *mux_hw;
1310 struct clk_hw *rate_hw;
1311 struct clk_hw *gate_hw;
1312
1313 const struct clk_ops *mux_ops;
1314 const struct clk_ops *rate_ops;
1315 const struct clk_ops *gate_ops;
1316};
1317
1318#define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw)
1319
1320struct clk *clk_register_composite(struct device *dev, const char *name,
1321 const char * const *parent_names, int num_parents,
1322 struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
1323 struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
1324 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
1325 unsigned long flags);
1326struct clk *clk_register_composite_pdata(struct device *dev, const char *name,
1327 const struct clk_parent_data *parent_data, int num_parents,
1328 struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
1329 struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
1330 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
1331 unsigned long flags);
1332void clk_unregister_composite(struct clk *clk);
1333struct clk_hw *clk_hw_register_composite(struct device *dev, const char *name,
1334 const char * const *parent_names, int num_parents,
1335 struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
1336 struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
1337 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
1338 unsigned long flags);
1339struct clk_hw *clk_hw_register_composite_pdata(struct device *dev,
1340 const char *name,
1341 const struct clk_parent_data *parent_data, int num_parents,
1342 struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
1343 struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
1344 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
1345 unsigned long flags);
1346struct clk_hw *devm_clk_hw_register_composite_pdata(struct device *dev,
1347 const char *name, const struct clk_parent_data *parent_data,
1348 int num_parents,
1349 struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
1350 struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
1351 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
1352 unsigned long flags);
1353void clk_hw_unregister_composite(struct clk_hw *hw);
1354
1355struct clk *clk_register(struct device *dev, struct clk_hw *hw);
1356struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw);
1357
1358int __must_check clk_hw_register(struct device *dev, struct clk_hw *hw);
1359int __must_check devm_clk_hw_register(struct device *dev, struct clk_hw *hw);
1360int __must_check of_clk_hw_register(struct device_node *node, struct clk_hw *hw);
1361
1362void clk_unregister(struct clk *clk);
1363
1364void clk_hw_unregister(struct clk_hw *hw);
1365
1366/* helper functions */
1367const char *__clk_get_name(const struct clk *clk);
1368const char *clk_hw_get_name(const struct clk_hw *hw);
1369
1370/**
1371 * clk_hw_get_dev() - get device from an hardware clock.
1372 * @hw: the clk_hw pointer to get the struct device from
1373 *
1374 * This is a helper to get the struct device associated with a hardware
1375 * clock. Some clock controllers, such as the one registered with
1376 * CLK_OF_DECLARE(), may have not provided a device pointer while
1377 * registering the clock.
1378 *
1379 * Return: the struct device associated with the clock, or NULL if there
1380 * is none.
1381 */
1382struct device *clk_hw_get_dev(const struct clk_hw *hw);
1383
1384/**
1385 * clk_hw_get_of_node() - get device_node from a hardware clock.
1386 * @hw: the clk_hw pointer to get the struct device_node from
1387 *
1388 * This is a helper to get the struct device_node associated with a
1389 * hardware clock.
1390 *
1391 * Return: the struct device_node associated with the clock, or NULL
1392 * if there is none.
1393 */
1394struct device_node *clk_hw_get_of_node(const struct clk_hw *hw);
1395#ifdef CONFIG_COMMON_CLK
1396struct clk_hw *__clk_get_hw(struct clk *clk);
1397#else
1398static inline struct clk_hw *__clk_get_hw(struct clk *clk)
1399{
1400 return (struct clk_hw *)clk;
1401}
1402#endif
1403
1404struct clk *clk_hw_get_clk(struct clk_hw *hw, const char *con_id);
1405struct clk *devm_clk_hw_get_clk(struct device *dev, struct clk_hw *hw,
1406 const char *con_id);
1407
1408unsigned int clk_hw_get_num_parents(const struct clk_hw *hw);
1409struct clk_hw *clk_hw_get_parent(const struct clk_hw *hw);
1410struct clk_hw *clk_hw_get_parent_by_index(const struct clk_hw *hw,
1411 unsigned int index);
1412int clk_hw_get_parent_index(struct clk_hw *hw);
1413int clk_hw_set_parent(struct clk_hw *hw, struct clk_hw *new_parent);
1414unsigned int __clk_get_enable_count(struct clk *clk);
1415unsigned long clk_hw_get_rate(const struct clk_hw *hw);
1416unsigned long clk_hw_get_flags(const struct clk_hw *hw);
1417#define clk_hw_can_set_rate_parent(hw) \
1418 (clk_hw_get_flags((hw)) & CLK_SET_RATE_PARENT)
1419
1420bool clk_hw_is_prepared(const struct clk_hw *hw);
1421bool clk_hw_is_enabled(const struct clk_hw *hw);
1422bool __clk_is_enabled(struct clk *clk);
1423struct clk *__clk_lookup(const char *name);
1424int __clk_mux_determine_rate(struct clk_hw *hw,
1425 struct clk_rate_request *req);
1426int __clk_determine_rate(struct clk_hw *core, struct clk_rate_request *req);
1427int __clk_mux_determine_rate_closest(struct clk_hw *hw,
1428 struct clk_rate_request *req);
1429int clk_mux_determine_rate_flags(struct clk_hw *hw,
1430 struct clk_rate_request *req,
1431 unsigned long flags);
1432int clk_hw_determine_rate_no_reparent(struct clk_hw *hw,
1433 struct clk_rate_request *req);
1434void clk_hw_reparent(struct clk_hw *hw, struct clk_hw *new_parent);
1435void clk_hw_get_rate_range(struct clk_hw *hw, unsigned long *min_rate,
1436 unsigned long *max_rate);
1437void clk_hw_set_rate_range(struct clk_hw *hw, unsigned long min_rate,
1438 unsigned long max_rate);
1439
1440static inline void __clk_hw_set_clk(struct clk_hw *dst, struct clk_hw *src)
1441{
1442 dst->clk = src->clk;
1443 dst->core = src->core;
1444}
1445
1446/*
1447 * FIXME clock api without lock protection
1448 */
1449unsigned long clk_hw_round_rate(struct clk_hw *hw, unsigned long rate);
1450
1451struct clk_onecell_data {
1452 struct clk **clks;
1453 unsigned int clk_num;
1454};
1455
1456struct clk_hw_onecell_data {
1457 unsigned int num;
1458 struct clk_hw *hws[] __counted_by(num);
1459};
1460
1461#define CLK_OF_DECLARE(name, compat, fn) \
1462 static void __init __##name##_of_clk_init_declare(struct device_node *np) \
1463 { \
1464 fn(np); \
1465 fwnode_dev_initialized(of_fwnode_handle(np), true); \
1466 } \
1467 OF_DECLARE_1(clk, name, compat, __##name##_of_clk_init_declare)
1468
1469/*
1470 * Use this macro when you have a driver that requires two initialization
1471 * routines, one at of_clk_init(), and one at platform device probe
1472 */
1473#define CLK_OF_DECLARE_DRIVER(name, compat, fn) \
1474 static void __init name##_of_clk_init_driver(struct device_node *np) \
1475 { \
1476 of_node_clear_flag(np, OF_POPULATED); \
1477 fn(np); \
1478 } \
1479 OF_DECLARE_1(clk, name, compat, name##_of_clk_init_driver)
1480
1481#define CLK_HW_INIT(_name, _parent, _ops, _flags) \
1482 (&(struct clk_init_data) { \
1483 .flags = _flags, \
1484 .name = _name, \
1485 .parent_names = (const char *[]) { _parent }, \
1486 .num_parents = 1, \
1487 .ops = _ops, \
1488 })
1489
1490#define CLK_HW_INIT_HW(_name, _parent, _ops, _flags) \
1491 (&(struct clk_init_data) { \
1492 .flags = _flags, \
1493 .name = _name, \
1494 .parent_hws = (const struct clk_hw*[]) { _parent }, \
1495 .num_parents = 1, \
1496 .ops = _ops, \
1497 })
1498
1499/*
1500 * This macro is intended for drivers to be able to share the otherwise
1501 * individual struct clk_hw[] compound literals created by the compiler
1502 * when using CLK_HW_INIT_HW. It does NOT support multiple parents.
1503 */
1504#define CLK_HW_INIT_HWS(_name, _parent, _ops, _flags) \
1505 (&(struct clk_init_data) { \
1506 .flags = _flags, \
1507 .name = _name, \
1508 .parent_hws = _parent, \
1509 .num_parents = 1, \
1510 .ops = _ops, \
1511 })
1512
1513#define CLK_HW_INIT_FW_NAME(_name, _parent, _ops, _flags) \
1514 (&(struct clk_init_data) { \
1515 .flags = _flags, \
1516 .name = _name, \
1517 .parent_data = (const struct clk_parent_data[]) { \
1518 { .fw_name = _parent }, \
1519 }, \
1520 .num_parents = 1, \
1521 .ops = _ops, \
1522 })
1523
1524#define CLK_HW_INIT_PARENTS(_name, _parents, _ops, _flags) \
1525 (&(struct clk_init_data) { \
1526 .flags = _flags, \
1527 .name = _name, \
1528 .parent_names = _parents, \
1529 .num_parents = ARRAY_SIZE(_parents), \
1530 .ops = _ops, \
1531 })
1532
1533#define CLK_HW_INIT_PARENTS_HW(_name, _parents, _ops, _flags) \
1534 (&(struct clk_init_data) { \
1535 .flags = _flags, \
1536 .name = _name, \
1537 .parent_hws = _parents, \
1538 .num_parents = ARRAY_SIZE(_parents), \
1539 .ops = _ops, \
1540 })
1541
1542#define CLK_HW_INIT_PARENTS_DATA(_name, _parents, _ops, _flags) \
1543 (&(struct clk_init_data) { \
1544 .flags = _flags, \
1545 .name = _name, \
1546 .parent_data = _parents, \
1547 .num_parents = ARRAY_SIZE(_parents), \
1548 .ops = _ops, \
1549 })
1550
1551#define CLK_HW_INIT_NO_PARENT(_name, _ops, _flags) \
1552 (&(struct clk_init_data) { \
1553 .flags = _flags, \
1554 .name = _name, \
1555 .parent_names = NULL, \
1556 .num_parents = 0, \
1557 .ops = _ops, \
1558 })
1559
1560#define CLK_FIXED_FACTOR(_struct, _name, _parent, \
1561 _div, _mult, _flags) \
1562 struct clk_fixed_factor _struct = { \
1563 .div = _div, \
1564 .mult = _mult, \
1565 .hw.init = CLK_HW_INIT(_name, \
1566 _parent, \
1567 &clk_fixed_factor_ops, \
1568 _flags), \
1569 }
1570
1571#define CLK_FIXED_FACTOR_HW(_struct, _name, _parent, \
1572 _div, _mult, _flags) \
1573 struct clk_fixed_factor _struct = { \
1574 .div = _div, \
1575 .mult = _mult, \
1576 .hw.init = CLK_HW_INIT_HW(_name, \
1577 _parent, \
1578 &clk_fixed_factor_ops, \
1579 _flags), \
1580 }
1581
1582/*
1583 * This macro allows the driver to reuse the _parent array for multiple
1584 * fixed factor clk declarations.
1585 */
1586#define CLK_FIXED_FACTOR_HWS(_struct, _name, _parent, \
1587 _div, _mult, _flags) \
1588 struct clk_fixed_factor _struct = { \
1589 .div = _div, \
1590 .mult = _mult, \
1591 .hw.init = CLK_HW_INIT_HWS(_name, \
1592 _parent, \
1593 &clk_fixed_factor_ops, \
1594 _flags), \
1595 }
1596
1597#define CLK_FIXED_FACTOR_FW_NAME(_struct, _name, _parent, \
1598 _div, _mult, _flags) \
1599 struct clk_fixed_factor _struct = { \
1600 .div = _div, \
1601 .mult = _mult, \
1602 .hw.init = CLK_HW_INIT_FW_NAME(_name, \
1603 _parent, \
1604 &clk_fixed_factor_ops, \
1605 _flags), \
1606 }
1607
1608#ifdef CONFIG_OF
1609int of_clk_add_provider(struct device_node *np,
1610 struct clk *(*clk_src_get)(struct of_phandle_args *args,
1611 void *data),
1612 void *data);
1613int of_clk_add_hw_provider(struct device_node *np,
1614 struct clk_hw *(*get)(struct of_phandle_args *clkspec,
1615 void *data),
1616 void *data);
1617int devm_of_clk_add_hw_provider(struct device *dev,
1618 struct clk_hw *(*get)(struct of_phandle_args *clkspec,
1619 void *data),
1620 void *data);
1621void of_clk_del_provider(struct device_node *np);
1622
1623struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec,
1624 void *data);
1625struct clk_hw *of_clk_hw_simple_get(struct of_phandle_args *clkspec,
1626 void *data);
1627struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data);
1628struct clk_hw *of_clk_hw_onecell_get(struct of_phandle_args *clkspec,
1629 void *data);
1630int of_clk_parent_fill(struct device_node *np, const char **parents,
1631 unsigned int size);
1632int of_clk_detect_critical(struct device_node *np, int index,
1633 unsigned long *flags);
1634
1635#else /* !CONFIG_OF */
1636
1637static inline int of_clk_add_provider(struct device_node *np,
1638 struct clk *(*clk_src_get)(struct of_phandle_args *args,
1639 void *data),
1640 void *data)
1641{
1642 return 0;
1643}
1644static inline int of_clk_add_hw_provider(struct device_node *np,
1645 struct clk_hw *(*get)(struct of_phandle_args *clkspec,
1646 void *data),
1647 void *data)
1648{
1649 return 0;
1650}
1651static inline int devm_of_clk_add_hw_provider(struct device *dev,
1652 struct clk_hw *(*get)(struct of_phandle_args *clkspec,
1653 void *data),
1654 void *data)
1655{
1656 return 0;
1657}
1658static inline void of_clk_del_provider(struct device_node *np) {}
1659
1660static inline struct clk *of_clk_src_simple_get(
1661 struct of_phandle_args *clkspec, void *data)
1662{
1663 return ERR_PTR(-ENOENT);
1664}
1665static inline struct clk_hw *
1666of_clk_hw_simple_get(struct of_phandle_args *clkspec, void *data)
1667{
1668 return ERR_PTR(-ENOENT);
1669}
1670static inline struct clk *of_clk_src_onecell_get(
1671 struct of_phandle_args *clkspec, void *data)
1672{
1673 return ERR_PTR(-ENOENT);
1674}
1675static inline struct clk_hw *
1676of_clk_hw_onecell_get(struct of_phandle_args *clkspec, void *data)
1677{
1678 return ERR_PTR(-ENOENT);
1679}
1680static inline int of_clk_parent_fill(struct device_node *np,
1681 const char **parents, unsigned int size)
1682{
1683 return 0;
1684}
1685static inline int of_clk_detect_critical(struct device_node *np, int index,
1686 unsigned long *flags)
1687{
1688 return 0;
1689}
1690#endif /* CONFIG_OF */
1691
1692void clk_gate_restore_context(struct clk_hw *hw);
1693
1694#endif /* CLK_PROVIDER_H */