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1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (c) 2012, The Linux Foundation. All rights reserved.
4 */
5
6#ifndef _LINUX_CORESIGHT_H
7#define _LINUX_CORESIGHT_H
8
9#include <linux/amba/bus.h>
10#include <linux/clk.h>
11#include <linux/device.h>
12#include <linux/io.h>
13#include <linux/perf_event.h>
14#include <linux/sched.h>
15#include <linux/platform_device.h>
16
17/* Peripheral id registers (0xFD0-0xFEC) */
18#define CORESIGHT_PERIPHIDR4 0xfd0
19#define CORESIGHT_PERIPHIDR5 0xfd4
20#define CORESIGHT_PERIPHIDR6 0xfd8
21#define CORESIGHT_PERIPHIDR7 0xfdC
22#define CORESIGHT_PERIPHIDR0 0xfe0
23#define CORESIGHT_PERIPHIDR1 0xfe4
24#define CORESIGHT_PERIPHIDR2 0xfe8
25#define CORESIGHT_PERIPHIDR3 0xfeC
26/* Component id registers (0xFF0-0xFFC) */
27#define CORESIGHT_COMPIDR0 0xff0
28#define CORESIGHT_COMPIDR1 0xff4
29#define CORESIGHT_COMPIDR2 0xff8
30#define CORESIGHT_COMPIDR3 0xffC
31
32#define ETM_ARCH_V3_3 0x23
33#define ETM_ARCH_V3_5 0x25
34#define PFT_ARCH_V1_0 0x30
35#define PFT_ARCH_V1_1 0x31
36
37#define CORESIGHT_UNLOCK 0xc5acce55
38
39extern const struct bus_type coresight_bustype;
40
41enum coresight_dev_type {
42 CORESIGHT_DEV_TYPE_SINK,
43 CORESIGHT_DEV_TYPE_LINK,
44 CORESIGHT_DEV_TYPE_LINKSINK,
45 CORESIGHT_DEV_TYPE_SOURCE,
46 CORESIGHT_DEV_TYPE_HELPER,
47 CORESIGHT_DEV_TYPE_MAX
48};
49
50enum coresight_dev_subtype_sink {
51 CORESIGHT_DEV_SUBTYPE_SINK_DUMMY,
52 CORESIGHT_DEV_SUBTYPE_SINK_PORT,
53 CORESIGHT_DEV_SUBTYPE_SINK_BUFFER,
54 CORESIGHT_DEV_SUBTYPE_SINK_SYSMEM,
55 CORESIGHT_DEV_SUBTYPE_SINK_PERCPU_SYSMEM,
56};
57
58enum coresight_dev_subtype_link {
59 CORESIGHT_DEV_SUBTYPE_LINK_MERG,
60 CORESIGHT_DEV_SUBTYPE_LINK_SPLIT,
61 CORESIGHT_DEV_SUBTYPE_LINK_FIFO,
62};
63
64enum coresight_dev_subtype_source {
65 CORESIGHT_DEV_SUBTYPE_SOURCE_PROC,
66 CORESIGHT_DEV_SUBTYPE_SOURCE_BUS,
67 CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE,
68 CORESIGHT_DEV_SUBTYPE_SOURCE_TPDM,
69 CORESIGHT_DEV_SUBTYPE_SOURCE_OTHERS,
70};
71
72enum coresight_dev_subtype_helper {
73 CORESIGHT_DEV_SUBTYPE_HELPER_CATU,
74 CORESIGHT_DEV_SUBTYPE_HELPER_ECT_CTI,
75 CORESIGHT_DEV_SUBTYPE_HELPER_CTCU,
76};
77
78/**
79 * union coresight_dev_subtype - further characterisation of a type
80 * @sink_subtype: type of sink this component is, as defined
81 * by @coresight_dev_subtype_sink.
82 * @link_subtype: type of link this component is, as defined
83 * by @coresight_dev_subtype_link.
84 * @source_subtype: type of source this component is, as defined
85 * by @coresight_dev_subtype_source.
86 * @helper_subtype: type of helper this component is, as defined
87 * by @coresight_dev_subtype_helper.
88 */
89union coresight_dev_subtype {
90 /* We have some devices which acts as LINK and SINK */
91 struct {
92 enum coresight_dev_subtype_sink sink_subtype;
93 enum coresight_dev_subtype_link link_subtype;
94 };
95 enum coresight_dev_subtype_source source_subtype;
96 enum coresight_dev_subtype_helper helper_subtype;
97};
98
99/**
100 * struct coresight_platform_data - data harvested from the firmware
101 * specification.
102 *
103 * @nr_inconns: Number of elements for the input connections.
104 * @nr_outconns: Number of elements for the output connections.
105 * @out_conns: Array of nr_outconns pointers to connections from this
106 * component.
107 * @in_conns: Sparse array of pointers to input connections. Sparse
108 * because the source device owns the connection so when it's
109 * unloaded the connection leaves an empty slot.
110 */
111struct coresight_platform_data {
112 int nr_inconns;
113 int nr_outconns;
114 struct coresight_connection **out_conns;
115 struct coresight_connection **in_conns;
116};
117
118/**
119 * struct csdev_access - Abstraction of a CoreSight device access.
120 *
121 * @io_mem : True if the device has memory mapped I/O
122 * @base : When io_mem == true, base address of the component
123 * @read : Read from the given "offset" of the given instance.
124 * @write : Write "val" to the given "offset".
125 */
126struct csdev_access {
127 bool io_mem;
128 union {
129 void __iomem *base;
130 struct {
131 u64 (*read)(u32 offset, bool relaxed, bool _64bit);
132 void (*write)(u64 val, u32 offset, bool relaxed,
133 bool _64bit);
134 };
135 };
136};
137
138#define CSDEV_ACCESS_IOMEM(_addr) \
139 ((struct csdev_access) { \
140 .io_mem = true, \
141 .base = (_addr), \
142 })
143
144/**
145 * struct coresight_desc - description of a component required from drivers
146 * @type: as defined by @coresight_dev_type.
147 * @subtype: as defined by @coresight_dev_subtype.
148 * @ops: generic operations for this component, as defined
149 * by @coresight_ops.
150 * @pdata: platform data collected from DT.
151 * @dev: The device entity associated to this component.
152 * @groups: operations specific to this component. These will end up
153 * in the component's sysfs sub-directory.
154 * @name: name for the coresight device, also shown under sysfs.
155 * @access: Describe access to the device
156 */
157struct coresight_desc {
158 enum coresight_dev_type type;
159 union coresight_dev_subtype subtype;
160 const struct coresight_ops *ops;
161 struct coresight_platform_data *pdata;
162 struct device *dev;
163 const struct attribute_group **groups;
164 const char *name;
165 struct csdev_access access;
166};
167
168/**
169 * struct coresight_connection - representation of a single connection
170 * @src_port: a connection's output port number.
171 * @dest_port: destination's input port number @src_port is connected to.
172 * @dest_fwnode: destination component's fwnode handle.
173 * @dest_dev: a @coresight_device representation of the component
174 connected to @src_port. NULL until the device is created
175 * @link: Representation of the connection as a sysfs link.
176 * @filter_src_fwnode: filter source component's fwnode handle.
177 * @filter_src_dev: a @coresight_device representation of the component that
178 needs to be filtered.
179 *
180 * The full connection structure looks like this, where in_conns store
181 * references to same connection as the source device's out_conns.
182 *
183 * +-----------------------------+ +-----------------------------+
184 * |coresight_device | |coresight_connection |
185 * |-----------------------------| |-----------------------------|
186 * | | | |
187 * | | | dest_dev*|<--
188 * |pdata->out_conns[nr_outconns]|<->|src_dev* | |
189 * | | | | |
190 * +-----------------------------+ +-----------------------------+ |
191 * |
192 * +-----------------------------+ |
193 * |coresight_device | |
194 * |------------------------------ |
195 * | | |
196 * | pdata->in_conns[nr_inconns]|<--
197 * | |
198 * +-----------------------------+
199 */
200struct coresight_connection {
201 int src_port;
202 int dest_port;
203 struct fwnode_handle *dest_fwnode;
204 struct coresight_device *dest_dev;
205 struct coresight_sysfs_link *link;
206 struct coresight_device *src_dev;
207 struct fwnode_handle *filter_src_fwnode;
208 struct coresight_device *filter_src_dev;
209 int src_refcnt;
210 int dest_refcnt;
211};
212
213/**
214 * struct coresight_sysfs_link - representation of a connection in sysfs.
215 * @orig: Originating (master) coresight device for the link.
216 * @orig_name: Name to use for the link orig->target.
217 * @target: Target (slave) coresight device for the link.
218 * @target_name: Name to use for the link target->orig.
219 */
220struct coresight_sysfs_link {
221 struct coresight_device *orig;
222 const char *orig_name;
223 struct coresight_device *target;
224 const char *target_name;
225};
226
227/* architecturally we have 128 IDs some of which are reserved */
228#define CORESIGHT_TRACE_IDS_MAX 128
229
230/**
231 * Trace ID map.
232 *
233 * @used_ids: Bitmap to register available (bit = 0) and in use (bit = 1) IDs.
234 * Initialised so that the reserved IDs are permanently marked as
235 * in use.
236 * @perf_cs_etm_session_active: Number of Perf sessions using this ID map.
237 */
238struct coresight_trace_id_map {
239 DECLARE_BITMAP(used_ids, CORESIGHT_TRACE_IDS_MAX);
240 atomic_t __percpu *cpu_map;
241 atomic_t perf_cs_etm_session_active;
242 raw_spinlock_t lock;
243};
244
245/**
246 * struct coresight_device - representation of a device as used by the framework
247 * @pdata: Platform data with device connections associated to this device.
248 * @type: as defined by @coresight_dev_type.
249 * @subtype: as defined by @coresight_dev_subtype.
250 * @ops: generic operations for this component, as defined
251 * by @coresight_ops.
252 * @access: Device i/o access abstraction for this device.
253 * @dev: The device entity associated to this component.
254 * @mode: The device mode, i.e sysFS, Perf or disabled. This is actually
255 * an 'enum cs_mode' but stored in an atomic type. Access is always
256 * through atomic APIs, ensuring SMP-safe synchronisation between
257 * racing from sysFS and Perf mode. A compare-and-exchange
258 * operation is done to atomically claim one mode or the other.
259 * @refcnt: keep track of what is in use. Only access this outside of the
260 * device's spinlock when the coresight_mutex held and mode ==
261 * CS_MODE_SYSFS. Otherwise it must be accessed from inside the
262 * spinlock.
263 * @orphan: true if the component has connections that haven't been linked.
264 * @sysfs_sink_activated: 'true' when a sink has been selected for use via sysfs
265 * by writing a 1 to the 'enable_sink' file. A sink can be
266 * activated but not yet enabled. Enabling for a _sink_ happens
267 * when a source has been selected and a path is enabled from
268 * source to that sink. A sink can also become enabled but not
269 * activated if it's used via Perf.
270 * @ea: Device attribute for sink representation under PMU directory.
271 * @def_sink: cached reference to default sink found for this device.
272 * @nr_links: number of sysfs links created to other components from this
273 * device. These will appear in the "connections" group.
274 * @has_conns_grp: Have added a "connections" group for sysfs links.
275 * @feature_csdev_list: List of complex feature programming added to the device.
276 * @config_csdev_list: List of system configurations added to the device.
277 * @cscfg_csdev_lock: Protect the lists of configurations and features.
278 * @active_cscfg_ctxt: Context information for current active system configuration.
279 */
280struct coresight_device {
281 struct coresight_platform_data *pdata;
282 enum coresight_dev_type type;
283 union coresight_dev_subtype subtype;
284 const struct coresight_ops *ops;
285 struct csdev_access access;
286 struct device dev;
287 atomic_t mode;
288 int refcnt;
289 bool orphan;
290 /* sink specific fields */
291 bool sysfs_sink_activated;
292 struct dev_ext_attribute *ea;
293 struct coresight_device *def_sink;
294 struct coresight_trace_id_map perf_sink_id_map;
295 /* sysfs links between components */
296 int nr_links;
297 bool has_conns_grp;
298 /* system configuration and feature lists */
299 struct list_head feature_csdev_list;
300 struct list_head config_csdev_list;
301 raw_spinlock_t cscfg_csdev_lock;
302 void *active_cscfg_ctxt;
303};
304
305/*
306 * coresight_dev_list - Mapping for devices to "name" index for device
307 * names.
308 *
309 * @node: Node on the global device index list.
310 * @nr_idx: Number of entries already allocated.
311 * @pfx: Prefix pattern for device name.
312 * @fwnode_list: Array of fwnode_handles associated with each allocated
313 * index, upto nr_idx entries.
314 */
315struct coresight_dev_list {
316 struct list_head node;
317 int nr_idx;
318 char *pfx;
319 struct fwnode_handle **fwnode_list;
320};
321
322#define to_coresight_device(d) container_of(d, struct coresight_device, dev)
323
324/**
325 * struct coresight_path - data needed by enable/disable path
326 * @path_list: path from source to sink.
327 * @trace_id: trace_id of the whole path.
328 * @handle: handle of the aux_event.
329 */
330struct coresight_path {
331 struct list_head path_list;
332 u8 trace_id;
333 struct perf_output_handle *handle;
334};
335
336enum cs_mode {
337 CS_MODE_DISABLED,
338 CS_MODE_SYSFS,
339 CS_MODE_PERF,
340};
341
342#define coresight_ops(csdev) csdev->ops
343#define source_ops(csdev) csdev->ops->source_ops
344#define sink_ops(csdev) csdev->ops->sink_ops
345#define link_ops(csdev) csdev->ops->link_ops
346#define helper_ops(csdev) csdev->ops->helper_ops
347#define ect_ops(csdev) csdev->ops->ect_ops
348#define panic_ops(csdev) csdev->ops->panic_ops
349
350/**
351 * struct coresight_ops_sink - basic operations for a sink
352 * Operations available for sinks
353 * @enable: enables the sink.
354 * @disable: disables the sink.
355 * @alloc_buffer: initialises perf's ring buffer for trace collection.
356 * @free_buffer: release memory allocated in @get_config.
357 * @update_buffer: update buffer pointers after a trace session.
358 */
359struct coresight_ops_sink {
360 int (*enable)(struct coresight_device *csdev, enum cs_mode mode,
361 struct coresight_path *path);
362 int (*disable)(struct coresight_device *csdev);
363 void *(*alloc_buffer)(struct coresight_device *csdev,
364 struct perf_event *event, void **pages,
365 int nr_pages, bool overwrite);
366 void (*free_buffer)(void *config);
367 unsigned long (*update_buffer)(struct coresight_device *csdev,
368 struct perf_output_handle *handle,
369 void *sink_config);
370};
371
372/**
373 * struct coresight_ops_link - basic operations for a link
374 * Operations available for links.
375 * @enable: enables flow between iport and oport.
376 * @disable: disables flow between iport and oport.
377 */
378struct coresight_ops_link {
379 int (*enable)(struct coresight_device *csdev,
380 struct coresight_connection *in,
381 struct coresight_connection *out);
382 void (*disable)(struct coresight_device *csdev,
383 struct coresight_connection *in,
384 struct coresight_connection *out);
385};
386
387/**
388 * struct coresight_ops_source - basic operations for a source
389 * Operations available for sources.
390 * @cpu_id: returns the value of the CPU number this component
391 * is associated to.
392 * @enable: enables tracing for a source.
393 * @disable: disables tracing for a source.
394 * @resume_perf: resumes tracing for a source in perf session.
395 * @pause_perf: pauses tracing for a source in perf session.
396 */
397struct coresight_ops_source {
398 int (*cpu_id)(struct coresight_device *csdev);
399 int (*enable)(struct coresight_device *csdev, struct perf_event *event,
400 enum cs_mode mode, struct coresight_path *path);
401 void (*disable)(struct coresight_device *csdev,
402 struct perf_event *event);
403 int (*resume_perf)(struct coresight_device *csdev);
404 void (*pause_perf)(struct coresight_device *csdev);
405};
406
407/**
408 * struct coresight_ops_helper - Operations for a helper device.
409 *
410 * All operations could pass in a device specific data, which could
411 * help the helper device to determine what to do.
412 *
413 * @enable : Enable the device
414 * @disable : Disable the device
415 */
416struct coresight_ops_helper {
417 int (*enable)(struct coresight_device *csdev, enum cs_mode mode,
418 struct coresight_path *path);
419 int (*disable)(struct coresight_device *csdev,
420 struct coresight_path *path);
421};
422
423
424/**
425 * struct coresight_ops_panic - Generic device ops for panic handing
426 *
427 * @sync : Sync the device register state/trace data
428 */
429struct coresight_ops_panic {
430 int (*sync)(struct coresight_device *csdev);
431};
432
433struct coresight_ops {
434 int (*trace_id)(struct coresight_device *csdev, enum cs_mode mode,
435 struct coresight_device *sink);
436 const struct coresight_ops_sink *sink_ops;
437 const struct coresight_ops_link *link_ops;
438 const struct coresight_ops_source *source_ops;
439 const struct coresight_ops_helper *helper_ops;
440 const struct coresight_ops_panic *panic_ops;
441};
442
443static inline u32 csdev_access_relaxed_read32(struct csdev_access *csa,
444 u32 offset)
445{
446 if (likely(csa->io_mem))
447 return readl_relaxed(csa->base + offset);
448
449 return csa->read(offset, true, false);
450}
451
452#define CORESIGHT_CIDRn(i) (0xFF0 + ((i) * 4))
453
454static inline u32 coresight_get_cid(void __iomem *base)
455{
456 u32 i, cid = 0;
457
458 for (i = 0; i < 4; i++)
459 cid |= readl(base + CORESIGHT_CIDRn(i)) << (i * 8);
460
461 return cid;
462}
463
464static inline bool is_coresight_device(void __iomem *base)
465{
466 u32 cid = coresight_get_cid(base);
467
468 return cid == CORESIGHT_CID;
469}
470
471#define CORESIGHT_PIDRn(i) (0xFE0 + ((i) * 4))
472
473static inline u32 coresight_get_pid(struct csdev_access *csa)
474{
475 u32 i, pid = 0;
476
477 for (i = 0; i < 4; i++)
478 pid |= csdev_access_relaxed_read32(csa, CORESIGHT_PIDRn(i)) << (i * 8);
479
480 return pid;
481}
482
483static inline u64 csdev_access_relaxed_read_pair(struct csdev_access *csa,
484 u32 lo_offset, u32 hi_offset)
485{
486 if (likely(csa->io_mem)) {
487 return readl_relaxed(csa->base + lo_offset) |
488 ((u64)readl_relaxed(csa->base + hi_offset) << 32);
489 }
490
491 return csa->read(lo_offset, true, false) | (csa->read(hi_offset, true, false) << 32);
492}
493
494static inline void csdev_access_relaxed_write_pair(struct csdev_access *csa, u64 val,
495 u32 lo_offset, u32 hi_offset)
496{
497 if (likely(csa->io_mem)) {
498 writel_relaxed((u32)val, csa->base + lo_offset);
499 writel_relaxed((u32)(val >> 32), csa->base + hi_offset);
500 } else {
501 csa->write((u32)val, lo_offset, true, false);
502 csa->write((u32)(val >> 32), hi_offset, true, false);
503 }
504}
505
506static inline u32 csdev_access_read32(struct csdev_access *csa, u32 offset)
507{
508 if (likely(csa->io_mem))
509 return readl(csa->base + offset);
510
511 return csa->read(offset, false, false);
512}
513
514static inline void csdev_access_relaxed_write32(struct csdev_access *csa,
515 u32 val, u32 offset)
516{
517 if (likely(csa->io_mem))
518 writel_relaxed(val, csa->base + offset);
519 else
520 csa->write(val, offset, true, false);
521}
522
523static inline void csdev_access_write32(struct csdev_access *csa, u32 val, u32 offset)
524{
525 if (likely(csa->io_mem))
526 writel(val, csa->base + offset);
527 else
528 csa->write(val, offset, false, false);
529}
530
531#ifdef CONFIG_64BIT
532
533static inline u64 csdev_access_relaxed_read64(struct csdev_access *csa,
534 u32 offset)
535{
536 if (likely(csa->io_mem))
537 return readq_relaxed(csa->base + offset);
538
539 return csa->read(offset, true, true);
540}
541
542static inline u64 csdev_access_read64(struct csdev_access *csa, u32 offset)
543{
544 if (likely(csa->io_mem))
545 return readq(csa->base + offset);
546
547 return csa->read(offset, false, true);
548}
549
550static inline void csdev_access_relaxed_write64(struct csdev_access *csa,
551 u64 val, u32 offset)
552{
553 if (likely(csa->io_mem))
554 writeq_relaxed(val, csa->base + offset);
555 else
556 csa->write(val, offset, true, true);
557}
558
559static inline void csdev_access_write64(struct csdev_access *csa, u64 val, u32 offset)
560{
561 if (likely(csa->io_mem))
562 writeq(val, csa->base + offset);
563 else
564 csa->write(val, offset, false, true);
565}
566
567#else /* !CONFIG_64BIT */
568
569static inline u64 csdev_access_relaxed_read64(struct csdev_access *csa,
570 u32 offset)
571{
572 WARN_ON(1);
573 return 0;
574}
575
576static inline u64 csdev_access_read64(struct csdev_access *csa, u32 offset)
577{
578 WARN_ON(1);
579 return 0;
580}
581
582static inline void csdev_access_relaxed_write64(struct csdev_access *csa,
583 u64 val, u32 offset)
584{
585 WARN_ON(1);
586}
587
588static inline void csdev_access_write64(struct csdev_access *csa, u64 val, u32 offset)
589{
590 WARN_ON(1);
591}
592#endif /* CONFIG_64BIT */
593
594static inline bool coresight_is_device_source(struct coresight_device *csdev)
595{
596 return csdev && (csdev->type == CORESIGHT_DEV_TYPE_SOURCE);
597}
598
599static inline bool coresight_is_percpu_source(struct coresight_device *csdev)
600{
601 return csdev && coresight_is_device_source(csdev) &&
602 (csdev->subtype.source_subtype == CORESIGHT_DEV_SUBTYPE_SOURCE_PROC);
603}
604
605static inline bool coresight_is_percpu_sink(struct coresight_device *csdev)
606{
607 return csdev && (csdev->type == CORESIGHT_DEV_TYPE_SINK) &&
608 (csdev->subtype.sink_subtype == CORESIGHT_DEV_SUBTYPE_SINK_PERCPU_SYSMEM);
609}
610
611/*
612 * Atomically try to take the device and set a new mode. Returns true on
613 * success, false if the device is already taken by someone else.
614 */
615static inline bool coresight_take_mode(struct coresight_device *csdev,
616 enum cs_mode new_mode)
617{
618 int curr = CS_MODE_DISABLED;
619
620 return atomic_try_cmpxchg_acquire(&csdev->mode, &curr, new_mode);
621}
622
623static inline enum cs_mode coresight_get_mode(struct coresight_device *csdev)
624{
625 return atomic_read_acquire(&csdev->mode);
626}
627
628static inline void coresight_set_mode(struct coresight_device *csdev,
629 enum cs_mode new_mode)
630{
631 enum cs_mode current_mode = coresight_get_mode(csdev);
632
633 /*
634 * Changing to a new mode must be done from an already disabled state
635 * unless it's synchronized with coresight_take_mode(). Otherwise the
636 * device is already in use and signifies a locking issue.
637 */
638 WARN(new_mode != CS_MODE_DISABLED && current_mode != CS_MODE_DISABLED &&
639 current_mode != new_mode, "Device already in use\n");
640
641 atomic_set_release(&csdev->mode, new_mode);
642}
643
644struct coresight_device *coresight_register(struct coresight_desc *desc);
645void coresight_unregister(struct coresight_device *csdev);
646int coresight_enable_sysfs(struct coresight_device *csdev);
647void coresight_disable_sysfs(struct coresight_device *csdev);
648int coresight_timeout(struct csdev_access *csa, u32 offset, int position, int value);
649typedef void (*coresight_timeout_cb_t) (struct csdev_access *, u32, int, int);
650int coresight_timeout_action(struct csdev_access *csa, u32 offset, int position, int value,
651 coresight_timeout_cb_t cb);
652int coresight_claim_device(struct coresight_device *csdev);
653int coresight_claim_device_unlocked(struct coresight_device *csdev);
654
655int coresight_claim_device(struct coresight_device *csdev);
656int coresight_claim_device_unlocked(struct coresight_device *csdev);
657void coresight_clear_self_claim_tag(struct csdev_access *csa);
658void coresight_clear_self_claim_tag_unlocked(struct csdev_access *csa);
659void coresight_disclaim_device(struct coresight_device *csdev);
660void coresight_disclaim_device_unlocked(struct coresight_device *csdev);
661char *coresight_alloc_device_name(const char *prefix, struct device *dev);
662
663bool coresight_loses_context_with_cpu(struct device *dev);
664
665u32 coresight_relaxed_read32(struct coresight_device *csdev, u32 offset);
666u32 coresight_read32(struct coresight_device *csdev, u32 offset);
667void coresight_write32(struct coresight_device *csdev, u32 val, u32 offset);
668void coresight_relaxed_write32(struct coresight_device *csdev,
669 u32 val, u32 offset);
670u64 coresight_relaxed_read64(struct coresight_device *csdev, u32 offset);
671u64 coresight_read64(struct coresight_device *csdev, u32 offset);
672void coresight_relaxed_write64(struct coresight_device *csdev,
673 u64 val, u32 offset);
674void coresight_write64(struct coresight_device *csdev, u64 val, u32 offset);
675
676int coresight_get_cpu(struct device *dev);
677int coresight_get_static_trace_id(struct device *dev, u32 *id);
678
679struct coresight_platform_data *coresight_get_platform_data(struct device *dev);
680struct coresight_connection *
681coresight_add_out_conn(struct device *dev,
682 struct coresight_platform_data *pdata,
683 const struct coresight_connection *new_conn);
684int coresight_add_in_conn(struct coresight_connection *conn);
685struct coresight_device *
686coresight_find_input_type(struct coresight_platform_data *pdata,
687 enum coresight_dev_type type,
688 union coresight_dev_subtype subtype);
689struct coresight_device *
690coresight_find_output_type(struct coresight_platform_data *pdata,
691 enum coresight_dev_type type,
692 union coresight_dev_subtype subtype);
693
694int coresight_init_driver(const char *drv, struct amba_driver *amba_drv,
695 struct platform_driver *pdev_drv, struct module *owner);
696
697void coresight_remove_driver(struct amba_driver *amba_drv,
698 struct platform_driver *pdev_drv);
699int coresight_etm_get_trace_id(struct coresight_device *csdev, enum cs_mode mode,
700 struct coresight_device *sink);
701int coresight_get_enable_clocks(struct device *dev, struct clk **pclk,
702 struct clk **atclk);
703#endif /* _LINUX_COREISGHT_H */