Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (c) 2023 Meta Platforms, Inc. and affiliates
4 * Copyright (c) 2023 Intel and affiliates
5 */
6
7#ifndef __DPLL_H__
8#define __DPLL_H__
9
10#include <uapi/linux/dpll.h>
11#include <linux/device.h>
12#include <linux/netlink.h>
13#include <linux/netdevice.h>
14#include <linux/notifier.h>
15#include <linux/rtnetlink.h>
16
17struct dpll_device;
18struct dpll_pin;
19struct dpll_pin_esync;
20struct fwnode_handle;
21struct ref_tracker;
22
23struct dpll_device_ops {
24 int (*mode_get)(const struct dpll_device *dpll, void *dpll_priv,
25 enum dpll_mode *mode, struct netlink_ext_ack *extack);
26 int (*mode_set)(const struct dpll_device *dpll, void *dpll_priv,
27 enum dpll_mode mode, struct netlink_ext_ack *extack);
28 int (*supported_modes_get)(const struct dpll_device *dpll,
29 void *dpll_priv, unsigned long *modes,
30 struct netlink_ext_ack *extack);
31 int (*lock_status_get)(const struct dpll_device *dpll, void *dpll_priv,
32 enum dpll_lock_status *status,
33 enum dpll_lock_status_error *status_error,
34 struct netlink_ext_ack *extack);
35 int (*temp_get)(const struct dpll_device *dpll, void *dpll_priv,
36 s32 *temp, struct netlink_ext_ack *extack);
37 int (*clock_quality_level_get)(const struct dpll_device *dpll,
38 void *dpll_priv,
39 unsigned long *qls,
40 struct netlink_ext_ack *extack);
41 int (*phase_offset_monitor_set)(const struct dpll_device *dpll,
42 void *dpll_priv,
43 enum dpll_feature_state state,
44 struct netlink_ext_ack *extack);
45 int (*phase_offset_monitor_get)(const struct dpll_device *dpll,
46 void *dpll_priv,
47 enum dpll_feature_state *state,
48 struct netlink_ext_ack *extack);
49 int (*phase_offset_avg_factor_set)(const struct dpll_device *dpll,
50 void *dpll_priv, u32 factor,
51 struct netlink_ext_ack *extack);
52 int (*phase_offset_avg_factor_get)(const struct dpll_device *dpll,
53 void *dpll_priv, u32 *factor,
54 struct netlink_ext_ack *extack);
55};
56
57struct dpll_pin_ops {
58 int (*frequency_set)(const struct dpll_pin *pin, void *pin_priv,
59 const struct dpll_device *dpll, void *dpll_priv,
60 const u64 frequency,
61 struct netlink_ext_ack *extack);
62 int (*frequency_get)(const struct dpll_pin *pin, void *pin_priv,
63 const struct dpll_device *dpll, void *dpll_priv,
64 u64 *frequency, struct netlink_ext_ack *extack);
65 int (*direction_set)(const struct dpll_pin *pin, void *pin_priv,
66 const struct dpll_device *dpll, void *dpll_priv,
67 const enum dpll_pin_direction direction,
68 struct netlink_ext_ack *extack);
69 int (*direction_get)(const struct dpll_pin *pin, void *pin_priv,
70 const struct dpll_device *dpll, void *dpll_priv,
71 enum dpll_pin_direction *direction,
72 struct netlink_ext_ack *extack);
73 int (*state_on_pin_get)(const struct dpll_pin *pin, void *pin_priv,
74 const struct dpll_pin *parent_pin,
75 void *parent_pin_priv,
76 enum dpll_pin_state *state,
77 struct netlink_ext_ack *extack);
78 int (*state_on_dpll_get)(const struct dpll_pin *pin, void *pin_priv,
79 const struct dpll_device *dpll,
80 void *dpll_priv, enum dpll_pin_state *state,
81 struct netlink_ext_ack *extack);
82 int (*state_on_pin_set)(const struct dpll_pin *pin, void *pin_priv,
83 const struct dpll_pin *parent_pin,
84 void *parent_pin_priv,
85 const enum dpll_pin_state state,
86 struct netlink_ext_ack *extack);
87 int (*state_on_dpll_set)(const struct dpll_pin *pin, void *pin_priv,
88 const struct dpll_device *dpll,
89 void *dpll_priv,
90 const enum dpll_pin_state state,
91 struct netlink_ext_ack *extack);
92 int (*prio_get)(const struct dpll_pin *pin, void *pin_priv,
93 const struct dpll_device *dpll, void *dpll_priv,
94 u32 *prio, struct netlink_ext_ack *extack);
95 int (*prio_set)(const struct dpll_pin *pin, void *pin_priv,
96 const struct dpll_device *dpll, void *dpll_priv,
97 const u32 prio, struct netlink_ext_ack *extack);
98 int (*phase_offset_get)(const struct dpll_pin *pin, void *pin_priv,
99 const struct dpll_device *dpll, void *dpll_priv,
100 s64 *phase_offset,
101 struct netlink_ext_ack *extack);
102 int (*phase_adjust_get)(const struct dpll_pin *pin, void *pin_priv,
103 const struct dpll_device *dpll, void *dpll_priv,
104 s32 *phase_adjust,
105 struct netlink_ext_ack *extack);
106 int (*phase_adjust_set)(const struct dpll_pin *pin, void *pin_priv,
107 const struct dpll_device *dpll, void *dpll_priv,
108 const s32 phase_adjust,
109 struct netlink_ext_ack *extack);
110 int (*ffo_get)(const struct dpll_pin *pin, void *pin_priv,
111 const struct dpll_device *dpll, void *dpll_priv,
112 s64 *ffo, struct netlink_ext_ack *extack);
113 int (*esync_set)(const struct dpll_pin *pin, void *pin_priv,
114 const struct dpll_device *dpll, void *dpll_priv,
115 u64 freq, struct netlink_ext_ack *extack);
116 int (*esync_get)(const struct dpll_pin *pin, void *pin_priv,
117 const struct dpll_device *dpll, void *dpll_priv,
118 struct dpll_pin_esync *esync,
119 struct netlink_ext_ack *extack);
120 int (*ref_sync_set)(const struct dpll_pin *pin, void *pin_priv,
121 const struct dpll_pin *ref_sync_pin,
122 void *ref_sync_pin_priv,
123 const enum dpll_pin_state state,
124 struct netlink_ext_ack *extack);
125 int (*ref_sync_get)(const struct dpll_pin *pin, void *pin_priv,
126 const struct dpll_pin *ref_sync_pin,
127 void *ref_sync_pin_priv,
128 enum dpll_pin_state *state,
129 struct netlink_ext_ack *extack);
130};
131
132struct dpll_pin_frequency {
133 u64 min;
134 u64 max;
135};
136
137#define DPLL_PIN_FREQUENCY_RANGE(_min, _max) \
138 { \
139 .min = _min, \
140 .max = _max, \
141 }
142
143#define DPLL_PIN_FREQUENCY(_val) DPLL_PIN_FREQUENCY_RANGE(_val, _val)
144#define DPLL_PIN_FREQUENCY_1PPS \
145 DPLL_PIN_FREQUENCY(DPLL_PIN_FREQUENCY_1_HZ)
146#define DPLL_PIN_FREQUENCY_10MHZ \
147 DPLL_PIN_FREQUENCY(DPLL_PIN_FREQUENCY_10_MHZ)
148#define DPLL_PIN_FREQUENCY_IRIG_B \
149 DPLL_PIN_FREQUENCY(DPLL_PIN_FREQUENCY_10_KHZ)
150#define DPLL_PIN_FREQUENCY_DCF77 \
151 DPLL_PIN_FREQUENCY(DPLL_PIN_FREQUENCY_77_5_KHZ)
152
153struct dpll_pin_phase_adjust_range {
154 s32 min;
155 s32 max;
156};
157
158struct dpll_pin_esync {
159 u64 freq;
160 const struct dpll_pin_frequency *range;
161 u8 range_num;
162 u8 pulse;
163};
164
165struct dpll_pin_properties {
166 const char *board_label;
167 const char *panel_label;
168 const char *package_label;
169 enum dpll_pin_type type;
170 unsigned long capabilities;
171 u32 freq_supported_num;
172 struct dpll_pin_frequency *freq_supported;
173 struct dpll_pin_phase_adjust_range phase_range;
174 u32 phase_gran;
175};
176
177#ifdef CONFIG_DPLL_REFCNT_TRACKER
178typedef struct ref_tracker *dpll_tracker;
179#else
180typedef struct {} dpll_tracker;
181#endif
182
183#define DPLL_DEVICE_CREATED 1
184#define DPLL_DEVICE_DELETED 2
185#define DPLL_DEVICE_CHANGED 3
186#define DPLL_PIN_CREATED 4
187#define DPLL_PIN_DELETED 5
188#define DPLL_PIN_CHANGED 6
189
190struct dpll_device_notifier_info {
191 struct dpll_device *dpll;
192 u32 id;
193 u32 idx;
194 u64 clock_id;
195 enum dpll_type type;
196};
197
198struct dpll_pin_notifier_info {
199 struct dpll_pin *pin;
200 u32 id;
201 u32 idx;
202 u64 clock_id;
203 const struct fwnode_handle *fwnode;
204 const struct dpll_pin_properties *prop;
205};
206
207#if IS_ENABLED(CONFIG_DPLL)
208void dpll_netdev_pin_set(struct net_device *dev, struct dpll_pin *dpll_pin);
209void dpll_netdev_pin_clear(struct net_device *dev);
210
211size_t dpll_netdev_pin_handle_size(const struct net_device *dev);
212int dpll_netdev_add_pin_handle(struct sk_buff *msg,
213 const struct net_device *dev);
214
215struct dpll_pin *fwnode_dpll_pin_find(struct fwnode_handle *fwnode,
216 dpll_tracker *tracker);
217#else
218static inline void
219dpll_netdev_pin_set(struct net_device *dev, struct dpll_pin *dpll_pin) { }
220static inline void dpll_netdev_pin_clear(struct net_device *dev) { }
221
222static inline size_t dpll_netdev_pin_handle_size(const struct net_device *dev)
223{
224 return 0;
225}
226
227static inline int
228dpll_netdev_add_pin_handle(struct sk_buff *msg, const struct net_device *dev)
229{
230 return 0;
231}
232
233static inline struct dpll_pin *
234fwnode_dpll_pin_find(struct fwnode_handle *fwnode, dpll_tracker *tracker)
235{
236 return NULL;
237}
238#endif
239
240struct dpll_device *
241dpll_device_get(u64 clock_id, u32 dev_driver_id, struct module *module,
242 dpll_tracker *tracker);
243
244void dpll_device_put(struct dpll_device *dpll, dpll_tracker *tracker);
245
246int dpll_device_register(struct dpll_device *dpll, enum dpll_type type,
247 const struct dpll_device_ops *ops, void *priv);
248
249void dpll_device_unregister(struct dpll_device *dpll,
250 const struct dpll_device_ops *ops, void *priv);
251
252#define DPLL_PIN_IDX_UNSPEC U32_MAX
253
254struct dpll_pin *
255dpll_pin_get(u64 clock_id, u32 dev_driver_id, struct module *module,
256 const struct dpll_pin_properties *prop, dpll_tracker *tracker);
257
258int dpll_pin_register(struct dpll_device *dpll, struct dpll_pin *pin,
259 const struct dpll_pin_ops *ops, void *priv);
260
261void dpll_pin_unregister(struct dpll_device *dpll, struct dpll_pin *pin,
262 const struct dpll_pin_ops *ops, void *priv);
263
264void dpll_pin_put(struct dpll_pin *pin, dpll_tracker *tracker);
265
266void dpll_pin_fwnode_set(struct dpll_pin *pin, struct fwnode_handle *fwnode);
267
268int dpll_pin_on_pin_register(struct dpll_pin *parent, struct dpll_pin *pin,
269 const struct dpll_pin_ops *ops, void *priv);
270
271void dpll_pin_on_pin_unregister(struct dpll_pin *parent, struct dpll_pin *pin,
272 const struct dpll_pin_ops *ops, void *priv);
273
274int dpll_pin_ref_sync_pair_add(struct dpll_pin *pin,
275 struct dpll_pin *ref_sync_pin);
276
277int dpll_device_change_ntf(struct dpll_device *dpll);
278
279int dpll_pin_change_ntf(struct dpll_pin *pin);
280
281int register_dpll_notifier(struct notifier_block *nb);
282
283int unregister_dpll_notifier(struct notifier_block *nb);
284
285#endif