Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef _LINUX_BRCMPHY_H
3#define _LINUX_BRCMPHY_H
4
5#include <linux/phy.h>
6
7/* All Broadcom Ethernet switches have a pseudo-PHY at address 30 which is used
8 * to configure the switch internal registers via MDIO accesses.
9 */
10#define BRCM_PSEUDO_PHY_ADDR 30
11
12#define PHY_ID_BCM50610 0x0143bd60
13#define PHY_ID_BCM50610M 0x0143bd70
14#define PHY_ID_BCM5221 0x004061e0
15#define PHY_ID_BCM5241 0x0143bc30
16#define PHY_ID_BCMAC131 0x0143bc70
17#define PHY_ID_BCM5481 0x0143bca0
18#define PHY_ID_BCM5395 0x0143bcf0
19#define PHY_ID_BCM53125 0x03625f20
20#define PHY_ID_BCM53128 0x03625e10
21#define PHY_ID_BCM54810 0x03625d00
22#define PHY_ID_BCM54811 0x03625cc0
23#define PHY_ID_BCM5482 0x0143bcb0
24#define PHY_ID_BCM5411 0x00206070
25#define PHY_ID_BCM5421 0x002060e0
26#define PHY_ID_BCM54210E 0x600d84a0
27#define PHY_ID_BCM5464 0x002060b0
28#define PHY_ID_BCM5461 0x002060c0
29#define PHY_ID_BCM54612E 0x03625e60
30#define PHY_ID_BCM54616S 0x03625d10
31#define PHY_ID_BCM54140 0xae025009
32#define PHY_ID_BCM57780 0x03625d90
33#define PHY_ID_BCM89610 0x03625cd0
34
35#define PHY_ID_BCM72113 0x35905310
36#define PHY_ID_BCM72116 0x35905350
37#define PHY_ID_BCM72165 0x35905340
38#define PHY_ID_BCM7250 0xae025280
39#define PHY_ID_BCM7255 0xae025120
40#define PHY_ID_BCM7260 0xae025190
41#define PHY_ID_BCM7268 0xae025090
42#define PHY_ID_BCM7271 0xae0253b0
43#define PHY_ID_BCM7278 0xae0251a0
44#define PHY_ID_BCM7364 0xae025260
45#define PHY_ID_BCM7366 0x600d8490
46#define PHY_ID_BCM7346 0x600d8650
47#define PHY_ID_BCM7362 0x600d84b0
48#define PHY_ID_BCM74165 0x359052c0
49#define PHY_ID_BCM7425 0x600d86b0
50#define PHY_ID_BCM7429 0x600d8730
51#define PHY_ID_BCM7435 0x600d8750
52#define PHY_ID_BCM74371 0xae0252e0
53#define PHY_ID_BCM7439 0x600d8480
54#define PHY_ID_BCM7439_2 0xae025080
55#define PHY_ID_BCM7445 0x600d8510
56#define PHY_ID_BCM7712 0x35905330
57
58#define PHY_ID_BCM_CYGNUS 0xae025200
59#define PHY_ID_BCM_OMEGA 0xae025100
60
61#define PHY_BCM_OUI_MASK 0xfffffc00
62#define PHY_BCM_OUI_1 0x00206000
63#define PHY_BCM_OUI_2 0x0143bc00
64#define PHY_BCM_OUI_3 0x03625c00
65#define PHY_BCM_OUI_4 0x600d8400
66#define PHY_BCM_OUI_5 0x03625e00
67#define PHY_BCM_OUI_6 0xae025000
68
69#define PHY_BRCM_AUTO_PWRDWN_ENABLE 0x00000001
70#define PHY_BRCM_RX_REFCLK_UNUSED 0x00000002
71#define PHY_BRCM_CLEAR_RGMII_MODE 0x00000004
72#define PHY_BRCM_DIS_TXCRXC_NOENRGY 0x00000008
73#define PHY_BRCM_EN_MASTER_MODE 0x00000010
74#define PHY_BRCM_IDDQ_SUSPEND 0x00000020
75
76/* Broadcom BCM7xxx specific workarounds */
77#define PHY_BRCM_7XXX_REV(x) (((x) >> 8) & 0xff)
78#define PHY_BRCM_7XXX_PATCH(x) ((x) & 0xff)
79#define PHY_BCM_FLAGS_VALID 0x80000000
80
81/* Broadcom BCM54XX register definitions, common to most Broadcom PHYs */
82#define MII_BCM54XX_ECR 0x10 /* BCM54xx extended control register */
83#define MII_BCM54XX_ECR_IM 0x1000 /* Interrupt mask */
84#define MII_BCM54XX_ECR_IF 0x0800 /* Interrupt force */
85#define MII_BCM54XX_ECR_FIFOE 0x0001 /* FIFO elasticity */
86
87#define MII_BCM54XX_ESR 0x11 /* BCM54xx extended status register */
88#define MII_BCM54XX_ESR_IS 0x1000 /* Interrupt status */
89
90#define MII_BCM54XX_EXP_DATA 0x15 /* Expansion register data */
91#define MII_BCM54XX_EXP_SEL 0x17 /* Expansion register select */
92#define MII_BCM54XX_EXP_SEL_TOP 0x0d00 /* TOP_MISC expansion register select */
93#define MII_BCM54XX_EXP_SEL_SSD 0x0e00 /* Secondary SerDes select */
94#define MII_BCM54XX_EXP_SEL_WOL 0x0e00 /* Wake-on-LAN expansion select register */
95#define MII_BCM54XX_EXP_SEL_ER 0x0f00 /* Expansion register select */
96#define MII_BCM54XX_EXP_SEL_ETC 0x0d00 /* Expansion register spare + 2k mem */
97
98#define MII_BCM54XX_AUX_CTL 0x18 /* Auxiliary control register */
99#define MII_BCM54XX_ISR 0x1a /* BCM54xx interrupt status register */
100#define MII_BCM54XX_IMR 0x1b /* BCM54xx interrupt mask register */
101#define MII_BCM54XX_INT_CRCERR 0x0001 /* CRC error */
102#define MII_BCM54XX_INT_LINK 0x0002 /* Link status changed */
103#define MII_BCM54XX_INT_SPEED 0x0004 /* Link speed change */
104#define MII_BCM54XX_INT_DUPLEX 0x0008 /* Duplex mode changed */
105#define MII_BCM54XX_INT_LRS 0x0010 /* Local receiver status changed */
106#define MII_BCM54XX_INT_RRS 0x0020 /* Remote receiver status changed */
107#define MII_BCM54XX_INT_SSERR 0x0040 /* Scrambler synchronization error */
108#define MII_BCM54XX_INT_UHCD 0x0080 /* Unsupported HCD negotiated */
109#define MII_BCM54XX_INT_NHCD 0x0100 /* No HCD */
110#define MII_BCM54XX_INT_NHCDL 0x0200 /* No HCD link */
111#define MII_BCM54XX_INT_ANPR 0x0400 /* Auto-negotiation page received */
112#define MII_BCM54XX_INT_LC 0x0800 /* All counters below 128 */
113#define MII_BCM54XX_INT_HC 0x1000 /* Counter above 32768 */
114#define MII_BCM54XX_INT_MDIX 0x2000 /* MDIX status change */
115#define MII_BCM54XX_INT_PSERR 0x4000 /* Pair swap error */
116
117#define MII_BCM54XX_SHD 0x1c /* 0x1c shadow registers */
118#define MII_BCM54XX_SHD_WRITE 0x8000
119#define MII_BCM54XX_SHD_VAL(x) ((x & 0x1f) << 10)
120#define MII_BCM54XX_SHD_DATA(x) ((x & 0x3ff) << 0)
121
122#define MII_BCM54XX_RDB_ADDR 0x1e
123#define MII_BCM54XX_RDB_DATA 0x1f
124
125/* legacy access control via rdb/expansion register */
126#define BCM54XX_RDB_REG0087 0x0087
127#define BCM54XX_EXP_REG7E (MII_BCM54XX_EXP_SEL_ER + 0x7E)
128#define BCM54XX_ACCESS_MODE_LEGACY_EN BIT(15)
129
130/*
131 * AUXILIARY CONTROL SHADOW ACCESS REGISTERS. (PHY REG 0x18)
132 */
133#define MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL 0x00
134#define MII_BCM54XX_AUXCTL_ACTL_TX_6DB 0x0400
135#define MII_BCM54XX_AUXCTL_ACTL_SMDSP_ENA 0x0800
136#define MII_BCM54XX_AUXCTL_ACTL_EXT_PKT_LEN 0x4000
137
138#define MII_BCM54XX_AUXCTL_SHDWSEL_MISC 0x07
139#define MII_BCM54XX_AUXCTL_SHDWSEL_MISC_WIRESPEED_EN 0x0010
140#define MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RSVD 0x0060
141#define MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_EN 0x0080
142#define MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN 0x0100
143#define MII_BCM54XX_AUXCTL_MISC_FORCE_AMDIX 0x0200
144#define MII_BCM54XX_AUXCTL_MISC_WREN 0x8000
145
146#define MII_BCM54XX_AUXCTL_SHDWSEL_READ_SHIFT 12
147#define MII_BCM54XX_AUXCTL_SHDWSEL_MASK 0x0007
148
149/*
150 * Broadcom LED source encodings. These are used in BCM5461, BCM5481,
151 * BCM5482, and possibly some others.
152 */
153#define BCM_LED_SRC_LINKSPD1 0x0
154#define BCM_LED_SRC_LINKSPD2 0x1
155#define BCM_LED_SRC_XMITLED 0x2
156#define BCM_LED_SRC_ACTIVITYLED 0x3
157#define BCM_LED_SRC_FDXLED 0x4
158#define BCM_LED_SRC_SLAVE 0x5
159#define BCM_LED_SRC_INTR 0x6
160#define BCM_LED_SRC_QUALITY 0x7
161#define BCM_LED_SRC_RCVLED 0x8
162#define BCM_LED_SRC_WIRESPEED 0x9
163#define BCM_LED_SRC_MULTICOLOR1 0xa
164#define BCM_LED_SRC_OPENSHORT 0xb
165#define BCM_LED_SRC_OFF 0xe /* Tied high */
166#define BCM_LED_SRC_ON 0xf /* Tied low */
167#define BCM_LED_SRC_MASK GENMASK(3, 0)
168
169/*
170 * Broadcom Multicolor LED configurations (expansion register 4)
171 */
172#define BCM_EXP_MULTICOLOR (MII_BCM54XX_EXP_SEL_ER + 0x04)
173#define BCM_LED_MULTICOLOR_IN_PHASE BIT(8)
174#define BCM_LED_MULTICOLOR_LINK_ACT 0x0
175#define BCM_LED_MULTICOLOR_SPEED 0x1
176#define BCM_LED_MULTICOLOR_ACT_FLASH 0x2
177#define BCM_LED_MULTICOLOR_FDX 0x3
178#define BCM_LED_MULTICOLOR_OFF 0x4
179#define BCM_LED_MULTICOLOR_ON 0x5
180#define BCM_LED_MULTICOLOR_ALT 0x6
181#define BCM_LED_MULTICOLOR_FLASH 0x7
182#define BCM_LED_MULTICOLOR_LINK 0x8
183#define BCM_LED_MULTICOLOR_ACT 0x9
184#define BCM_LED_MULTICOLOR_PROGRAM 0xa
185
186/*
187 * Broadcom Synchronous Ethernet Controls (expansion register 0x0E)
188 */
189#define BCM_EXP_SYNC_ETHERNET (MII_BCM54XX_EXP_SEL_ER + 0x0E)
190#define BCM_EXP_SYNC_ETHERNET_MII_LITE BIT(11)
191
192/*
193 * BCM5482: Shadow registers
194 * Shadow values go into bits [14:10] of register 0x1c to select a shadow
195 * register to access.
196 */
197
198/* 00100: Reserved control register 2 */
199#define BCM54XX_SHD_SCR2 0x04
200#define BCM54XX_SHD_SCR2_WSPD_RTRY_DIS 0x100
201#define BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_SHIFT 2
202#define BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_OFFSET 2
203#define BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_MASK 0x7
204
205/* 00101: Spare Control Register 3 */
206#define BCM54XX_SHD_SCR3 0x05
207#define BCM54XX_SHD_SCR3_DEF_CLK125 0x0001
208#define BCM54XX_SHD_SCR3_DLLAPD_DIS 0x0002
209#define BCM54XX_SHD_SCR3_TRDDAPD 0x0004
210#define BCM54XX_SHD_SCR3_RXCTXC_DIS 0x0100
211
212/* 01010: Auto Power-Down */
213#define BCM54XX_SHD_APD 0x0a
214#define BCM_APD_CLR_MASK 0xFE9F /* clear bits 5, 6 & 8 */
215#define BCM54XX_SHD_APD_EN 0x0020
216#define BCM_NO_ANEG_APD_EN 0x0060 /* bits 5 & 6 */
217#define BCM_APD_SINGLELP_EN 0x0100 /* Bit 8 */
218
219#define BCM54XX_SHD_LEDS1 0x0d /* 01101: LED Selector 1 */
220 /* LED3 / ~LINKSPD[2] selector */
221#define BCM54XX_SHD_LEDS_SHIFT(led) (4 * (led))
222#define BCM54XX_SHD_LEDS1_LED3(src) ((src & 0xf) << 4)
223 /* LED1 / ~LINKSPD[1] selector */
224#define BCM54XX_SHD_LEDS1_LED1(src) ((src & 0xf) << 0)
225#define BCM54XX_SHD_LEDS2 0x0e /* 01110: LED Selector 2 */
226#define BCM54XX_SHD_RGMII_MODE 0x0b /* 01011: RGMII Mode Selector */
227#define BCM5482_SHD_SSD 0x14 /* 10100: Secondary SerDes control */
228#define BCM5482_SHD_SSD_LEDM 0x0008 /* SSD LED Mode enable */
229#define BCM5482_SHD_SSD_EN 0x0001 /* SSD enable */
230
231/* 10011: SerDes 100-FX Control Register */
232#define BCM54616S_SHD_100FX_CTRL 0x13
233#define BCM54616S_100FX_MODE BIT(0) /* 100-FX SerDes Enable */
234
235/* 11111: Mode Control Register */
236#define BCM54XX_SHD_MODE 0x1f
237#define BCM54XX_SHD_INTF_SEL_MASK GENMASK(2, 1) /* INTERF_SEL[1:0] */
238#define BCM54XX_SHD_INTF_SEL_RGMII 0x02
239#define BCM54XX_SHD_INTF_SEL_SGMII 0x04
240#define BCM54XX_SHD_INTF_SEL_GBIC 0x06
241#define BCM54XX_SHD_MODE_1000BX BIT(0) /* Enable 1000-X registers */
242
243/*
244 * EXPANSION SHADOW ACCESS REGISTERS. (PHY REG 0x15, 0x16, and 0x17)
245 */
246#define MII_BCM54XX_EXP_AADJ1CH0 0x001f
247#define MII_BCM54XX_EXP_AADJ1CH0_SWP_ABCD_OEN 0x0200
248#define MII_BCM54XX_EXP_AADJ1CH0_SWSEL_THPF 0x0100
249#define MII_BCM54XX_EXP_AADJ1CH3 0x601f
250#define MII_BCM54XX_EXP_AADJ1CH3_ADCCKADJ 0x0002
251#define MII_BCM54XX_EXP_EXP08 0x0F08
252#define MII_BCM54XX_EXP_EXP08_RJCT_2MHZ 0x0001
253#define MII_BCM54XX_EXP_EXP08_EARLY_DAC_WAKE 0x0200
254#define MII_BCM54XX_EXP_EXP08_FORCE_DAC_WAKE 0x0100
255#define MII_BCM54XX_EXP_EXP75 0x0f75
256#define MII_BCM54XX_EXP_EXP75_VDACCTRL 0x003c
257#define MII_BCM54XX_EXP_EXP75_CM_OSC 0x0001
258#define MII_BCM54XX_EXP_EXP96 0x0f96
259#define MII_BCM54XX_EXP_EXP96_MYST 0x0010
260#define MII_BCM54XX_EXP_EXP97 0x0f97
261#define MII_BCM54XX_EXP_EXP97_MYST 0x0c0c
262
263/* Top-MISC expansion registers */
264#define BCM54XX_TOP_MISC_IDDQ_CTRL (MII_BCM54XX_EXP_SEL_TOP + 0x06)
265#define BCM54XX_TOP_MISC_IDDQ_LP (1 << 0)
266#define BCM54XX_TOP_MISC_IDDQ_SD (1 << 2)
267#define BCM54XX_TOP_MISC_IDDQ_SR (1 << 3)
268
269#define BCM54XX_TOP_MISC_MII_BUF_CNTL0 (MII_BCM54XX_EXP_SEL_TOP + 0x00)
270#define BCM54XX_MII_BUF_CNTL0_AUTOGREEEN_EN BIT(0)
271
272#define BCM54XX_TOP_MISC_LED_CTL (MII_BCM54XX_EXP_SEL_TOP + 0x0C)
273#define BCM54XX_LED4_SEL_INTR BIT(1)
274
275/*
276 * BCM5482: Secondary SerDes registers
277 */
278#define BCM5482_SSD_1000BX_CTL 0x00 /* 1000BASE-X Control */
279#define BCM5482_SSD_1000BX_CTL_PWRDOWN 0x0800 /* Power-down SSD */
280#define BCM5482_SSD_SGMII_SLAVE 0x15 /* SGMII Slave Register */
281#define BCM5482_SSD_SGMII_SLAVE_EN 0x0002 /* Slave mode enable */
282#define BCM5482_SSD_SGMII_SLAVE_AD 0x0001 /* Slave auto-detection */
283
284/* BroadR-Reach LRE Registers. */
285#define MII_BCM54XX_LRECR 0x00 /* LRE Control Register */
286#define MII_BCM54XX_LRESR 0x01 /* LRE Status Register */
287#define MII_BCM54XX_LREPHYSID1 0x02 /* LRE PHYS ID 1 */
288#define MII_BCM54XX_LREPHYSID2 0x03 /* LRE PHYS ID 2 */
289#define MII_BCM54XX_LREANAA 0x04 /* LDS Auto-Negotiation Advertised Ability */
290#define MII_BCM54XX_LREANAC 0x05 /* LDS Auto-Negotiation Advertised Control */
291#define MII_BCM54XX_LREANPT 0x06 /* LDS Ability Next Page Transmit */
292#define MII_BCM54XX_LRELPA 0x07 /* LDS Link Partner Ability */
293#define MII_BCM54XX_LRELPNPM 0x08 /* LDS Link Partner Next Page Message */
294#define MII_BCM54XX_LRELPNPC 0x09 /* LDS Link Partner Next Page Control */
295#define MII_BCM54XX_LRELDSE 0x0a /* LDS Expansion Register */
296#define MII_BCM54XX_LREES 0x0f /* LRE Extended Status */
297
298/* LRE control register. */
299#define LRECR_RESET 0x8000 /* Reset to default state */
300#define LRECR_LOOPBACK 0x4000 /* Internal Loopback */
301#define LRECR_LDSRES 0x2000 /* Restart LDS Process */
302#define LRECR_LDSEN 0x1000 /* LDS Enable */
303#define LRECR_PDOWN 0x0800 /* Enable low power state */
304#define LRECR_ISOLATE 0x0400 /* Isolate data paths from MII */
305#define LRECR_SPEED100 0x0200 /* Select 100 Mbps */
306#define LRECR_SPEED10 0x0000 /* Select 10 Mbps */
307#define LRECR_4PAIRS 0x0020 /* Select 4 Pairs */
308#define LRECR_2PAIRS 0x0010 /* Select 2 Pairs */
309#define LRECR_1PAIR 0x0000 /* Select 1 Pair */
310#define LRECR_MASTER 0x0008 /* Force Master when LDS disabled */
311#define LRECR_SLAVE 0x0000 /* Force Slave when LDS disabled */
312
313/* LRE status register. */
314#define LRESR_100_1PAIR 0x2000 /* Can do 100Mbps 1 Pair */
315#define LRESR_100_4PAIR 0x1000 /* Can do 100Mbps 4 Pairs */
316#define LRESR_100_2PAIR 0x0800 /* Can do 100Mbps 2 Pairs */
317#define LRESR_10_2PAIR 0x0400 /* Can do 10Mbps 2 Pairs */
318#define LRESR_10_1PAIR 0x0200 /* Can do 10Mbps 1 Pair */
319#define LRESR_ESTATEN 0x0100 /* Extended Status in R15 */
320#define LRESR_RESV 0x0080 /* Unused... */
321#define LRESR_MFPS 0x0040 /* Can suppress Management Frames Preamble */
322#define LRESR_LDSCOMPLETE 0x0020 /* LDS Auto-negotiation complete */
323#define LRESR_8023 0x0010 /* Has IEEE 802.3 Support */
324#define LRESR_LDSABILITY 0x0008 /* LDS auto-negotiation capable */
325#define LRESR_LSTATUS 0x0004 /* Link status */
326#define LRESR_JCD 0x0002 /* Jabber detected */
327#define LRESR_ERCAP 0x0001 /* Ext-reg capability */
328
329/* LDS Auto-Negotiation Advertised Ability. */
330#define LREANAA_PAUSE_ASYM 0x8000 /* Can pause asymmetrically */
331#define LREANAA_PAUSE 0x4000 /* Can pause */
332#define LREANAA_100_1PAIR 0x0020 /* Can do 100Mbps 1 Pair */
333#define LREANAA_100_4PAIR 0x0010 /* Can do 100Mbps 4 Pair */
334#define LREANAA_100_2PAIR 0x0008 /* Can do 100Mbps 2 Pair */
335#define LREANAA_10_2PAIR 0x0004 /* Can do 10Mbps 2 Pair */
336#define LREANAA_10_1PAIR 0x0002 /* Can do 10Mbps 1 Pair */
337
338#define LRE_ADVERTISE_FULL (LREANAA_100_1PAIR | LREANAA_100_4PAIR | \
339 LREANAA_100_2PAIR | LREANAA_10_2PAIR | \
340 LREANAA_10_1PAIR)
341
342#define LRE_ADVERTISE_ALL LRE_ADVERTISE_FULL
343
344/* LDS Link Partner Ability. */
345#define LRELPA_PAUSE_ASYM 0x8000 /* Supports asymmetric pause */
346#define LRELPA_PAUSE 0x4000 /* Supports pause capability */
347#define LRELPA_100_1PAIR 0x0020 /* 100Mbps 1 Pair capable */
348#define LRELPA_100_4PAIR 0x0010 /* 100Mbps 4 Pair capable */
349#define LRELPA_100_2PAIR 0x0008 /* 100Mbps 2 Pair capable */
350#define LRELPA_10_2PAIR 0x0004 /* 10Mbps 2 Pair capable */
351#define LRELPA_10_1PAIR 0x0002 /* 10Mbps 1 Pair capable */
352
353/* LDS Expansion register. */
354#define LDSE_DOWNGRADE 0x8000 /* Can do LDS Speed Downgrade */
355#define LDSE_MASTER 0x4000 /* Master / Slave */
356#define LDSE_PAIRS_MASK 0x3000 /* Pair Count Mask */
357#define LDSE_PAIRS_SHIFT 12
358#define LDSE_4PAIRS (2 << LDSE_PAIRS_SHIFT) /* 4 Pairs Connection */
359#define LDSE_2PAIRS (1 << LDSE_PAIRS_SHIFT) /* 2 Pairs Connection */
360#define LDSE_1PAIR (0 << LDSE_PAIRS_SHIFT) /* 1 Pair Connection */
361#define LDSE_CABLEN_MASK 0x0FFF /* Cable Length Mask */
362
363/* BCM54810 Registers */
364#define BCM54810_EXP_BROADREACH_LRE_MISC_CTL (MII_BCM54XX_EXP_SEL_ER + 0x90)
365#define BCM54810_EXP_BROADREACH_LRE_MISC_CTL_EN (1 << 0)
366#define BCM54810_SHD_CLK_CTL 0x3
367#define BCM54810_SHD_CLK_CTL_GTXCLK_EN (1 << 9)
368
369/* BCM54811 Registers */
370#define BCM54811_EXP_BROADREACH_LRE_OVERLAY_CTL (MII_BCM54XX_EXP_SEL_ER + 0x9A)
371/* Access Control Override Enable */
372#define BCM54811_EXP_BROADREACH_LRE_OVERLAY_CTL_EN BIT(15)
373/* Access Control Override Value */
374#define BCM54811_EXP_BROADREACH_LRE_OVERLAY_CTL_OVERRIDE_VAL BIT(14)
375/* Access Control Value */
376#define BCM54811_EXP_BROADREACH_LRE_OVERLAY_CTL_VAL BIT(13)
377
378/* BCM54612E Registers */
379#define BCM54612E_EXP_SPARE0 (MII_BCM54XX_EXP_SEL_ETC + 0x34)
380#define BCM54612E_LED4_CLK125OUT_EN (1 << 1)
381
382
383/* Wake-on-LAN registers */
384#define BCM54XX_WOL_MAIN_CTL (MII_BCM54XX_EXP_SEL_WOL + 0x80)
385#define BCM54XX_WOL_EN BIT(0)
386#define BCM54XX_WOL_MODE_SINGLE_MPD 0
387#define BCM54XX_WOL_MODE_SINGLE_MPDSEC 1
388#define BCM54XX_WOL_MODE_DUAL 2
389#define BCM54XX_WOL_MODE_SHIFT 1
390#define BCM54XX_WOL_MODE_MASK 0x3
391#define BCM54XX_WOL_MP_MSB_FF_EN BIT(3)
392#define BCM54XX_WOL_SECKEY_OPT_4B 0
393#define BCM54XX_WOL_SECKEY_OPT_6B 1
394#define BCM54XX_WOL_SECKEY_OPT_8B 2
395#define BCM54XX_WOL_SECKEY_OPT_SHIFT 4
396#define BCM54XX_WOL_SECKEY_OPT_MASK 0x3
397#define BCM54XX_WOL_L2_TYPE_CHK BIT(6)
398#define BCM54XX_WOL_L4IPV4UDP_CHK BIT(7)
399#define BCM54XX_WOL_L4IPV6UDP_CHK BIT(8)
400#define BCM54XX_WOL_UDPPORT_CHK BIT(9)
401#define BCM54XX_WOL_CRC_CHK BIT(10)
402#define BCM54XX_WOL_SECKEY_MODE BIT(11)
403#define BCM54XX_WOL_RST BIT(12)
404#define BCM54XX_WOL_DIR_PKT_EN BIT(13)
405#define BCM54XX_WOL_MASK_MODE_DA_FF 0
406#define BCM54XX_WOL_MASK_MODE_DA_MPD 1
407#define BCM54XX_WOL_MASK_MODE_DA_ONLY 2
408#define BCM54XX_WOL_MASK_MODE_MPD 3
409#define BCM54XX_WOL_MASK_MODE_SHIFT 14
410#define BCM54XX_WOL_MASK_MODE_MASK 0x3
411
412#define BCM54XX_WOL_INNER_PROTO (MII_BCM54XX_EXP_SEL_WOL + 0x81)
413#define BCM54XX_WOL_OUTER_PROTO (MII_BCM54XX_EXP_SEL_WOL + 0x82)
414#define BCM54XX_WOL_OUTER_PROTO2 (MII_BCM54XX_EXP_SEL_WOL + 0x83)
415
416#define BCM54XX_WOL_MPD_DATA1(x) (MII_BCM54XX_EXP_SEL_WOL + 0x84 + (x))
417#define BCM54XX_WOL_MPD_DATA2(x) (MII_BCM54XX_EXP_SEL_WOL + 0x87 + (x))
418#define BCM54XX_WOL_SEC_KEY_8B (MII_BCM54XX_EXP_SEL_WOL + 0x8A)
419#define BCM54XX_WOL_MASK(x) (MII_BCM54XX_EXP_SEL_WOL + 0x8B + (x))
420#define BCM54XX_SEC_KEY_STORE(x) (MII_BCM54XX_EXP_SEL_WOL + 0x8E)
421#define BCM54XX_WOL_SHARED_CNT (MII_BCM54XX_EXP_SEL_WOL + 0x92)
422
423#define BCM54XX_WOL_INT_MASK (MII_BCM54XX_EXP_SEL_WOL + 0x93)
424#define BCM54XX_WOL_PKT1 BIT(0)
425#define BCM54XX_WOL_PKT2 BIT(1)
426#define BCM54XX_WOL_DIR BIT(2)
427#define BCM54XX_WOL_ALL_INTRS (BCM54XX_WOL_PKT1 | \
428 BCM54XX_WOL_PKT2 | \
429 BCM54XX_WOL_DIR)
430
431#define BCM54XX_WOL_INT_STATUS (MII_BCM54XX_EXP_SEL_WOL + 0x94)
432
433/* BCM5221 Registers */
434#define BCM5221_AEGSR 0x1C
435#define BCM5221_AEGSR_MDIX_STATUS BIT(13)
436#define BCM5221_AEGSR_MDIX_MAN_SWAP BIT(12)
437#define BCM5221_AEGSR_MDIX_DIS BIT(11)
438
439#define BCM5221_SHDW_AM4_EN_CLK_LPM BIT(2)
440#define BCM5221_SHDW_AM4_FORCE_LPM BIT(1)
441
442/*****************************************************************************/
443/* Fast Ethernet Transceiver definitions. */
444/*****************************************************************************/
445
446#define MII_BRCM_FET_INTREG 0x1a /* Interrupt register */
447#define MII_BRCM_FET_IR_MASK 0x0100 /* Mask all interrupts */
448#define MII_BRCM_FET_IR_LINK_EN 0x0200 /* Link status change enable */
449#define MII_BRCM_FET_IR_SPEED_EN 0x0400 /* Link speed change enable */
450#define MII_BRCM_FET_IR_DUPLEX_EN 0x0800 /* Duplex mode change enable */
451#define MII_BRCM_FET_IR_ENABLE 0x4000 /* Interrupt enable */
452
453#define MII_BRCM_FET_BRCMTEST 0x1f /* Brcm test register */
454#define MII_BRCM_FET_BT_SRE 0x0080 /* Shadow register enable */
455
456
457/*** Shadow register definitions ***/
458
459#define MII_BRCM_FET_SHDW_MISCCTRL 0x10 /* Shadow misc ctrl */
460#define MII_BRCM_FET_SHDW_MC_FAME 0x4000 /* Force Auto MDIX enable */
461
462#define MII_BRCM_FET_SHDW_AUXMODE4 0x1a /* Auxiliary mode 4 */
463#define MII_BRCM_FET_SHDW_AM4_STANDBY 0x0008 /* Standby enable */
464#define MII_BRCM_FET_SHDW_AM4_LED_MASK 0x0003
465#define MII_BRCM_FET_SHDW_AM4_LED_MODE1 0x0001
466
467#define MII_BRCM_FET_SHDW_AUXSTAT2 0x1b /* Auxiliary status 2 */
468#define MII_BRCM_FET_SHDW_AS2_APDE 0x0020 /* Auto power down enable */
469
470#define BRCM_CL45VEN_EEE_CONTROL 0x803d
471#define LPI_FEATURE_EN 0x8000
472#define LPI_FEATURE_EN_DIG1000X 0x4000
473
474#define BRCM_CL45VEN_EEE_LPI_CNT 0x803f
475
476/* Core register definitions*/
477#define MII_BRCM_CORE_BASE12 0x12
478#define MII_BRCM_CORE_BASE13 0x13
479#define MII_BRCM_CORE_BASE14 0x14
480#define MII_BRCM_CORE_BASE1E 0x1E
481#define MII_BRCM_CORE_EXPB0 0xB0
482#define MII_BRCM_CORE_EXPB1 0xB1
483
484/* Enhanced Cable Diagnostics */
485#define BCM54XX_RDB_ECD_CTRL 0x2a0
486#define BCM54XX_EXP_ECD_CTRL (MII_BCM54XX_EXP_SEL_ER + 0xc0)
487
488#define BCM54XX_ECD_CTRL_CABLE_TYPE_CAT3 1 /* CAT3 or worse */
489#define BCM54XX_ECD_CTRL_CABLE_TYPE_CAT5 0 /* CAT5 or better */
490#define BCM54XX_ECD_CTRL_CABLE_TYPE_MASK BIT(0) /* cable type */
491#define BCM54XX_ECD_CTRL_INVALID BIT(3) /* invalid result */
492#define BCM54XX_ECD_CTRL_UNIT_CM 0 /* centimeters */
493#define BCM54XX_ECD_CTRL_UNIT_M 1 /* meters */
494#define BCM54XX_ECD_CTRL_UNIT_MASK BIT(10) /* cable length unit */
495#define BCM54XX_ECD_CTRL_IN_PROGRESS BIT(11) /* test in progress */
496#define BCM54XX_ECD_CTRL_BREAK_LINK BIT(12) /* unconnect link
497 * during test
498 */
499#define BCM54XX_ECD_CTRL_CROSS_SHORT_DIS BIT(13) /* disable inter-pair
500 * short check
501 */
502#define BCM54XX_ECD_CTRL_RUN BIT(15) /* run immediate */
503
504#define BCM54XX_RDB_ECD_FAULT_TYPE 0x2a1
505#define BCM54XX_EXP_ECD_FAULT_TYPE (MII_BCM54XX_EXP_SEL_ER + 0xc1)
506#define BCM54XX_ECD_FAULT_TYPE_INVALID 0x0
507#define BCM54XX_ECD_FAULT_TYPE_OK 0x1
508#define BCM54XX_ECD_FAULT_TYPE_OPEN 0x2
509#define BCM54XX_ECD_FAULT_TYPE_SAME_SHORT 0x3 /* short same pair */
510#define BCM54XX_ECD_FAULT_TYPE_CROSS_SHORT 0x4 /* short different pairs */
511#define BCM54XX_ECD_FAULT_TYPE_BUSY 0x9
512#define BCM54XX_ECD_FAULT_TYPE_PAIR_D_MASK GENMASK(3, 0)
513#define BCM54XX_ECD_FAULT_TYPE_PAIR_C_MASK GENMASK(7, 4)
514#define BCM54XX_ECD_FAULT_TYPE_PAIR_B_MASK GENMASK(11, 8)
515#define BCM54XX_ECD_FAULT_TYPE_PAIR_A_MASK GENMASK(15, 12)
516#define BCM54XX_ECD_PAIR_A_LENGTH_RESULTS 0x2a2
517#define BCM54XX_ECD_PAIR_B_LENGTH_RESULTS 0x2a3
518#define BCM54XX_ECD_PAIR_C_LENGTH_RESULTS 0x2a4
519#define BCM54XX_ECD_PAIR_D_LENGTH_RESULTS 0x2a5
520
521#define BCM54XX_RDB_ECD_PAIR_A_LENGTH_RESULTS 0x2a2
522#define BCM54XX_EXP_ECD_PAIR_A_LENGTH_RESULTS (MII_BCM54XX_EXP_SEL_ER + 0xc2)
523#define BCM54XX_RDB_ECD_PAIR_B_LENGTH_RESULTS 0x2a3
524#define BCM54XX_EXP_ECD_PAIR_B_LENGTH_RESULTS (MII_BCM54XX_EXP_SEL_ER + 0xc3)
525#define BCM54XX_RDB_ECD_PAIR_C_LENGTH_RESULTS 0x2a4
526#define BCM54XX_EXP_ECD_PAIR_C_LENGTH_RESULTS (MII_BCM54XX_EXP_SEL_ER + 0xc4)
527#define BCM54XX_RDB_ECD_PAIR_D_LENGTH_RESULTS 0x2a5
528#define BCM54XX_EXP_ECD_PAIR_D_LENGTH_RESULTS (MII_BCM54XX_EXP_SEL_ER + 0xc5)
529#define BCM54XX_ECD_LENGTH_RESULTS_INVALID 0xffff
530
531#endif /* _LINUX_BRCMPHY_H */