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1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * CPPI5 descriptors interface
4 *
5 * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com
6 */
7
8#ifndef __TI_CPPI5_H__
9#define __TI_CPPI5_H__
10
11#include <linux/bitops.h>
12#include <linux/printk.h>
13#include <linux/bug.h>
14
15/**
16 * struct cppi5_desc_hdr_t - Descriptor header, present in all types of
17 * descriptors
18 * @pkt_info0: Packet info word 0 (n/a in Buffer desc)
19 * @pkt_info1: Packet info word 1 (n/a in Buffer desc)
20 * @pkt_info2: Packet info word 2 (n/a in Buffer desc)
21 * @src_dst_tag: Packet info word 3 (n/a in Buffer desc)
22 */
23struct cppi5_desc_hdr_t {
24 u32 pkt_info0;
25 u32 pkt_info1;
26 u32 pkt_info2;
27 u32 src_dst_tag;
28} __packed;
29
30/**
31 * struct cppi5_host_desc_t - Host-mode packet and buffer descriptor definition
32 * @hdr: Descriptor header
33 * @next_desc: word 4/5: Linking word
34 * @buf_ptr: word 6/7: Buffer pointer
35 * @buf_info1: word 8: Buffer valid data length
36 * @org_buf_len: word 9: Original buffer length
37 * @org_buf_ptr: word 10/11: Original buffer pointer
38 * @epib: Extended Packet Info Data (optional, 4 words), and/or
39 * Protocol Specific Data (optional, 0-128 bytes in
40 * multiples of 4), and/or
41 * Other Software Data (0-N bytes, optional)
42 */
43struct cppi5_host_desc_t {
44 struct cppi5_desc_hdr_t hdr;
45 u64 next_desc;
46 u64 buf_ptr;
47 u32 buf_info1;
48 u32 org_buf_len;
49 u64 org_buf_ptr;
50 u32 epib[];
51} __packed;
52
53#define CPPI5_DESC_MIN_ALIGN (16U)
54
55#define CPPI5_INFO0_HDESC_EPIB_SIZE (16U)
56#define CPPI5_INFO0_HDESC_PSDATA_MAX_SIZE (128U)
57
58#define CPPI5_INFO0_HDESC_TYPE_SHIFT (30U)
59#define CPPI5_INFO0_HDESC_TYPE_MASK GENMASK(31, 30)
60#define CPPI5_INFO0_DESC_TYPE_VAL_HOST (1U)
61#define CPPI5_INFO0_DESC_TYPE_VAL_MONO (2U)
62#define CPPI5_INFO0_DESC_TYPE_VAL_TR (3U)
63#define CPPI5_INFO0_HDESC_EPIB_PRESENT BIT(29)
64/*
65 * Protocol Specific Words location:
66 * 0 - located in the descriptor,
67 * 1 = located in the SOP Buffer immediately prior to the data.
68 */
69#define CPPI5_INFO0_HDESC_PSINFO_LOCATION BIT(28)
70#define CPPI5_INFO0_HDESC_PSINFO_SIZE_SHIFT (22U)
71#define CPPI5_INFO0_HDESC_PSINFO_SIZE_MASK GENMASK(27, 22)
72#define CPPI5_INFO0_HDESC_PKTLEN_SHIFT (0)
73#define CPPI5_INFO0_HDESC_PKTLEN_MASK GENMASK(21, 0)
74
75#define CPPI5_INFO1_DESC_PKTERROR_SHIFT (28U)
76#define CPPI5_INFO1_DESC_PKTERROR_MASK GENMASK(31, 28)
77#define CPPI5_INFO1_HDESC_PSFLGS_SHIFT (24U)
78#define CPPI5_INFO1_HDESC_PSFLGS_MASK GENMASK(27, 24)
79#define CPPI5_INFO1_DESC_PKTID_SHIFT (14U)
80#define CPPI5_INFO1_DESC_PKTID_MASK GENMASK(23, 14)
81#define CPPI5_INFO1_DESC_FLOWID_SHIFT (0)
82#define CPPI5_INFO1_DESC_FLOWID_MASK GENMASK(13, 0)
83#define CPPI5_INFO1_DESC_FLOWID_DEFAULT CPPI5_INFO1_DESC_FLOWID_MASK
84
85#define CPPI5_INFO2_HDESC_PKTTYPE_SHIFT (27U)
86#define CPPI5_INFO2_HDESC_PKTTYPE_MASK GENMASK(31, 27)
87/* Return Policy: 0 - Entire packet 1 - Each buffer */
88#define CPPI5_INFO2_HDESC_RETPOLICY BIT(18)
89/*
90 * Early Return:
91 * 0 = desc pointers should be returned after all reads have been completed
92 * 1 = desc pointers should be returned immediately upon fetching
93 * the descriptor and beginning to transfer data.
94 */
95#define CPPI5_INFO2_HDESC_EARLYRET BIT(17)
96/*
97 * Return Push Policy:
98 * 0 = Descriptor must be returned to tail of queue
99 * 1 = Descriptor must be returned to head of queue
100 */
101#define CPPI5_INFO2_DESC_RETPUSHPOLICY BIT(16)
102#define CPPI5_INFO2_DESC_RETP_MASK GENMASK(18, 16)
103
104#define CPPI5_INFO2_DESC_RETQ_SHIFT (0)
105#define CPPI5_INFO2_DESC_RETQ_MASK GENMASK(15, 0)
106
107#define CPPI5_INFO3_DESC_SRCTAG_SHIFT (16U)
108#define CPPI5_INFO3_DESC_SRCTAG_MASK GENMASK(31, 16)
109#define CPPI5_INFO3_DESC_DSTTAG_SHIFT (0)
110#define CPPI5_INFO3_DESC_DSTTAG_MASK GENMASK(15, 0)
111
112#define CPPI5_BUFINFO1_HDESC_DATA_LEN_SHIFT (0)
113#define CPPI5_BUFINFO1_HDESC_DATA_LEN_MASK GENMASK(27, 0)
114
115#define CPPI5_OBUFINFO0_HDESC_BUF_LEN_SHIFT (0)
116#define CPPI5_OBUFINFO0_HDESC_BUF_LEN_MASK GENMASK(27, 0)
117
118/**
119 * struct cppi5_desc_epib_t - Host Packet Descriptor Extended Packet Info Block
120 * @timestamp: word 0: application specific timestamp
121 * @sw_info0: word 1: Software Info 0
122 * @sw_info1: word 1: Software Info 1
123 * @sw_info2: word 1: Software Info 2
124 */
125struct cppi5_desc_epib_t {
126 u32 timestamp; /* w0: application specific timestamp */
127 u32 sw_info0; /* w1: Software Info 0 */
128 u32 sw_info1; /* w2: Software Info 1 */
129 u32 sw_info2; /* w3: Software Info 2 */
130};
131
132/**
133 * struct cppi5_monolithic_desc_t - Monolithic-mode packet descriptor
134 * @hdr: Descriptor header
135 * @epib: Extended Packet Info Data (optional, 4 words), and/or
136 * Protocol Specific Data (optional, 0-128 bytes in
137 * multiples of 4), and/or
138 * Other Software Data (0-N bytes, optional)
139 */
140struct cppi5_monolithic_desc_t {
141 struct cppi5_desc_hdr_t hdr;
142 u32 epib[];
143};
144
145#define CPPI5_INFO2_MDESC_DATA_OFFSET_SHIFT (18U)
146#define CPPI5_INFO2_MDESC_DATA_OFFSET_MASK GENMASK(26, 18)
147
148/*
149 * Reload Count:
150 * 0 = Finish the packet and place the descriptor back on the return queue
151 * 1-0x1ff = Vector to the Reload Index and resume processing
152 * 0x1ff indicates perpetual loop, infinite reload until the channel is stopped
153 */
154#define CPPI5_INFO0_TRDESC_RLDCNT_SHIFT (20U)
155#define CPPI5_INFO0_TRDESC_RLDCNT_MASK GENMASK(28, 20)
156#define CPPI5_INFO0_TRDESC_RLDCNT_MAX (0x1ff)
157#define CPPI5_INFO0_TRDESC_RLDCNT_INFINITE CPPI5_INFO0_TRDESC_RLDCNT_MAX
158#define CPPI5_INFO0_TRDESC_RLDIDX_SHIFT (14U)
159#define CPPI5_INFO0_TRDESC_RLDIDX_MASK GENMASK(19, 14)
160#define CPPI5_INFO0_TRDESC_RLDIDX_MAX (0x3f)
161#define CPPI5_INFO0_TRDESC_LASTIDX_SHIFT (0)
162#define CPPI5_INFO0_TRDESC_LASTIDX_MASK GENMASK(13, 0)
163
164#define CPPI5_INFO1_TRDESC_RECSIZE_SHIFT (24U)
165#define CPPI5_INFO1_TRDESC_RECSIZE_MASK GENMASK(26, 24)
166#define CPPI5_INFO1_TRDESC_RECSIZE_VAL_16B (0)
167#define CPPI5_INFO1_TRDESC_RECSIZE_VAL_32B (1U)
168#define CPPI5_INFO1_TRDESC_RECSIZE_VAL_64B (2U)
169#define CPPI5_INFO1_TRDESC_RECSIZE_VAL_128B (3U)
170
171static inline void cppi5_desc_dump(void *desc, u32 size)
172{
173 print_hex_dump(KERN_ERR, "dump udmap_desc: ", DUMP_PREFIX_NONE,
174 32, 4, desc, size, false);
175}
176
177#define CPPI5_TDCM_MARKER (0x1)
178/**
179 * cppi5_desc_is_tdcm - check if the paddr indicates Teardown Complete Message
180 * @paddr: Physical address of the packet popped from the ring
181 *
182 * Returns: true if the address indicates TDCM
183 */
184static inline bool cppi5_desc_is_tdcm(dma_addr_t paddr)
185{
186 return (paddr & CPPI5_TDCM_MARKER) ? true : false;
187}
188
189/**
190 * cppi5_desc_get_type - get descriptor type
191 * @desc_hdr: packet descriptor/TR header
192 *
193 * Returns: descriptor type:
194 * CPPI5_INFO0_DESC_TYPE_VAL_HOST
195 * CPPI5_INFO0_DESC_TYPE_VAL_MONO
196 * CPPI5_INFO0_DESC_TYPE_VAL_TR
197 */
198static inline u32 cppi5_desc_get_type(struct cppi5_desc_hdr_t *desc_hdr)
199{
200 return (desc_hdr->pkt_info0 & CPPI5_INFO0_HDESC_TYPE_MASK) >>
201 CPPI5_INFO0_HDESC_TYPE_SHIFT;
202}
203
204/**
205 * cppi5_desc_get_errflags - get Error Flags from Desc
206 * @desc_hdr: packet/TR descriptor header
207 *
208 * Returns: Error Flags from Packet/TR Descriptor
209 */
210static inline u32 cppi5_desc_get_errflags(struct cppi5_desc_hdr_t *desc_hdr)
211{
212 return (desc_hdr->pkt_info1 & CPPI5_INFO1_DESC_PKTERROR_MASK) >>
213 CPPI5_INFO1_DESC_PKTERROR_SHIFT;
214}
215
216/**
217 * cppi5_desc_get_pktids - get Packet and Flow ids from Desc
218 * @desc_hdr: packet/TR descriptor header
219 * @pkt_id: Packet ID
220 * @flow_id: Flow ID
221 *
222 * Returns Packet and Flow ids from packet/TR descriptor
223 */
224static inline void cppi5_desc_get_pktids(struct cppi5_desc_hdr_t *desc_hdr,
225 u32 *pkt_id, u32 *flow_id)
226{
227 *pkt_id = (desc_hdr->pkt_info1 & CPPI5_INFO1_DESC_PKTID_MASK) >>
228 CPPI5_INFO1_DESC_PKTID_SHIFT;
229 *flow_id = (desc_hdr->pkt_info1 & CPPI5_INFO1_DESC_FLOWID_MASK) >>
230 CPPI5_INFO1_DESC_FLOWID_SHIFT;
231}
232
233/**
234 * cppi5_desc_set_pktids - set Packet and Flow ids in Desc
235 * @desc_hdr: packet/TR descriptor header
236 * @pkt_id: Packet ID
237 * @flow_id: Flow ID
238 */
239static inline void cppi5_desc_set_pktids(struct cppi5_desc_hdr_t *desc_hdr,
240 u32 pkt_id, u32 flow_id)
241{
242 desc_hdr->pkt_info1 &= ~(CPPI5_INFO1_DESC_PKTID_MASK |
243 CPPI5_INFO1_DESC_FLOWID_MASK);
244 desc_hdr->pkt_info1 |= (pkt_id << CPPI5_INFO1_DESC_PKTID_SHIFT) &
245 CPPI5_INFO1_DESC_PKTID_MASK;
246 desc_hdr->pkt_info1 |= (flow_id << CPPI5_INFO1_DESC_FLOWID_SHIFT) &
247 CPPI5_INFO1_DESC_FLOWID_MASK;
248}
249
250/**
251 * cppi5_desc_set_retpolicy - set Packet Return Policy in Desc
252 * @desc_hdr: packet/TR descriptor header
253 * @flags: fags, supported values
254 * CPPI5_INFO2_HDESC_RETPOLICY
255 * CPPI5_INFO2_HDESC_EARLYRET
256 * CPPI5_INFO2_DESC_RETPUSHPOLICY
257 * @return_ring_id: Packet Return Queue/Ring id, value 0xFFFF reserved
258 */
259static inline void cppi5_desc_set_retpolicy(struct cppi5_desc_hdr_t *desc_hdr,
260 u32 flags, u32 return_ring_id)
261{
262 desc_hdr->pkt_info2 &= ~(CPPI5_INFO2_DESC_RETP_MASK |
263 CPPI5_INFO2_DESC_RETQ_MASK);
264 desc_hdr->pkt_info2 |= flags & CPPI5_INFO2_DESC_RETP_MASK;
265 desc_hdr->pkt_info2 |= return_ring_id & CPPI5_INFO2_DESC_RETQ_MASK;
266}
267
268/**
269 * cppi5_desc_get_tags_ids - get Packet Src/Dst Tags from Desc
270 * @desc_hdr: packet/TR descriptor header
271 * @src_tag_id: Source Tag
272 * @dst_tag_id: Dest Tag
273 *
274 * Returns Packet Src/Dst Tags from packet/TR descriptor
275 */
276static inline void cppi5_desc_get_tags_ids(struct cppi5_desc_hdr_t *desc_hdr,
277 u32 *src_tag_id, u32 *dst_tag_id)
278{
279 if (src_tag_id)
280 *src_tag_id = (desc_hdr->src_dst_tag &
281 CPPI5_INFO3_DESC_SRCTAG_MASK) >>
282 CPPI5_INFO3_DESC_SRCTAG_SHIFT;
283 if (dst_tag_id)
284 *dst_tag_id = desc_hdr->src_dst_tag &
285 CPPI5_INFO3_DESC_DSTTAG_MASK;
286}
287
288/**
289 * cppi5_desc_set_tags_ids - set Packet Src/Dst Tags in HDesc
290 * @desc_hdr: packet/TR descriptor header
291 * @src_tag_id: Source Tag
292 * @dst_tag_id: Dest Tag
293 *
294 * Returns Packet Src/Dst Tags from packet/TR descriptor
295 */
296static inline void cppi5_desc_set_tags_ids(struct cppi5_desc_hdr_t *desc_hdr,
297 u32 src_tag_id, u32 dst_tag_id)
298{
299 desc_hdr->src_dst_tag = (src_tag_id << CPPI5_INFO3_DESC_SRCTAG_SHIFT) &
300 CPPI5_INFO3_DESC_SRCTAG_MASK;
301 desc_hdr->src_dst_tag |= dst_tag_id & CPPI5_INFO3_DESC_DSTTAG_MASK;
302}
303
304/**
305 * cppi5_hdesc_calc_size - Calculate Host Packet Descriptor size
306 * @epib: is EPIB present
307 * @psdata_size: PSDATA size
308 * @sw_data_size: SWDATA size
309 *
310 * Returns: required Host Packet Descriptor size
311 * 0 - if PSDATA > CPPI5_INFO0_HDESC_PSDATA_MAX_SIZE
312 */
313static inline u32 cppi5_hdesc_calc_size(bool epib, u32 psdata_size,
314 u32 sw_data_size)
315{
316 u32 desc_size;
317
318 if (psdata_size > CPPI5_INFO0_HDESC_PSDATA_MAX_SIZE)
319 return 0;
320
321 desc_size = sizeof(struct cppi5_host_desc_t) + psdata_size +
322 sw_data_size;
323
324 if (epib)
325 desc_size += CPPI5_INFO0_HDESC_EPIB_SIZE;
326
327 return ALIGN(desc_size, CPPI5_DESC_MIN_ALIGN);
328}
329
330/**
331 * cppi5_hdesc_init - Init Host Packet Descriptor size
332 * @desc: Host packet descriptor
333 * @flags: supported values
334 * CPPI5_INFO0_HDESC_EPIB_PRESENT
335 * CPPI5_INFO0_HDESC_PSINFO_LOCATION
336 * @psdata_size: PSDATA size
337 *
338 * Returns required Host Packet Descriptor size
339 * 0 - if PSDATA > CPPI5_INFO0_HDESC_PSDATA_MAX_SIZE
340 */
341static inline void cppi5_hdesc_init(struct cppi5_host_desc_t *desc, u32 flags,
342 u32 psdata_size)
343{
344 desc->hdr.pkt_info0 = (CPPI5_INFO0_DESC_TYPE_VAL_HOST <<
345 CPPI5_INFO0_HDESC_TYPE_SHIFT) | (flags);
346 desc->hdr.pkt_info0 |= ((psdata_size >> 2) <<
347 CPPI5_INFO0_HDESC_PSINFO_SIZE_SHIFT) &
348 CPPI5_INFO0_HDESC_PSINFO_SIZE_MASK;
349 desc->next_desc = 0;
350}
351
352/**
353 * cppi5_hdesc_update_flags - Replace descriptor flags
354 * @desc: Host packet descriptor
355 * @flags: supported values
356 * CPPI5_INFO0_HDESC_EPIB_PRESENT
357 * CPPI5_INFO0_HDESC_PSINFO_LOCATION
358 */
359static inline void cppi5_hdesc_update_flags(struct cppi5_host_desc_t *desc,
360 u32 flags)
361{
362 desc->hdr.pkt_info0 &= ~(CPPI5_INFO0_HDESC_EPIB_PRESENT |
363 CPPI5_INFO0_HDESC_PSINFO_LOCATION);
364 desc->hdr.pkt_info0 |= flags;
365}
366
367/**
368 * cppi5_hdesc_update_psdata_size - Replace PSdata size
369 * @desc: Host packet descriptor
370 * @psdata_size: PSDATA size
371 */
372static inline void
373cppi5_hdesc_update_psdata_size(struct cppi5_host_desc_t *desc, u32 psdata_size)
374{
375 desc->hdr.pkt_info0 &= ~CPPI5_INFO0_HDESC_PSINFO_SIZE_MASK;
376 desc->hdr.pkt_info0 |= ((psdata_size >> 2) <<
377 CPPI5_INFO0_HDESC_PSINFO_SIZE_SHIFT) &
378 CPPI5_INFO0_HDESC_PSINFO_SIZE_MASK;
379}
380
381/**
382 * cppi5_hdesc_get_psdata_size - get PSdata size in bytes
383 * @desc: Host packet descriptor
384 *
385 * Returns: PSdata size in bytes
386 */
387static inline u32 cppi5_hdesc_get_psdata_size(struct cppi5_host_desc_t *desc)
388{
389 u32 psdata_size = 0;
390
391 if (!(desc->hdr.pkt_info0 & CPPI5_INFO0_HDESC_PSINFO_LOCATION))
392 psdata_size = (desc->hdr.pkt_info0 &
393 CPPI5_INFO0_HDESC_PSINFO_SIZE_MASK) >>
394 CPPI5_INFO0_HDESC_PSINFO_SIZE_SHIFT;
395
396 return (psdata_size << 2);
397}
398
399/**
400 * cppi5_hdesc_get_pktlen - get Packet Length from HDesc
401 * @desc: Host packet descriptor
402 *
403 * Returns: Packet Length from Host Packet Descriptor
404 */
405static inline u32 cppi5_hdesc_get_pktlen(struct cppi5_host_desc_t *desc)
406{
407 return (desc->hdr.pkt_info0 & CPPI5_INFO0_HDESC_PKTLEN_MASK);
408}
409
410/**
411 * cppi5_hdesc_set_pktlen - set Packet Length in HDesc
412 * @desc: Host packet descriptor
413 * @pkt_len: Packet length to set
414 */
415static inline void cppi5_hdesc_set_pktlen(struct cppi5_host_desc_t *desc,
416 u32 pkt_len)
417{
418 desc->hdr.pkt_info0 &= ~CPPI5_INFO0_HDESC_PKTLEN_MASK;
419 desc->hdr.pkt_info0 |= (pkt_len & CPPI5_INFO0_HDESC_PKTLEN_MASK);
420}
421
422/**
423 * cppi5_hdesc_get_psflags - get Protocol Specific Flags from HDesc
424 * @desc: Host packet descriptor
425 *
426 * Returns: Protocol Specific Flags from Host Packet Descriptor
427 */
428static inline u32 cppi5_hdesc_get_psflags(struct cppi5_host_desc_t *desc)
429{
430 return (desc->hdr.pkt_info1 & CPPI5_INFO1_HDESC_PSFLGS_MASK) >>
431 CPPI5_INFO1_HDESC_PSFLGS_SHIFT;
432}
433
434/**
435 * cppi5_hdesc_set_psflags - set Protocol Specific Flags in HDesc
436 * @desc: Host packet descriptor
437 * @ps_flags: Protocol Specific flags to set
438 */
439static inline void cppi5_hdesc_set_psflags(struct cppi5_host_desc_t *desc,
440 u32 ps_flags)
441{
442 desc->hdr.pkt_info1 &= ~CPPI5_INFO1_HDESC_PSFLGS_MASK;
443 desc->hdr.pkt_info1 |= (ps_flags <<
444 CPPI5_INFO1_HDESC_PSFLGS_SHIFT) &
445 CPPI5_INFO1_HDESC_PSFLGS_MASK;
446}
447
448/**
449 * cppi5_hdesc_get_pkttype - get Packet Type from HDesc
450 * @desc: Host packet descriptor
451 *
452 * Returns: Packet type
453 */
454static inline u32 cppi5_hdesc_get_pkttype(struct cppi5_host_desc_t *desc)
455{
456 return (desc->hdr.pkt_info2 & CPPI5_INFO2_HDESC_PKTTYPE_MASK) >>
457 CPPI5_INFO2_HDESC_PKTTYPE_SHIFT;
458}
459
460/**
461 * cppi5_hdesc_set_pkttype - set Packet Type in HDesc
462 * @desc: Host packet descriptor
463 * @pkt_type: Packet Type
464 */
465static inline void cppi5_hdesc_set_pkttype(struct cppi5_host_desc_t *desc,
466 u32 pkt_type)
467{
468 desc->hdr.pkt_info2 &= ~CPPI5_INFO2_HDESC_PKTTYPE_MASK;
469 desc->hdr.pkt_info2 |=
470 (pkt_type << CPPI5_INFO2_HDESC_PKTTYPE_SHIFT) &
471 CPPI5_INFO2_HDESC_PKTTYPE_MASK;
472}
473
474/**
475 * cppi5_hdesc_attach_buf - attach buffer to HDesc
476 * @desc: Host packet descriptor
477 * @buf: Buffer physical address
478 * @buf_data_len: Buffer length
479 * @obuf: Original Buffer physical address
480 * @obuf_len: Original Buffer length
481 *
482 * Attaches buffer to Host Packet Descriptor
483 */
484static inline void cppi5_hdesc_attach_buf(struct cppi5_host_desc_t *desc,
485 dma_addr_t buf, u32 buf_data_len,
486 dma_addr_t obuf, u32 obuf_len)
487{
488 desc->buf_ptr = buf;
489 desc->buf_info1 = buf_data_len & CPPI5_BUFINFO1_HDESC_DATA_LEN_MASK;
490 desc->org_buf_ptr = obuf;
491 desc->org_buf_len = obuf_len & CPPI5_OBUFINFO0_HDESC_BUF_LEN_MASK;
492}
493
494static inline void cppi5_hdesc_get_obuf(struct cppi5_host_desc_t *desc,
495 dma_addr_t *obuf, u32 *obuf_len)
496{
497 *obuf = desc->org_buf_ptr;
498 *obuf_len = desc->org_buf_len & CPPI5_OBUFINFO0_HDESC_BUF_LEN_MASK;
499}
500
501static inline void cppi5_hdesc_reset_to_original(struct cppi5_host_desc_t *desc)
502{
503 desc->buf_ptr = desc->org_buf_ptr;
504 desc->buf_info1 = desc->org_buf_len;
505}
506
507/**
508 * cppi5_hdesc_link_hbdesc - link Host Buffer Descriptor to HDesc
509 * @desc: Host Packet Descriptor
510 * @hbuf_desc: Host Buffer Descriptor physical address
511 *
512 * add and link Host Buffer Descriptor to HDesc
513 */
514static inline void cppi5_hdesc_link_hbdesc(struct cppi5_host_desc_t *desc,
515 dma_addr_t hbuf_desc)
516{
517 desc->next_desc = hbuf_desc;
518}
519
520static inline dma_addr_t
521cppi5_hdesc_get_next_hbdesc(struct cppi5_host_desc_t *desc)
522{
523 return (dma_addr_t)desc->next_desc;
524}
525
526static inline void cppi5_hdesc_reset_hbdesc(struct cppi5_host_desc_t *desc)
527{
528 desc->hdr = (struct cppi5_desc_hdr_t) { 0 };
529 desc->next_desc = 0;
530}
531
532/**
533 * cppi5_hdesc_epib_present - check if EPIB present
534 * @desc_hdr: packet descriptor/TR header
535 *
536 * Returns: true if EPIB present in the packet
537 */
538static inline bool cppi5_hdesc_epib_present(struct cppi5_desc_hdr_t *desc_hdr)
539{
540 return !!(desc_hdr->pkt_info0 & CPPI5_INFO0_HDESC_EPIB_PRESENT);
541}
542
543/**
544 * cppi5_hdesc_get_psdata - Get pointer on PSDATA
545 * @desc: Host packet descriptor
546 *
547 * Returns: pointer on PSDATA in HDesc.
548 * NULL - if ps_data placed at the start of data buffer.
549 */
550static inline void *cppi5_hdesc_get_psdata(struct cppi5_host_desc_t *desc)
551{
552 u32 psdata_size;
553 void *psdata;
554
555 if (desc->hdr.pkt_info0 & CPPI5_INFO0_HDESC_PSINFO_LOCATION)
556 return NULL;
557
558 psdata_size = (desc->hdr.pkt_info0 &
559 CPPI5_INFO0_HDESC_PSINFO_SIZE_MASK) >>
560 CPPI5_INFO0_HDESC_PSINFO_SIZE_SHIFT;
561
562 if (!psdata_size)
563 return NULL;
564
565 psdata = &desc->epib;
566
567 if (cppi5_hdesc_epib_present(&desc->hdr))
568 psdata += CPPI5_INFO0_HDESC_EPIB_SIZE;
569
570 return psdata;
571}
572
573/**
574 * cppi5_hdesc_get_swdata - Get pointer on swdata
575 * @desc: Host packet descriptor
576 *
577 * Returns: pointer on SWDATA in HDesc.
578 * NOTE. It's caller responsibility to be sure hdesc actually has swdata.
579 */
580static inline void *cppi5_hdesc_get_swdata(struct cppi5_host_desc_t *desc)
581{
582 u32 psdata_size = 0;
583 void *swdata;
584
585 if (!(desc->hdr.pkt_info0 & CPPI5_INFO0_HDESC_PSINFO_LOCATION))
586 psdata_size = (desc->hdr.pkt_info0 &
587 CPPI5_INFO0_HDESC_PSINFO_SIZE_MASK) >>
588 CPPI5_INFO0_HDESC_PSINFO_SIZE_SHIFT;
589
590 swdata = &desc->epib;
591
592 if (cppi5_hdesc_epib_present(&desc->hdr))
593 swdata += CPPI5_INFO0_HDESC_EPIB_SIZE;
594
595 swdata += (psdata_size << 2);
596
597 return swdata;
598}
599
600/* ================================== TR ================================== */
601
602#define CPPI5_TR_TYPE_SHIFT (0U)
603#define CPPI5_TR_TYPE_MASK GENMASK(3, 0)
604#define CPPI5_TR_STATIC BIT(4)
605#define CPPI5_TR_WAIT BIT(5)
606#define CPPI5_TR_EVENT_SIZE_SHIFT (6U)
607#define CPPI5_TR_EVENT_SIZE_MASK GENMASK(7, 6)
608#define CPPI5_TR_TRIGGER0_SHIFT (8U)
609#define CPPI5_TR_TRIGGER0_MASK GENMASK(9, 8)
610#define CPPI5_TR_TRIGGER0_TYPE_SHIFT (10U)
611#define CPPI5_TR_TRIGGER0_TYPE_MASK GENMASK(11, 10)
612#define CPPI5_TR_TRIGGER1_SHIFT (12U)
613#define CPPI5_TR_TRIGGER1_MASK GENMASK(13, 12)
614#define CPPI5_TR_TRIGGER1_TYPE_SHIFT (14U)
615#define CPPI5_TR_TRIGGER1_TYPE_MASK GENMASK(15, 14)
616#define CPPI5_TR_CMD_ID_SHIFT (16U)
617#define CPPI5_TR_CMD_ID_MASK GENMASK(23, 16)
618#define CPPI5_TR_CSF_FLAGS_SHIFT (24U)
619#define CPPI5_TR_CSF_FLAGS_MASK GENMASK(31, 24)
620#define CPPI5_TR_CSF_SA_INDIRECT BIT(0)
621#define CPPI5_TR_CSF_DA_INDIRECT BIT(1)
622#define CPPI5_TR_CSF_SUPR_EVT BIT(2)
623#define CPPI5_TR_CSF_EOL_ADV_SHIFT (4U)
624#define CPPI5_TR_CSF_EOL_ADV_MASK GENMASK(6, 4)
625#define CPPI5_TR_CSF_EOL_ICNT0 BIT(4)
626#define CPPI5_TR_CSF_EOP BIT(7)
627
628/**
629 * enum cppi5_tr_types - TR types
630 * @CPPI5_TR_TYPE0: One dimensional data move
631 * @CPPI5_TR_TYPE1: Two dimensional data move
632 * @CPPI5_TR_TYPE2: Three dimensional data move
633 * @CPPI5_TR_TYPE3: Four dimensional data move
634 * @CPPI5_TR_TYPE4: Four dimensional data move with data formatting
635 * @CPPI5_TR_TYPE5: Four dimensional Cache Warm
636 * @CPPI5_TR_TYPE8: Four Dimensional Block Move
637 * @CPPI5_TR_TYPE9: Four Dimensional Block Move with Repacking
638 * @CPPI5_TR_TYPE10: Two Dimensional Block Move
639 * @CPPI5_TR_TYPE11: Two Dimensional Block Move with Repacking
640 * @CPPI5_TR_TYPE15: Four Dimensional Block Move with Repacking and
641 * Indirection
642 */
643enum cppi5_tr_types {
644 CPPI5_TR_TYPE0 = 0,
645 CPPI5_TR_TYPE1,
646 CPPI5_TR_TYPE2,
647 CPPI5_TR_TYPE3,
648 CPPI5_TR_TYPE4,
649 CPPI5_TR_TYPE5,
650 /* type6-7: Reserved */
651 CPPI5_TR_TYPE8 = 8,
652 CPPI5_TR_TYPE9,
653 CPPI5_TR_TYPE10,
654 CPPI5_TR_TYPE11,
655 /* type12-14: Reserved */
656 CPPI5_TR_TYPE15 = 15,
657 /* private: */
658 CPPI5_TR_TYPE_MAX
659};
660
661/**
662 * enum cppi5_tr_event_size - TR Flags EVENT_SIZE field specifies when an event
663 * is generated for each TR.
664 * @CPPI5_TR_EVENT_SIZE_COMPLETION: When TR is complete and all status for
665 * the TR has been received
666 * @CPPI5_TR_EVENT_SIZE_ICNT1_DEC: Type 0: when the last data transaction
667 * is sent for the TR
668 * Type 1-11: when ICNT1 is decremented
669 * @CPPI5_TR_EVENT_SIZE_ICNT2_DEC: Type 0-1,10-11: when the last data
670 * transaction is sent for the TR
671 * All other types: when ICNT2 is
672 * decremented
673 * @CPPI5_TR_EVENT_SIZE_ICNT3_DEC: Type 0-2,10-11: when the last data
674 * transaction is sent for the TR
675 * All other types: when ICNT3 is
676 * decremented
677 */
678enum cppi5_tr_event_size {
679 CPPI5_TR_EVENT_SIZE_COMPLETION,
680 CPPI5_TR_EVENT_SIZE_ICNT1_DEC,
681 CPPI5_TR_EVENT_SIZE_ICNT2_DEC,
682 CPPI5_TR_EVENT_SIZE_ICNT3_DEC,
683 /* private: */
684 CPPI5_TR_EVENT_SIZE_MAX
685};
686
687/**
688 * enum cppi5_tr_trigger - TR Flags TRIGGERx field specifies the type of trigger
689 * used to enable the TR to transfer data as specified
690 * by TRIGGERx_TYPE field.
691 * @CPPI5_TR_TRIGGER_NONE: No trigger
692 * @CPPI5_TR_TRIGGER_GLOBAL0: Global trigger 0
693 * @CPPI5_TR_TRIGGER_GLOBAL1: Global trigger 1
694 * @CPPI5_TR_TRIGGER_LOCAL_EVENT: Local Event
695 */
696enum cppi5_tr_trigger {
697 CPPI5_TR_TRIGGER_NONE,
698 CPPI5_TR_TRIGGER_GLOBAL0,
699 CPPI5_TR_TRIGGER_GLOBAL1,
700 CPPI5_TR_TRIGGER_LOCAL_EVENT,
701 /* private: */
702 CPPI5_TR_TRIGGER_MAX
703};
704
705/**
706 * enum cppi5_tr_trigger_type - TR Flags TRIGGERx_TYPE field specifies the type
707 * of data transfer that will be enabled by
708 * receiving a trigger as specified by TRIGGERx.
709 * @CPPI5_TR_TRIGGER_TYPE_ICNT1_DEC: The second inner most loop (ICNT1) will
710 * be decremented by 1
711 * @CPPI5_TR_TRIGGER_TYPE_ICNT2_DEC: The third inner most loop (ICNT2) will
712 * be decremented by 1
713 * @CPPI5_TR_TRIGGER_TYPE_ICNT3_DEC: The outer most loop (ICNT3) will be
714 * decremented by 1
715 * @CPPI5_TR_TRIGGER_TYPE_ALL: The entire TR will be allowed to
716 * complete
717 */
718enum cppi5_tr_trigger_type {
719 CPPI5_TR_TRIGGER_TYPE_ICNT1_DEC,
720 CPPI5_TR_TRIGGER_TYPE_ICNT2_DEC,
721 CPPI5_TR_TRIGGER_TYPE_ICNT3_DEC,
722 CPPI5_TR_TRIGGER_TYPE_ALL,
723 /* private: */
724 CPPI5_TR_TRIGGER_TYPE_MAX
725};
726
727typedef u32 cppi5_tr_flags_t;
728
729/**
730 * struct cppi5_tr_type0_t - Type 0 (One dimensional data move) TR (16 byte)
731 * @flags: TR flags (type, triggers, event, configuration)
732 * @icnt0: Total loop iteration count for level 0 (innermost)
733 * @_reserved: Not used
734 * @addr: Starting address for the source data or destination data
735 */
736struct cppi5_tr_type0_t {
737 cppi5_tr_flags_t flags;
738 u16 icnt0;
739 u16 _reserved;
740 u64 addr;
741} __aligned(16) __packed;
742
743/**
744 * struct cppi5_tr_type1_t - Type 1 (Two dimensional data move) TR (32 byte)
745 * @flags: TR flags (type, triggers, event, configuration)
746 * @icnt0: Total loop iteration count for level 0 (innermost)
747 * @icnt1: Total loop iteration count for level 1
748 * @addr: Starting address for the source data or destination data
749 * @dim1: Signed dimension for loop level 1
750 */
751struct cppi5_tr_type1_t {
752 cppi5_tr_flags_t flags;
753 u16 icnt0;
754 u16 icnt1;
755 u64 addr;
756 s32 dim1;
757} __aligned(32) __packed;
758
759/**
760 * struct cppi5_tr_type2_t - Type 2 (Three dimensional data move) TR (32 byte)
761 * @flags: TR flags (type, triggers, event, configuration)
762 * @icnt0: Total loop iteration count for level 0 (innermost)
763 * @icnt1: Total loop iteration count for level 1
764 * @addr: Starting address for the source data or destination data
765 * @dim1: Signed dimension for loop level 1
766 * @icnt2: Total loop iteration count for level 2
767 * @_reserved: Not used
768 * @dim2: Signed dimension for loop level 2
769 */
770struct cppi5_tr_type2_t {
771 cppi5_tr_flags_t flags;
772 u16 icnt0;
773 u16 icnt1;
774 u64 addr;
775 s32 dim1;
776 u16 icnt2;
777 u16 _reserved;
778 s32 dim2;
779} __aligned(32) __packed;
780
781/**
782 * struct cppi5_tr_type3_t - Type 3 (Four dimensional data move) TR (32 byte)
783 * @flags: TR flags (type, triggers, event, configuration)
784 * @icnt0: Total loop iteration count for level 0 (innermost)
785 * @icnt1: Total loop iteration count for level 1
786 * @addr: Starting address for the source data or destination data
787 * @dim1: Signed dimension for loop level 1
788 * @icnt2: Total loop iteration count for level 2
789 * @icnt3: Total loop iteration count for level 3 (outermost)
790 * @dim2: Signed dimension for loop level 2
791 * @dim3: Signed dimension for loop level 3
792 */
793struct cppi5_tr_type3_t {
794 cppi5_tr_flags_t flags;
795 u16 icnt0;
796 u16 icnt1;
797 u64 addr;
798 s32 dim1;
799 u16 icnt2;
800 u16 icnt3;
801 s32 dim2;
802 s32 dim3;
803} __aligned(32) __packed;
804
805/**
806 * struct cppi5_tr_type15_t - Type 15 (Four Dimensional Block Copy with
807 * Repacking and Indirection Support) TR (64 byte)
808 * @flags: TR flags (type, triggers, event, configuration)
809 * @icnt0: Total loop iteration count for level 0 (innermost) for
810 * source
811 * @icnt1: Total loop iteration count for level 1 for source
812 * @addr: Starting address for the source data
813 * @dim1: Signed dimension for loop level 1 for source
814 * @icnt2: Total loop iteration count for level 2 for source
815 * @icnt3: Total loop iteration count for level 3 (outermost) for
816 * source
817 * @dim2: Signed dimension for loop level 2 for source
818 * @dim3: Signed dimension for loop level 3 for source
819 * @_reserved: Not used
820 * @ddim1: Signed dimension for loop level 1 for destination
821 * @daddr: Starting address for the destination data
822 * @ddim2: Signed dimension for loop level 2 for destination
823 * @ddim3: Signed dimension for loop level 3 for destination
824 * @dicnt0: Total loop iteration count for level 0 (innermost) for
825 * destination
826 * @dicnt1: Total loop iteration count for level 1 for destination
827 * @dicnt2: Total loop iteration count for level 2 for destination
828 * @dicnt3: Total loop iteration count for level 3 (outermost) for
829 * destination
830 */
831struct cppi5_tr_type15_t {
832 cppi5_tr_flags_t flags;
833 u16 icnt0;
834 u16 icnt1;
835 u64 addr;
836 s32 dim1;
837 u16 icnt2;
838 u16 icnt3;
839 s32 dim2;
840 s32 dim3;
841 u32 _reserved;
842 s32 ddim1;
843 u64 daddr;
844 s32 ddim2;
845 s32 ddim3;
846 u16 dicnt0;
847 u16 dicnt1;
848 u16 dicnt2;
849 u16 dicnt3;
850} __aligned(64) __packed;
851
852/**
853 * struct cppi5_tr_resp_t - TR response record
854 * @status: Status type and info
855 * @_reserved: Not used
856 * @cmd_id: Command ID for the TR for TR identification
857 * @flags: Configuration Specific Flags
858 */
859struct cppi5_tr_resp_t {
860 u8 status;
861 u8 _reserved;
862 u8 cmd_id;
863 u8 flags;
864} __packed;
865
866#define CPPI5_TR_RESPONSE_STATUS_TYPE_SHIFT (0U)
867#define CPPI5_TR_RESPONSE_STATUS_TYPE_MASK GENMASK(3, 0)
868#define CPPI5_TR_RESPONSE_STATUS_INFO_SHIFT (4U)
869#define CPPI5_TR_RESPONSE_STATUS_INFO_MASK GENMASK(7, 4)
870#define CPPI5_TR_RESPONSE_CMDID_SHIFT (16U)
871#define CPPI5_TR_RESPONSE_CMDID_MASK GENMASK(23, 16)
872#define CPPI5_TR_RESPONSE_CFG_SPECIFIC_SHIFT (24U)
873#define CPPI5_TR_RESPONSE_CFG_SPECIFIC_MASK GENMASK(31, 24)
874
875/**
876 * enum cppi5_tr_resp_status_type - TR Response Status Type field is used to
877 * determine what type of status is being
878 * returned.
879 * @CPPI5_TR_RESPONSE_STATUS_NONE: No error, completion: completed
880 * @CPPI5_TR_RESPONSE_STATUS_TRANSFER_ERR: Transfer Error, completion: none
881 * or partially completed
882 * @CPPI5_TR_RESPONSE_STATUS_ABORTED_ERR: Aborted Error, completion: none
883 * or partially completed
884 * @CPPI5_TR_RESPONSE_STATUS_SUBMISSION_ERR: Submission Error, completion:
885 * none
886 * @CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_ERR: Unsupported Error, completion:
887 * none
888 * @CPPI5_TR_RESPONSE_STATUS_TRANSFER_EXCEPTION: Transfer Exception, completion:
889 * partially completed
890 * @CPPI5_TR_RESPONSE_STATUS__TEARDOWN_FLUSH: Teardown Flush, completion: none
891 */
892enum cppi5_tr_resp_status_type {
893 CPPI5_TR_RESPONSE_STATUS_NONE,
894 CPPI5_TR_RESPONSE_STATUS_TRANSFER_ERR,
895 CPPI5_TR_RESPONSE_STATUS_ABORTED_ERR,
896 CPPI5_TR_RESPONSE_STATUS_SUBMISSION_ERR,
897 CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_ERR,
898 CPPI5_TR_RESPONSE_STATUS_TRANSFER_EXCEPTION,
899 CPPI5_TR_RESPONSE_STATUS__TEARDOWN_FLUSH,
900 /* private: */
901 CPPI5_TR_RESPONSE_STATUS_MAX
902};
903
904/**
905 * enum cppi5_tr_resp_status_submission - TR Response Status field values which
906 * corresponds Submission Error
907 * @CPPI5_TR_RESPONSE_STATUS_SUBMISSION_ICNT0: ICNT0 was 0
908 * @CPPI5_TR_RESPONSE_STATUS_SUBMISSION_FIFO_FULL: Channel FIFO was full when TR
909 * received
910 * @CPPI5_TR_RESPONSE_STATUS_SUBMISSION_OWN: Channel is not owned by the
911 * submitter
912 */
913enum cppi5_tr_resp_status_submission {
914 CPPI5_TR_RESPONSE_STATUS_SUBMISSION_ICNT0,
915 CPPI5_TR_RESPONSE_STATUS_SUBMISSION_FIFO_FULL,
916 CPPI5_TR_RESPONSE_STATUS_SUBMISSION_OWN,
917 /* private: */
918 CPPI5_TR_RESPONSE_STATUS_SUBMISSION_MAX
919};
920
921/**
922 * enum cppi5_tr_resp_status_unsupported - TR Response Status field values which
923 * corresponds Unsupported Error
924 * @CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_TR_TYPE: TR Type not supported
925 * @CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_STATIC: STATIC not supported
926 * @CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_EOL: EOL not supported
927 * @CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_CFG_SPECIFIC: CONFIGURATION SPECIFIC
928 * not supported
929 * @CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_AMODE: AMODE not supported
930 * @CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_ELTYPE: ELTYPE not supported
931 * @CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_DFMT: DFMT not supported
932 * @CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_SECTR: SECTR not supported
933 * @CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_AMODE_SPECIFIC: AMODE SPECIFIC field
934 * not supported
935 */
936enum cppi5_tr_resp_status_unsupported {
937 CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_TR_TYPE,
938 CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_STATIC,
939 CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_EOL,
940 CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_CFG_SPECIFIC,
941 CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_AMODE,
942 CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_ELTYPE,
943 CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_DFMT,
944 CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_SECTR,
945 CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_AMODE_SPECIFIC,
946 /* private: */
947 CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_MAX
948};
949
950/**
951 * cppi5_trdesc_calc_size - Calculate TR Descriptor size
952 * @tr_count: number of TR records
953 * @tr_size: Nominal size of TR record (max) [16, 32, 64, 128]
954 *
955 * Returns: required TR Descriptor size
956 */
957static inline size_t cppi5_trdesc_calc_size(u32 tr_count, u32 tr_size)
958{
959 /*
960 * The Size of a TR descriptor is:
961 * 1 x tr_size : the first 16 bytes is used by the packet info block +
962 * tr_count x tr_size : Transfer Request Records +
963 * tr_count x sizeof(struct cppi5_tr_resp_t) : Transfer Response Records
964 */
965 return tr_size * (tr_count + 1) +
966 sizeof(struct cppi5_tr_resp_t) * tr_count;
967}
968
969/**
970 * cppi5_trdesc_init - Init TR Descriptor
971 * @desc_hdr: TR Descriptor
972 * @tr_count: number of TR records
973 * @tr_size: Nominal size of TR record (max) [16, 32, 64, 128]
974 * @reload_idx: Absolute index to jump to on the 2nd and following passes
975 * through the TR packet.
976 * @reload_count: Number of times to jump from last entry to reload_idx. 0x1ff
977 * indicates infinite looping.
978 *
979 * Init TR Descriptor
980 */
981static inline void cppi5_trdesc_init(struct cppi5_desc_hdr_t *desc_hdr,
982 u32 tr_count, u32 tr_size, u32 reload_idx,
983 u32 reload_count)
984{
985 desc_hdr->pkt_info0 = CPPI5_INFO0_DESC_TYPE_VAL_TR <<
986 CPPI5_INFO0_HDESC_TYPE_SHIFT;
987 desc_hdr->pkt_info0 |=
988 (reload_count << CPPI5_INFO0_TRDESC_RLDCNT_SHIFT) &
989 CPPI5_INFO0_TRDESC_RLDCNT_MASK;
990 desc_hdr->pkt_info0 |=
991 (reload_idx << CPPI5_INFO0_TRDESC_RLDIDX_SHIFT) &
992 CPPI5_INFO0_TRDESC_RLDIDX_MASK;
993 desc_hdr->pkt_info0 |= (tr_count - 1) & CPPI5_INFO0_TRDESC_LASTIDX_MASK;
994
995 desc_hdr->pkt_info1 |= ((ffs(tr_size >> 4) - 1) <<
996 CPPI5_INFO1_TRDESC_RECSIZE_SHIFT) &
997 CPPI5_INFO1_TRDESC_RECSIZE_MASK;
998}
999
1000/**
1001 * cppi5_tr_init - Init TR record
1002 * @flags: Pointer to the TR's flags
1003 * @type: TR type
1004 * @static_tr: TR is static
1005 * @wait: Wait for TR completion before allow the next TR to start
1006 * @event_size: output event generation cfg
1007 * @cmd_id: TR identifier (application specifics)
1008 *
1009 * Init TR record
1010 */
1011static inline void cppi5_tr_init(cppi5_tr_flags_t *flags,
1012 enum cppi5_tr_types type, bool static_tr,
1013 bool wait, enum cppi5_tr_event_size event_size,
1014 u32 cmd_id)
1015{
1016 *flags = type;
1017 *flags |= (event_size << CPPI5_TR_EVENT_SIZE_SHIFT) &
1018 CPPI5_TR_EVENT_SIZE_MASK;
1019
1020 *flags |= (cmd_id << CPPI5_TR_CMD_ID_SHIFT) &
1021 CPPI5_TR_CMD_ID_MASK;
1022
1023 if (static_tr && (type == CPPI5_TR_TYPE8 || type == CPPI5_TR_TYPE9))
1024 *flags |= CPPI5_TR_STATIC;
1025
1026 if (wait)
1027 *flags |= CPPI5_TR_WAIT;
1028}
1029
1030/**
1031 * cppi5_tr_set_trigger - Configure trigger0/1 and trigger0/1_type
1032 * @flags: Pointer to the TR's flags
1033 * @trigger0: trigger0 selection
1034 * @trigger0_type: type of data transfer that will be enabled by trigger0
1035 * @trigger1: trigger1 selection
1036 * @trigger1_type: type of data transfer that will be enabled by trigger1
1037 *
1038 * Configure the triggers for the TR
1039 */
1040static inline void cppi5_tr_set_trigger(cppi5_tr_flags_t *flags,
1041 enum cppi5_tr_trigger trigger0,
1042 enum cppi5_tr_trigger_type trigger0_type,
1043 enum cppi5_tr_trigger trigger1,
1044 enum cppi5_tr_trigger_type trigger1_type)
1045{
1046 *flags &= ~(CPPI5_TR_TRIGGER0_MASK | CPPI5_TR_TRIGGER0_TYPE_MASK |
1047 CPPI5_TR_TRIGGER1_MASK | CPPI5_TR_TRIGGER1_TYPE_MASK);
1048 *flags |= (trigger0 << CPPI5_TR_TRIGGER0_SHIFT) &
1049 CPPI5_TR_TRIGGER0_MASK;
1050 *flags |= (trigger0_type << CPPI5_TR_TRIGGER0_TYPE_SHIFT) &
1051 CPPI5_TR_TRIGGER0_TYPE_MASK;
1052
1053 *flags |= (trigger1 << CPPI5_TR_TRIGGER1_SHIFT) &
1054 CPPI5_TR_TRIGGER1_MASK;
1055 *flags |= (trigger1_type << CPPI5_TR_TRIGGER1_TYPE_SHIFT) &
1056 CPPI5_TR_TRIGGER1_TYPE_MASK;
1057}
1058
1059/**
1060 * cppi5_tr_csf_set - Update the Configuration specific flags
1061 * @flags: Pointer to the TR's flags
1062 * @csf: Configuration specific flags
1063 *
1064 * Set a bit in Configuration Specific Flags section of the TR flags.
1065 */
1066static inline void cppi5_tr_csf_set(cppi5_tr_flags_t *flags, u32 csf)
1067{
1068 *flags &= ~CPPI5_TR_CSF_FLAGS_MASK;
1069 *flags |= (csf << CPPI5_TR_CSF_FLAGS_SHIFT) &
1070 CPPI5_TR_CSF_FLAGS_MASK;
1071}
1072
1073#endif /* __TI_CPPI5_H__ */