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1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Functions to access TPS65215/TPS65219 Power Management Integrated Chips
4 *
5 * Copyright (C) 2022 BayLibre Incorporated - https://www.baylibre.com/
6 * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
7 */
8
9#ifndef MFD_TPS65219_H
10#define MFD_TPS65219_H
11
12#include <linux/bitops.h>
13#include <linux/regmap.h>
14#include <linux/regulator/driver.h>
15
16/* Chip id list*/
17enum pmic_id {
18 TPS65214,
19 TPS65215,
20 TPS65219,
21};
22
23/* I2C ID for TPS65219 part */
24#define TPS65219_I2C_ID 0x24
25
26/* All register addresses */
27#define TPS65219_REG_TI_DEV_ID 0x00
28#define TPS65219_REG_NVM_ID 0x01
29#define TPS65219_REG_ENABLE_CTRL 0x02
30#define TPS65219_REG_BUCKS_CONFIG 0x03
31#define TPS65214_REG_LOCK 0x03
32#define TPS65219_REG_LDO4_VOUT 0x04
33#define TPS65214_REG_LDO1_VOUT_STBY 0x04
34#define TPS65219_REG_LDO3_VOUT 0x05
35#define TPS65215_REG_LDO2_VOUT 0x05
36#define TPS65214_REG_LDO1_VOUT 0x05
37#define TPS65219_REG_LDO2_VOUT 0x06
38#define TPS65214_REG_LDO2_VOUT 0x06
39#define TPS65219_REG_LDO1_VOUT 0x07
40#define TPS65214_REG_LDO2_VOUT_STBY 0x07
41#define TPS65219_REG_BUCK3_VOUT 0x8
42#define TPS65219_REG_BUCK2_VOUT 0x9
43#define TPS65219_REG_BUCK1_VOUT 0xA
44#define TPS65219_REG_LDO4_SEQUENCE_SLOT 0xB
45#define TPS65219_REG_LDO3_SEQUENCE_SLOT 0xC
46#define TPS65215_REG_LDO2_SEQUENCE_SLOT 0xC
47#define TPS65214_REG_LDO1_SEQUENCE_SLOT 0xC
48#define TPS65219_REG_LDO2_SEQUENCE_SLOT 0xD
49#define TPS65219_REG_LDO1_SEQUENCE_SLOT 0xE
50#define TPS65219_REG_BUCK3_SEQUENCE_SLOT 0xF
51#define TPS65219_REG_BUCK2_SEQUENCE_SLOT 0x10
52#define TPS65219_REG_BUCK1_SEQUENCE_SLOT 0x11
53#define TPS65219_REG_nRST_SEQUENCE_SLOT 0x12
54#define TPS65219_REG_GPIO_SEQUENCE_SLOT 0x13
55#define TPS65219_REG_GPO2_SEQUENCE_SLOT 0x14
56#define TPS65214_REG_GPIO_GPI_SEQUENCE_SLOT 0x14
57#define TPS65219_REG_GPO1_SEQUENCE_SLOT 0x15
58#define TPS65214_REG_GPO_SEQUENCE_SLOT 0x15
59#define TPS65219_REG_POWER_UP_SLOT_DURATION_1 0x16
60#define TPS65219_REG_POWER_UP_SLOT_DURATION_2 0x17
61/* _SLOT_DURATION_3 doesn't apply to TPS65215*/
62#define TPS65219_REG_POWER_UP_SLOT_DURATION_3 0x18
63#define TPS65219_REG_POWER_UP_SLOT_DURATION_4 0x19
64#define TPS65214_REG_BUCK3_VOUT_STBY 0x19
65#define TPS65219_REG_POWER_DOWN_SLOT_DURATION_1 0x1A
66#define TPS65219_REG_POWER_DOWN_SLOT_DURATION_2 0x1B
67#define TPS65219_REG_POWER_DOWN_SLOT_DURATION_3 0x1C
68#define TPS65214_REG_BUCK2_VOUT_STBY 0x1C
69#define TPS65219_REG_POWER_DOWN_SLOT_DURATION_4 0x1D
70#define TPS65214_REG_BUCK1_VOUT_STBY 0x1D
71#define TPS65219_REG_GENERAL_CONFIG 0x1E
72#define TPS65219_REG_MFP_1_CONFIG 0x1F
73#define TPS65219_REG_MFP_2_CONFIG 0x20
74#define TPS65219_REG_STBY_1_CONFIG 0x21
75#define TPS65219_REG_STBY_2_CONFIG 0x22
76#define TPS65219_REG_OC_DEGL_CONFIG 0x23
77/* 'sub irq' MASK registers */
78#define TPS65219_REG_INT_MASK_UV 0x24
79#define TPS65219_REG_MASK_CONFIG 0x25
80
81#define TPS65219_REG_I2C_ADDRESS_REG 0x26
82#define TPS65219_REG_USER_GENERAL_NVM_STORAGE 0x27
83#define TPS65219_REG_MANUFACTURING_VER 0x28
84#define TPS65219_REG_MFP_CTRL 0x29
85#define TPS65219_REG_DISCHARGE_CONFIG 0x2A
86/* main irq registers */
87#define TPS65219_REG_INT_SOURCE 0x2B
88
89/* TPS65219 'sub irq' registers */
90#define TPS65219_REG_INT_LDO_3_4 0x2C
91#define TPS65219_REG_INT_LDO_1_2 0x2D
92
93/* TPS65215 specific 'sub irq' registers */
94#define TPS65215_REG_INT_LDO_2 0x2C
95#define TPS65215_REG_INT_LDO_1 0x2D
96
97/* TPS65214 specific 'sub irq' register */
98#define TPS65214_REG_INT_LDO_1_2 0x2D
99
100/* Common TPS65215 & TPS65219 'sub irq' registers */
101#define TPS65219_REG_INT_BUCK_3 0x2E
102#define TPS65219_REG_INT_BUCK_1_2 0x2F
103#define TPS65219_REG_INT_SYSTEM 0x30
104#define TPS65219_REG_INT_RV 0x31
105#define TPS65219_REG_INT_TIMEOUT_RV_SD 0x32
106#define TPS65219_REG_INT_PB 0x33
107
108#define TPS65219_REG_INT_LDO_3_4_POS 0
109#define TPS65219_REG_INT_LDO_1_2_POS 1
110#define TPS65219_REG_INT_BUCK_3_POS 2
111#define TPS65219_REG_INT_BUCK_1_2_POS 3
112#define TPS65219_REG_INT_SYS_POS 4
113#define TPS65219_REG_INT_RV_POS 5
114#define TPS65219_REG_INT_TO_RV_POS 6
115#define TPS65219_REG_INT_PB_POS 7
116
117#define TPS65215_REG_INT_LDO_2_POS 0
118#define TPS65215_REG_INT_LDO_1_POS 1
119
120#define TPS65214_REG_INT_LDO_1_2_POS 0
121#define TPS65214_REG_INT_BUCK_3_POS 1
122#define TPS65214_REG_INT_BUCK_1_2_POS 2
123#define TPS65214_REG_INT_SYS_POS 3
124#define TPS65214_REG_INT_RV_POS 4
125#define TPS65214_REG_INT_TO_RV_POS 5
126#define TPS65214_REG_INT_PB_POS 6
127
128#define TPS65219_REG_USER_NVM_CMD 0x34
129#define TPS65219_REG_POWER_UP_STATUS 0x35
130#define TPS65219_REG_SPARE_2 0x36
131#define TPS65219_REG_SPARE_3 0x37
132#define TPS65219_REG_FACTORY_CONFIG_2 0x41
133
134/* Register field definitions */
135#define TPS65219_DEVID_REV_MASK GENMASK(7, 0)
136#define TPS65219_BUCKS_LDOS_VOUT_VSET_MASK GENMASK(5, 0)
137#define TPS65219_BUCKS_UV_THR_SEL_MASK BIT(6)
138#define TPS65219_BUCKS_BW_SEL_MASK BIT(7)
139#define LDO_BYP_SHIFT 6
140#define TPS65219_LDOS_BYP_CONFIG_MASK BIT(LDO_BYP_SHIFT)
141#define TPS65219_LDOS_LSW_CONFIG_MASK BIT(7)
142/* Regulators enable control */
143#define TPS65219_ENABLE_BUCK1_EN_MASK BIT(0)
144#define TPS65219_ENABLE_BUCK2_EN_MASK BIT(1)
145#define TPS65219_ENABLE_BUCK3_EN_MASK BIT(2)
146#define TPS65219_ENABLE_LDO1_EN_MASK BIT(3)
147#define TPS65219_ENABLE_LDO2_EN_MASK BIT(4)
148#define TPS65219_ENABLE_LDO3_EN_MASK BIT(5)
149#define TPS65215_ENABLE_LDO2_EN_MASK BIT(5)
150#define TPS65214_ENABLE_LDO1_EN_MASK BIT(5)
151#define TPS65219_ENABLE_LDO4_EN_MASK BIT(6)
152/* Register Unlock */
153#define TPS65214_LOCK_ACCESS_CMD 0x5a
154/* power ON-OFF sequence slot */
155#define TPS65219_BUCKS_LDOS_SEQUENCE_OFF_SLOT_MASK GENMASK(3, 0)
156#define TPS65219_BUCKS_LDOS_SEQUENCE_ON_SLOT_MASK GENMASK(7, 4)
157/* TODO: Not needed, same mapping as TPS65219_ENABLE_REGNAME_EN, factorize */
158#define TPS65219_STBY1_BUCK1_STBY_EN_MASK BIT(0)
159#define TPS65219_STBY1_BUCK2_STBY_EN_MASK BIT(1)
160#define TPS65219_STBY1_BUCK3_STBY_EN_MASK BIT(2)
161#define TPS65219_STBY1_LDO1_STBY_EN_MASK BIT(3)
162#define TPS65219_STBY1_LDO2_STBY_EN_MASK BIT(4)
163#define TPS65219_STBY1_LDO3_STBY_EN_MASK BIT(5)
164#define TPS65219_STBY1_LDO4_STBY_EN_MASK BIT(6)
165/* STBY_2 config */
166#define TPS65219_STBY2_GPO1_STBY_EN_MASK BIT(0)
167#define TPS65219_STBY2_GPO2_STBY_EN_MASK BIT(1)
168#define TPS65219_STBY2_GPIO_STBY_EN_MASK BIT(2)
169/* MFP Control */
170#define TPS65219_MFP_I2C_OFF_REQ_MASK BIT(0)
171#define TPS65219_MFP_STBY_I2C_CTRL_MASK BIT(1)
172#define TPS65219_MFP_COLD_RESET_I2C_CTRL_MASK BIT(2)
173#define TPS65219_MFP_WARM_RESET_I2C_CTRL_MASK BIT(3)
174#define TPS65219_MFP_GPIO_STATUS_MASK BIT(4)
175/* MFP_1 Config */
176#define TPS65219_MFP_1_VSEL_DDR_SEL_MASK BIT(0)
177#define TPS65219_MFP_1_VSEL_SD_POL_MASK BIT(1)
178#define TPS65219_MFP_1_VSEL_RAIL_MASK BIT(2)
179/* MFP_2 Config */
180#define TPS65219_MFP_2_MODE_STBY_MASK GENMASK(1, 0)
181#define TPS65219_MFP_2_MODE_RESET_MASK BIT(2)
182#define TPS65219_MFP_2_EN_PB_VSENSE_DEGL_MASK BIT(3)
183#define TPS65219_MFP_2_EN_PB_VSENSE_MASK GENMASK(5, 4)
184#define TPS65219_MFP_2_WARM_COLD_RESET_MASK BIT(6)
185#define TPS65219_MFP_2_PU_ON_FSD_MASK BIT(7)
186#define TPS65219_MFP_2_EN 0
187#define TPS65219_MFP_2_PB BIT(4)
188#define TPS65219_MFP_2_VSENSE BIT(5)
189/* MASK_UV Config */
190#define TPS65219_REG_MASK_UV_LDO1_UV_MASK BIT(0)
191#define TPS65219_REG_MASK_UV_LDO2_UV_MASK BIT(1)
192#define TPS65219_REG_MASK_UV_LDO3_UV_MASK BIT(2)
193#define TPS65219_REG_MASK_UV_LDO4_UV_MASK BIT(3)
194#define TPS65219_REG_MASK_UV_BUCK1_UV_MASK BIT(4)
195#define TPS65219_REG_MASK_UV_BUCK2_UV_MASK BIT(5)
196#define TPS65219_REG_MASK_UV_BUCK3_UV_MASK BIT(6)
197#define TPS65219_REG_MASK_UV_RETRY_MASK BIT(7)
198/* MASK Config */
199// SENSOR_N_WARM_MASK already defined in Thermal
200#define TPS65219_REG_MASK_INT_FOR_RV_MASK BIT(4)
201#define TPS65219_REG_MASK_EFFECT_MASK GENMASK(2, 1)
202#define TPS65219_REG_MASK_INT_FOR_PB_MASK BIT(7)
203/* UnderVoltage - Short to GND - OverCurrent*/
204/* LDO3-4: only for TPS65219*/
205#define TPS65219_INT_LDO3_SCG_MASK BIT(0)
206#define TPS65219_INT_LDO3_OC_MASK BIT(1)
207#define TPS65219_INT_LDO3_UV_MASK BIT(2)
208#define TPS65219_INT_LDO4_SCG_MASK BIT(3)
209#define TPS65219_INT_LDO4_OC_MASK BIT(4)
210#define TPS65219_INT_LDO4_UV_MASK BIT(5)
211/* LDO1-2: TPS65214 & TPS65219 */
212#define TPS65219_INT_LDO1_SCG_MASK BIT(0)
213#define TPS65219_INT_LDO1_OC_MASK BIT(1)
214#define TPS65219_INT_LDO1_UV_MASK BIT(2)
215#define TPS65219_INT_LDO2_SCG_MASK BIT(3)
216#define TPS65219_INT_LDO2_OC_MASK BIT(4)
217#define TPS65219_INT_LDO2_UV_MASK BIT(5)
218/* TPS65215 LDO1-2*/
219#define TPS65215_INT_LDO1_SCG_MASK BIT(0)
220#define TPS65215_INT_LDO1_OC_MASK BIT(1)
221#define TPS65215_INT_LDO1_UV_MASK BIT(2)
222#define TPS65215_INT_LDO2_SCG_MASK BIT(0)
223#define TPS65215_INT_LDO2_OC_MASK BIT(1)
224#define TPS65215_INT_LDO2_UV_MASK BIT(2)
225/* BUCK3 */
226#define TPS65219_INT_BUCK3_SCG_MASK BIT(0)
227#define TPS65219_INT_BUCK3_OC_MASK BIT(1)
228#define TPS65219_INT_BUCK3_NEG_OC_MASK BIT(2)
229#define TPS65219_INT_BUCK3_UV_MASK BIT(3)
230/* BUCK1-2 */
231#define TPS65219_INT_BUCK1_SCG_MASK BIT(0)
232#define TPS65219_INT_BUCK1_OC_MASK BIT(1)
233#define TPS65219_INT_BUCK1_NEG_OC_MASK BIT(2)
234#define TPS65219_INT_BUCK1_UV_MASK BIT(3)
235#define TPS65219_INT_BUCK2_SCG_MASK BIT(4)
236#define TPS65219_INT_BUCK2_OC_MASK BIT(5)
237#define TPS65219_INT_BUCK2_NEG_OC_MASK BIT(6)
238#define TPS65219_INT_BUCK2_UV_MASK BIT(7)
239/* Thermal Sensor: TPS65219/TPS65215 */
240#define TPS65219_INT_SENSOR_3_WARM_MASK BIT(0)
241#define TPS65219_INT_SENSOR_3_HOT_MASK BIT(4)
242/* Thermal Sensor: TPS65219/TPS65215/TPS65214 */
243#define TPS65219_INT_SENSOR_2_WARM_MASK BIT(1)
244#define TPS65219_INT_SENSOR_1_WARM_MASK BIT(2)
245#define TPS65219_INT_SENSOR_0_WARM_MASK BIT(3)
246#define TPS65219_INT_SENSOR_2_HOT_MASK BIT(5)
247#define TPS65219_INT_SENSOR_1_HOT_MASK BIT(6)
248#define TPS65219_INT_SENSOR_0_HOT_MASK BIT(7)
249/* Residual Voltage */
250#define TPS65219_INT_BUCK1_RV_MASK BIT(0)
251#define TPS65219_INT_BUCK2_RV_MASK BIT(1)
252#define TPS65219_INT_BUCK3_RV_MASK BIT(2)
253#define TPS65219_INT_LDO1_RV_MASK BIT(3)
254#define TPS65219_INT_LDO2_RV_MASK BIT(4)
255#define TPS65219_INT_LDO3_RV_MASK BIT(5)
256#define TPS65215_INT_LDO2_RV_MASK BIT(5)
257#define TPS65214_INT_LDO2_RV_MASK BIT(5)
258#define TPS65219_INT_LDO4_RV_MASK BIT(6)
259/* Residual Voltage ShutDown */
260#define TPS65219_INT_BUCK1_RV_SD_MASK BIT(0)
261#define TPS65219_INT_BUCK2_RV_SD_MASK BIT(1)
262#define TPS65219_INT_BUCK3_RV_SD_MASK BIT(2)
263#define TPS65219_INT_LDO1_RV_SD_MASK BIT(3)
264#define TPS65219_INT_LDO2_RV_SD_MASK BIT(4)
265#define TPS65219_INT_LDO3_RV_SD_MASK BIT(5)
266#define TPS65215_INT_LDO2_RV_SD_MASK BIT(5)
267#define TPS65214_INT_LDO1_RV_SD_MASK BIT(5)
268#define TPS65219_INT_LDO4_RV_SD_MASK BIT(6)
269#define TPS65219_INT_TIMEOUT_MASK BIT(7)
270/* Power Button */
271#define TPS65219_INT_PB_FALLING_EDGE_DETECT_MASK BIT(0)
272#define TPS65219_INT_PB_RISING_EDGE_DETECT_MASK BIT(1)
273#define TPS65219_INT_PB_REAL_TIME_STATUS_MASK BIT(2)
274
275#define TPS65219_PB_POS 7
276#define TPS65219_TO_RV_POS 6
277#define TPS65219_RV_POS 5
278#define TPS65219_SYS_POS 4
279#define TPS65219_BUCK_1_2_POS 3
280#define TPS65219_BUCK_3_POS 2
281#define TPS65219_LDO_1_2_POS 1
282#define TPS65219_LDO_3_4_POS 0
283
284/* IRQs */
285enum {
286 /* LDO3-4 register IRQs */
287 TPS65219_INT_LDO3_SCG,
288 TPS65219_INT_LDO3_OC,
289 TPS65219_INT_LDO3_UV,
290 TPS65219_INT_LDO4_SCG,
291 TPS65219_INT_LDO4_OC,
292 TPS65219_INT_LDO4_UV,
293 /* TPS65215 LDO1*/
294 TPS65215_INT_LDO1_SCG,
295 TPS65215_INT_LDO1_OC,
296 TPS65215_INT_LDO1_UV,
297 /* TPS65215 LDO2*/
298 TPS65215_INT_LDO2_SCG,
299 TPS65215_INT_LDO2_OC,
300 TPS65215_INT_LDO2_UV,
301 /* LDO1-2: TPS65219/TPS65214 */
302 TPS65219_INT_LDO1_SCG,
303 TPS65219_INT_LDO1_OC,
304 TPS65219_INT_LDO1_UV,
305 TPS65219_INT_LDO2_SCG,
306 TPS65219_INT_LDO2_OC,
307 TPS65219_INT_LDO2_UV,
308 /* BUCK3 */
309 TPS65219_INT_BUCK3_SCG,
310 TPS65219_INT_BUCK3_OC,
311 TPS65219_INT_BUCK3_NEG_OC,
312 TPS65219_INT_BUCK3_UV,
313 /* BUCK1-2 */
314 TPS65219_INT_BUCK1_SCG,
315 TPS65219_INT_BUCK1_OC,
316 TPS65219_INT_BUCK1_NEG_OC,
317 TPS65219_INT_BUCK1_UV,
318 TPS65219_INT_BUCK2_SCG,
319 TPS65219_INT_BUCK2_OC,
320 TPS65219_INT_BUCK2_NEG_OC,
321 TPS65219_INT_BUCK2_UV,
322 /* Thermal Sensor */
323 TPS65219_INT_SENSOR_3_WARM,
324 TPS65219_INT_SENSOR_2_WARM,
325 TPS65219_INT_SENSOR_1_WARM,
326 TPS65219_INT_SENSOR_0_WARM,
327 TPS65219_INT_SENSOR_3_HOT,
328 TPS65219_INT_SENSOR_2_HOT,
329 TPS65219_INT_SENSOR_1_HOT,
330 TPS65219_INT_SENSOR_0_HOT,
331 /* Residual Voltage */
332 TPS65219_INT_BUCK1_RV,
333 TPS65219_INT_BUCK2_RV,
334 TPS65219_INT_BUCK3_RV,
335 TPS65219_INT_LDO1_RV,
336 TPS65219_INT_LDO2_RV,
337 TPS65215_INT_LDO2_RV,
338 TPS65214_INT_LDO2_RV,
339 TPS65219_INT_LDO3_RV,
340 TPS65219_INT_LDO4_RV,
341 /* Residual Voltage ShutDown */
342 TPS65219_INT_BUCK1_RV_SD,
343 TPS65219_INT_BUCK2_RV_SD,
344 TPS65219_INT_BUCK3_RV_SD,
345 TPS65219_INT_LDO1_RV_SD,
346 TPS65214_INT_LDO1_RV_SD,
347 TPS65215_INT_LDO2_RV_SD,
348 TPS65219_INT_LDO2_RV_SD,
349 TPS65219_INT_LDO3_RV_SD,
350 TPS65219_INT_LDO4_RV_SD,
351 TPS65219_INT_TIMEOUT,
352 /* Power Button */
353 TPS65219_INT_PB_FALLING_EDGE_DETECT,
354 TPS65219_INT_PB_RISING_EDGE_DETECT,
355};
356
357enum tps65214_regulator_id {
358 /*
359 * DCDC's same as TPS65219
360 * LDO1 maps to TPS65219's LDO3
361 * LDO2 is the same as TPS65219
362 *
363 */
364 TPS65214_LDO_1 = 3,
365 TPS65214_LDO_2 = 4,
366};
367
368enum tps65215_regulator_id {
369 /* DCDC's same as TPS65219 */
370 /* LDO1 is the same as TPS65219 */
371 TPS65215_LDO_2 = 4,
372};
373
374enum tps65219_regulator_id {
375 /* DCDC's */
376 TPS65219_BUCK_1,
377 TPS65219_BUCK_2,
378 TPS65219_BUCK_3,
379 /* LDOs */
380 TPS65219_LDO_1,
381 TPS65219_LDO_2,
382 TPS65219_LDO_3,
383 TPS65219_LDO_4,
384};
385
386/* Number of step-down converters available */
387#define TPS6521X_NUM_BUCKS 3
388/* Number of LDO voltage regulators available */
389#define TPS65219_NUM_LDO 4
390#define TPS65215_NUM_LDO 2
391#define TPS65214_NUM_LDO 2
392/* Number of total regulators available */
393#define TPS65219_NUM_REGULATOR (TPS6521X_NUM_BUCKS + TPS65219_NUM_LDO)
394#define TPS65215_NUM_REGULATOR (TPS6521X_NUM_BUCKS + TPS65215_NUM_LDO)
395#define TPS65214_NUM_REGULATOR (TPS6521X_NUM_BUCKS + TPS65214_NUM_LDO)
396
397/* Define the TPS65214 IRQ numbers */
398enum tps65214_irqs {
399 /* INT source registers */
400 TPS65214_TO_RV_SD_SET_IRQ,
401 TPS65214_RV_SET_IRQ,
402 TPS65214_SYS_SET_IRQ,
403 TPS65214_BUCK_1_2_SET_IRQ,
404 TPS65214_BUCK_3_SET_IRQ,
405 TPS65214_LDO_1_2_SET_IRQ,
406 TPS65214_PB_SET_IRQ = 7,
407};
408
409/* Define the TPS65215 IRQ numbers */
410enum tps65215_irqs {
411 /* INT source registers */
412 TPS65215_TO_RV_SD_SET_IRQ,
413 TPS65215_RV_SET_IRQ,
414 TPS65215_SYS_SET_IRQ,
415 TPS65215_BUCK_1_2_SET_IRQ,
416 TPS65215_BUCK_3_SET_IRQ,
417 TPS65215_LDO_1_SET_IRQ,
418 TPS65215_LDO_2_SET_IRQ,
419 TPS65215_PB_SET_IRQ,
420};
421
422/* Define the TPS65219 IRQ numbers */
423enum tps65219_irqs {
424 /* INT source registers */
425 TPS65219_TO_RV_SD_SET_IRQ,
426 TPS65219_RV_SET_IRQ,
427 TPS65219_SYS_SET_IRQ,
428 TPS65219_BUCK_1_2_SET_IRQ,
429 TPS65219_BUCK_3_SET_IRQ,
430 TPS65219_LDO_1_2_SET_IRQ,
431 TPS65219_LDO_3_4_SET_IRQ,
432 TPS65219_PB_SET_IRQ,
433};
434
435/**
436 * struct tps65219 - tps65219 sub-driver chip access routines
437 *
438 * Device data may be used to access the TPS65219 chip
439 *
440 * @dev: MFD device
441 * @regmap: Regmap for accessing the device registers
442 * @irq_data: Regmap irq data used for the irq chip
443 */
444struct tps65219 {
445 struct device *dev;
446 struct regmap *regmap;
447
448 struct regmap_irq_chip_data *irq_data;
449};
450
451#endif /* MFD_TPS65219_H */