Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#ifndef MLX5_DEVICE_H
34#define MLX5_DEVICE_H
35
36#include <linux/types.h>
37#include <rdma/ib_verbs.h>
38#include <linux/mlx5/mlx5_ifc.h>
39#include <linux/bitfield.h>
40
41#if defined(__LITTLE_ENDIAN)
42#define MLX5_SET_HOST_ENDIANNESS 0
43#elif defined(__BIG_ENDIAN)
44#define MLX5_SET_HOST_ENDIANNESS 0x80
45#else
46#error Host endianness not defined
47#endif
48
49/* helper macros */
50#define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0)
51#define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld)
52#define __mlx5_bit_off(typ, fld) (offsetof(struct mlx5_ifc_##typ##_bits, fld))
53#define __mlx5_16_off(typ, fld) (__mlx5_bit_off(typ, fld) / 16)
54#define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32)
55#define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64)
56#define __mlx5_16_bit_off(typ, fld) (16 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0xf))
57#define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0x1f))
58#define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
59#define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << __mlx5_dw_bit_off(typ, fld))
60#define __mlx5_mask16(typ, fld) ((u16)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
61#define __mlx5_16_mask(typ, fld) (__mlx5_mask16(typ, fld) << __mlx5_16_bit_off(typ, fld))
62#define __mlx5_st_sz_bits(typ) sizeof(struct mlx5_ifc_##typ##_bits)
63
64#define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)
65#define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8)
66#define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32)
67#define MLX5_ST_SZ_QW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 64)
68#define MLX5_UN_SZ_BYTES(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 8)
69#define MLX5_UN_SZ_DW(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 32)
70#define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8)
71#define MLX5_ADDR_OF(typ, p, fld) ((void *)((u8 *)(p) + MLX5_BYTE_OFF(typ, fld)))
72
73/* insert a value to a struct */
74#define MLX5_SET(typ, p, fld, v) do { \
75 u32 _v = v; \
76 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \
77 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
78 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
79 (~__mlx5_dw_mask(typ, fld))) | (((_v) & __mlx5_mask(typ, fld)) \
80 << __mlx5_dw_bit_off(typ, fld))); \
81} while (0)
82
83#define MLX5_ARRAY_SET(typ, p, fld, idx, v) do { \
84 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 32); \
85 MLX5_SET(typ, p, fld[idx], v); \
86} while (0)
87
88#define MLX5_SET_TO_ONES(typ, p, fld) do { \
89 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \
90 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
91 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
92 (~__mlx5_dw_mask(typ, fld))) | ((__mlx5_mask(typ, fld)) \
93 << __mlx5_dw_bit_off(typ, fld))); \
94} while (0)
95
96#define MLX5_GET(typ, p, fld) ((be32_to_cpu(*((__be32 *)(p) +\
97__mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
98__mlx5_mask(typ, fld))
99
100#define MLX5_GET_PR(typ, p, fld) ({ \
101 u32 ___t = MLX5_GET(typ, p, fld); \
102 pr_debug(#fld " = 0x%x\n", ___t); \
103 ___t; \
104})
105
106#define __MLX5_SET64(typ, p, fld, v) do { \
107 BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) != 64); \
108 *((__be64 *)(p) + __mlx5_64_off(typ, fld)) = cpu_to_be64(v); \
109} while (0)
110
111#define MLX5_SET64(typ, p, fld, v) do { \
112 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \
113 __MLX5_SET64(typ, p, fld, v); \
114} while (0)
115
116#define MLX5_ARRAY_SET64(typ, p, fld, idx, v) do { \
117 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \
118 __MLX5_SET64(typ, p, fld[idx], v); \
119} while (0)
120
121#define MLX5_GET64(typ, p, fld) be64_to_cpu(*((__be64 *)(p) + __mlx5_64_off(typ, fld)))
122
123#define MLX5_GET64_PR(typ, p, fld) ({ \
124 u64 ___t = MLX5_GET64(typ, p, fld); \
125 pr_debug(#fld " = 0x%llx\n", ___t); \
126 ___t; \
127})
128
129#define MLX5_GET16(typ, p, fld) ((be16_to_cpu(*((__be16 *)(p) +\
130__mlx5_16_off(typ, fld))) >> __mlx5_16_bit_off(typ, fld)) & \
131__mlx5_mask16(typ, fld))
132
133#define MLX5_SET16(typ, p, fld, v) do { \
134 u16 _v = v; \
135 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 16); \
136 *((__be16 *)(p) + __mlx5_16_off(typ, fld)) = \
137 cpu_to_be16((be16_to_cpu(*((__be16 *)(p) + __mlx5_16_off(typ, fld))) & \
138 (~__mlx5_16_mask(typ, fld))) | (((_v) & __mlx5_mask16(typ, fld)) \
139 << __mlx5_16_bit_off(typ, fld))); \
140} while (0)
141
142/* Big endian getters */
143#define MLX5_GET64_BE(typ, p, fld) (*((__be64 *)(p) +\
144 __mlx5_64_off(typ, fld)))
145
146#define MLX5_GET_BE(type_t, typ, p, fld) ({ \
147 type_t tmp; \
148 switch (sizeof(tmp)) { \
149 case sizeof(u8): \
150 tmp = (__force type_t)MLX5_GET(typ, p, fld); \
151 break; \
152 case sizeof(u16): \
153 tmp = (__force type_t)cpu_to_be16(MLX5_GET(typ, p, fld)); \
154 break; \
155 case sizeof(u32): \
156 tmp = (__force type_t)cpu_to_be32(MLX5_GET(typ, p, fld)); \
157 break; \
158 case sizeof(u64): \
159 tmp = (__force type_t)MLX5_GET64_BE(typ, p, fld); \
160 break; \
161 } \
162 tmp; \
163 })
164
165enum mlx5_inline_modes {
166 MLX5_INLINE_MODE_NONE,
167 MLX5_INLINE_MODE_L2,
168 MLX5_INLINE_MODE_IP,
169 MLX5_INLINE_MODE_TCP_UDP,
170};
171
172enum {
173 MLX5_MAX_COMMANDS = 32,
174 MLX5_CMD_DATA_BLOCK_SIZE = 512,
175 MLX5_PCI_CMD_XPORT = 7,
176 MLX5_MKEY_BSF_OCTO_SIZE = 4,
177 MLX5_MAX_PSVS = 4,
178};
179
180enum {
181 MLX5_EXTENDED_UD_AV = 0x80000000,
182};
183
184enum {
185 MLX5_CQ_STATE_ARMED = 9,
186 MLX5_CQ_STATE_ALWAYS_ARMED = 0xb,
187 MLX5_CQ_STATE_FIRED = 0xa,
188};
189
190enum {
191 MLX5_STAT_RATE_OFFSET = 5,
192};
193
194enum {
195 MLX5_INLINE_SEG = 0x80000000,
196};
197
198enum {
199 MLX5_HW_START_PADDING = MLX5_INLINE_SEG,
200};
201
202enum {
203 MLX5_MIN_PKEY_TABLE_SIZE = 128,
204 MLX5_MAX_LOG_PKEY_TABLE = 5,
205};
206
207enum {
208 MLX5_MKEY_INBOX_PG_ACCESS = 1 << 31
209};
210
211enum {
212 MLX5_PFAULT_SUBTYPE_WQE = 0,
213 MLX5_PFAULT_SUBTYPE_RDMA = 1,
214 MLX5_PFAULT_SUBTYPE_MEMORY = 2,
215};
216
217enum wqe_page_fault_type {
218 MLX5_WQE_PF_TYPE_RMP = 0,
219 MLX5_WQE_PF_TYPE_REQ_SEND_OR_WRITE = 1,
220 MLX5_WQE_PF_TYPE_RESP = 2,
221 MLX5_WQE_PF_TYPE_REQ_READ_OR_ATOMIC = 3,
222};
223
224enum {
225 MLX5_PERM_LOCAL_READ = 1 << 2,
226 MLX5_PERM_LOCAL_WRITE = 1 << 3,
227 MLX5_PERM_REMOTE_READ = 1 << 4,
228 MLX5_PERM_REMOTE_WRITE = 1 << 5,
229 MLX5_PERM_ATOMIC = 1 << 6,
230 MLX5_PERM_UMR_EN = 1 << 7,
231};
232
233enum {
234 MLX5_PCIE_CTRL_SMALL_FENCE = 1 << 0,
235 MLX5_PCIE_CTRL_RELAXED_ORDERING = 1 << 2,
236 MLX5_PCIE_CTRL_NO_SNOOP = 1 << 3,
237 MLX5_PCIE_CTRL_TLP_PROCE_EN = 1 << 6,
238 MLX5_PCIE_CTRL_TPH_MASK = 3 << 4,
239};
240
241enum {
242 MLX5_EN_RD = (u64)1,
243 MLX5_EN_WR = (u64)2
244};
245
246enum {
247 MLX5_ADAPTER_PAGE_SHIFT = 12,
248 MLX5_ADAPTER_PAGE_SIZE = 1 << MLX5_ADAPTER_PAGE_SHIFT,
249};
250
251enum {
252 MLX5_BFREGS_PER_UAR = 4,
253 MLX5_MAX_UARS = 1 << 8,
254 MLX5_NON_FP_BFREGS_PER_UAR = 2,
255 MLX5_FP_BFREGS_PER_UAR = MLX5_BFREGS_PER_UAR -
256 MLX5_NON_FP_BFREGS_PER_UAR,
257 MLX5_MAX_BFREGS = MLX5_MAX_UARS *
258 MLX5_NON_FP_BFREGS_PER_UAR,
259 MLX5_UARS_IN_PAGE = PAGE_SIZE / MLX5_ADAPTER_PAGE_SIZE,
260 MLX5_NON_FP_BFREGS_IN_PAGE = MLX5_NON_FP_BFREGS_PER_UAR * MLX5_UARS_IN_PAGE,
261 MLX5_MIN_DYN_BFREGS = 512,
262 MLX5_MAX_DYN_BFREGS = 1024,
263};
264
265enum {
266 MLX5_MKEY_MASK_LEN = 1ull << 0,
267 MLX5_MKEY_MASK_PAGE_SIZE = 1ull << 1,
268 MLX5_MKEY_MASK_START_ADDR = 1ull << 6,
269 MLX5_MKEY_MASK_PD = 1ull << 7,
270 MLX5_MKEY_MASK_EN_RINVAL = 1ull << 8,
271 MLX5_MKEY_MASK_EN_SIGERR = 1ull << 9,
272 MLX5_MKEY_MASK_BSF_EN = 1ull << 12,
273 MLX5_MKEY_MASK_KEY = 1ull << 13,
274 MLX5_MKEY_MASK_QPN = 1ull << 14,
275 MLX5_MKEY_MASK_LR = 1ull << 17,
276 MLX5_MKEY_MASK_LW = 1ull << 18,
277 MLX5_MKEY_MASK_RR = 1ull << 19,
278 MLX5_MKEY_MASK_RW = 1ull << 20,
279 MLX5_MKEY_MASK_A = 1ull << 21,
280 MLX5_MKEY_MASK_SMALL_FENCE = 1ull << 23,
281 MLX5_MKEY_MASK_RELAXED_ORDERING_WRITE = 1ull << 25,
282 MLX5_MKEY_MASK_FREE = 1ull << 29,
283 MLX5_MKEY_MASK_PAGE_SIZE_5 = 1ull << 42,
284 MLX5_MKEY_MASK_RELAXED_ORDERING_READ = 1ull << 47,
285};
286
287enum {
288 MLX5_UMR_TRANSLATION_OFFSET_EN = (1 << 4),
289
290 MLX5_UMR_CHECK_NOT_FREE = (1 << 5),
291 MLX5_UMR_CHECK_FREE = (2 << 5),
292
293 MLX5_UMR_INLINE = (1 << 7),
294};
295
296#define MLX5_UMR_ALIGN (2048)
297#define MLX5_UMR_FLEX_ALIGNMENT 0x40
298#define MLX5_UMR_MTT_NUM_ENTRIES_ALIGNMENT (MLX5_UMR_FLEX_ALIGNMENT / sizeof(struct mlx5_mtt))
299#define MLX5_UMR_KLM_NUM_ENTRIES_ALIGNMENT (MLX5_UMR_FLEX_ALIGNMENT / sizeof(struct mlx5_klm))
300#define MLX5_UMR_KSM_NUM_ENTRIES_ALIGNMENT (MLX5_UMR_FLEX_ALIGNMENT / sizeof(struct mlx5_ksm))
301
302#define MLX5_USER_INDEX_LEN (MLX5_FLD_SZ_BYTES(qpc, user_index) * 8)
303
304enum {
305 MLX5_EVENT_QUEUE_TYPE_QP = 0,
306 MLX5_EVENT_QUEUE_TYPE_RQ = 1,
307 MLX5_EVENT_QUEUE_TYPE_SQ = 2,
308 MLX5_EVENT_QUEUE_TYPE_DCT = 6,
309};
310
311/* mlx5 components can subscribe to any one of these events via
312 * mlx5_eq_notifier_register API.
313 */
314enum mlx5_event {
315 /* Special value to subscribe to any event */
316 MLX5_EVENT_TYPE_NOTIFY_ANY = 0x0,
317 /* HW events enum start: comp events are not subscribable */
318 MLX5_EVENT_TYPE_COMP = 0x0,
319 /* HW Async events enum start: subscribable events */
320 MLX5_EVENT_TYPE_PATH_MIG = 0x01,
321 MLX5_EVENT_TYPE_COMM_EST = 0x02,
322 MLX5_EVENT_TYPE_SQ_DRAINED = 0x03,
323 MLX5_EVENT_TYPE_SRQ_LAST_WQE = 0x13,
324 MLX5_EVENT_TYPE_SRQ_RQ_LIMIT = 0x14,
325
326 MLX5_EVENT_TYPE_CQ_ERROR = 0x04,
327 MLX5_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
328 MLX5_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
329 MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
330 MLX5_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
331 MLX5_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
332 MLX5_EVENT_TYPE_OBJECT_CHANGE = 0x27,
333
334 MLX5_EVENT_TYPE_INTERNAL_ERROR = 0x08,
335 MLX5_EVENT_TYPE_PORT_CHANGE = 0x09,
336 MLX5_EVENT_TYPE_GPIO_EVENT = 0x15,
337 MLX5_EVENT_TYPE_PORT_MODULE_EVENT = 0x16,
338 MLX5_EVENT_TYPE_TEMP_WARN_EVENT = 0x17,
339 MLX5_EVENT_TYPE_XRQ_ERROR = 0x18,
340 MLX5_EVENT_TYPE_REMOTE_CONFIG = 0x19,
341 MLX5_EVENT_TYPE_GENERAL_EVENT = 0x22,
342 MLX5_EVENT_TYPE_MONITOR_COUNTER = 0x24,
343 MLX5_EVENT_TYPE_PPS_EVENT = 0x25,
344
345 MLX5_EVENT_TYPE_DB_BF_CONGESTION = 0x1a,
346 MLX5_EVENT_TYPE_STALL_EVENT = 0x1b,
347
348 MLX5_EVENT_TYPE_CMD = 0x0a,
349 MLX5_EVENT_TYPE_PAGE_REQUEST = 0xb,
350
351 MLX5_EVENT_TYPE_PAGE_FAULT = 0xc,
352 MLX5_EVENT_TYPE_NIC_VPORT_CHANGE = 0xd,
353
354 MLX5_EVENT_TYPE_ESW_FUNCTIONS_CHANGED = 0xe,
355 MLX5_EVENT_TYPE_VHCA_STATE_CHANGE = 0xf,
356
357 MLX5_EVENT_TYPE_DCT_DRAINED = 0x1c,
358 MLX5_EVENT_TYPE_DCT_KEY_VIOLATION = 0x1d,
359
360 MLX5_EVENT_TYPE_FPGA_ERROR = 0x20,
361 MLX5_EVENT_TYPE_FPGA_QP_ERROR = 0x21,
362
363 MLX5_EVENT_TYPE_DEVICE_TRACER = 0x26,
364
365 MLX5_EVENT_TYPE_MAX = 0x100,
366};
367
368enum mlx5_driver_event {
369 MLX5_DRIVER_EVENT_TYPE_TRAP = 0,
370 MLX5_DRIVER_EVENT_UPLINK_NETDEV,
371 MLX5_DRIVER_EVENT_MACSEC_SA_ADDED,
372 MLX5_DRIVER_EVENT_MACSEC_SA_DELETED,
373 MLX5_DRIVER_EVENT_SF_PEER_DEVLINK,
374 MLX5_DRIVER_EVENT_AFFILIATION_DONE,
375 MLX5_DRIVER_EVENT_AFFILIATION_REMOVED,
376 MLX5_DRIVER_EVENT_ACTIVE_BACKUP_LAG_CHANGE_LOWERSTATE,
377};
378
379enum {
380 MLX5_TRACER_SUBTYPE_OWNERSHIP_CHANGE = 0x0,
381 MLX5_TRACER_SUBTYPE_TRACES_AVAILABLE = 0x1,
382 MLX5_TRACER_SUBTYPE_STRINGS_DB_UPDATE = 0x2,
383};
384
385enum {
386 MLX5_GENERAL_SUBTYPE_DELAY_DROP_TIMEOUT = 0x1,
387 MLX5_GENERAL_SUBTYPE_PCI_POWER_CHANGE_EVENT = 0x5,
388 MLX5_GENERAL_SUBTYPE_FW_LIVE_PATCH_EVENT = 0x7,
389 MLX5_GENERAL_SUBTYPE_PCI_SYNC_FOR_FW_UPDATE_EVENT = 0x8,
390};
391
392enum {
393 MLX5_PORT_CHANGE_SUBTYPE_DOWN = 1,
394 MLX5_PORT_CHANGE_SUBTYPE_ACTIVE = 4,
395 MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED = 5,
396 MLX5_PORT_CHANGE_SUBTYPE_LID = 6,
397 MLX5_PORT_CHANGE_SUBTYPE_PKEY = 7,
398 MLX5_PORT_CHANGE_SUBTYPE_GUID = 8,
399 MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG = 9,
400};
401
402enum {
403 MLX5_ROCE_VERSION_1 = 0,
404 MLX5_ROCE_VERSION_2 = 2,
405};
406
407enum {
408 MLX5_ROCE_VERSION_1_CAP = 1 << MLX5_ROCE_VERSION_1,
409 MLX5_ROCE_VERSION_2_CAP = 1 << MLX5_ROCE_VERSION_2,
410};
411
412enum {
413 MLX5_ROCE_L3_TYPE_IPV4 = 0,
414 MLX5_ROCE_L3_TYPE_IPV6 = 1,
415};
416
417enum {
418 MLX5_ROCE_L3_TYPE_IPV4_CAP = 1 << 1,
419 MLX5_ROCE_L3_TYPE_IPV6_CAP = 1 << 2,
420};
421
422enum {
423 MLX5_OPCODE_NOP = 0x00,
424 MLX5_OPCODE_SEND_INVAL = 0x01,
425 MLX5_OPCODE_RDMA_WRITE = 0x08,
426 MLX5_OPCODE_RDMA_WRITE_IMM = 0x09,
427 MLX5_OPCODE_SEND = 0x0a,
428 MLX5_OPCODE_SEND_IMM = 0x0b,
429 MLX5_OPCODE_LSO = 0x0e,
430 MLX5_OPCODE_RDMA_READ = 0x10,
431 MLX5_OPCODE_ATOMIC_CS = 0x11,
432 MLX5_OPCODE_ATOMIC_FA = 0x12,
433 MLX5_OPCODE_ATOMIC_MASKED_CS = 0x14,
434 MLX5_OPCODE_ATOMIC_MASKED_FA = 0x15,
435 MLX5_OPCODE_BIND_MW = 0x18,
436 MLX5_OPCODE_CONFIG_CMD = 0x1f,
437 MLX5_OPCODE_ENHANCED_MPSW = 0x29,
438
439 MLX5_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
440 MLX5_RECV_OPCODE_SEND = 0x01,
441 MLX5_RECV_OPCODE_SEND_IMM = 0x02,
442 MLX5_RECV_OPCODE_SEND_INVAL = 0x03,
443
444 MLX5_CQE_OPCODE_ERROR = 0x1e,
445 MLX5_CQE_OPCODE_RESIZE = 0x16,
446
447 MLX5_OPCODE_SET_PSV = 0x20,
448 MLX5_OPCODE_GET_PSV = 0x21,
449 MLX5_OPCODE_CHECK_PSV = 0x22,
450 MLX5_OPCODE_DUMP = 0x23,
451 MLX5_OPCODE_RGET_PSV = 0x26,
452 MLX5_OPCODE_RCHECK_PSV = 0x27,
453
454 MLX5_OPCODE_UMR = 0x25,
455
456 MLX5_OPCODE_FLOW_TBL_ACCESS = 0x2c,
457
458 MLX5_OPCODE_ACCESS_ASO = 0x2d,
459};
460
461enum {
462 MLX5_OPC_MOD_TLS_TIS_STATIC_PARAMS = 0x1,
463 MLX5_OPC_MOD_TLS_TIR_STATIC_PARAMS = 0x2,
464};
465
466enum {
467 MLX5_OPC_MOD_TLS_TIS_PROGRESS_PARAMS = 0x1,
468 MLX5_OPC_MOD_TLS_TIR_PROGRESS_PARAMS = 0x2,
469};
470
471struct mlx5_wqe_tls_static_params_seg {
472 u8 ctx[MLX5_ST_SZ_BYTES(tls_static_params)];
473};
474
475struct mlx5_wqe_tls_progress_params_seg {
476 __be32 tis_tir_num;
477 u8 ctx[MLX5_ST_SZ_BYTES(tls_progress_params)];
478};
479
480enum {
481 MLX5_SET_PORT_RESET_QKEY = 0,
482 MLX5_SET_PORT_GUID0 = 16,
483 MLX5_SET_PORT_NODE_GUID = 17,
484 MLX5_SET_PORT_SYS_GUID = 18,
485 MLX5_SET_PORT_GID_TABLE = 19,
486 MLX5_SET_PORT_PKEY_TABLE = 20,
487};
488
489enum {
490 MLX5_BW_NO_LIMIT = 0,
491 MLX5_100_MBPS_UNIT = 3,
492 MLX5_GBPS_UNIT = 4,
493};
494
495enum {
496 MLX5_MAX_PAGE_SHIFT = 31
497};
498
499enum {
500 /*
501 * Max wqe size for rdma read is 512 bytes, so this
502 * limits our max_sge_rd as the wqe needs to fit:
503 * - ctrl segment (16 bytes)
504 * - rdma segment (16 bytes)
505 * - scatter elements (16 bytes each)
506 */
507 MLX5_MAX_SGE_RD = (512 - 16 - 16) / 16
508};
509
510enum mlx5_odp_transport_cap_bits {
511 MLX5_ODP_SUPPORT_SEND = 1 << 31,
512 MLX5_ODP_SUPPORT_RECV = 1 << 30,
513 MLX5_ODP_SUPPORT_WRITE = 1 << 29,
514 MLX5_ODP_SUPPORT_READ = 1 << 28,
515};
516
517struct mlx5_odp_caps {
518 char reserved[0x10];
519 struct {
520 __be32 rc_odp_caps;
521 __be32 uc_odp_caps;
522 __be32 ud_odp_caps;
523 } per_transport_caps;
524 char reserved2[0xe4];
525};
526
527struct mlx5_cmd_layout {
528 u8 type;
529 u8 rsvd0[3];
530 __be32 inlen;
531 __be64 in_ptr;
532 __be32 in[4];
533 __be32 out[4];
534 __be64 out_ptr;
535 __be32 outlen;
536 u8 token;
537 u8 sig;
538 u8 rsvd1;
539 u8 status_own;
540};
541
542enum mlx5_rfr_severity_bit_offsets {
543 MLX5_CRR_BIT_OFFSET = 0x6,
544 MLX5_RFR_BIT_OFFSET = 0x7,
545};
546
547struct health_buffer {
548 __be32 assert_var[6];
549 __be32 rsvd0[2];
550 __be32 assert_exit_ptr;
551 __be32 assert_callra;
552 __be32 rsvd1[1];
553 __be32 time;
554 __be32 fw_ver;
555 __be32 hw_id;
556 u8 rfr_severity;
557 u8 rsvd2[3];
558 u8 irisc_index;
559 u8 synd;
560 __be16 ext_synd;
561};
562
563enum mlx5_initializing_bit_offsets {
564 MLX5_FW_RESET_SUPPORTED_OFFSET = 30,
565};
566
567enum mlx5_cmd_addr_l_sz_offset {
568 MLX5_NIC_IFC_OFFSET = 8,
569};
570
571struct mlx5_init_seg {
572 __be32 fw_rev;
573 __be32 cmdif_rev_fw_sub;
574 __be32 rsvd0[2];
575 __be32 cmdq_addr_h;
576 __be32 cmdq_addr_l_sz;
577 __be32 cmd_dbell;
578 __be32 rsvd1[120];
579 __be32 initializing;
580 struct health_buffer health;
581 __be32 rsvd2[878];
582 __be32 cmd_exec_to;
583 __be32 cmd_q_init_to;
584 __be32 internal_timer_h;
585 __be32 internal_timer_l;
586 __be32 rsvd3[2];
587 __be32 health_counter;
588 __be32 rsvd4[11];
589 __be32 real_time_h;
590 __be32 real_time_l;
591 __be32 rsvd5[1006];
592 __be64 ieee1588_clk;
593 __be32 ieee1588_clk_type;
594 __be32 clr_intx;
595};
596
597struct mlx5_eqe_comp {
598 __be32 reserved[6];
599 __be32 cqn;
600};
601
602struct mlx5_eqe_qp_srq {
603 __be32 reserved1[5];
604 u8 type;
605 u8 reserved2[3];
606 __be32 qp_srq_n;
607};
608
609struct mlx5_eqe_cq_err {
610 __be32 cqn;
611 u8 reserved1[7];
612 u8 syndrome;
613};
614
615struct mlx5_eqe_xrq_err {
616 __be32 reserved1[5];
617 __be32 type_xrqn;
618 __be32 reserved2;
619};
620
621struct mlx5_eqe_port_state {
622 u8 reserved0[8];
623 u8 port;
624};
625
626struct mlx5_eqe_gpio {
627 __be32 reserved0[2];
628 __be64 gpio_event;
629};
630
631struct mlx5_eqe_congestion {
632 u8 type;
633 u8 rsvd0;
634 u8 congestion_level;
635};
636
637struct mlx5_eqe_stall_vl {
638 u8 rsvd0[3];
639 u8 port_vl;
640};
641
642struct mlx5_eqe_cmd {
643 __be32 vector;
644 __be32 rsvd[6];
645};
646
647struct mlx5_eqe_page_req {
648 __be16 ec_function;
649 __be16 func_id;
650 __be32 num_pages;
651 __be32 rsvd1[5];
652};
653
654#define MEMORY_SCHEME_PAGE_FAULT_GRANULARITY 4096
655struct mlx5_eqe_page_fault {
656 union {
657 struct {
658 __be32 bytes_committed;
659 u16 reserved1;
660 __be16 wqe_index;
661 u16 reserved2;
662 __be16 packet_length;
663 __be32 token;
664 u8 reserved4[8];
665 __be32 pftype_wq;
666 } __packed wqe;
667 struct {
668 __be32 bytes_committed;
669 __be32 r_key;
670 u16 reserved1;
671 __be16 packet_length;
672 __be32 rdma_op_len;
673 __be64 rdma_va;
674 __be32 pftype_token;
675 } __packed rdma;
676 struct {
677 u8 flags;
678 u8 reserved1;
679 __be16 post_demand_fault_pages;
680 __be16 pre_demand_fault_pages;
681 __be16 token47_32;
682 __be32 token31_0;
683 /*
684 * FW changed from specifying the fault size in byte
685 * count to 4k pages granularity. The size specified
686 * in pages uses bits 31:12, to keep backward
687 * compatibility.
688 */
689 __be32 demand_fault_pages;
690 __be32 mkey;
691 __be64 va;
692 } __packed memory;
693 } __packed;
694} __packed;
695
696struct mlx5_eqe_vport_change {
697 u8 rsvd0[2];
698 __be16 vport_num;
699 __be32 rsvd1[6];
700} __packed;
701
702struct mlx5_eqe_port_module {
703 u8 reserved_at_0[1];
704 u8 module;
705 u8 reserved_at_2[1];
706 u8 module_status;
707 u8 reserved_at_4[2];
708 u8 error_type;
709} __packed;
710
711struct mlx5_eqe_pps {
712 u8 rsvd0[3];
713 u8 pin;
714 u8 rsvd1[4];
715 union {
716 struct {
717 __be32 time_sec;
718 __be32 time_nsec;
719 };
720 struct {
721 __be64 time_stamp;
722 };
723 };
724 u8 rsvd2[12];
725} __packed;
726
727struct mlx5_eqe_dct {
728 __be32 reserved[6];
729 __be32 dctn;
730};
731
732struct mlx5_eqe_temp_warning {
733 __be64 sensor_warning_msb;
734 __be64 sensor_warning_lsb;
735} __packed;
736
737struct mlx5_eqe_obj_change {
738 u8 rsvd0[2];
739 __be16 obj_type;
740 __be32 obj_id;
741} __packed;
742
743#define SYNC_RST_STATE_MASK 0xf
744
745enum sync_rst_state_type {
746 MLX5_SYNC_RST_STATE_RESET_REQUEST = 0x0,
747 MLX5_SYNC_RST_STATE_RESET_NOW = 0x1,
748 MLX5_SYNC_RST_STATE_RESET_ABORT = 0x2,
749 MLX5_SYNC_RST_STATE_RESET_UNLOAD = 0x3,
750};
751
752struct mlx5_eqe_sync_fw_update {
753 u8 reserved_at_0[3];
754 u8 sync_rst_state;
755};
756
757struct mlx5_eqe_vhca_state {
758 __be16 ec_function;
759 __be16 function_id;
760} __packed;
761
762union ev_data {
763 __be32 raw[7];
764 struct mlx5_eqe_cmd cmd;
765 struct mlx5_eqe_comp comp;
766 struct mlx5_eqe_qp_srq qp_srq;
767 struct mlx5_eqe_cq_err cq_err;
768 struct mlx5_eqe_port_state port;
769 struct mlx5_eqe_gpio gpio;
770 struct mlx5_eqe_congestion cong;
771 struct mlx5_eqe_stall_vl stall_vl;
772 struct mlx5_eqe_page_req req_pages;
773 struct mlx5_eqe_page_fault page_fault;
774 struct mlx5_eqe_vport_change vport_change;
775 struct mlx5_eqe_port_module port_module;
776 struct mlx5_eqe_pps pps;
777 struct mlx5_eqe_dct dct;
778 struct mlx5_eqe_temp_warning temp_warning;
779 struct mlx5_eqe_xrq_err xrq_err;
780 struct mlx5_eqe_sync_fw_update sync_fw_update;
781 struct mlx5_eqe_vhca_state vhca_state;
782 struct mlx5_eqe_obj_change obj_change;
783} __packed;
784
785struct mlx5_eqe {
786 u8 rsvd0;
787 u8 type;
788 u8 rsvd1;
789 u8 sub_type;
790 __be32 rsvd2[7];
791 union ev_data data;
792 __be16 rsvd3;
793 u8 signature;
794 u8 owner;
795} __packed;
796
797struct mlx5_cmd_prot_block {
798 u8 data[MLX5_CMD_DATA_BLOCK_SIZE];
799 u8 rsvd0[48];
800 __be64 next;
801 __be32 block_num;
802 u8 rsvd1;
803 u8 token;
804 u8 ctrl_sig;
805 u8 sig;
806};
807
808enum {
809 MLX5_CQE_SYND_FLUSHED_IN_ERROR = 5,
810};
811
812struct mlx5_err_cqe {
813 u8 rsvd0[32];
814 __be32 srqn;
815 u8 rsvd1[18];
816 u8 vendor_err_synd;
817 u8 syndrome;
818 __be32 s_wqe_opcode_qpn;
819 __be16 wqe_counter;
820 u8 signature;
821 u8 op_own;
822};
823
824struct mlx5_cqe64 {
825 u8 tls_outer_l3_tunneled;
826 u8 rsvd0;
827 __be16 wqe_id;
828 union {
829 struct {
830 u8 tcppsh_abort_dupack;
831 u8 min_ttl;
832 __be16 tcp_win;
833 __be32 ack_seq_num;
834 } lro;
835 struct {
836 u8 reserved0:1;
837 u8 match:1;
838 u8 flush:1;
839 u8 reserved3:5;
840 u8 header_size;
841 __be16 header_entry_index;
842 __be32 data_offset;
843 } shampo;
844 };
845 __be32 rss_hash_result;
846 u8 rss_hash_type;
847 u8 ml_path;
848 u8 rsvd20[2];
849 __be16 check_sum;
850 __be16 slid;
851 __be32 flags_rqpn;
852 u8 hds_ip_ext;
853 u8 l4_l3_hdr_type;
854 __be16 vlan_info;
855 __be32 srqn; /* [31:24]: lro_num_seg, [23:0]: srqn */
856 union {
857 __be32 immediate;
858 __be32 inval_rkey;
859 __be32 pkey;
860 __be32 ft_metadata;
861 };
862 u8 rsvd40[4];
863 __be32 byte_cnt;
864 __be32 timestamp_h;
865 __be32 timestamp_l;
866 __be32 sop_drop_qpn;
867 __be16 wqe_counter;
868 union {
869 u8 signature;
870 u8 validity_iteration_count;
871 };
872 u8 op_own;
873};
874
875struct mlx5_mini_cqe8 {
876 union {
877 __be32 rx_hash_result;
878 struct {
879 __be16 checksum;
880 __be16 stridx;
881 };
882 struct {
883 __be16 wqe_counter;
884 u8 s_wqe_opcode;
885 u8 reserved;
886 } s_wqe_info;
887 };
888 __be32 byte_cnt;
889};
890
891enum {
892 MLX5_NO_INLINE_DATA,
893 MLX5_INLINE_DATA32_SEG,
894 MLX5_INLINE_DATA64_SEG,
895 MLX5_COMPRESSED,
896};
897
898enum {
899 MLX5_CQE_FORMAT_CSUM = 0x1,
900 MLX5_CQE_FORMAT_CSUM_STRIDX = 0x3,
901};
902
903enum {
904 MLX5_CQE_COMPRESS_LAYOUT_BASIC = 0,
905 MLX5_CQE_COMPRESS_LAYOUT_ENHANCED = 1,
906};
907
908#define MLX5_MINI_CQE_ARRAY_SIZE 8
909
910static inline u8 mlx5_get_cqe_format(struct mlx5_cqe64 *cqe)
911{
912 return (cqe->op_own >> 2) & 0x3;
913}
914
915static inline u8 get_cqe_opcode(struct mlx5_cqe64 *cqe)
916{
917 return cqe->op_own >> 4;
918}
919
920static inline u8 get_cqe_enhanced_num_mini_cqes(struct mlx5_cqe64 *cqe)
921{
922 /* num_of_mini_cqes is zero based */
923 return get_cqe_opcode(cqe) + 1;
924}
925
926static inline u8 get_cqe_lro_tcppsh(struct mlx5_cqe64 *cqe)
927{
928 return (cqe->lro.tcppsh_abort_dupack >> 6) & 1;
929}
930
931static inline u8 get_cqe_l4_hdr_type(struct mlx5_cqe64 *cqe)
932{
933 return (cqe->l4_l3_hdr_type >> 4) & 0x7;
934}
935
936static inline bool cqe_is_tunneled(struct mlx5_cqe64 *cqe)
937{
938 return cqe->tls_outer_l3_tunneled & 0x1;
939}
940
941static inline u8 get_cqe_tls_offload(struct mlx5_cqe64 *cqe)
942{
943 return (cqe->tls_outer_l3_tunneled >> 3) & 0x3;
944}
945
946static inline bool cqe_has_vlan(const struct mlx5_cqe64 *cqe)
947{
948 return cqe->l4_l3_hdr_type & 0x1;
949}
950
951static inline u64 get_cqe_ts(struct mlx5_cqe64 *cqe)
952{
953 u32 hi, lo;
954
955 hi = be32_to_cpu(cqe->timestamp_h);
956 lo = be32_to_cpu(cqe->timestamp_l);
957
958 return (u64)lo | ((u64)hi << 32);
959}
960
961static inline u16 get_cqe_flow_tag(struct mlx5_cqe64 *cqe)
962{
963 return be32_to_cpu(cqe->sop_drop_qpn) & 0xFFF;
964}
965
966static inline u8 get_cqe_lro_num_seg(struct mlx5_cqe64 *cqe)
967{
968 return be32_to_cpu(cqe->srqn) >> 24;
969}
970
971#define MLX5_MPWQE_LOG_NUM_STRIDES_EXT_BASE 3
972#define MLX5_MPWQE_LOG_NUM_STRIDES_BASE 9
973#define MLX5_MPWQE_LOG_NUM_STRIDES_MAX 16
974#define MLX5_MPWQE_LOG_STRIDE_SZ_BASE 6
975#define MLX5_MPWQE_LOG_STRIDE_SZ_MAX 13
976
977struct mpwrq_cqe_bc {
978 __be16 filler_consumed_strides;
979 __be16 byte_cnt;
980};
981
982static inline u16 mpwrq_get_cqe_byte_cnt(struct mlx5_cqe64 *cqe)
983{
984 struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt;
985
986 return be16_to_cpu(bc->byte_cnt);
987}
988
989static inline u16 mpwrq_get_cqe_bc_consumed_strides(struct mpwrq_cqe_bc *bc)
990{
991 return 0x7fff & be16_to_cpu(bc->filler_consumed_strides);
992}
993
994static inline u16 mpwrq_get_cqe_consumed_strides(struct mlx5_cqe64 *cqe)
995{
996 struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt;
997
998 return mpwrq_get_cqe_bc_consumed_strides(bc);
999}
1000
1001static inline bool mpwrq_is_filler_cqe(struct mlx5_cqe64 *cqe)
1002{
1003 struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt;
1004
1005 return 0x8000 & be16_to_cpu(bc->filler_consumed_strides);
1006}
1007
1008static inline u16 mpwrq_get_cqe_stride_index(struct mlx5_cqe64 *cqe)
1009{
1010 return be16_to_cpu(cqe->wqe_counter);
1011}
1012
1013enum {
1014 CQE_L4_HDR_TYPE_NONE = 0x0,
1015 CQE_L4_HDR_TYPE_TCP_NO_ACK = 0x1,
1016 CQE_L4_HDR_TYPE_UDP = 0x2,
1017 CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA = 0x3,
1018 CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA = 0x4,
1019};
1020
1021enum {
1022 CQE_RSS_HTYPE_IP = GENMASK(3, 2),
1023 /* cqe->rss_hash_type[3:2] - IP destination selected for hash
1024 * (00 = none, 01 = IPv4, 10 = IPv6, 11 = Reserved)
1025 */
1026 CQE_RSS_IP_NONE = 0x0,
1027 CQE_RSS_IPV4 = 0x1,
1028 CQE_RSS_IPV6 = 0x2,
1029 CQE_RSS_RESERVED = 0x3,
1030
1031 CQE_RSS_HTYPE_L4 = GENMASK(7, 6),
1032 /* cqe->rss_hash_type[7:6] - L4 destination selected for hash
1033 * (00 = none, 01 = TCP. 10 = UDP, 11 = IPSEC.SPI
1034 */
1035 CQE_RSS_L4_NONE = 0x0,
1036 CQE_RSS_L4_TCP = 0x1,
1037 CQE_RSS_L4_UDP = 0x2,
1038 CQE_RSS_L4_IPSEC = 0x3,
1039};
1040
1041enum {
1042 MLX5_CQE_ROCE_L3_HEADER_TYPE_GRH = 0x0,
1043 MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV6 = 0x1,
1044 MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV4 = 0x2,
1045};
1046
1047enum {
1048 CQE_L2_OK = 1 << 0,
1049 CQE_L3_OK = 1 << 1,
1050 CQE_L4_OK = 1 << 2,
1051};
1052
1053enum {
1054 CQE_TLS_OFFLOAD_NOT_DECRYPTED = 0x0,
1055 CQE_TLS_OFFLOAD_DECRYPTED = 0x1,
1056 CQE_TLS_OFFLOAD_RESYNC = 0x2,
1057 CQE_TLS_OFFLOAD_ERROR = 0x3,
1058};
1059
1060struct mlx5_sig_err_cqe {
1061 u8 rsvd0[16];
1062 __be32 expected_trans_sig;
1063 __be32 actual_trans_sig;
1064 __be32 expected_reftag;
1065 __be32 actual_reftag;
1066 __be16 syndrome;
1067 u8 rsvd22[2];
1068 __be32 mkey;
1069 __be64 err_offset;
1070 u8 rsvd30[8];
1071 __be32 qpn;
1072 u8 rsvd38[2];
1073 u8 signature;
1074 u8 op_own;
1075};
1076
1077struct mlx5_wqe_srq_next_seg {
1078 u8 rsvd0[2];
1079 __be16 next_wqe_index;
1080 u8 signature;
1081 u8 rsvd1[11];
1082};
1083
1084union mlx5_ext_cqe {
1085 struct ib_grh grh;
1086 u8 inl[64];
1087};
1088
1089struct mlx5_cqe128 {
1090 union mlx5_ext_cqe inl_grh;
1091 struct mlx5_cqe64 cqe64;
1092};
1093
1094enum {
1095 MLX5_MKEY_STATUS_FREE = 1 << 6,
1096};
1097
1098enum {
1099 MLX5_MKEY_REMOTE_INVAL = 1 << 24,
1100 MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29,
1101 MLX5_MKEY_BSF_EN = 1 << 30,
1102};
1103
1104struct mlx5_mkey_seg {
1105 /* This is a two bit field occupying bits 31-30.
1106 * bit 31 is always 0,
1107 * bit 30 is zero for regular MRs and 1 (e.g free) for UMRs that do not have translation
1108 */
1109 u8 status;
1110 u8 pcie_control;
1111 u8 flags;
1112 u8 version;
1113 __be32 qpn_mkey7_0;
1114 u8 rsvd1[4];
1115 __be32 flags_pd;
1116 __be64 start_addr;
1117 __be64 len;
1118 __be32 bsfs_octo_size;
1119 u8 rsvd2[16];
1120 __be32 xlt_oct_size;
1121 u8 rsvd3[3];
1122 u8 log2_page_size;
1123 u8 rsvd4[4];
1124};
1125
1126#define MLX5_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
1127
1128enum {
1129 MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO = 1 << 0
1130};
1131
1132enum {
1133 VPORT_STATE_DOWN = 0x0,
1134 VPORT_STATE_UP = 0x1,
1135};
1136
1137enum {
1138 MLX5_VPORT_ADMIN_STATE_DOWN = 0x0,
1139 MLX5_VPORT_ADMIN_STATE_UP = 0x1,
1140 MLX5_VPORT_ADMIN_STATE_AUTO = 0x2,
1141};
1142
1143enum {
1144 MLX5_VPORT_CVLAN_INSERT_WHEN_NO_CVLAN = 0x1,
1145 MLX5_VPORT_CVLAN_INSERT_ALWAYS = 0x3,
1146};
1147
1148enum {
1149 MLX5_L3_PROT_TYPE_IPV4 = 0,
1150 MLX5_L3_PROT_TYPE_IPV6 = 1,
1151};
1152
1153enum {
1154 MLX5_L4_PROT_TYPE_TCP = 0,
1155 MLX5_L4_PROT_TYPE_UDP = 1,
1156};
1157
1158enum {
1159 MLX5_HASH_FIELD_SEL_SRC_IP = 1 << 0,
1160 MLX5_HASH_FIELD_SEL_DST_IP = 1 << 1,
1161 MLX5_HASH_FIELD_SEL_L4_SPORT = 1 << 2,
1162 MLX5_HASH_FIELD_SEL_L4_DPORT = 1 << 3,
1163 MLX5_HASH_FIELD_SEL_IPSEC_SPI = 1 << 4,
1164};
1165
1166enum {
1167 MLX5_MATCH_OUTER_HEADERS = 1 << 0,
1168 MLX5_MATCH_MISC_PARAMETERS = 1 << 1,
1169 MLX5_MATCH_INNER_HEADERS = 1 << 2,
1170 MLX5_MATCH_MISC_PARAMETERS_2 = 1 << 3,
1171 MLX5_MATCH_MISC_PARAMETERS_3 = 1 << 4,
1172 MLX5_MATCH_MISC_PARAMETERS_4 = 1 << 5,
1173 MLX5_MATCH_MISC_PARAMETERS_5 = 1 << 6,
1174};
1175
1176enum {
1177 MLX5_FLOW_TABLE_TYPE_NIC_RCV = 0,
1178 MLX5_FLOW_TABLE_TYPE_ESWITCH = 4,
1179};
1180
1181enum {
1182 MLX5_FLOW_CONTEXT_DEST_TYPE_VPORT = 0,
1183 MLX5_FLOW_CONTEXT_DEST_TYPE_FLOW_TABLE = 1,
1184 MLX5_FLOW_CONTEXT_DEST_TYPE_TIR = 2,
1185};
1186
1187enum mlx5_list_type {
1188 MLX5_NVPRT_LIST_TYPE_UC = 0x0,
1189 MLX5_NVPRT_LIST_TYPE_MC = 0x1,
1190 MLX5_NVPRT_LIST_TYPE_VLAN = 0x2,
1191};
1192
1193enum {
1194 MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
1195 MLX5_RQC_RQ_TYPE_MEMORY_RQ_RPM = 0x1,
1196};
1197
1198enum mlx5_wol_mode {
1199 MLX5_WOL_DISABLE = 0,
1200 MLX5_WOL_SECURED_MAGIC = 1 << 1,
1201 MLX5_WOL_MAGIC = 1 << 2,
1202 MLX5_WOL_ARP = 1 << 3,
1203 MLX5_WOL_BROADCAST = 1 << 4,
1204 MLX5_WOL_MULTICAST = 1 << 5,
1205 MLX5_WOL_UNICAST = 1 << 6,
1206 MLX5_WOL_PHY_ACTIVITY = 1 << 7,
1207};
1208
1209enum mlx5_mpls_supported_fields {
1210 MLX5_FIELD_SUPPORT_MPLS_LABEL = 1 << 0,
1211 MLX5_FIELD_SUPPORT_MPLS_EXP = 1 << 1,
1212 MLX5_FIELD_SUPPORT_MPLS_S_BOS = 1 << 2,
1213 MLX5_FIELD_SUPPORT_MPLS_TTL = 1 << 3
1214};
1215
1216enum mlx5_flex_parser_protos {
1217 MLX5_FLEX_PROTO_GENEVE = 1 << 3,
1218 MLX5_FLEX_PROTO_CW_MPLS_GRE = 1 << 4,
1219 MLX5_FLEX_PROTO_CW_MPLS_UDP = 1 << 5,
1220 MLX5_FLEX_PROTO_ICMP = 1 << 8,
1221 MLX5_FLEX_PROTO_ICMPV6 = 1 << 9,
1222};
1223
1224/* MLX5 DEV CAPs */
1225
1226/* TODO: EAT.ME */
1227enum mlx5_cap_mode {
1228 HCA_CAP_OPMOD_GET_MAX = 0,
1229 HCA_CAP_OPMOD_GET_CUR = 1,
1230};
1231
1232/* Any new cap addition must update mlx5_hca_caps_alloc() to allocate
1233 * capability memory.
1234 */
1235enum mlx5_cap_type {
1236 MLX5_CAP_GENERAL = 0,
1237 MLX5_CAP_ETHERNET_OFFLOADS,
1238 MLX5_CAP_ODP,
1239 MLX5_CAP_ATOMIC,
1240 MLX5_CAP_ROCE,
1241 MLX5_CAP_IPOIB_OFFLOADS,
1242 MLX5_CAP_IPOIB_ENHANCED_OFFLOADS,
1243 MLX5_CAP_FLOW_TABLE,
1244 MLX5_CAP_ESWITCH_FLOW_TABLE,
1245 MLX5_CAP_ESWITCH,
1246 MLX5_CAP_QOS = 0xc,
1247 MLX5_CAP_DEBUG,
1248 MLX5_CAP_RESERVED_14,
1249 MLX5_CAP_DEV_MEM,
1250 MLX5_CAP_RESERVED_16,
1251 MLX5_CAP_TLS,
1252 MLX5_CAP_VDPA_EMULATION = 0x13,
1253 MLX5_CAP_DEV_EVENT = 0x14,
1254 MLX5_CAP_IPSEC,
1255 MLX5_CAP_CRYPTO = 0x1a,
1256 MLX5_CAP_SHAMPO = 0x1d,
1257 MLX5_CAP_PSP = 0x1e,
1258 MLX5_CAP_MACSEC = 0x1f,
1259 MLX5_CAP_GENERAL_2 = 0x20,
1260 MLX5_CAP_PORT_SELECTION = 0x25,
1261 MLX5_CAP_ADV_VIRTUALIZATION = 0x26,
1262 MLX5_CAP_ADV_RDMA = 0x28,
1263 MLX5_CAP_TLP_EMULATION = 0x2a,
1264 /* NUM OF CAP Types */
1265 MLX5_CAP_NUM
1266};
1267
1268enum mlx5_pcam_reg_groups {
1269 MLX5_PCAM_REGS_5000_TO_507F = 0x0,
1270};
1271
1272enum mlx5_pcam_feature_groups {
1273 MLX5_PCAM_FEATURE_ENHANCED_FEATURES = 0x0,
1274};
1275
1276enum mlx5_mcam_reg_groups {
1277 MLX5_MCAM_REGS_FIRST_128 = 0x0,
1278 MLX5_MCAM_REGS_0x9100_0x917F = 0x2,
1279 MLX5_MCAM_REGS_0x9180_0x91FF = 0x3,
1280 MLX5_MCAM_REGS_NUM = 0x4,
1281};
1282
1283enum mlx5_mcam_feature_groups {
1284 MLX5_MCAM_FEATURE_ENHANCED_FEATURES = 0x0,
1285};
1286
1287enum mlx5_qcam_reg_groups {
1288 MLX5_QCAM_REGS_FIRST_128 = 0x0,
1289};
1290
1291enum mlx5_qcam_feature_groups {
1292 MLX5_QCAM_FEATURE_ENHANCED_FEATURES = 0x0,
1293};
1294
1295/* GET Dev Caps macros */
1296#define MLX5_CAP_GEN(mdev, cap) \
1297 MLX5_GET(cmd_hca_cap, mdev->caps.hca[MLX5_CAP_GENERAL]->cur, cap)
1298
1299#define MLX5_CAP_GEN_64(mdev, cap) \
1300 MLX5_GET64(cmd_hca_cap, mdev->caps.hca[MLX5_CAP_GENERAL]->cur, cap)
1301
1302#define MLX5_CAP_GEN_MAX(mdev, cap) \
1303 MLX5_GET(cmd_hca_cap, mdev->caps.hca[MLX5_CAP_GENERAL]->max, cap)
1304
1305#define MLX5_CAP_GEN_2(mdev, cap) \
1306 MLX5_GET(cmd_hca_cap_2, mdev->caps.hca[MLX5_CAP_GENERAL_2]->cur, cap)
1307
1308#define MLX5_CAP_GEN_2_64(mdev, cap) \
1309 MLX5_GET64(cmd_hca_cap_2, mdev->caps.hca[MLX5_CAP_GENERAL_2]->cur, cap)
1310
1311#define MLX5_CAP_GEN_2_MAX(mdev, cap) \
1312 MLX5_GET(cmd_hca_cap_2, mdev->caps.hca[MLX5_CAP_GENERAL_2]->max, cap)
1313
1314#define MLX5_CAP_ETH(mdev, cap) \
1315 MLX5_GET(per_protocol_networking_offload_caps,\
1316 mdev->caps.hca[MLX5_CAP_ETHERNET_OFFLOADS]->cur, cap)
1317
1318#define MLX5_CAP_IPOIB_ENHANCED(mdev, cap) \
1319 MLX5_GET(per_protocol_networking_offload_caps,\
1320 mdev->caps.hca[MLX5_CAP_IPOIB_ENHANCED_OFFLOADS]->cur, cap)
1321
1322#define MLX5_CAP_ROCE(mdev, cap) \
1323 MLX5_GET(roce_cap, mdev->caps.hca[MLX5_CAP_ROCE]->cur, cap)
1324
1325#define MLX5_CAP_ROCE_MAX(mdev, cap) \
1326 MLX5_GET(roce_cap, mdev->caps.hca[MLX5_CAP_ROCE]->max, cap)
1327
1328#define MLX5_CAP_ATOMIC(mdev, cap) \
1329 MLX5_GET(atomic_caps, mdev->caps.hca[MLX5_CAP_ATOMIC]->cur, cap)
1330
1331#define MLX5_CAP_ATOMIC_MAX(mdev, cap) \
1332 MLX5_GET(atomic_caps, mdev->caps.hca[MLX5_CAP_ATOMIC]->max, cap)
1333
1334#define MLX5_CAP_FLOWTABLE(mdev, cap) \
1335 MLX5_GET(flow_table_nic_cap, mdev->caps.hca[MLX5_CAP_FLOW_TABLE]->cur, cap)
1336
1337#define MLX5_CAP64_FLOWTABLE(mdev, cap) \
1338 MLX5_GET64(flow_table_nic_cap, (mdev)->caps.hca[MLX5_CAP_FLOW_TABLE]->cur, cap)
1339
1340#define MLX5_CAP_FLOWTABLE_NIC_RX(mdev, cap) \
1341 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.cap)
1342
1343#define MLX5_CAP_FLOWTABLE_NIC_TX(mdev, cap) \
1344 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit.cap)
1345
1346#define MLX5_CAP_FLOWTABLE_SNIFFER_RX(mdev, cap) \
1347 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive_sniffer.cap)
1348
1349#define MLX5_CAP_FLOWTABLE_SNIFFER_TX(mdev, cap) \
1350 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit_sniffer.cap)
1351
1352#define MLX5_CAP_FLOWTABLE_RDMA_RX(mdev, cap) \
1353 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive_rdma.cap)
1354
1355#define MLX5_CAP_FLOWTABLE_RDMA_TX(mdev, cap) \
1356 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit_rdma.cap)
1357
1358#define MLX5_CAP_FLOWTABLE_RDMA_TRANSPORT_RX(mdev, cap) \
1359 MLX5_CAP_ADV_RDMA(mdev, rdma_transport_rx_flow_table_properties.cap)
1360
1361#define MLX5_CAP_FLOWTABLE_RDMA_TRANSPORT_TX(mdev, cap) \
1362 MLX5_CAP_ADV_RDMA(mdev, rdma_transport_tx_flow_table_properties.cap)
1363
1364#define MLX5_CAP_ESW_FLOWTABLE(mdev, cap) \
1365 MLX5_GET(flow_table_eswitch_cap, \
1366 mdev->caps.hca[MLX5_CAP_ESWITCH_FLOW_TABLE]->cur, cap)
1367
1368#define MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, cap) \
1369 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_nic_esw_fdb.cap)
1370
1371#define MLX5_CAP_ESW_EGRESS_ACL(mdev, cap) \
1372 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_egress.cap)
1373
1374#define MLX5_CAP_ESW_INGRESS_ACL(mdev, cap) \
1375 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_ingress.cap)
1376
1377#define MLX5_CAP_ESW_FT_FIELD_SUPPORT_2(mdev, cap) \
1378 MLX5_CAP_ESW_FLOWTABLE(mdev, ft_field_support_2_esw_fdb.cap)
1379
1380#define MLX5_CAP_NIC_RX_FT_FIELD_SUPPORT_2(mdev, cap) \
1381 MLX5_CAP_FLOWTABLE(mdev, ft_field_support_2_nic_receive.cap)
1382
1383#define MLX5_CAP_ESW(mdev, cap) \
1384 MLX5_GET(e_switch_cap, \
1385 mdev->caps.hca[MLX5_CAP_ESWITCH]->cur, cap)
1386
1387#define MLX5_CAP64_ESW_FLOWTABLE(mdev, cap) \
1388 MLX5_GET64(flow_table_eswitch_cap, \
1389 (mdev)->caps.hca[MLX5_CAP_ESWITCH_FLOW_TABLE]->cur, cap)
1390
1391#define MLX5_CAP_PORT_SELECTION(mdev, cap) \
1392 MLX5_GET(port_selection_cap, \
1393 mdev->caps.hca[MLX5_CAP_PORT_SELECTION]->cur, cap)
1394
1395#define MLX5_CAP_PORT_SELECTION_MAX(mdev, cap) \
1396 MLX5_GET(port_selection_cap, \
1397 mdev->caps.hca[MLX5_CAP_PORT_SELECTION]->max, cap)
1398
1399#define MLX5_CAP_ADV_VIRTUALIZATION(mdev, cap) \
1400 MLX5_GET(adv_virtualization_cap, \
1401 mdev->caps.hca[MLX5_CAP_ADV_VIRTUALIZATION]->cur, cap)
1402
1403#define MLX5_CAP_ADV_RDMA(mdev, cap) \
1404 MLX5_GET(adv_rdma_cap, \
1405 mdev->caps.hca[MLX5_CAP_ADV_RDMA]->cur, cap)
1406
1407#define MLX5_CAP_FLOWTABLE_PORT_SELECTION(mdev, cap) \
1408 MLX5_CAP_PORT_SELECTION(mdev, flow_table_properties_port_selection.cap)
1409
1410#define MLX5_CAP_PORT_SELECTION_FT_FIELD_SUPPORT_2(mdev, cap) \
1411 MLX5_CAP_PORT_SELECTION(mdev, ft_field_support_2_port_selection.cap)
1412
1413#define MLX5_CAP_ODP(mdev, cap)\
1414 MLX5_GET(odp_cap, mdev->caps.hca[MLX5_CAP_ODP]->cur, cap)
1415
1416#define MLX5_CAP_ODP_SCHEME(mdev, cap) \
1417 (MLX5_GET(odp_cap, mdev->caps.hca[MLX5_CAP_ODP]->cur, \
1418 mem_page_fault) ? \
1419 MLX5_GET(odp_cap, mdev->caps.hca[MLX5_CAP_ODP]->cur, \
1420 memory_page_fault_scheme_cap.cap) : \
1421 MLX5_GET(odp_cap, mdev->caps.hca[MLX5_CAP_ODP]->cur, \
1422 transport_page_fault_scheme_cap.cap))
1423
1424#define MLX5_CAP_ODP_MAX(mdev, cap)\
1425 MLX5_GET(odp_cap, mdev->caps.hca[MLX5_CAP_ODP]->max, cap)
1426
1427#define MLX5_CAP_QOS(mdev, cap)\
1428 MLX5_GET(qos_cap, mdev->caps.hca[MLX5_CAP_QOS]->cur, cap)
1429
1430#define MLX5_CAP_DEBUG(mdev, cap)\
1431 MLX5_GET(debug_cap, mdev->caps.hca[MLX5_CAP_DEBUG]->cur, cap)
1432
1433#define MLX5_CAP_PCAM_FEATURE(mdev, fld) \
1434 MLX5_GET(pcam_reg, (mdev)->caps.pcam, feature_cap_mask.enhanced_features.fld)
1435
1436#define MLX5_CAP_PCAM_REG(mdev, reg) \
1437 MLX5_GET(pcam_reg, (mdev)->caps.pcam, port_access_reg_cap_mask.regs_5000_to_507f.reg)
1438
1439#define MLX5_CAP_MCAM_REG(mdev, reg) \
1440 MLX5_GET(mcam_reg, (mdev)->caps.mcam[MLX5_MCAM_REGS_FIRST_128], \
1441 mng_access_reg_cap_mask.access_regs.reg)
1442
1443#define MLX5_CAP_MCAM_REG2(mdev, reg) \
1444 MLX5_GET(mcam_reg, (mdev)->caps.mcam[MLX5_MCAM_REGS_0x9100_0x917F], \
1445 mng_access_reg_cap_mask.access_regs2.reg)
1446
1447#define MLX5_CAP_MCAM_REG3(mdev, reg) \
1448 MLX5_GET(mcam_reg, (mdev)->caps.mcam[MLX5_MCAM_REGS_0x9180_0x91FF], \
1449 mng_access_reg_cap_mask.access_regs3.reg)
1450
1451#define MLX5_CAP_MCAM_FEATURE(mdev, fld) \
1452 MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_feature_cap_mask.enhanced_features.fld)
1453
1454#define MLX5_CAP_QCAM_REG(mdev, fld) \
1455 MLX5_GET(qcam_reg, (mdev)->caps.qcam, qos_access_reg_cap_mask.reg_cap.fld)
1456
1457#define MLX5_CAP_QCAM_FEATURE(mdev, fld) \
1458 MLX5_GET(qcam_reg, (mdev)->caps.qcam, qos_feature_cap_mask.feature_cap.fld)
1459
1460#define MLX5_CAP_FPGA(mdev, cap) \
1461 MLX5_GET(fpga_cap, (mdev)->caps.fpga, cap)
1462
1463#define MLX5_CAP64_FPGA(mdev, cap) \
1464 MLX5_GET64(fpga_cap, (mdev)->caps.fpga, cap)
1465
1466#define MLX5_CAP_DEV_MEM(mdev, cap)\
1467 MLX5_GET(device_mem_cap, mdev->caps.hca[MLX5_CAP_DEV_MEM]->cur, cap)
1468
1469#define MLX5_CAP64_DEV_MEM(mdev, cap)\
1470 MLX5_GET64(device_mem_cap, mdev->caps.hca[MLX5_CAP_DEV_MEM]->cur, cap)
1471
1472#define MLX5_CAP_TLS(mdev, cap) \
1473 MLX5_GET(tls_cap, (mdev)->caps.hca[MLX5_CAP_TLS]->cur, cap)
1474
1475#define MLX5_CAP_DEV_EVENT(mdev, cap)\
1476 MLX5_ADDR_OF(device_event_cap, (mdev)->caps.hca[MLX5_CAP_DEV_EVENT]->cur, cap)
1477
1478#define MLX5_CAP_DEV_VDPA_EMULATION(mdev, cap)\
1479 MLX5_GET(virtio_emulation_cap, \
1480 (mdev)->caps.hca[MLX5_CAP_VDPA_EMULATION]->cur, cap)
1481
1482#define MLX5_CAP64_DEV_VDPA_EMULATION(mdev, cap)\
1483 MLX5_GET64(virtio_emulation_cap, \
1484 (mdev)->caps.hca[MLX5_CAP_VDPA_EMULATION]->cur, cap)
1485
1486#define MLX5_CAP_DEV_TLP_EMULATION(mdev, cap)\
1487 MLX5_GET(tlp_dev_emu_capabilities, \
1488 (mdev)->caps.hca[MLX5_CAP_TLP_EMULATION]->cur, cap)
1489
1490#define MLX5_CAP64_DEV_TLP_EMULATION(mdev, cap)\
1491 MLX5_GET64(tlp_dev_emu_capabilities, \
1492 (mdev)->caps.hca[MLX5_CAP_TLP_EMULATION]->cur, cap)
1493
1494#define MLX5_CAP_IPSEC(mdev, cap)\
1495 MLX5_GET(ipsec_cap, (mdev)->caps.hca[MLX5_CAP_IPSEC]->cur, cap)
1496
1497#define MLX5_CAP_CRYPTO(mdev, cap)\
1498 MLX5_GET(crypto_cap, (mdev)->caps.hca[MLX5_CAP_CRYPTO]->cur, cap)
1499
1500#define MLX5_CAP_MACSEC(mdev, cap)\
1501 MLX5_GET(macsec_cap, (mdev)->caps.hca[MLX5_CAP_MACSEC]->cur, cap)
1502
1503#define MLX5_CAP_SHAMPO(mdev, cap) \
1504 MLX5_GET(shampo_cap, mdev->caps.hca[MLX5_CAP_SHAMPO]->cur, cap)
1505
1506#define MLX5_CAP_PSP(mdev, cap)\
1507 MLX5_GET(psp_cap, (mdev)->caps.hca[MLX5_CAP_PSP]->cur, cap)
1508
1509enum {
1510 MLX5_CMD_STAT_OK = 0x0,
1511 MLX5_CMD_STAT_INT_ERR = 0x1,
1512 MLX5_CMD_STAT_BAD_OP_ERR = 0x2,
1513 MLX5_CMD_STAT_BAD_PARAM_ERR = 0x3,
1514 MLX5_CMD_STAT_BAD_SYS_STATE_ERR = 0x4,
1515 MLX5_CMD_STAT_BAD_RES_ERR = 0x5,
1516 MLX5_CMD_STAT_RES_BUSY = 0x6,
1517 MLX5_CMD_STAT_NOT_READY = 0x7,
1518 MLX5_CMD_STAT_LIM_ERR = 0x8,
1519 MLX5_CMD_STAT_BAD_RES_STATE_ERR = 0x9,
1520 MLX5_CMD_STAT_IX_ERR = 0xa,
1521 MLX5_CMD_STAT_NO_RES_ERR = 0xf,
1522 MLX5_CMD_STAT_BAD_INP_LEN_ERR = 0x50,
1523 MLX5_CMD_STAT_BAD_OUTP_LEN_ERR = 0x51,
1524 MLX5_CMD_STAT_BAD_QP_STATE_ERR = 0x10,
1525 MLX5_CMD_STAT_BAD_PKT_ERR = 0x30,
1526 MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR = 0x40,
1527};
1528
1529enum {
1530 MLX5_IEEE_802_3_COUNTERS_GROUP = 0x0,
1531 MLX5_RFC_2863_COUNTERS_GROUP = 0x1,
1532 MLX5_RFC_2819_COUNTERS_GROUP = 0x2,
1533 MLX5_RFC_3635_COUNTERS_GROUP = 0x3,
1534 MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP = 0x5,
1535 MLX5_PER_PRIORITY_COUNTERS_GROUP = 0x10,
1536 MLX5_PER_TRAFFIC_CLASS_COUNTERS_GROUP = 0x11,
1537 MLX5_PHYSICAL_LAYER_COUNTERS_GROUP = 0x12,
1538 MLX5_PER_TRAFFIC_CLASS_CONGESTION_GROUP = 0x13,
1539 MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP = 0x16,
1540 MLX5_PHYSICAL_LAYER_RECOVERY_GROUP = 0x1a,
1541 MLX5_INFINIBAND_PORT_COUNTERS_GROUP = 0x20,
1542 MLX5_INFINIBAND_EXTENDED_PORT_COUNTERS_GROUP = 0x21,
1543 MLX5_RS_FEC_HISTOGRAM_GROUP = 0x23,
1544};
1545
1546enum {
1547 MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP = 0x0,
1548};
1549
1550static inline u16 mlx5_to_sw_pkey_sz(int pkey_sz)
1551{
1552 if (pkey_sz > MLX5_MAX_LOG_PKEY_TABLE)
1553 return 0;
1554 return MLX5_MIN_PKEY_TABLE_SIZE << pkey_sz;
1555}
1556
1557#define MLX5_RDMA_RX_NUM_COUNTERS_PRIOS 6
1558#define MLX5_RDMA_TX_NUM_COUNTERS_PRIOS 4
1559#define MLX5_BY_PASS_NUM_REGULAR_PRIOS 16
1560#define MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS 16
1561#define MLX5_BY_PASS_NUM_MULTICAST_PRIOS 1
1562#define MLX5_BY_PASS_NUM_PRIOS (MLX5_BY_PASS_NUM_REGULAR_PRIOS +\
1563 MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS +\
1564 MLX5_BY_PASS_NUM_MULTICAST_PRIOS)
1565
1566#endif /* MLX5_DEVICE_H */