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1/* SPDX-License-Identifier: GPL-2.0-only */
2/*******************************************************************************
3
4 Header file for stmmac platform data
5
6 Copyright (C) 2009 STMicroelectronics Ltd
7
8
9 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
10*******************************************************************************/
11
12#ifndef __STMMAC_PLATFORM_DATA
13#define __STMMAC_PLATFORM_DATA
14
15#include <linux/platform_device.h>
16#include <linux/phylink.h>
17
18#define MTL_MAX_RX_QUEUES 8
19#define MTL_MAX_TX_QUEUES 8
20#define STMMAC_CH_MAX 8
21
22#define STMMAC_RX_COE_NONE 0
23#define STMMAC_RX_COE_TYPE1 1
24#define STMMAC_RX_COE_TYPE2 2
25
26/* Define the macros for CSR clock range parameters to be passed by
27 * platform code.
28 * This could also be configured at run time using CPU freq framework. */
29
30/* MDC Clock Selection define*/
31#define STMMAC_CSR_60_100M 0x0 /* MDC = clk_csr_i/42 */
32#define STMMAC_CSR_100_150M 0x1 /* MDC = clk_csr_i/62 */
33#define STMMAC_CSR_20_35M 0x2 /* MDC = clk_csr_i/16 */
34#define STMMAC_CSR_35_60M 0x3 /* MDC = clk_csr_i/26 */
35#define STMMAC_CSR_150_250M 0x4 /* MDC = clk_csr_i/102 */
36#define STMMAC_CSR_250_300M 0x5 /* MDC = clk_csr_i/124 */
37#define STMMAC_CSR_300_500M 0x6 /* MDC = clk_csr_i/204 */
38#define STMMAC_CSR_500_800M 0x7 /* MDC = clk_csr_i/324 */
39
40/* MTL algorithms identifiers */
41#define MTL_TX_ALGORITHM_WRR 0x0
42#define MTL_TX_ALGORITHM_WFQ 0x1
43#define MTL_TX_ALGORITHM_DWRR 0x2
44#define MTL_TX_ALGORITHM_SP 0x3
45#define MTL_RX_ALGORITHM_SP 0x4
46#define MTL_RX_ALGORITHM_WSP 0x5
47
48/* RX/TX Queue Mode */
49#define MTL_QUEUE_AVB 0x0
50#define MTL_QUEUE_DCB 0x1
51
52/* The MDC clock could be set higher than the IEEE 802.3
53 * specified frequency limit 0f 2.5 MHz, by programming a clock divider
54 * of value different than the above defined values. The resultant MDIO
55 * clock frequency of 12.5 MHz is applicable for the interfacing chips
56 * supporting higher MDC clocks.
57 * The MDC clock selection macros need to be defined for MDC clock rate
58 * of 12.5 MHz, corresponding to the following selection.
59 */
60#define STMMAC_CSR_I_4 0x8 /* clk_csr_i/4 */
61#define STMMAC_CSR_I_6 0x9 /* clk_csr_i/6 */
62#define STMMAC_CSR_I_8 0xA /* clk_csr_i/8 */
63#define STMMAC_CSR_I_10 0xB /* clk_csr_i/10 */
64#define STMMAC_CSR_I_12 0xC /* clk_csr_i/12 */
65#define STMMAC_CSR_I_14 0xD /* clk_csr_i/14 */
66#define STMMAC_CSR_I_16 0xE /* clk_csr_i/16 */
67#define STMMAC_CSR_I_18 0xF /* clk_csr_i/18 */
68
69/* AXI DMA Burst length supported */
70#define DMA_AXI_BLEN_4 (1 << 1)
71#define DMA_AXI_BLEN_8 (1 << 2)
72#define DMA_AXI_BLEN_16 (1 << 3)
73#define DMA_AXI_BLEN_32 (1 << 4)
74#define DMA_AXI_BLEN_64 (1 << 5)
75#define DMA_AXI_BLEN_128 (1 << 6)
76#define DMA_AXI_BLEN_256 (1 << 7)
77#define DMA_AXI_BLEN_ALL (DMA_AXI_BLEN_4 | DMA_AXI_BLEN_8 | DMA_AXI_BLEN_16 \
78 | DMA_AXI_BLEN_32 | DMA_AXI_BLEN_64 \
79 | DMA_AXI_BLEN_128 | DMA_AXI_BLEN_256)
80
81struct clk;
82struct stmmac_priv;
83
84/* Platfrom data for platform device structure's platform_data field */
85
86struct stmmac_mdio_bus_data {
87 u32 phy_mask;
88 u32 pcs_mask;
89 int *irqs;
90 int probed_phy_irq;
91 bool needs_reset;
92};
93
94struct stmmac_dma_cfg {
95 /* pbl: programmable burst limit
96 * txpbl: transmit programmable burst limit
97 * rxpbl: receive programmable burst limit
98 * If txpbl or rxpbl are zero, the value of pbl will be substituted.
99 * Range 0 - 63.
100 */
101 int pbl;
102 int txpbl;
103 int rxpbl;
104 /* pblx8: multiplies pbl, txpbl, rxpbl by a factor of 8 for dwmac >=
105 * 3.50a, or a factor of 4 for previous versions.
106 */
107 bool pblx8;
108 /* fixed_burst:
109 * when set, AXI bursts defined by axi_blen_regval are permitted.
110 * AHB uses SINGLE, INCR4, INCR8 or INCR16 during burst transfers.
111 * when clear, AXI and AHB use SINGLE or INCR bursts.
112 */
113 bool fixed_burst;
114 /* mixed_burst:
115 * when set and fixed_burst is clear, AHB uses INCR for bursts > 16
116 * and SINGLE or INCRx for bursts <= 16.
117 */
118 bool mixed_burst;
119 /* aal: address aligned bursts for AHB and AXI master interface */
120 bool aal;
121 bool dche;
122 bool eame;
123 /* multi_msi_en: stmmac core internal */
124 bool multi_msi_en;
125 /* atds: stmmac core internal */
126 bool atds;
127};
128
129#define AXI_BLEN 7
130struct stmmac_axi {
131 u32 axi_wr_osr_lmt;
132 u32 axi_rd_osr_lmt;
133 u32 axi_blen_regval;
134 bool axi_lpi_en;
135 bool axi_xit_frm;
136 bool axi_fb;
137};
138
139struct stmmac_rxq_cfg {
140 u32 chan;
141 u32 prio;
142 u8 mode_to_use;
143 u8 pkt_route;
144 bool use_prio;
145};
146
147struct stmmac_txq_cfg {
148 u32 weight;
149 /* Credit Base Shaper parameters */
150 u32 send_slope;
151 u32 idle_slope;
152 u32 high_credit;
153 u32 low_credit;
154 u32 prio;
155 int tbs_en;
156 bool use_prio;
157 bool coe_unsupported;
158 u8 mode_to_use;
159};
160
161struct stmmac_safety_feature_cfg {
162 u32 tsoee;
163 u32 mrxpee;
164 u32 mestee;
165 u32 mrxee;
166 u32 mtxee;
167 u32 epsi;
168 u32 edpp;
169 u32 prtyen;
170 u32 tmouten;
171};
172
173/* Addresses that may be customized by a platform */
174struct dwmac4_addrs {
175 u32 dma_chan;
176 u32 dma_chan_offset;
177 u32 mtl_chan;
178 u32 mtl_chan_offset;
179 u32 mtl_ets_ctrl;
180 u32 mtl_ets_ctrl_offset;
181 u32 mtl_txq_weight;
182 u32 mtl_txq_weight_offset;
183 u32 mtl_send_slp_cred;
184 u32 mtl_send_slp_cred_offset;
185 u32 mtl_high_cred;
186 u32 mtl_high_cred_offset;
187 u32 mtl_low_cred;
188 u32 mtl_low_cred_offset;
189};
190
191enum dwmac_core_type {
192 DWMAC_CORE_MAC100,
193 DWMAC_CORE_GMAC,
194 DWMAC_CORE_GMAC4,
195 DWMAC_CORE_XGMAC,
196};
197
198#define STMMAC_FLAG_SPH_DISABLE BIT(1)
199#define STMMAC_FLAG_USE_PHY_WOL BIT(2)
200#define STMMAC_FLAG_HAS_SUN8I BIT(3)
201#define STMMAC_FLAG_TSO_EN BIT(4)
202#define STMMAC_FLAG_SERDES_UP_AFTER_PHY_LINKUP BIT(5)
203#define STMMAC_FLAG_VLAN_FAIL_Q_EN BIT(6)
204#define STMMAC_FLAG_MULTI_MSI_EN BIT(7)
205#define STMMAC_FLAG_EXT_SNAPSHOT_EN BIT(8)
206#define STMMAC_FLAG_INT_SNAPSHOT_EN BIT(9)
207#define STMMAC_FLAG_EEE_DISABLE BIT(10)
208#define STMMAC_FLAG_RX_CLK_RUNS_IN_LPI BIT(11)
209#define STMMAC_FLAG_EN_TX_LPI_CLOCKGATING BIT(12)
210#define STMMAC_FLAG_EN_TX_LPI_CLK_PHY_CAP BIT(13)
211#define STMMAC_FLAG_HWTSTAMP_CORRECT_LATENCY BIT(14)
212#define STMMAC_FLAG_KEEP_PREAMBLE_BEFORE_SFD BIT(15)
213#define STMMAC_FLAG_SERDES_SUPPORTS_2500M BIT(16)
214
215struct mac_device_info;
216
217struct plat_stmmacenet_data {
218 enum dwmac_core_type core_type;
219 int bus_id;
220 int phy_addr;
221 /* MAC ----- optional PCS ----- SerDes ----- optional PHY ----- Media
222 * ^
223 * phy_interface
224 *
225 * The Synopsys dwmac core only covers the MAC and an optional
226 * integrated PCS. Where the integrated PCS is used with a SerDes,
227 * e.g. for 1000base-X or Cisco SGMII, the connection between the
228 * PCS and SerDes will be TBI.
229 *
230 * Where the Synopsys dwmac core has been instantiated with multiple
231 * interface modes, these are selected via core-external configuration
232 * which is sampled when the dwmac core is reset. How this is done is
233 * platform glue specific, but this defines the interface used from
234 * the Synopsys dwmac core to the rest of the SoC.
235 *
236 * Where PCS other than the optional integrated Synopsys dwmac PCS
237 * is used, this counts as "the rest of the SoC" in the above
238 * paragraph.
239 *
240 * phy_interface is the PHY-side interface - the interface used by
241 * an attached PHY or SFP etc. This is equivalent to the interface
242 * that phylink uses.
243 */
244 phy_interface_t phy_interface;
245 struct stmmac_mdio_bus_data *mdio_bus_data;
246 struct device_node *phy_node;
247 struct device_node *mdio_node;
248 struct stmmac_dma_cfg *dma_cfg;
249 struct stmmac_safety_feature_cfg *safety_feat_cfg;
250 int clk_csr;
251 bool default_an_inband;
252 bool enh_desc;
253 bool tx_coe;
254 bool bugged_jumbo;
255 bool pmt;
256 bool force_sf_dma_mode;
257 bool force_thresh_dma_mode;
258 bool riwt_off;
259 int rx_coe;
260 int max_speed;
261 int maxmtu;
262 int multicast_filter_bins;
263 int unicast_filter_entries;
264 int tx_fifo_size;
265 int rx_fifo_size;
266 u8 host_dma_width;
267 u8 rx_queues_to_use;
268 u8 tx_queues_to_use;
269 u8 rx_sched_algorithm;
270 u8 tx_sched_algorithm;
271 struct stmmac_rxq_cfg rx_queues_cfg[MTL_MAX_RX_QUEUES];
272 struct stmmac_txq_cfg tx_queues_cfg[MTL_MAX_TX_QUEUES];
273 void (*get_interfaces)(struct stmmac_priv *priv, void *bsp_priv,
274 unsigned long *interfaces);
275 int (*set_phy_intf_sel)(void *priv, u8 phy_intf_sel);
276 int (*set_clk_tx_rate)(void *priv, struct clk *clk_tx_i,
277 phy_interface_t interface, int speed);
278 void (*fix_mac_speed)(void *priv, phy_interface_t interface,
279 int speed, unsigned int mode);
280 int (*fix_soc_reset)(struct stmmac_priv *priv);
281 int (*serdes_powerup)(struct net_device *ndev, void *priv);
282 void (*serdes_powerdown)(struct net_device *ndev, void *priv);
283 int (*mac_finish)(struct net_device *ndev,
284 void *priv,
285 unsigned int mode,
286 phy_interface_t interface);
287 void (*ptp_clk_freq_config)(struct stmmac_priv *priv);
288 int (*init)(struct device *dev, void *priv);
289 void (*exit)(struct device *dev, void *priv);
290 int (*suspend)(struct device *dev, void *priv);
291 int (*resume)(struct device *dev, void *priv);
292 int (*mac_setup)(void *priv, struct mac_device_info *mac);
293 int (*clks_config)(void *priv, bool enabled);
294 int (*crosststamp)(ktime_t *device, struct system_counterval_t *system,
295 void *ctx);
296 void (*dump_debug_regs)(void *priv);
297 int (*pcs_init)(struct stmmac_priv *priv);
298 void (*pcs_exit)(struct stmmac_priv *priv);
299 struct phylink_pcs *(*select_pcs)(struct stmmac_priv *priv,
300 phy_interface_t interface);
301 void *bsp_priv;
302
303 /* stmmac clocks:
304 * stmmac_clk: CSR clock (which can be hclk_i, clk_csr_i, aclk_i,
305 * or clk_app_i depending on GMAC configuration). This clock
306 * generates the MDC clock.
307 *
308 * pclk: introduced for Imagination Technologies Pistachio board -
309 * see 5f9755d26fbf ("stmmac: Add an optional register interface
310 * clock"). This is probably used for cases where separate clocks
311 * are provided for the host interface and register interface. In
312 * this case, as the MDC clock is derived from stmmac_clk, pclk
313 * can only really be the "application clock" for the "host
314 * interface" and not the "register interface" aka CSR clock as
315 * it is never used when determining the divider for the MDC
316 * clock.
317 *
318 * clk_ptp_ref: optional PTP reference clock (clk_ptp_ref_i). When
319 * present, this clock increments the timestamp value. Otherwise,
320 * the rate of stmmac_clk will be used.
321 *
322 * clk_tx_i: MAC transmit clock, which will be 2.5MHz for 10M,
323 * 25MHz for 100M, or 125MHz for 1G irrespective of the interface
324 * mode. For the DWMAC PHY interface modes:
325 *
326 * GMII/MII PHY's transmit clock for 10M (2.5MHz) or 100M (25MHz),
327 * or 125MHz local clock for 1G mode
328 * RMII 50MHz RMII clock divided by 2 or 20.
329 * RGMII 125MHz local clock divided by 1, 5, or 50.
330 * SGMII 125MHz SerDes clock divided by 1, 5, or 50.
331 * TBI/RTBI 125MHz SerDes clock
332 */
333 struct clk *stmmac_clk;
334 struct clk *pclk;
335 struct clk *clk_ptp_ref;
336 struct clk *clk_tx_i;
337 unsigned long clk_ptp_rate;
338 unsigned long clk_ref_rate;
339 struct clk_bulk_data *clks;
340 int num_clks;
341 unsigned int mult_fact_100ns;
342 s32 ptp_max_adj;
343 u32 cdc_error_adj;
344 struct reset_control *stmmac_rst;
345 struct reset_control *stmmac_ahb_rst;
346 struct stmmac_axi *axi;
347 int rss_en;
348 int mac_port_sel_speed;
349 u8 vlan_fail_q;
350 bool provide_bus_info;
351 int int_snapshot_num;
352 int msi_mac_vec;
353 int msi_wol_vec;
354 int msi_sfty_ce_vec;
355 int msi_sfty_ue_vec;
356 int msi_rx_base_vec;
357 int msi_tx_base_vec;
358 const struct dwmac4_addrs *dwmac4_addrs;
359 unsigned int flags;
360 struct stmmac_dma_cfg __dma_cfg;
361};
362#endif