Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/asic_health
2Date: June 2018
3KernelVersion: 4.19
4Contact: Vadim Pasternak <vadimp@nvidia.com>
5Description: This file shows ASIC health status. The possible values are:
6 0 - health failed, 2 - health OK, 3 - ASIC in booting state.
7
8 The files are read only.
9
10What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/cpld1_version
11What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/cpld2_version
12Date: June 2018
13KernelVersion: 4.19
14Contact: Vadim Pasternak <vadimp@nvidia.com>
15Description: These files show with which CPLD versions have been burned
16 on carrier and switch boards.
17
18 The files are read only.
19
20What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/fan_dir
21Date: December 2018
22KernelVersion: 5.0
23Contact: Vadim Pasternak <vadimp@nvidia.com>
24Description: This file shows the system fans direction:
25 forward direction - relevant bit is set 0;
26 reversed direction - relevant bit is set 1.
27
28 The files are read only.
29
30What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/cpld3_version
31Date: November 2018
32KernelVersion: 5.0
33Contact: Vadim Pasternak <vadimp@nvidia.com>
34Description: These files show with which CPLD versions have been burned
35 on LED or Gearbox board.
36
37 The files are read only.
38
39What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/jtag_enable
40Date: November 2018
41KernelVersion: 5.0
42Contact: Vadim Pasternak <vadimp@nvidia.com>
43Description: These files enable and disable the access to the JTAG domain.
44 By default access to the JTAG domain is disabled.
45
46 The file is read/write.
47
48What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/select_iio
49Date: June 2018
50KernelVersion: 4.19
51Contact: Vadim Pasternak <vadimp@nvidia.com>
52Description: This file allows iio devices selection.
53
54 Attribute select_iio can be written with 0 or with 1. It
55 selects which one of iio devices can be accessed.
56
57 The file is read/write.
58
59What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/psu1_on
60 /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/psu2_on
61 /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/pwr_cycle
62 /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/pwr_down
63Date: June 2018
64KernelVersion: 4.19
65Contact: Vadim Pasternak <vadimp@nvidia.com>
66Description: These files allow asserting system power cycling, switching
67 power supply units on and off and system's main power domain
68 shutdown.
69 Expected behavior:
70 When pwr_cycle is written 1: auxiliary power domain will go
71 down and after short period (about 1 second) up.
72 When psu1_on or psu2_on is written 1, related unit will be
73 disconnected from the power source, when written 0 - connected.
74 If both are written 1 - power supplies main power domain will
75 go down.
76 When pwr_down is written 1, system's main power domain will go
77 down.
78
79 The files are write only.
80
81What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/reset_aux_pwr_or_ref
82What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/reset_asic_thermal
83What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/reset_hotswap_or_halt
84What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/reset_hotswap_or_wd
85What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/reset_fw_reset
86What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/reset_long_pb
87What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/reset_main_pwr_fail
88What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/reset_short_pb
89What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/reset_sw_reset
90Date: June 2018
91KernelVersion: 4.19
92Contact: Vadim Pasternak <vadimp@nvidia.com>
93Description: These files show the system reset cause, as following: power
94 auxiliary outage or power refresh, ASIC thermal shutdown, halt,
95 hotswap, watchdog, firmware reset, long press power button,
96 short press power button, software reset. Value 1 in file means
97 this is reset cause, 0 - otherwise. Only one of the above
98 causes could be 1 at the same time, representing only last
99 reset cause.
100
101 The files are read only.
102
103What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/reset_comex_pwr_fail
104What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/reset_from_comex
105What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/reset_system
106What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/reset_voltmon_upgrade_fail
107Date: November 2018
108KernelVersion: 5.0
109Contact: Vadim Pasternak <vadimp@nvidia.com>
110Description: These files show the system reset cause, as following: ComEx
111 power fail, reset from ComEx, system platform reset, reset
112 due to voltage monitor devices upgrade failure,
113 Value 1 in file means this is reset cause, 0 - otherwise.
114 Only one bit could be 1 at the same time, representing only
115 the last reset cause.
116
117 The files are read only.
118
119What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/cpld4_version
120Date: November 2018
121KernelVersion: 5.0
122Contact: Vadim Pasternak <vadimp@nvidia.com>
123Description: These files show with which CPLD versions have been burned
124 on LED board.
125
126 The files are read only.
127
128What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/reset_comex_thermal
129What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/reset_comex_wd
130What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/reset_from_asic
131What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/reset_reload_bios
132What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/reset_sff_wd
133What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/reset_swb_wd
134Date: June 2019
135KernelVersion: 5.3
136Contact: Vadim Pasternak <vadimp@nvidia.com>
137Description: These files show the system reset cause, as following:
138 COMEX thermal shutdown; wathchdog power off or reset was derived
139 by one of the next components: COMEX, switch board or by Small Form
140 Factor mezzanine, reset requested from ASIC, reset caused by BIOS
141 reload. Value 1 in file means this is reset cause, 0 - otherwise.
142 Only one of the above causes could be 1 at the same time, representing
143 only last reset cause.
144
145 The files are read only.
146
147What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/config1
148What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/config2
149Date: January 2020
150KernelVersion: 5.6
151Contact: Vadim Pasternak <vadimp@nvidia.com>
152Description: These files show system static topology identification
153 like system's static I2C topology, number and type of FPGA
154 devices within the system and so on.
155
156 The files are read only.
157
158What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/reset_ac_pwr_fail
159What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/reset_platform
160What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/reset_soc
161What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/reset_sw_pwr_off
162Date: January 2020
163KernelVersion: 5.6
164Contact: Vadim Pasternak <vadimp@nvidia.com>
165Description: These files show the system reset causes, as following: reset
166 due to AC power failure, reset invoked from software by
167 assertion reset signal through CPLD. reset caused by signal
168 asserted by SOC through ACPI register, reset invoked from
169 software by assertion power off signal through CPLD.
170
171 The files are read only.
172
173What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/pcie_asic_reset_dis
174Date: January 2020
175KernelVersion: 5.6
176Contact: Vadim Pasternak <vadimp@nvidia.com>
177Description: This file allows to retain ASIC up during PCIe root complex
178 reset, when attribute is set 1.
179
180 The file is read/write.
181
182What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/vpd_wp
183Date: January 2020
184KernelVersion: 5.6
185Contact: Vadim Pasternak <vadimp@nvidia.com>
186Description: This file allows to overwrite system VPD hardware write
187 protection when attribute is set 1.
188
189 The file is read/write.
190
191What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/voltreg_update_status
192Date: January 2020
193KernelVersion: 5.6
194Contact: Vadim Pasternak <vadimp@nvidia.com>
195Description: This file exposes the configuration update status of burnable
196 voltage regulator devices. The status values are as following:
197 0 - OK; 1 - CRC failure; 2 = I2C failure; 3 - in progress.
198
199 The file is read only.
200
201What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/ufm_version
202Date: January 2020
203KernelVersion: 5.6
204Contact: Vadim Pasternak <vadimp@nvidia.com>
205Description: This file exposes the firmware version of burnable voltage
206 regulator devices.
207
208 The file is read only.
209
210What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/cpld1_pn
211What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/cpld2_pn
212What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/cpld3_pn
213What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/cpld4_pn
214What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/cpld1_version_min
215What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/cpld2_version_min
216What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/cpld3_version_min
217What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/cpld4_version_min
218Date: July 2020
219KernelVersion: 5.9
220Contact: Vadim Pasternak <vadimp@nvidia.com>
221Description: These files show with which CPLD part numbers and minor
222 versions have been burned CPLD devices equipped on a
223 system.
224
225 The files are read only.
226
227What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/bios_active_image
228What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/bios_auth_fail
229What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/bios_upgrade_fail
230Date: October 2021
231KernelVersion: 5.16
232Contact: Vadim Pasternak <vadimp@nvidia.com>
233Description: The files represent BIOS statuses:
234
235 bios_active_image: location of current active BIOS image:
236 0: Top, 1: Bottom.
237 The reported value should correspond to value expected by OS
238 in case of BIOS safe mode is 0. This bit is related to Intel
239 top-swap feature of DualBios on the same flash.
240
241 bios_auth_fail: BIOS upgrade is failed because provided BIOS
242 image is not signed correctly.
243
244 bios_upgrade_fail: BIOS upgrade is failed by some other
245 reason not because authentication. For example due to
246 physical SPI flash problem.
247
248 The files are read only.
249
250What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/lc1_enable
251What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/lc2_enable
252What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/lc3_enable
253What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/lc4_enable
254What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/lc5_enable
255What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/lc6_enable
256What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/lc7_enable
257What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/lc8_enable
258Date: October 2021
259KernelVersion: 5.16
260Contact: Vadim Pasternak <vadimp@nvidia.com>
261Description: These files allow line cards enable state control.
262 Expected behavior:
263 When lc{n}_enable is written 1, related line card is released
264 from the reset state, when 0 - is hold in reset state.
265
266 The files are read/write.
267
268What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/lc1_pwr
269What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/lc2_pwr
270What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/lc3_pwr
271What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/lc4_pwr
272What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/lc5_pwr
273What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/lc6_pwr
274What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/lc7_pwr
275What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/lc8_pwr
276Date: October 2021
277KernelVersion: 5.16
278Contact: Vadim Pasternak <vadimp@nvidia.com>
279Description: These files switching line cards power on and off.
280 Expected behavior:
281 When lc{n}_pwr is written 1, related line card is powered
282 on, when written 0 - powered off.
283
284 The files are read/write.
285
286What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/lc1_rst_mask
287What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/lc2_rst_mask
288What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/lc3_rst_mask
289What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/lc4_rst_mask
290What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/lc5_rst_mask
291What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/lc6_rst_mask
292What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/lc7_rst_mask
293What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/lc8_rst_mask
294Date: October 2021
295KernelVersion: 5.16
296Contact: Vadim Pasternak <vadimp@nvidia.com>
297Description: These files clear line card reset bit enforced by ASIC, when it
298 sets it due to some abnormal ASIC behavior.
299 Expected behavior:
300 When lc{n}_rst_mask is written 1, related line card reset bit
301 is cleared, when written 0 - no effect.
302
303 The files are write only.
304
305What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/os_started
306Date: October 2021
307KernelVersion: 5.16
308Contact: Vadim Pasternak <vadimp@nvidia.com>
309Description: This file, when written 1, indicates to programmable devices
310 that OS is taking control over it.
311
312 The file is read/write.
313
314What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/pm_mgmt_en
315Date: October 2021
316KernelVersion: 5.16
317Contact: Vadim Pasternak <vadimp@nvidia.com>
318Description: This file assigns power management control ownership.
319 When power management control is provided by hardware, hardware
320 will automatically power off one or more line previously
321 powered line cards in case system power budget is getting
322 insufficient. It could be in case when some of power units lost
323 power good state.
324 When pm_mgmt_en is written 1, power management control by
325 software is enabled, 0 - power management control by hardware.
326 Note that for any setting of pm_mgmt_en attribute hardware will
327 not allow to power on any new line card in case system power
328 budget is insufficient.
329 Same in case software will try to power on several line cards
330 at once - hardware will power line cards while system has
331 enough power budget.
332 Default is 0.
333
334 The file is read/write.
335
336What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/psu3_on
337What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/psu4_on
338Date: October 2021
339KernelVersion: 5.16
340Contact: Vadim Pasternak <vadimp@nvidia.com>
341Description: These files switching power supply units on and off.
342 Expected behavior:
343 When psu3_on or psu4_on is written 1, related unit will be
344 disconnected from the power source, when written 0 - connected.
345
346 The files are write only.
347
348What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/shutdown_unlock
349Date: October 2021
350KernelVersion: 5.16
351Contact: Vadim Pasternak <vadimp@nvidia.com>
352Description: This file allows to unlock ASIC after thermal shutdown event.
353 When system thermal shutdown is enforced by ASIC, ASIC is
354 getting locked and after system boot it will not be available.
355 Software can decide to unlock it by setting this attribute to
356 1 and then perform system power cycle by setting pwr_cycle
357 attribute to 1 (power cycle of main power domain).
358 Before setting shutdown_unlock to 1 it is recommended to
359 validate that system reboot cause is reset_asic_thermal or
360 reset_thermal_spc_or_pciesw.
361 In case shutdown_unlock is not set 1, the only way to release
362 ASIC from locking - is full system power cycle through the
363 external power distribution unit.
364 Default is 1.
365
366 The file is read/write.
367
368What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/i2c-*/*-0032/mlxreg-io.*/hwmon/hwmon*/cpld1_pn
369What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/i2c-*/*-0032/mlxreg-io.*/hwmon/hwmon*/cpld1_version
370What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/i2c-*/*-0032/mlxreg-io.*/hwmon/hwmon*/cpld1_version_min
371Date: October 2021
372KernelVersion: 5.16
373Contact: Vadim Pasternak <vadimp@nvidia.com>
374Description: These files show with which CPLD major and minor versions
375 and part number has been burned CPLD device on line card.
376
377 The files are read only.
378
379What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/i2c-*/*-0032/mlxreg-io.*/hwmon/hwmon*/fpga1_pn
380What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/i2c-*/*-0032/mlxreg-io.*/hwmon/hwmon*/fpga1_version
381What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/i2c-*/*-0032/mlxreg-io.*/hwmon/hwmon*/fpga1_version_min
382Date: October 2021
383KernelVersion: 5.16
384Contact: Vadim Pasternak <vadimp@nvidia.com>
385Description: These files show with which FPGA major and minor versions
386 and part number has been burned FPGA device on line card.
387
388 The files are read only.
389
390What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/i2c-*/*-0032/mlxreg-io.*/hwmon/hwmon*/vpd_wp
391Date: October 2021
392KernelVersion: 5.16
393Contact: Vadim Pasternak <vadimp@nvidia.com>
394Description: This file allow to overwrite line card VPD hardware write
395 protection mode. When attribute is set 1 - write protection is
396 disabled, when 0 - enabled.
397 Default is 0.
398 If the system is in locked-down mode writing this file will not
399 be allowed.
400 The purpose if this file is to allow line card VPD burning
401 during production flow.
402
403 The file is read/write.
404
405What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/i2c-*/*-0032/mlxreg-io.*/hwmon/hwmon*/reset_aux_pwr_or_ref
406What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/i2c-*/*-0032/mlxreg-io.*/hwmon/hwmon*/reset_dc_dc_pwr_fail
407What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/i2c-*/*-0032/mlxreg-io.*/hwmon/hwmon*/reset_fpga_not_done
408What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/i2c-*/*-0032/mlxreg-io.*/hwmon/hwmon*/reset_from_chassis
409What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/i2c-*/*-0032/mlxreg-io.*/hwmon/hwmon*/reset_line_card
410What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/i2c-*/*-0032/mlxreg-io.*/hwmon/hwmon*/reset_pwr_off_from_chassis
411Date: October 2021
412KernelVersion: 5.16
413Contact: Vadim Pasternak <vadimp@nvidia.com>
414Description: These files show the line reset cause, as following: power
415 auxiliary outage or power refresh, DC-to-DC power failure, FPGA reset
416 failed, line card reset failed, power off from chassis.
417 Value 1 in file means this is reset cause, 0 - otherwise. Only one of
418 the above causes could be 1 at the same time, representing only last
419 reset cause.
420
421 The files are read only.
422
423What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/i2c-*/*-0032/mlxreg-io.*/hwmon/hwmon*/cpld_upgrade_en
424What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/i2c-*/*-0032/mlxreg-io.*/hwmon/hwmon*/fpga_upgrade_en
425Date: October 2021
426KernelVersion: 5.16
427Contact: Vadim Pasternak <vadimp@nvidia.com>
428Description: These files allow CPLD and FPGA burning. Value 1 in file means burning
429 is enabled, 0 - otherwise.
430 If the system is in locked-down mode writing these files will
431 not be allowed.
432 The purpose of these files to allow line card CPLD and FPGA
433 upgrade through the JTAG daisy-chain.
434
435 The files are read/write.
436
437What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/i2c-*/*-0032/mlxreg-io.*/hwmon/hwmon*/qsfp_pwr_en
438What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/i2c-*/*-0032/mlxreg-io.*/hwmon/hwmon*/pwr_en
439Date: October 2021
440KernelVersion: 5.16
441Contact: Vadim Pasternak <vadimp@nvidia.com>
442Description: These files allow to power on/off all QSFP ports and whole line card.
443 The attributes are set 1 for power on, 0 - for power off.
444
445 The files are read/write.
446
447What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/i2c-*/*-0032/mlxreg-io.*/hwmon/hwmon*/agb_spi_burn_en
448What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/i2c-*/*-0032/mlxreg-io.*/hwmon/hwmon*/fpga_spi_burn_en
449Date: October 2021
450KernelVersion: 5.16
451Contact: Vadim Pasternak <vadimp@nvidia.com>
452Description: These files allow gearboxes and FPGA SPI flash burning.
453 The attributes are set 1 to enable burning, 0 - to disable.
454 If the system is in locked-down mode writing these files will
455 not be allowed.
456 The purpose of these files to allow line card Gearboxes and FPGA
457 burning during production flow.
458
459 The file is read/write.
460
461What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/i2c-*/*-0032/mlxreg-io.*/hwmon/hwmon*/max_power
462What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/i2c-*/*-0032/mlxreg-io.*/hwmon/hwmon*/config
463Date: October 2021
464KernelVersion: 5.16
465Contact: Vadim Pasternak <vadimp@nvidia.com>
466Description: These files provide the maximum powered required for line card
467 feeding and line card configuration Id.
468
469 The files are read only.
470
471What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/phy_reset
472Date: May 2022
473KernelVersion: 5.19
474Contact: Vadim Pasternak <vadimp@nvidia.com>
475Description: This file allows to reset PHY 88E1548 when attribute is set 0
476 due to some abnormal PHY behavior.
477 Expected behavior:
478 When phy_reset is written 1, all PHY 88E1548 are released
479 from the reset state, when 0 - are hold in reset state.
480
481 The files are read/write.
482
483What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/mac_reset
484Date: May 2022
485KernelVersion: 5.19
486Contact: Vadim Pasternak <vadimp@nvidia.com>
487Description: This file allows to reset ASIC MT52132 when attribute is set 0
488 due to some abnormal ASIC behavior.
489 Expected behavior:
490 When mac_reset is written 1, the ASIC MT52132 is released
491 from the reset state, when 0 - is hold in reset state.
492
493 The files are read/write.
494
495What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/qsfp_pwr_good
496Date: May 2022
497KernelVersion: 5.19
498Contact: Vadim Pasternak <vadimp@nvidia.com>
499Description: This file shows QSFP ports power status. The value is set to 0
500 when one of any QSFP ports is plugged. The value is set to 1 when
501 there are no any QSFP ports are plugged.
502 The possible values are:
503 0 - Power good, 1 - Not power good.
504
505 The files are read only.
506
507What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/asic2_health
508Date: July 2022
509KernelVersion: 5.20
510Contact: Vadim Pasternak <vadimp@nvidia.com>
511Description: This file shows 2-nd ASIC health status. The possible values are:
512 0 - health failed, 2 - health OK, 3 - ASIC in booting state.
513
514 The file is read only.
515
516What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/asic_reset
517What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/asic2_reset
518Date: July 2022
519KernelVersion: 5.20
520Contact: Vadim Pasternak <vadimp@nvidia.com>
521Description: These files allow to each of ASICs by writing 1.
522
523 The files are write only.
524
525What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/comm_chnl_ready
526Date: July 2022
527KernelVersion: 5.20
528Contact: Vadim Pasternak <vadimp@nvidia.com>
529Description: This file is used to indicate remote end (for example BMC) that system
530 host CPU is ready for sending telemetry data to remote end.
531 For indication the file should be written 1.
532
533 The file is write only.
534
535What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/config3
536Date: January 2020
537KernelVersion: 5.6
538Contact: Vadim Pasternak <vadimp@nvidia.com>
539Description: The file indicates COME module hardware configuration.
540 The value is pushed by hardware through GPIO pins.
541 The purpose is to expose some minor BOM changes for the same system SKU.
542
543 The file is read only.
544
545What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/reset_pwr_converter_fail
546Date: February 2023
547KernelVersion: 6.3
548Contact: Vadim Pasternak <vadimp@nvidia.com>
549Description: This file shows the system reset cause due to power converter
550 devices failure.
551 Value 1 in file means this is reset cause, 0 - otherwise.
552
553 The file is read only.
554
555What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/erot1_ap_reset
556What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/erot2_ap_reset
557Date: February 2023
558KernelVersion: 6.3
559Contact: Vadim Pasternak <vadimp@nvidia.com>
560Description: These files aim to monitor the status of the External Root of Trust (EROT)
561 processor's RESET output to the Application Processor (AP).
562 By reading this file, could be determined if the EROT has invalidated or
563 revoked AP Firmware, at which point it will hold the AP in RESET until a
564 valid firmware is loaded. This protects the AP from running an
565 unauthorized firmware. In the normal flow, the AP reset should be released
566 after the EROT validates the integrity of the FW, and it should be done so
567 as quickly as possible so that the AP boots before the CPU starts to
568 communicate to each ASIC.
569
570 The files are read only.
571
572What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/erot1_recovery
573What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/erot2_recovery
574What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/erot1_reset
575What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/erot2_reset
576Date: February 2023
577KernelVersion: 6.3
578Contact: Vadim Pasternak <vadimp@nvidia.com>
579Description: These files aim to perform External Root of Trust (EROT) recovery
580 sequence after EROT device failure.
581 These EROT devices protect ASICs from unauthorized access and in normal
582 flow their reset should be released with system power – earliest power
583 up stage, so that EROTs can begin boot and authentication process before
584 CPU starts to communicate to ASICs.
585 Issuing a reset to the EROT while asserting the recovery signal will cause
586 the EROT Application Processor to enter recovery mode so that the EROT FW
587 can be updated/recovered.
588 For reset/recovery the related file should be toggled by 1/0.
589
590 The files are read/write.
591
592What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/erot1_wp
593What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/erot2_wp
594Date: February 2023
595KernelVersion: 6.3
596Contact: Vadim Pasternak <vadimp@nvidia.com>
597Description: These files allow access to External Root of Trust (EROT) for reset
598 and recovery sequence after EROT device failure.
599 Default is 0 (programming disabled).
600 If the system is in locked-down mode writing this file will not be allowed.
601
602 The files are read/write.
603
604What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/spi_chnl_select
605Date: February 2023
606KernelVersion: 6.3
607Contact: Vadim Pasternak <vadimp@nvidia.com>
608Description: This file allows SPI chip selection for External Root of Trust (EROT)
609 device Out-of-Band recovery.
610 File can be written with 0 or with 1. It selects which EROT can be accessed
611 through SPI device.
612
613 The file is read/write.
614
615What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/asic_pg_fail
616Date: February 2023
617KernelVersion: 6.3
618Contact: Vadim Pasternak vadimp@nvidia.com
619Description: This file shows ASIC Power Good status.
620 Value 1 in file means ASIC Power Good failed, 0 - otherwise.
621
622 The file is read only.
623
624What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/clk_brd1_boot_fail
625What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/clk_brd2_boot_fail
626What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/clk_brd_fail
627Date: February 2023
628KernelVersion: 6.3
629Contact: Vadim Pasternak vadimp@nvidia.com
630Description: These files are related to clock boards status in system.
631 - clk_brd1_boot_fail: warning about 1-st clock board failed to boot from CI.
632 - clk_brd2_boot_fail: warning about 2-nd clock board failed to boot from CI.
633 - clk_brd_fail: error about common clock board boot failure.
634
635 The files are read only.
636
637What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/clk_brd_prog_en
638Date: February 2023
639KernelVersion: 6.3
640Contact: Vadim Pasternak <vadimp@nvidia.com>
641Description: This file enables programming of clock boards.
642 Default is 0 (programming disabled).
643 If the system is in locked-down mode writing this file will not be allowed.
644
645 The file is read/write.
646
647What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/pwr_converter_prog_en
648Date: February 2023
649KernelVersion: 6.3
650Contact: Vadim Pasternak <vadimp@nvidia.com>
651Description: This file enables programming of power converters.
652 Default is 0 (programming disabled).
653 If the system is in locked-down mode writing this file will not be allowed.
654
655 The file is read/write.
656
657What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/reset_ac_ok_fail
658Date: February 2023
659KernelVersion: 6.3
660Contact: Vadim Pasternak <vadimp@nvidia.com>
661Description: This file shows the system reset cause due to AC power failure.
662 Value 1 in file means this is reset cause, 0 - otherwise.
663
664 The file is read only.
665
666What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/cpld5_pn
667What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/cpld5_version
668What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/cpld5_version_min
669Date: August 2023
670KernelVersion: 6.6
671Contact: Vadim Pasternak <vadimp@nvidia.com>
672Description: These files show with which CPLD part numbers, version and minor
673 versions have been burned the 5-th CPLD device equipped on a
674 system.
675
676 The files are read only.
677
678What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/jtag_cap
679Date: August 2023
680KernelVersion: 6.6
681Contact: Vadim Pasternak <vadimp@nvidia.com>
682Description: This file indicates the available method of CPLD/FPGA devices
683 field update through the JTAG chain:
684
685 b00 - field update through LPC bus register memory space.
686 b01 - Reserved.
687 b10 - Reserved.
688 b11 - field update through CPU GPIOs bit-banging.
689
690 The file is read only.
691
692What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/lid_open
693Date: August 2023
694KernelVersion: 6.6
695Contact: Vadim Pasternak <vadimp@nvidia.com>
696Description: 1 - indicates that system lid is opened, otherwise 0.
697
698 The file is read only.
699
700What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/reset_long_pwr_pb
701Date: August 2023
702KernelVersion: 6.6
703Contact: Vadim Pasternak <vadimp@nvidia.com>
704Description: This file if set 1 indicates that system has been reset by
705 long press of power button.
706
707 The file is read only.
708
709What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/reset_swb_dc_dc_pwr_fail
710Date: August 2023
711KernelVersion: 6.6
712Contact: Vadim Pasternak <vadimp@nvidia.com>
713Description: This file shows 1 in case the system reset happened due to the
714 failure of any DC-DC power converter devices equipped on the
715 switch board.
716
717 The file is read only.
718
719What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/global_wp_request
720Date: May 2025
721KernelVersion: 6.16
722Contact: Vadim Pasternak <vadimp@nvidia.com>
723Description: This file when written 1 activates request to allow access to
724 the write protected flashes. Such request can be performed only
725 for system equipped with BMC (Board Management Controller),
726 which can grant access to protected flashes. In case BMC allows
727 access - it will respond with "global_wp_response". BMC decides
728 regarding time window of granted access. After granted window is
729 expired, BMC will change value back to 0.
730 Default value is 0.
731
732 The file is read/write.
733
734What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/global_wp_response
735Date: May 2025
736KernelVersion: 6.16
737Contact: Vadim Pasternak <vadimp@nvidia.com>
738Description: This file, when set 1, indicates that access to protected
739 flashes have been granted to host CPU by BMC.
740 Default value is 0.
741
742 The file is read only.
743
744What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/shutdown_unlock
745Date: May 2025
746KernelVersion: 6.16
747Contact: Vadim Pasternak <vadimp@nvidia.com>
748Description: When ASICs are getting overheated, system protection
749 hardware mechanism enforces system reboot. After system
750 reboot ASICs come up in locked state. To unlock ASICs,
751 this file should be written 1
752 Default value is 0.
753
754 The file is read/write.
755
756What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/*-00**/mlxreg-io.*/hwmon/hwmon*/boot_progress
757Date: May 2025
758KernelVersion: 6.16
759Contact: Vadim Pasternak <vadimp@nvidia.com>
760Description: These files show the Data Process Unit board boot progress
761 state. Valid states are:
762 - 4 : OS starting.
763 - 5 : OS running.
764 - 6 : Low-Power Standby.
765
766 The file is read only.
767
768What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/*-00**/mlxreg-io.*/hwmon/hwmon*/dpu_id
769Date: May 2025
770KernelVersion: 6.16
771Contact: Vadim Pasternak <vadimp@nvidia.com>
772Description: This file shows hardware Id of Data Process Unit board.
773
774 The file is read only.
775
776What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/*-00**/mlxreg-io.*/hwmon/hwmon*/reset_aux_pwr_or_reload
777What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/*-00**/mlxreg-io.*/hwmon/hwmon*/reset_dpu_thermal
778What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/*-00**/mlxreg-io.*/hwmon/hwmon*/reset_from_main_board
779Date: May 2025
780KernelVersion: 6.16
781Contact: Vadim Pasternak <vadimp@nvidia.com>
782Description: These files expose the cause of the most recent reset of the Data
783 Processing Unit (DPU) board. The possible causes are:
784 - Power auxiliary outage or power reload.
785 - Thermal shutdown.
786 - Reset request from the main board.
787 Value 1 in file means this is reset cause, 0 - otherwise. Only one of
788 the above causes could be 1 at the same time, representing only last
789 reset cause.
790
791 The files are read only.
792
793What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/*-00**/mlxreg-io.*/hwmon/hwmon*/perst_rst
794What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/*-00**/mlxreg-io.*/hwmon/hwmon*/phy_rst
795What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/*-00**/mlxreg-io.*/hwmon/hwmon*/tpm_rst
796What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/*-00**/mlxreg-io.*/hwmon/hwmon*/usbphy_rst
797Date: May 2025
798KernelVersion: 6.16
799Contact: Vadim Pasternak <vadimp@nvidia.com>
800Description: These files allow to reset hardware components of Data Process
801 Unit board. Respectively PCI, Ethernet PHY, TPM and USB PHY
802 resets.
803 Default values for all the attributes is 1. Writing 0 will
804 cause reset of the related component.
805
806 The files are read/write.
807
808What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/*-00**/mlxreg-io.*/hwmon/hwmon*/ufm_upgrade
809Date: May 2025
810KernelVersion: 6.16
811Contact: Vadim Pasternak <vadimp@nvidia.com>
812Description: These files show status of Unified Fabric Manager upgrade.
813 state. 0 - means upgrade is done, 1 - otherwise.
814
815 The file is read only.