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linux
1What: /sys/bus/cxl/flush
2Date: January, 2022
3KernelVersion: v5.18
4Contact: linux-cxl@vger.kernel.org
5Description:
6 (WO) If userspace manually unbinds a port the kernel schedules
7 all descendant memdevs for unbind. Writing '1' to this attribute
8 flushes that work.
9
10
11What: /sys/bus/cxl/devices/memX/firmware_version
12Date: December, 2020
13KernelVersion: v5.12
14Contact: linux-cxl@vger.kernel.org
15Description:
16 (RO) "FW Revision" string as reported by the Identify
17 Memory Device Output Payload in the CXL-2.0
18 specification.
19
20
21What: /sys/bus/cxl/devices/memX/payload_max
22Date: December, 2020
23KernelVersion: v5.12
24Contact: linux-cxl@vger.kernel.org
25Description:
26 (RO) Maximum size (in bytes) of the mailbox command payload
27 registers. Linux caps this at 1MB if the device reports a
28 larger size.
29
30
31What: /sys/bus/cxl/devices/memX/label_storage_size
32Date: May, 2021
33KernelVersion: v5.13
34Contact: linux-cxl@vger.kernel.org
35Description:
36 (RO) Size (in bytes) of the Label Storage Area (LSA).
37
38
39What: /sys/bus/cxl/devices/memX/ram/size
40Date: December, 2020
41KernelVersion: v5.12
42Contact: linux-cxl@vger.kernel.org
43Description:
44 (RO) "Volatile Only Capacity" as bytes. Represents the
45 identically named field in the Identify Memory Device Output
46 Payload in the CXL-2.0 specification.
47
48
49What: /sys/bus/cxl/devices/memX/ram/qos_class
50Date: May, 2023
51KernelVersion: v6.8
52Contact: linux-cxl@vger.kernel.org
53Description:
54 (RO) For CXL host platforms that support "QoS Telemetry"
55 this attribute conveys a comma delimited list of platform
56 specific cookies that identifies a QoS performance class
57 for the volatile partition of the CXL mem device. These
58 class-ids can be compared against a similar "qos_class"
59 published for a root decoder. While it is not required
60 that the endpoints map their local memory-class to a
61 matching platform class, mismatches are not recommended
62 and there are platform specific performance related
63 side-effects that may result. First class-id is displayed.
64
65
66What: /sys/bus/cxl/devices/memX/pmem/size
67Date: December, 2020
68KernelVersion: v5.12
69Contact: linux-cxl@vger.kernel.org
70Description:
71 (RO) "Persistent Only Capacity" as bytes. Represents the
72 identically named field in the Identify Memory Device Output
73 Payload in the CXL-2.0 specification.
74
75
76What: /sys/bus/cxl/devices/memX/pmem/qos_class
77Date: May, 2023
78KernelVersion: v6.8
79Contact: linux-cxl@vger.kernel.org
80Description:
81 (RO) For CXL host platforms that support "QoS Telemetry"
82 this attribute conveys a comma delimited list of platform
83 specific cookies that identifies a QoS performance class
84 for the persistent partition of the CXL mem device. These
85 class-ids can be compared against a similar "qos_class"
86 published for a root decoder. While it is not required
87 that the endpoints map their local memory-class to a
88 matching platform class, mismatches are not recommended
89 and there are platform specific performance related
90 side-effects that may result. First class-id is displayed.
91
92
93What: /sys/bus/cxl/devices/memX/serial
94Date: January, 2022
95KernelVersion: v5.18
96Contact: linux-cxl@vger.kernel.org
97Description:
98 (RO) 64-bit serial number per the PCIe Device Serial Number
99 capability. Mandatory for CXL devices, see CXL 2.0 8.1.12.2
100 Memory Device PCIe Capabilities and Extended Capabilities.
101
102
103What: /sys/bus/cxl/devices/memX/numa_node
104Date: January, 2022
105KernelVersion: v5.18
106Contact: linux-cxl@vger.kernel.org
107Description:
108 (RO) If NUMA is enabled and the platform has affinitized the
109 host PCI device for this memory device, emit the CPU node
110 affinity for this device.
111
112
113What: /sys/bus/cxl/devices/memX/security/state
114Date: June, 2023
115KernelVersion: v6.5
116Contact: linux-cxl@vger.kernel.org
117Description:
118 (RO) Reading this file will display the CXL security state for
119 that device. Such states can be: 'disabled', 'sanitize', when
120 a sanitization is currently underway; or those available only
121 for persistent memory: 'locked', 'unlocked' or 'frozen'. This
122 sysfs entry is select/poll capable from userspace to notify
123 upon completion of a sanitize operation.
124
125
126What: /sys/bus/cxl/devices/memX/security/sanitize
127Date: June, 2023
128KernelVersion: v6.5
129Contact: linux-cxl@vger.kernel.org
130Description:
131 (WO) Write a boolean 'true' string value to this attribute to
132 sanitize the device to securely re-purpose or decommission it.
133 This is done by ensuring that all user data and meta-data,
134 whether it resides in persistent capacity, volatile capacity,
135 or the LSA, is made permanently unavailable by whatever means
136 is appropriate for the media type. This functionality requires
137 the device to be disabled, that is, not actively decoding any
138 HPA ranges. This permits avoiding explicit global CPU cache
139 management, relying instead for it to be done when a region
140 transitions between software programmed and hardware committed
141 states. If this file is not present, then there is no hardware
142 support for the operation.
143
144
145What /sys/bus/cxl/devices/memX/security/erase
146Date: June, 2023
147KernelVersion: v6.5
148Contact: linux-cxl@vger.kernel.org
149Description:
150 (WO) Write a boolean 'true' string value to this attribute to
151 secure erase user data by changing the media encryption keys for
152 all user data areas of the device. This functionality requires
153 the device to be disabled, that is, not actively decoding any
154 HPA ranges. This permits avoiding explicit global CPU cache
155 management, relying instead for it to be done when a region
156 transitions between software programmed and hardware committed
157 states. If this file is not present, then there is no hardware
158 support for the operation.
159
160
161What: /sys/bus/cxl/devices/memX/firmware/
162Date: April, 2023
163KernelVersion: v6.5
164Contact: linux-cxl@vger.kernel.org
165Description:
166 (RW) Firmware uploader mechanism. The different files under
167 this directory can be used to upload and activate new
168 firmware for CXL devices. The interfaces under this are
169 documented in sysfs-class-firmware.
170
171
172What: /sys/bus/cxl/devices/*/devtype
173Date: June, 2021
174KernelVersion: v5.14
175Contact: linux-cxl@vger.kernel.org
176Description:
177 (RO) CXL device objects export the devtype attribute which
178 mirrors the same value communicated in the DEVTYPE environment
179 variable for uevents for devices on the "cxl" bus.
180
181
182What: /sys/bus/cxl/devices/*/modalias
183Date: December, 2021
184KernelVersion: v5.18
185Contact: linux-cxl@vger.kernel.org
186Description:
187 (RO) CXL device objects export the modalias attribute which
188 mirrors the same value communicated in the MODALIAS environment
189 variable for uevents for devices on the "cxl" bus.
190
191
192What: /sys/bus/cxl/devices/portX/uport
193Date: June, 2021
194KernelVersion: v5.14
195Contact: linux-cxl@vger.kernel.org
196Description:
197 (RO) CXL port objects are enumerated from either a platform
198 firmware device (ACPI0017 and ACPI0016) or PCIe switch upstream
199 port with CXL component registers. The 'uport' symlink connects
200 the CXL portX object to the device that published the CXL port
201 capability.
202
203
204What: /sys/bus/cxl/devices/{port,endpoint}X/parent_dport
205Date: January, 2023
206KernelVersion: v6.3
207Contact: linux-cxl@vger.kernel.org
208Description:
209 (RO) CXL port objects are instantiated for each upstream port in
210 a CXL/PCIe switch, and for each endpoint to map the
211 corresponding memory device into the CXL port hierarchy. When a
212 descendant CXL port (switch or endpoint) is enumerated it is
213 useful to know which 'dport' object in the parent CXL port
214 routes to this descendant. The 'parent_dport' symlink points to
215 the device representing the downstream port of a CXL switch that
216 routes to {port,endpoint}X.
217
218
219What: /sys/bus/cxl/devices/portX/dportY
220Date: June, 2021
221KernelVersion: v5.14
222Contact: linux-cxl@vger.kernel.org
223Description:
224 (RO) CXL port objects are enumerated from either a platform
225 firmware device (ACPI0017 and ACPI0016) or PCIe switch upstream
226 port with CXL component registers. The 'dportY' symlink
227 identifies one or more downstream ports that the upstream port
228 may target in its decode of CXL memory resources. The 'Y'
229 integer reflects the hardware port unique-id used in the
230 hardware decoder target list.
231
232
233What: /sys/bus/cxl/devices/portX/decoders_committed
234Date: October, 2023
235KernelVersion: v6.7
236Contact: linux-cxl@vger.kernel.org
237Description:
238 (RO) A memory device is considered active when any of its
239 decoders are in the "committed" state (See CXL 3.0 8.2.4.19.7
240 CXL HDM Decoder n Control Register). Hotplug and destructive
241 operations like "sanitize" are blocked while device is actively
242 decoding a Host Physical Address range. Note that this number
243 may be elevated without any regionX objects active or even
244 enumerated, as this may be due to decoders established by
245 platform firmware or a previous kernel (kexec).
246
247
248What: /sys/bus/cxl/devices/decoderX.Y
249Date: June, 2021
250KernelVersion: v5.14
251Contact: linux-cxl@vger.kernel.org
252Description:
253 (RO) CXL decoder objects are enumerated from either a platform
254 firmware description, or a CXL HDM decoder register set in a
255 PCIe device (see CXL 2.0 section 8.2.5.12 CXL HDM Decoder
256 Capability Structure). The 'X' in decoderX.Y represents the
257 cxl_port container of this decoder, and 'Y' represents the
258 instance id of a given decoder resource.
259
260
261What: /sys/bus/cxl/devices/decoderX.Y/{start,size}
262Date: June, 2021
263KernelVersion: v5.14
264Contact: linux-cxl@vger.kernel.org
265Description:
266 (RO) The 'start' and 'size' attributes together convey the
267 physical address base and number of bytes mapped in the
268 decoder's decode window. For decoders of devtype
269 "cxl_decoder_root" the address range is fixed. For decoders of
270 devtype "cxl_decoder_switch" the address is bounded by the
271 decode range of the cxl_port ancestor of the decoder's cxl_port,
272 and dynamically updates based on the active memory regions in
273 that address space.
274
275
276What: /sys/bus/cxl/devices/decoderX.Y/locked
277Date: June, 2021
278KernelVersion: v5.14
279Contact: linux-cxl@vger.kernel.org
280Description:
281 (RO) CXL HDM decoders have the capability to lock the
282 configuration until the next device reset. For decoders of
283 devtype "cxl_decoder_root" there is no standard facility to
284 unlock them. For decoders of devtype "cxl_decoder_switch" a
285 secondary bus reset, of the PCIe bridge that provides the bus
286 for this decoders uport, unlocks / resets the decoder.
287
288
289What: /sys/bus/cxl/devices/decoderX.Y/target_list
290Date: June, 2021
291KernelVersion: v5.14
292Contact: linux-cxl@vger.kernel.org
293Description:
294 (RO) Display a comma separated list of the current decoder
295 target configuration. The list is ordered by the current
296 configured interleave order of the decoder's dport instances.
297 Each entry in the list is a dport id.
298
299
300What: /sys/bus/cxl/devices/decoderX.Y/cap_{pmem,ram,type2,type3}
301Date: June, 2021
302KernelVersion: v5.14
303Contact: linux-cxl@vger.kernel.org
304Description:
305 (RO) When a CXL decoder is of devtype "cxl_decoder_root", it
306 represents a fixed memory window identified by platform
307 firmware. A fixed window may only support a subset of memory
308 types. The 'cap_*' attributes indicate whether persistent
309 memory, volatile memory, accelerator memory, and / or expander
310 memory may be mapped behind this decoder's memory window.
311
312
313What: /sys/bus/cxl/devices/decoderX.Y/target_type
314Date: June, 2021
315KernelVersion: v5.14
316Contact: linux-cxl@vger.kernel.org
317Description:
318 (RO) When a CXL decoder is of devtype "cxl_decoder_switch", it
319 can optionally decode either accelerator memory (type-2) or
320 expander memory (type-3). The 'target_type' attribute indicates
321 the current setting which may dynamically change based on what
322 memory regions are activated in this decode hierarchy.
323
324
325What: /sys/bus/cxl/devices/endpointX/CDAT
326Date: July, 2022
327KernelVersion: v6.0
328Contact: linux-cxl@vger.kernel.org
329Description:
330 (RO) If this sysfs entry is not present no DOE mailbox was
331 found to support CDAT data. If it is present and the length of
332 the data is 0 reading the CDAT data failed. Otherwise the CDAT
333 data is reported.
334
335
336What: /sys/bus/cxl/devices/decoderX.Y/mode
337Date: May, 2022
338KernelVersion: v6.0
339Contact: linux-cxl@vger.kernel.org
340Description:
341 (RW) When a CXL decoder is of devtype "cxl_decoder_endpoint" it
342 translates from a host physical address range, to a device
343 local address range. Device-local address ranges are further
344 split into a 'ram' (volatile memory) range and 'pmem'
345 (persistent memory) range. The 'mode' attribute emits one of
346 'ram', 'pmem', or 'none'. The 'none' indicates the decoder is
347 not actively decoding, or no DPA allocation policy has been
348 set.
349
350 'mode' can be written, when the decoder is in the 'disabled'
351 state, with either 'ram' or 'pmem' to set the boundaries for the
352 next allocation.
353
354
355What: /sys/bus/cxl/devices/decoderX.Y/dpa_resource
356Date: May, 2022
357KernelVersion: v6.0
358Contact: linux-cxl@vger.kernel.org
359Description:
360 (RO) When a CXL decoder is of devtype "cxl_decoder_endpoint",
361 and its 'dpa_size' attribute is non-zero, this attribute
362 indicates the device physical address (DPA) base address of the
363 allocation.
364
365
366What: /sys/bus/cxl/devices/decoderX.Y/dpa_size
367Date: May, 2022
368KernelVersion: v6.0
369Contact: linux-cxl@vger.kernel.org
370Description:
371 (RW) When a CXL decoder is of devtype "cxl_decoder_endpoint" it
372 translates from a host physical address range, to a device local
373 address range. The range, base address plus length in bytes, of
374 DPA allocated to this decoder is conveyed in these 2 attributes.
375 Allocations can be mutated as long as the decoder is in the
376 disabled state. A write to 'dpa_size' releases the previous DPA
377 allocation and then attempts to allocate from the free capacity
378 in the device partition referred to by 'decoderX.Y/mode'.
379 Allocate and free requests can only be performed on the highest
380 instance number disabled decoder with non-zero size. I.e.
381 allocations are enforced to occur in increasing 'decoderX.Y/id'
382 order and frees are enforced to occur in decreasing
383 'decoderX.Y/id' order.
384
385
386What: /sys/bus/cxl/devices/decoderX.Y/interleave_ways
387Date: May, 2022
388KernelVersion: v6.0
389Contact: linux-cxl@vger.kernel.org
390Description:
391 (RO) The number of targets across which this decoder's host
392 physical address (HPA) memory range is interleaved. The device
393 maps every Nth block of HPA (of size ==
394 'interleave_granularity') to consecutive DPA addresses. The
395 decoder's position in the interleave is determined by the
396 device's (endpoint or switch) switch ancestry. For root
397 decoders their interleave is specified by platform firmware and
398 they only specify a downstream target order for host bridges.
399
400
401What: /sys/bus/cxl/devices/decoderX.Y/interleave_granularity
402Date: May, 2022
403KernelVersion: v6.0
404Contact: linux-cxl@vger.kernel.org
405Description:
406 (RO) The number of consecutive bytes of host physical address
407 space this decoder claims at address N before the decode rotates
408 to the next target in the interleave at address N +
409 interleave_granularity (assuming N is aligned to
410 interleave_granularity).
411
412
413What: /sys/bus/cxl/devices/decoderX.Y/create_{pmem,ram}_region
414Date: May, 2022, January, 2023
415KernelVersion: v6.0 (pmem), v6.3 (ram)
416Contact: linux-cxl@vger.kernel.org
417Description:
418 (RW) Write a string in the form 'regionZ' to start the process
419 of defining a new persistent, or volatile memory region
420 (interleave-set) within the decode range bounded by root decoder
421 'decoderX.Y'. The value written must match the current value
422 returned from reading this attribute. An atomic compare exchange
423 operation is done on write to assign the requested id to a
424 region and allocate the region-id for the next creation attempt.
425 EBUSY is returned if the region name written does not match the
426 current cached value.
427
428
429What: /sys/bus/cxl/devices/decoderX.Y/delete_region
430Date: May, 2022
431KernelVersion: v6.0
432Contact: linux-cxl@vger.kernel.org
433Description:
434 (WO) Write a string in the form 'regionZ' to delete that region,
435 provided it is currently idle / not bound to a driver.
436
437
438What: /sys/bus/cxl/devices/decoderX.Y/qos_class
439Date: May, 2023
440KernelVersion: v6.5
441Contact: linux-cxl@vger.kernel.org
442Description:
443 (RO) For CXL host platforms that support "QoS Telemetry" this
444 root-decoder-only attribute conveys a platform specific cookie
445 that identifies a QoS performance class for the CXL Window.
446 This class-id can be compared against a similar "qos_class"
447 published for each memory-type that an endpoint supports. While
448 it is not required that endpoints map their local memory-class
449 to a matching platform class, mismatches are not recommended and
450 there are platform specific side-effects that may result.
451
452
453What: /sys/bus/cxl/devices/regionZ/uuid
454Date: May, 2022
455KernelVersion: v6.0
456Contact: linux-cxl@vger.kernel.org
457Description:
458 (RW) Write a unique identifier for the region. This field must
459 be set for persistent regions and it must not conflict with the
460 UUID of another region. For volatile ram regions this
461 attribute is a read-only empty string.
462
463
464What: /sys/bus/cxl/devices/regionZ/interleave_granularity
465Date: May, 2022
466KernelVersion: v6.0
467Contact: linux-cxl@vger.kernel.org
468Description:
469 (RW) Set the number of consecutive bytes each device in the
470 interleave set will claim. The possible interleave granularity
471 values are determined by the CXL spec and the participating
472 devices.
473
474
475What: /sys/bus/cxl/devices/regionZ/interleave_ways
476Date: May, 2022
477KernelVersion: v6.0
478Contact: linux-cxl@vger.kernel.org
479Description:
480 (RW) Configures the number of devices participating in the
481 region is set by writing this value. Each device will provide
482 1/interleave_ways of storage for the region.
483
484
485What: /sys/bus/cxl/devices/regionZ/size
486Date: May, 2022
487KernelVersion: v6.0
488Contact: linux-cxl@vger.kernel.org
489Description:
490 (RW) System physical address space to be consumed by the region.
491 When written trigger the driver to allocate space out of the
492 parent root decoder's address space. When read the size of the
493 address space is reported and should match the span of the
494 region's resource attribute. Size shall be set after the
495 interleave configuration parameters. Once set it cannot be
496 changed, only freed by writing 0. The kernel makes no guarantees
497 that data is maintained over an address space freeing event, and
498 there is no guarantee that a free followed by an allocate
499 results in the same address being allocated. If extended linear
500 cache is present, the size indicates extended linear cache size
501 plus the CXL region size.
502
503What: /sys/bus/cxl/devices/regionZ/extended_linear_cache_size
504Date: October, 2025
505KernelVersion: v6.19
506Contact: linux-cxl@vger.kernel.org
507Description:
508 (RO) The size of extended linear cache, if there is an extended
509 linear cache. Otherwise the attribute will not be visible.
510
511
512What: /sys/bus/cxl/devices/regionZ/locked
513Date: Mar, 2026
514KernelVersion: v7.1
515Contact: linux-cxl@vger.kernel.org
516Description:
517 (RO) The CXL driver has the capability to lock a region based on
518 a BIOS or platform dependent configuration. Regions created as
519 locked are never permitted to be destroyed. Resets to participating
520 decoders will not result in a region destroy and will not free the
521 decoder resources.
522
523
524What: /sys/bus/cxl/devices/regionZ/mode
525Date: January, 2023
526KernelVersion: v6.3
527Contact: linux-cxl@vger.kernel.org
528Description:
529 (RO) The mode of a region is established at region creation time
530 and dictates the mode of the endpoint decoder that comprise the
531 region. For more details on the possible modes see
532 /sys/bus/cxl/devices/decoderX.Y/mode
533
534
535What: /sys/bus/cxl/devices/regionZ/resource
536Date: May, 2022
537KernelVersion: v6.0
538Contact: linux-cxl@vger.kernel.org
539Description:
540 (RO) A region is a contiguous partition of a CXL root decoder
541 address space. Region capacity is allocated by writing to the
542 size attribute, the resulting physical address space determined
543 by the driver is reflected here. It is therefore not useful to
544 read this before writing a value to the size attribute.
545
546
547What: /sys/bus/cxl/devices/regionZ/target[0..N]
548Date: May, 2022
549KernelVersion: v6.0
550Contact: linux-cxl@vger.kernel.org
551Description:
552 (RW) Write an endpoint decoder object name to 'targetX' where X
553 is the intended position of the endpoint device in the region
554 interleave and N is the 'interleave_ways' setting for the
555 region. ENXIO is returned if the write results in an impossible
556 to map decode scenario, like the endpoint is unreachable at that
557 position relative to the root decoder interleave. EBUSY is
558 returned if the position in the region is already occupied, or
559 if the region is not in a state to accept interleave
560 configuration changes. EINVAL is returned if the object name is
561 not an endpoint decoder. Once all positions have been
562 successfully written a final validation for decode conflicts is
563 performed before activating the region.
564
565
566What: /sys/bus/cxl/devices/regionZ/commit
567Date: May, 2022
568KernelVersion: v6.0
569Contact: linux-cxl@vger.kernel.org
570Description:
571 (RW) Write a boolean 'true' string value to this attribute to
572 trigger the region to transition from the software programmed
573 state to the actively decoding in hardware state. The commit
574 operation in addition to validating that the region is in proper
575 configured state, validates that the decoders are being
576 committed in spec mandated order (last committed decoder id +
577 1), and checks that the hardware accepts the commit request.
578 Reading this value indicates whether the region is committed or
579 not.
580
581
582What: /sys/bus/cxl/devices/memX/trigger_poison_list
583Date: April, 2023
584KernelVersion: v6.4
585Contact: linux-cxl@vger.kernel.org
586Description:
587 (WO) When a boolean 'true' is written to this attribute the
588 memdev driver retrieves the poison list from the device. The
589 list consists of addresses that are poisoned, or would result
590 in poison if accessed, and the source of the poison. This
591 attribute is only visible for devices supporting the
592 capability. The retrieved errors are logged as kernel
593 events when cxl_poison event tracing is enabled.
594
595
596What: /sys/bus/cxl/devices/regionZ/accessY/read_bandwidth
597 /sys/bus/cxl/devices/regionZ/accessY/write_bandwidth
598Date: Jan, 2024
599KernelVersion: v6.9
600Contact: linux-cxl@vger.kernel.org
601Description:
602 (RO) The aggregated read or write bandwidth of the region. The
603 number is the accumulated read or write bandwidth of all CXL memory
604 devices that contributes to the region in MB/s. It is
605 identical data that should appear in
606 /sys/devices/system/node/nodeX/accessY/initiators/read_bandwidth or
607 /sys/devices/system/node/nodeX/accessY/initiators/write_bandwidth.
608 See Documentation/ABI/stable/sysfs-devices-node. access0 provides
609 the number to the closest initiator and access1 provides the
610 number to the closest CPU.
611
612
613What: /sys/bus/cxl/devices/regionZ/accessY/read_latency
614 /sys/bus/cxl/devices/regionZ/accessY/write_latency
615Date: Jan, 2024
616KernelVersion: v6.9
617Contact: linux-cxl@vger.kernel.org
618Description:
619 (RO) The read or write latency of the region. The number is
620 the worst read or write latency of all CXL memory devices that
621 contributes to the region in nanoseconds. It is identical data
622 that should appear in
623 /sys/devices/system/node/nodeX/accessY/initiators/read_latency or
624 /sys/devices/system/node/nodeX/accessY/initiators/write_latency.
625 See Documentation/ABI/stable/sysfs-devices-node. access0 provides
626 the number to the closest initiator and access1 provides the
627 number to the closest CPU.
628
629
630What: /sys/bus/cxl/devices/nvdimm-bridge0/ndbusX/nmemY/cxl/dirty_shutdown
631Date: Feb, 2025
632KernelVersion: v6.15
633Contact: linux-cxl@vger.kernel.org
634Description:
635 (RO) The device dirty shutdown count value, which is the number
636 of times the device could have incurred in potential data loss.
637 The count is persistent across power loss and wraps back to 0
638 upon overflow. If this file is not present, the device does not
639 have the necessary support for dirty tracking.