Linux kernel mirror (for testing)
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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/google,gs101-clock.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Google GS101 SoC clock controller
8
9maintainers:
10 - Peter Griffin <peter.griffin@linaro.org>
11
12description: |
13 Google GS101 clock controller is comprised of several CMU units, generating
14 clocks for different domains. Those CMU units are modeled as separate device
15 tree nodes, and might depend on each other. The root clock in that clock tree
16 is OSCCLK (24.576 MHz). That external clock must be defined as a fixed-rate
17 clock in dts.
18
19 CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
20 dividers; all other leaf clocks (other CMUs) are usually derived from CMU_TOP.
21
22 Each clock is assigned an identifier and client nodes can use this identifier
23 to specify the clock which they consume. All clocks available for usage
24 in clock consumer nodes are defined as preprocessor macros in
25 'dt-bindings/clock/gs101.h' header.
26
27properties:
28 compatible:
29 enum:
30 - google,gs101-cmu-top
31 - google,gs101-cmu-apm
32 - google,gs101-cmu-dpu
33 - google,gs101-cmu-hsi0
34 - google,gs101-cmu-hsi2
35 - google,gs101-cmu-misc
36 - google,gs101-cmu-peric0
37 - google,gs101-cmu-peric1
38
39 clocks:
40 minItems: 1
41 maxItems: 5
42
43 clock-names:
44 minItems: 1
45 maxItems: 5
46
47 "#clock-cells":
48 const: 1
49
50 power-domains:
51 maxItems: 1
52
53 reg:
54 maxItems: 1
55
56 samsung,sysreg:
57 $ref: /schemas/types.yaml#/definitions/phandle
58 description:
59 Phandle to system registers interface.
60
61required:
62 - compatible
63 - "#clock-cells"
64 - clocks
65 - clock-names
66 - reg
67
68allOf:
69 - if:
70 properties:
71 compatible:
72 contains:
73 enum:
74 - google,gs101-cmu-top
75 - google,gs101-cmu-apm
76 then:
77 properties:
78 clocks:
79 items:
80 - description: External reference clock (24.576 MHz)
81
82 clock-names:
83 items:
84 - const: oscclk
85
86 - if:
87 properties:
88 compatible:
89 contains:
90 const: google,gs101-cmu-dpu
91
92 then:
93 properties:
94 clocks:
95 items:
96 - description: External reference clock (24.576 MHz)
97 - description: DPU bus clock (from CMU_TOP)
98
99 clock-names:
100 items:
101 - const: oscclk
102 - const: bus
103
104 - if:
105 properties:
106 compatible:
107 contains:
108 const: google,gs101-cmu-hsi0
109
110 then:
111 properties:
112 clocks:
113 items:
114 - description: External reference clock (24.576 MHz)
115 - description: HSI0 bus clock (from CMU_TOP)
116 - description: DPGTC (from CMU_TOP)
117 - description: USB DRD controller clock (from CMU_TOP)
118 - description: USB Display Port debug clock (from CMU_TOP)
119
120 clock-names:
121 items:
122 - const: oscclk
123 - const: bus
124 - const: dpgtc
125 - const: usb31drd
126 - const: usbdpdbg
127
128 - if:
129 properties:
130 compatible:
131 contains:
132 enum:
133 - google,gs101-cmu-hsi2
134
135 then:
136 properties:
137 clocks:
138 items:
139 - description: External reference clock (24.576 MHz)
140 - description: High Speed Interface bus clock (from CMU_TOP)
141 - description: High Speed Interface pcie clock (from CMU_TOP)
142 - description: High Speed Interface ufs clock (from CMU_TOP)
143 - description: High Speed Interface mmc clock (from CMU_TOP)
144
145 clock-names:
146 items:
147 - const: oscclk
148 - const: bus
149 - const: pcie
150 - const: ufs
151 - const: mmc
152
153 - if:
154 properties:
155 compatible:
156 contains:
157 const: google,gs101-cmu-misc
158
159 then:
160 properties:
161 clocks:
162 items:
163 - description: Misc bus clock (from CMU_TOP)
164 - description: Misc sss clock (from CMU_TOP)
165
166 clock-names:
167 items:
168 - const: bus
169 - const: sss
170
171 - if:
172 properties:
173 compatible:
174 contains:
175 enum:
176 - google,gs101-cmu-peric0
177 - google,gs101-cmu-peric1
178
179 then:
180 properties:
181 clocks:
182 items:
183 - description: External reference clock (24.576 MHz)
184 - description: Connectivity Peripheral 0/1 bus clock (from CMU_TOP)
185 - description: Connectivity Peripheral 0/1 IP clock (from CMU_TOP)
186
187 clock-names:
188 items:
189 - const: oscclk
190 - const: bus
191 - const: ip
192
193 - if:
194 properties:
195 compatible:
196 contains:
197 const: google,gs101-cmu-top
198 then:
199 properties:
200 samsung,sysreg: false
201 else:
202 required:
203 - samsung,sysreg
204
205additionalProperties: false
206
207examples:
208 # Clock controller node for CMU_TOP
209 - |
210 #include <dt-bindings/clock/google,gs101.h>
211
212 cmu_top: clock-controller@1e080000 {
213 compatible = "google,gs101-cmu-top";
214 reg = <0x1e080000 0x10000>;
215 #clock-cells = <1>;
216 clocks = <&ext_24_5m>;
217 clock-names = "oscclk";
218 };
219
220...