Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/memory-controllers/arm,pl172.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: ARM PL172/PL175/PL176 MultiPort Memory Controller
8
9maintainers:
10 - Frank Li <Frank.Li@nxp.com>
11
12# We need a select here so we don't match all nodes with 'arm,primecell'
13select:
14 properties:
15 compatible:
16 contains:
17 enum:
18 - arm,pl172
19 - arm,pl175
20 - arm,pl176
21 required:
22 - compatible
23
24properties:
25 compatible:
26 items:
27 - enum:
28 - arm,pl172
29 - arm,pl175
30 - arm,pl176
31 - const: arm,primecell
32
33 reg:
34 maxItems: 1
35
36 '#address-cells':
37 const: 2
38
39 '#size-cells':
40 const: 1
41
42 ranges: true
43
44 clocks:
45 maxItems: 2
46
47 clock-names:
48 items:
49 - const: mpmcclk
50 - const: apb_pclk
51
52 clock-ranges: true
53
54 resets:
55 maxItems: 1
56
57patternProperties:
58 "^cs[0-9]$":
59 type: object
60 additionalProperties: false
61 patternProperties:
62 "^flash@[0-9],[0-9a-f]+$":
63 type: object
64 $ref: /schemas/mtd/mtd-physmap.yaml#
65 unevaluatedProperties: false
66
67 "^(gpio|sram)@[0-9],[0-9a-f]+$":
68 type: object
69 additionalProperties: true
70
71 properties:
72 '#address-cells':
73 const: 2
74
75 '#size-cells':
76 const: 1
77
78 ranges: true
79
80 clocks:
81 maxItems: 2
82
83 clock-ranges: true
84
85 mpmc,cs:
86 $ref: /schemas/types.yaml#/definitions/uint32
87 description:
88 Chip select number. Indicates to the pl0172 driver
89 which chipselect is used for accessing the memory.
90
91 mpmc,memory-width:
92 $ref: /schemas/types.yaml#/definitions/uint32
93 enum: [8, 16, 32]
94 description:
95 Width of the chip select memory. Must be equal to either 8, 16 or 32.
96
97 mpmc,async-page-mode:
98 $ref: /schemas/types.yaml#/definitions/flag
99 description:
100 Enable asynchronous page mode.
101
102 mpmc,cs-active-high:
103 $ref: /schemas/types.yaml#/definitions/flag
104 description:
105 Set chip select polarity to active high.
106
107 mpmc,byte-lane-low:
108 $ref: /schemas/types.yaml#/definitions/flag
109 description:
110 Set byte lane state to low.
111
112 mpmc,extended-wait:
113 $ref: /schemas/types.yaml#/definitions/flag
114 description:
115 Enable extended wait.
116
117 mpmc,buffer-enable:
118 $ref: /schemas/types.yaml#/definitions/flag
119 description:
120 Enable write buffer, option is not supported by
121 PL175 and PL176 controllers.
122
123 mpmc,write-protect:
124 $ref: /schemas/types.yaml#/definitions/flag
125 description:
126 Enable write protect.
127
128 mpmc,read-enable-delay:
129 $ref: /schemas/types.yaml#/definitions/uint32
130 description:
131 Delay from chip select assertion to read
132 enable (RE signal) in nano seconds.
133
134 mpmc,write-enable-delay:
135 $ref: /schemas/types.yaml#/definitions/uint32
136 description:
137 Delay from chip select assertion to write
138 enable (WE signal) in nano seconds.
139
140 mpmc,output-enable-delay:
141 $ref: /schemas/types.yaml#/definitions/uint32
142 description:
143 Delay from chip select assertion to output
144 enable (OE signal) in nano seconds.
145
146 mpmc,write-access-delay:
147 $ref: /schemas/types.yaml#/definitions/uint32
148 description:
149 Delay from chip select assertion to write
150 access in nano seconds.
151
152 mpmc,read-access-delay:
153 $ref: /schemas/types.yaml#/definitions/uint32
154 description:
155 Delay from chip select assertion to read
156 access in nano seconds.
157
158 mpmc,page-mode-read-delay:
159 $ref: /schemas/types.yaml#/definitions/uint32
160 description:
161 Delay for asynchronous page mode sequential
162 accesses in nano seconds.
163
164 mpmc,turn-round-delay:
165 $ref: /schemas/types.yaml#/definitions/uint32
166 description:
167 Delay between access to memory banks in nano
168 seconds.
169
170required:
171 - compatible
172 - reg
173 - '#address-cells'
174 - '#size-cells'
175 - ranges
176 - clocks
177 - clock-names
178
179additionalProperties: false
180
181examples:
182 - |
183 #include <dt-bindings/clock/lpc18xx-ccu.h>
184
185 memory-controller@40005000 {
186 compatible = "arm,pl172", "arm,primecell";
187 reg = <0x40005000 0x1000>;
188 clocks = <&ccu1 CLK_CPU_EMCDIV>, <&ccu1 CLK_CPU_EMC>;
189 clock-names = "mpmcclk", "apb_pclk";
190 #address-cells = <2>;
191 #size-cells = <1>;
192 ranges = <0 0 0x1c000000 0x1000000
193 1 0 0x1d000000 0x1000000
194 2 0 0x1e000000 0x1000000
195 3 0 0x1f000000 0x1000000>;
196
197 cs0 {
198 #address-cells = <2>;
199 #size-cells = <1>;
200 ranges;
201
202 mpmc,cs = <0>;
203 mpmc,memory-width = <16>;
204 mpmc,byte-lane-low;
205 mpmc,write-enable-delay = <0>;
206 mpmc,output-enable-delay = <0>;
207 mpmc,read-enable-delay = <70>;
208 mpmc,page-mode-read-delay = <70>;
209
210 flash@0,0 {
211 compatible = "sst,sst39vf320", "cfi-flash";
212 reg = <0 0 0x400000>;
213 bank-width = <2>;
214 #address-cells = <1>;
215 #size-cells = <1>;
216 partition@0 {
217 label = "data";
218 reg = <0 0x400000>;
219 };
220 };
221 };
222 };