Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (C) 2022-2024, Advanced Micro Devices, Inc.
4 */
5
6#ifndef _AMDXDNA_CTX_H_
7#define _AMDXDNA_CTX_H_
8
9#include <linux/bitfield.h>
10
11#include "amdxdna_gem.h"
12
13struct amdxdna_hwctx_priv;
14
15enum ert_cmd_opcode {
16 ERT_START_CU = 0,
17 ERT_CMD_CHAIN = 19,
18 ERT_START_NPU = 20,
19 ERT_START_NPU_PREEMPT = 21,
20 ERT_START_NPU_PREEMPT_ELF = 22,
21 ERT_INVALID_CMD = ~0U,
22};
23
24enum ert_cmd_state {
25 ERT_CMD_STATE_INVALID,
26 ERT_CMD_STATE_NEW,
27 ERT_CMD_STATE_QUEUED,
28 ERT_CMD_STATE_RUNNING,
29 ERT_CMD_STATE_COMPLETED,
30 ERT_CMD_STATE_ERROR,
31 ERT_CMD_STATE_ABORT,
32 ERT_CMD_STATE_SUBMITTED,
33 ERT_CMD_STATE_TIMEOUT,
34 ERT_CMD_STATE_NORESPONSE,
35};
36
37/*
38 * Interpretation of the beginning of data payload for ERT_START_NPU in
39 * amdxdna_cmd. The rest of the payload in amdxdna_cmd is regular kernel args.
40 */
41struct amdxdna_cmd_start_npu {
42 u64 buffer; /* instruction buffer address */
43 u32 buffer_size; /* size of buffer in bytes */
44 u32 prop_count; /* properties count */
45 u32 prop_args[]; /* properties and regular kernel arguments */
46};
47
48/*
49 * Interpretation of the beginning of data payload for ERT_CMD_CHAIN in
50 * amdxdna_cmd. The rest of the payload in amdxdna_cmd is cmd BO handles.
51 */
52struct amdxdna_cmd_chain {
53 u32 command_count;
54 u32 submit_index;
55 u32 error_index;
56 u32 reserved[3];
57 u64 data[] __counted_by(command_count);
58};
59
60/*
61 * Interpretation of the beginning of data payload for ERT_START_NPU_PREEMPT in
62 * amdxdna_cmd. The rest of the payload in amdxdna_cmd is regular kernel args.
63 */
64struct amdxdna_cmd_preempt_data {
65 u64 inst_buf; /* instruction buffer address */
66 u64 save_buf; /* save buffer address */
67 u64 restore_buf; /* restore buffer address */
68 u32 inst_size; /* size of instruction buffer in bytes */
69 u32 save_size; /* size of save buffer in bytes */
70 u32 restore_size; /* size of restore buffer in bytes */
71 u32 inst_prop_cnt; /* properties count */
72 u32 prop_args[]; /* properties and regular kernel arguments */
73};
74
75#define AMDXDNA_CMD_CTX_HEALTH_V1 1
76#define AMDXDNA_CMD_CTX_HEALTH_AIE2 0
77struct amdxdna_ctx_health {
78 u32 version;
79 u32 npu_gen;
80};
81
82/* Exec buffer command header format */
83#define AMDXDNA_CMD_STATE GENMASK(3, 0)
84#define AMDXDNA_CMD_EXTRA_CU_MASK GENMASK(11, 10)
85#define AMDXDNA_CMD_COUNT GENMASK(22, 12)
86#define AMDXDNA_CMD_OPCODE GENMASK(27, 23)
87struct amdxdna_cmd {
88 u32 header;
89 u32 data[];
90};
91
92#define INVALID_CU_IDX (~0U)
93
94struct amdxdna_hwctx {
95 struct amdxdna_client *client;
96 struct amdxdna_hwctx_priv *priv;
97 char *name;
98
99 u32 id;
100 u32 max_opc;
101 u32 num_tiles;
102 u32 mem_size;
103 u32 fw_ctx_id;
104 u32 col_list_len;
105 u32 *col_list;
106 u32 start_col;
107 u32 num_col;
108 u32 num_unused_col;
109
110 struct amdxdna_qos_info qos;
111 struct amdxdna_hwctx_param_config_cu *cus;
112 u32 syncobj_hdl;
113
114 atomic64_t job_submit_cnt;
115 atomic64_t job_free_cnt ____cacheline_aligned_in_smp;
116};
117
118#define drm_job_to_xdna_job(j) \
119 container_of(j, struct amdxdna_sched_job, base)
120
121enum amdxdna_job_opcode {
122 SYNC_DEBUG_BO,
123 ATTACH_DEBUG_BO,
124 DETACH_DEBUG_BO,
125};
126
127struct amdxdna_drv_cmd {
128 enum amdxdna_job_opcode opcode;
129 u32 result;
130};
131
132struct app_health_report;
133union amdxdna_job_priv {
134 struct app_health_report *aie2_health;
135};
136
137struct amdxdna_sched_job {
138 struct drm_sched_job base;
139 struct kref refcnt;
140 struct amdxdna_hwctx *hwctx;
141 struct mm_struct *mm;
142 /* The fence to notice DRM scheduler that job is done by hardware */
143 struct dma_fence *fence;
144 /* user can wait on this fence */
145 struct dma_fence *out_fence;
146 bool job_done;
147 bool job_timeout;
148 u64 seq;
149 struct amdxdna_drv_cmd *drv_cmd;
150 struct amdxdna_gem_obj *cmd_bo;
151 union amdxdna_job_priv priv;
152 size_t bo_cnt;
153 struct drm_gem_object *bos[] __counted_by(bo_cnt);
154};
155
156#define aie2_job_health priv.aie2_health
157
158static inline u32
159amdxdna_cmd_get_op(struct amdxdna_gem_obj *abo)
160{
161 struct amdxdna_cmd *cmd = amdxdna_gem_vmap(abo);
162
163 if (!cmd)
164 return ERT_INVALID_CMD;
165
166 return FIELD_GET(AMDXDNA_CMD_OPCODE, cmd->header);
167}
168
169static inline void
170amdxdna_cmd_set_state(struct amdxdna_gem_obj *abo, enum ert_cmd_state s)
171{
172 struct amdxdna_cmd *cmd = amdxdna_gem_vmap(abo);
173
174 if (!cmd)
175 return;
176
177 cmd->header &= ~AMDXDNA_CMD_STATE;
178 cmd->header |= FIELD_PREP(AMDXDNA_CMD_STATE, s);
179}
180
181static inline enum ert_cmd_state
182amdxdna_cmd_get_state(struct amdxdna_gem_obj *abo)
183{
184 struct amdxdna_cmd *cmd = amdxdna_gem_vmap(abo);
185
186 if (!cmd)
187 return ERT_CMD_STATE_INVALID;
188
189 return FIELD_GET(AMDXDNA_CMD_STATE, cmd->header);
190}
191
192void *amdxdna_cmd_get_payload(struct amdxdna_gem_obj *abo, u32 *size);
193u32 amdxdna_cmd_get_cu_idx(struct amdxdna_gem_obj *abo);
194int amdxdna_cmd_set_error(struct amdxdna_gem_obj *abo,
195 struct amdxdna_sched_job *job, u32 cmd_idx,
196 enum ert_cmd_state error_state,
197 void *err_data, size_t size);
198
199void amdxdna_sched_job_cleanup(struct amdxdna_sched_job *job);
200void amdxdna_hwctx_remove_all(struct amdxdna_client *client);
201int amdxdna_hwctx_walk(struct amdxdna_client *client, void *arg,
202 int (*walk)(struct amdxdna_hwctx *hwctx, void *arg));
203int amdxdna_hwctx_sync_debug_bo(struct amdxdna_client *client, u32 debug_bo_hdl);
204
205int amdxdna_cmd_submit(struct amdxdna_client *client,
206 struct amdxdna_drv_cmd *drv_cmd, u32 cmd_bo_hdls,
207 u32 *arg_bo_hdls, u32 arg_bo_cnt,
208 u32 hwctx_hdl, u64 *seq);
209
210int amdxdna_cmd_wait(struct amdxdna_client *client, u32 hwctx_hdl,
211 u64 seq, u32 timeout);
212
213int amdxdna_drm_create_hwctx_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
214int amdxdna_drm_config_hwctx_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
215int amdxdna_drm_destroy_hwctx_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
216int amdxdna_drm_submit_cmd_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
217
218#endif /* _AMDXDNA_CTX_H_ */