Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
4 * Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao@linaro.org>
5 * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
6 *
7 * Adjustable divider clock implementation
8 */
9
10#include <linux/clk-provider.h>
11#include <linux/device.h>
12#include <linux/module.h>
13#include <linux/slab.h>
14#include <linux/io.h>
15#include <linux/err.h>
16#include <linux/string.h>
17#include <linux/log2.h>
18
19/*
20 * DOC: basic adjustable divider clock that cannot gate
21 *
22 * Traits of this clock:
23 * prepare - clk_prepare only ensures that parents are prepared
24 * enable - clk_enable only ensures that parents are enabled
25 * rate - rate is adjustable. clk->rate = ceiling(parent->rate / divisor)
26 * parent - fixed parent. No clk_set_parent support
27 */
28
29static inline u32 clk_div_readl(struct clk_divider *divider)
30{
31 if (divider->flags & CLK_DIVIDER_BIG_ENDIAN)
32 return ioread32be(divider->reg);
33
34 return readl(divider->reg);
35}
36
37static inline void clk_div_writel(struct clk_divider *divider, u32 val)
38{
39 if (divider->flags & CLK_DIVIDER_BIG_ENDIAN)
40 iowrite32be(val, divider->reg);
41 else
42 writel(val, divider->reg);
43}
44
45static unsigned int _get_table_maxdiv(const struct clk_div_table *table,
46 u8 width)
47{
48 unsigned int maxdiv = 0, mask = clk_div_mask(width);
49 const struct clk_div_table *clkt;
50
51 for (clkt = table; clkt->div; clkt++)
52 if (clkt->div > maxdiv && clkt->val <= mask)
53 maxdiv = clkt->div;
54 return maxdiv;
55}
56
57static unsigned int _get_table_mindiv(const struct clk_div_table *table)
58{
59 unsigned int mindiv = UINT_MAX;
60 const struct clk_div_table *clkt;
61
62 for (clkt = table; clkt->div; clkt++)
63 if (clkt->div < mindiv)
64 mindiv = clkt->div;
65 return mindiv;
66}
67
68static unsigned int _get_maxdiv(const struct clk_div_table *table, u8 width,
69 unsigned long flags)
70{
71 if (flags & CLK_DIVIDER_ONE_BASED)
72 return clk_div_mask(width);
73 if (flags & CLK_DIVIDER_POWER_OF_TWO)
74 return 1 << clk_div_mask(width);
75 if (flags & CLK_DIVIDER_EVEN_INTEGERS)
76 return 2 * (clk_div_mask(width) + 1);
77 if (table)
78 return _get_table_maxdiv(table, width);
79 return clk_div_mask(width) + 1;
80}
81
82static unsigned int _get_table_div(const struct clk_div_table *table,
83 unsigned int val)
84{
85 const struct clk_div_table *clkt;
86
87 for (clkt = table; clkt->div; clkt++)
88 if (clkt->val == val)
89 return clkt->div;
90 return 0;
91}
92
93static unsigned int _get_div(const struct clk_div_table *table,
94 unsigned int val, unsigned long flags, u8 width)
95{
96 if (flags & CLK_DIVIDER_ONE_BASED)
97 return val;
98 if (flags & CLK_DIVIDER_POWER_OF_TWO)
99 return 1 << val;
100 if (flags & CLK_DIVIDER_MAX_AT_ZERO)
101 return val ? val : clk_div_mask(width) + 1;
102 if (flags & CLK_DIVIDER_EVEN_INTEGERS)
103 return 2 * (val + 1);
104 if (table)
105 return _get_table_div(table, val);
106 return val + 1;
107}
108
109static unsigned int _get_table_val(const struct clk_div_table *table,
110 unsigned int div)
111{
112 const struct clk_div_table *clkt;
113
114 for (clkt = table; clkt->div; clkt++)
115 if (clkt->div == div)
116 return clkt->val;
117 return 0;
118}
119
120static unsigned int _get_val(const struct clk_div_table *table,
121 unsigned int div, unsigned long flags, u8 width)
122{
123 if (flags & CLK_DIVIDER_ONE_BASED)
124 return div;
125 if (flags & CLK_DIVIDER_POWER_OF_TWO)
126 return __ffs(div);
127 if (flags & CLK_DIVIDER_MAX_AT_ZERO)
128 return (div == clk_div_mask(width) + 1) ? 0 : div;
129 if (flags & CLK_DIVIDER_EVEN_INTEGERS)
130 return (div >> 1) - 1;
131 if (table)
132 return _get_table_val(table, div);
133 return div - 1;
134}
135
136unsigned long divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate,
137 unsigned int val,
138 const struct clk_div_table *table,
139 unsigned long flags, unsigned long width)
140{
141 unsigned int div;
142
143 div = _get_div(table, val, flags, width);
144 if (!div) {
145 WARN(!(flags & CLK_DIVIDER_ALLOW_ZERO),
146 "%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n",
147 clk_hw_get_name(hw));
148 return parent_rate;
149 }
150
151 return DIV_ROUND_UP_ULL((u64)parent_rate, div);
152}
153EXPORT_SYMBOL_GPL(divider_recalc_rate);
154
155static unsigned long clk_divider_recalc_rate(struct clk_hw *hw,
156 unsigned long parent_rate)
157{
158 struct clk_divider *divider = to_clk_divider(hw);
159 unsigned int val;
160
161 val = clk_div_readl(divider) >> divider->shift;
162 val &= clk_div_mask(divider->width);
163
164 return divider_recalc_rate(hw, parent_rate, val, divider->table,
165 divider->flags, divider->width);
166}
167
168static bool _is_valid_table_div(const struct clk_div_table *table,
169 unsigned int div)
170{
171 const struct clk_div_table *clkt;
172
173 for (clkt = table; clkt->div; clkt++)
174 if (clkt->div == div)
175 return true;
176 return false;
177}
178
179static bool _is_valid_div(const struct clk_div_table *table, unsigned int div,
180 unsigned long flags)
181{
182 if (flags & CLK_DIVIDER_POWER_OF_TWO)
183 return is_power_of_2(div);
184 if (table)
185 return _is_valid_table_div(table, div);
186 return true;
187}
188
189static int _round_up_table(const struct clk_div_table *table, int div)
190{
191 const struct clk_div_table *clkt;
192 int up = INT_MAX;
193
194 for (clkt = table; clkt->div; clkt++) {
195 if (clkt->div == div)
196 return clkt->div;
197 else if (clkt->div < div)
198 continue;
199
200 if ((clkt->div - div) < (up - div))
201 up = clkt->div;
202 }
203
204 return up;
205}
206
207static int _round_down_table(const struct clk_div_table *table, int div)
208{
209 const struct clk_div_table *clkt;
210 int down = _get_table_mindiv(table);
211
212 for (clkt = table; clkt->div; clkt++) {
213 if (clkt->div == div)
214 return clkt->div;
215 else if (clkt->div > div)
216 continue;
217
218 if ((div - clkt->div) < (div - down))
219 down = clkt->div;
220 }
221
222 return down;
223}
224
225static int _div_round_up(const struct clk_div_table *table,
226 unsigned long parent_rate, unsigned long rate,
227 unsigned long flags)
228{
229 int div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
230
231 if (flags & CLK_DIVIDER_POWER_OF_TWO)
232 div = __roundup_pow_of_two(div);
233 if (table)
234 div = _round_up_table(table, div);
235
236 return div;
237}
238
239static int _div_round_closest(const struct clk_div_table *table,
240 unsigned long parent_rate, unsigned long rate,
241 unsigned long flags)
242{
243 int up, down;
244 unsigned long up_rate, down_rate;
245
246 up = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
247 down = parent_rate / rate;
248
249 if (flags & CLK_DIVIDER_POWER_OF_TWO) {
250 up = __roundup_pow_of_two(up);
251 down = __rounddown_pow_of_two(down);
252 } else if (table) {
253 up = _round_up_table(table, up);
254 down = _round_down_table(table, down);
255 }
256
257 up_rate = DIV_ROUND_UP_ULL((u64)parent_rate, up);
258 down_rate = DIV_ROUND_UP_ULL((u64)parent_rate, down);
259
260 return (rate - up_rate) <= (down_rate - rate) ? up : down;
261}
262
263static int _div_round(const struct clk_div_table *table,
264 unsigned long parent_rate, unsigned long rate,
265 unsigned long flags)
266{
267 if (flags & CLK_DIVIDER_ROUND_CLOSEST)
268 return _div_round_closest(table, parent_rate, rate, flags);
269
270 return _div_round_up(table, parent_rate, rate, flags);
271}
272
273static bool _is_best_div(unsigned long rate, unsigned long now,
274 unsigned long best, unsigned long flags)
275{
276 if (flags & CLK_DIVIDER_ROUND_CLOSEST)
277 return abs(rate - now) < abs(rate - best);
278
279 return now <= rate && now > best;
280}
281
282static int _next_div(const struct clk_div_table *table, int div,
283 unsigned long flags)
284{
285 div++;
286
287 if (flags & CLK_DIVIDER_POWER_OF_TWO)
288 return __roundup_pow_of_two(div);
289 if (table)
290 return _round_up_table(table, div);
291
292 return div;
293}
294
295static int clk_divider_bestdiv(struct clk_hw *hw, struct clk_hw *parent,
296 unsigned long rate,
297 unsigned long *best_parent_rate,
298 const struct clk_div_table *table, u8 width,
299 unsigned long flags)
300{
301 int i, bestdiv = 0;
302 unsigned long parent_rate, best = 0, now, maxdiv;
303 unsigned long parent_rate_saved = *best_parent_rate;
304
305 if (!rate)
306 rate = 1;
307
308 maxdiv = _get_maxdiv(table, width, flags);
309
310 if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) {
311 parent_rate = *best_parent_rate;
312 bestdiv = _div_round(table, parent_rate, rate, flags);
313 bestdiv = bestdiv == 0 ? 1 : bestdiv;
314 bestdiv = bestdiv > maxdiv ? maxdiv : bestdiv;
315 return bestdiv;
316 }
317
318 /*
319 * The maximum divider we can use without overflowing
320 * unsigned long in rate * i below
321 */
322 maxdiv = min(ULONG_MAX / rate, maxdiv);
323
324 for (i = _next_div(table, 0, flags); i <= maxdiv;
325 i = _next_div(table, i, flags)) {
326 if (rate * i == parent_rate_saved) {
327 /*
328 * It's the most ideal case if the requested rate can be
329 * divided from parent clock without needing to change
330 * parent rate, so return the divider immediately.
331 */
332 *best_parent_rate = parent_rate_saved;
333 return i;
334 }
335 parent_rate = clk_hw_round_rate(parent, rate * i);
336 now = DIV_ROUND_UP_ULL((u64)parent_rate, i);
337 if (_is_best_div(rate, now, best, flags)) {
338 bestdiv = i;
339 best = now;
340 *best_parent_rate = parent_rate;
341 }
342 }
343
344 if (!bestdiv) {
345 bestdiv = _get_maxdiv(table, width, flags);
346 *best_parent_rate = clk_hw_round_rate(parent, 1);
347 }
348
349 return bestdiv;
350}
351
352int divider_determine_rate(struct clk_hw *hw, struct clk_rate_request *req,
353 const struct clk_div_table *table, u8 width,
354 unsigned long flags)
355{
356 int div;
357
358 div = clk_divider_bestdiv(hw, req->best_parent_hw, req->rate,
359 &req->best_parent_rate, table, width, flags);
360
361 req->rate = DIV_ROUND_UP_ULL((u64)req->best_parent_rate, div);
362
363 return 0;
364}
365EXPORT_SYMBOL_GPL(divider_determine_rate);
366
367int divider_ro_determine_rate(struct clk_hw *hw, struct clk_rate_request *req,
368 const struct clk_div_table *table, u8 width,
369 unsigned long flags, unsigned int val)
370{
371 int div;
372
373 div = _get_div(table, val, flags, width);
374
375 /* Even a read-only clock can propagate a rate change */
376 if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {
377 if (!req->best_parent_hw)
378 return -EINVAL;
379
380 req->best_parent_rate = clk_hw_round_rate(req->best_parent_hw,
381 req->rate * div);
382 }
383
384 req->rate = DIV_ROUND_UP_ULL((u64)req->best_parent_rate, div);
385
386 return 0;
387}
388EXPORT_SYMBOL_GPL(divider_ro_determine_rate);
389
390static int clk_divider_determine_rate(struct clk_hw *hw,
391 struct clk_rate_request *req)
392{
393 struct clk_divider *divider = to_clk_divider(hw);
394
395 /* if read only, just return current value */
396 if (divider->flags & CLK_DIVIDER_READ_ONLY) {
397 u32 val;
398
399 val = clk_div_readl(divider) >> divider->shift;
400 val &= clk_div_mask(divider->width);
401
402 return divider_ro_determine_rate(hw, req, divider->table,
403 divider->width,
404 divider->flags, val);
405 }
406
407 return divider_determine_rate(hw, req, divider->table, divider->width,
408 divider->flags);
409}
410
411int divider_get_val(unsigned long rate, unsigned long parent_rate,
412 const struct clk_div_table *table, u8 width,
413 unsigned long flags)
414{
415 unsigned int div, value;
416
417 div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
418
419 if (!_is_valid_div(table, div, flags))
420 return -EINVAL;
421
422 value = _get_val(table, div, flags, width);
423
424 return min_t(unsigned int, value, clk_div_mask(width));
425}
426EXPORT_SYMBOL_GPL(divider_get_val);
427
428static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
429 unsigned long parent_rate)
430{
431 struct clk_divider *divider = to_clk_divider(hw);
432 int value;
433 unsigned long flags = 0;
434 u32 val;
435
436 value = divider_get_val(rate, parent_rate, divider->table,
437 divider->width, divider->flags);
438 if (value < 0)
439 return value;
440
441 if (divider->lock)
442 spin_lock_irqsave(divider->lock, flags);
443 else
444 __acquire(divider->lock);
445
446 if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {
447 val = clk_div_mask(divider->width) << (divider->shift + 16);
448 } else {
449 val = clk_div_readl(divider);
450 val &= ~(clk_div_mask(divider->width) << divider->shift);
451 }
452 val |= (u32)value << divider->shift;
453 clk_div_writel(divider, val);
454
455 if (divider->lock)
456 spin_unlock_irqrestore(divider->lock, flags);
457 else
458 __release(divider->lock);
459
460 return 0;
461}
462
463const struct clk_ops clk_divider_ops = {
464 .recalc_rate = clk_divider_recalc_rate,
465 .determine_rate = clk_divider_determine_rate,
466 .set_rate = clk_divider_set_rate,
467};
468EXPORT_SYMBOL_GPL(clk_divider_ops);
469
470const struct clk_ops clk_divider_ro_ops = {
471 .recalc_rate = clk_divider_recalc_rate,
472 .determine_rate = clk_divider_determine_rate,
473};
474EXPORT_SYMBOL_GPL(clk_divider_ro_ops);
475
476struct clk_hw *__clk_hw_register_divider(struct device *dev,
477 struct device_node *np, const char *name,
478 const char *parent_name, const struct clk_hw *parent_hw,
479 const struct clk_parent_data *parent_data, unsigned long flags,
480 void __iomem *reg, u8 shift, u8 width,
481 unsigned long clk_divider_flags,
482 const struct clk_div_table *table, spinlock_t *lock)
483{
484 struct clk_divider *div;
485 struct clk_hw *hw;
486 struct clk_init_data init = {};
487 int ret;
488
489 if (clk_divider_flags & CLK_DIVIDER_HIWORD_MASK) {
490 if (width + shift > 16) {
491 pr_warn("divider value exceeds LOWORD field\n");
492 return ERR_PTR(-EINVAL);
493 }
494 }
495
496 /* allocate the divider */
497 div = kzalloc_obj(*div);
498 if (!div)
499 return ERR_PTR(-ENOMEM);
500
501 init.name = name;
502 if (clk_divider_flags & CLK_DIVIDER_READ_ONLY)
503 init.ops = &clk_divider_ro_ops;
504 else
505 init.ops = &clk_divider_ops;
506 init.flags = flags;
507 init.parent_names = parent_name ? &parent_name : NULL;
508 init.parent_hws = parent_hw ? &parent_hw : NULL;
509 init.parent_data = parent_data;
510 if (parent_name || parent_hw || parent_data)
511 init.num_parents = 1;
512 else
513 init.num_parents = 0;
514
515 /* struct clk_divider assignments */
516 div->reg = reg;
517 div->shift = shift;
518 div->width = width;
519 div->flags = clk_divider_flags;
520 div->lock = lock;
521 div->hw.init = &init;
522 div->table = table;
523
524 /* register the clock */
525 hw = &div->hw;
526 ret = clk_hw_register(dev, hw);
527 if (ret) {
528 kfree(div);
529 hw = ERR_PTR(ret);
530 }
531
532 return hw;
533}
534EXPORT_SYMBOL_GPL(__clk_hw_register_divider);
535
536/**
537 * clk_register_divider_table - register a table based divider clock with
538 * the clock framework
539 * @dev: device registering this clock
540 * @name: name of this clock
541 * @parent_name: name of clock's parent
542 * @flags: framework-specific flags
543 * @reg: register address to adjust divider
544 * @shift: number of bits to shift the bitfield
545 * @width: width of the bitfield
546 * @clk_divider_flags: divider-specific flags for this clock
547 * @table: array of divider/value pairs ending with a div set to 0
548 * @lock: shared register lock for this clock
549 */
550struct clk *clk_register_divider_table(struct device *dev, const char *name,
551 const char *parent_name, unsigned long flags,
552 void __iomem *reg, u8 shift, u8 width,
553 unsigned long clk_divider_flags,
554 const struct clk_div_table *table, spinlock_t *lock)
555{
556 struct clk_hw *hw;
557
558 hw = __clk_hw_register_divider(dev, NULL, name, parent_name, NULL,
559 NULL, flags, reg, shift, width, clk_divider_flags,
560 table, lock);
561 if (IS_ERR(hw))
562 return ERR_CAST(hw);
563 return hw->clk;
564}
565EXPORT_SYMBOL_GPL(clk_register_divider_table);
566
567void clk_unregister_divider(struct clk *clk)
568{
569 struct clk_divider *div;
570 struct clk_hw *hw;
571
572 hw = __clk_get_hw(clk);
573 if (!hw)
574 return;
575
576 div = to_clk_divider(hw);
577
578 clk_unregister(clk);
579 kfree(div);
580}
581EXPORT_SYMBOL_GPL(clk_unregister_divider);
582
583/**
584 * clk_hw_unregister_divider - unregister a clk divider
585 * @hw: hardware-specific clock data to unregister
586 */
587void clk_hw_unregister_divider(struct clk_hw *hw)
588{
589 struct clk_divider *div;
590
591 div = to_clk_divider(hw);
592
593 clk_hw_unregister(hw);
594 kfree(div);
595}
596EXPORT_SYMBOL_GPL(clk_hw_unregister_divider);
597
598static void devm_clk_hw_release_divider(struct device *dev, void *res)
599{
600 clk_hw_unregister_divider(*(struct clk_hw **)res);
601}
602
603struct clk_hw *__devm_clk_hw_register_divider(struct device *dev,
604 struct device_node *np, const char *name,
605 const char *parent_name, const struct clk_hw *parent_hw,
606 const struct clk_parent_data *parent_data, unsigned long flags,
607 void __iomem *reg, u8 shift, u8 width,
608 unsigned long clk_divider_flags,
609 const struct clk_div_table *table, spinlock_t *lock)
610{
611 struct clk_hw **ptr, *hw;
612
613 ptr = devres_alloc(devm_clk_hw_release_divider, sizeof(*ptr), GFP_KERNEL);
614 if (!ptr)
615 return ERR_PTR(-ENOMEM);
616
617 hw = __clk_hw_register_divider(dev, np, name, parent_name, parent_hw,
618 parent_data, flags, reg, shift, width,
619 clk_divider_flags, table, lock);
620
621 if (!IS_ERR(hw)) {
622 *ptr = hw;
623 devres_add(dev, ptr);
624 } else {
625 devres_free(ptr);
626 }
627
628 return hw;
629}
630EXPORT_SYMBOL_GPL(__devm_clk_hw_register_divider);