Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Amlogic Meson-G12A Clock Controller Driver
4 *
5 * Copyright (c) 2016 Baylibre SAS.
6 * Author: Michael Turquette <mturquette@baylibre.com>
7 *
8 * Copyright (c) 2018 Amlogic, inc.
9 * Author: Qiufang Dai <qiufang.dai@amlogic.com>
10 * Author: Jian Hu <jian.hu@amlogic.com>
11 */
12
13#include <linux/clk-provider.h>
14#include <linux/init.h>
15#include <linux/of.h>
16#include <linux/platform_device.h>
17#include <linux/clk.h>
18#include <linux/module.h>
19
20#include "clk-mpll.h"
21#include "clk-pll.h"
22#include "clk-regmap.h"
23#include "clk-cpu-dyndiv.h"
24#include "vid-pll-div.h"
25#include "vclk.h"
26#include "meson-clkc-utils.h"
27
28#include <dt-bindings/clock/g12a-clkc.h>
29
30#define HHI_MIPI_CNTL0 0x000
31#define HHI_MIPI_CNTL1 0x004
32#define HHI_MIPI_CNTL2 0x008
33#define HHI_MIPI_STS 0x00c
34#define HHI_GP0_PLL_CNTL0 0x040
35#define HHI_GP0_PLL_CNTL1 0x044
36#define HHI_GP0_PLL_CNTL2 0x048
37#define HHI_GP0_PLL_CNTL3 0x04c
38#define HHI_GP0_PLL_CNTL4 0x050
39#define HHI_GP0_PLL_CNTL5 0x054
40#define HHI_GP0_PLL_CNTL6 0x058
41#define HHI_GP0_PLL_STS 0x05c
42#define HHI_GP1_PLL_CNTL0 0x060
43#define HHI_GP1_PLL_CNTL1 0x064
44#define HHI_GP1_PLL_CNTL2 0x068
45#define HHI_GP1_PLL_CNTL3 0x06c
46#define HHI_GP1_PLL_CNTL4 0x070
47#define HHI_GP1_PLL_CNTL5 0x074
48#define HHI_GP1_PLL_CNTL6 0x078
49#define HHI_GP1_PLL_STS 0x07c
50#define HHI_PCIE_PLL_CNTL0 0x098
51#define HHI_PCIE_PLL_CNTL1 0x09c
52#define HHI_PCIE_PLL_CNTL2 0x0a0
53#define HHI_PCIE_PLL_CNTL3 0x0a4
54#define HHI_PCIE_PLL_CNTL4 0x0a8
55#define HHI_PCIE_PLL_CNTL5 0x0ac
56#define HHI_PCIE_PLL_STS 0x0b8
57#define HHI_HIFI_PLL_CNTL0 0x0d8
58#define HHI_HIFI_PLL_CNTL1 0x0dc
59#define HHI_HIFI_PLL_CNTL2 0x0e0
60#define HHI_HIFI_PLL_CNTL3 0x0e4
61#define HHI_HIFI_PLL_CNTL4 0x0e8
62#define HHI_HIFI_PLL_CNTL5 0x0ec
63#define HHI_HIFI_PLL_CNTL6 0x0f0
64#define HHI_VIID_CLK_DIV 0x128
65#define HHI_VIID_CLK_CNTL 0x12c
66#define HHI_GCLK_MPEG0 0x140
67#define HHI_GCLK_MPEG1 0x144
68#define HHI_GCLK_MPEG2 0x148
69#define HHI_GCLK_OTHER 0x150
70#define HHI_GCLK_OTHER2 0x154
71#define HHI_SYS_CPU_CLK_CNTL1 0x15c
72#define HHI_VID_CLK_DIV 0x164
73#define HHI_MPEG_CLK_CNTL 0x174
74#define HHI_AUD_CLK_CNTL 0x178
75#define HHI_VID_CLK_CNTL 0x17c
76#define HHI_TS_CLK_CNTL 0x190
77#define HHI_VID_CLK_CNTL2 0x194
78#define HHI_SYS_CPU_CLK_CNTL0 0x19c
79#define HHI_VID_PLL_CLK_DIV 0x1a0
80#define HHI_MALI_CLK_CNTL 0x1b0
81#define HHI_VPU_CLKC_CNTL 0x1b4
82#define HHI_VPU_CLK_CNTL 0x1bc
83#define HHI_ISP_CLK_CNTL 0x1c0
84#define HHI_NNA_CLK_CNTL 0x1c8
85#define HHI_HDMI_CLK_CNTL 0x1cc
86#define HHI_VDEC_CLK_CNTL 0x1e0
87#define HHI_VDEC2_CLK_CNTL 0x1e4
88#define HHI_VDEC3_CLK_CNTL 0x1e8
89#define HHI_VDEC4_CLK_CNTL 0x1ec
90#define HHI_HDCP22_CLK_CNTL 0x1f0
91#define HHI_VAPBCLK_CNTL 0x1f4
92#define HHI_SYS_CPUB_CLK_CNTL1 0x200
93#define HHI_SYS_CPUB_CLK_CNTL 0x208
94#define HHI_VPU_CLKB_CNTL 0x20c
95#define HHI_SYS_CPU_CLK_CNTL2 0x210
96#define HHI_SYS_CPU_CLK_CNTL3 0x214
97#define HHI_SYS_CPU_CLK_CNTL4 0x218
98#define HHI_SYS_CPU_CLK_CNTL5 0x21c
99#define HHI_SYS_CPU_CLK_CNTL6 0x220
100#define HHI_GEN_CLK_CNTL 0x228
101#define HHI_VDIN_MEAS_CLK_CNTL 0x250
102#define HHI_MIPIDSI_PHY_CLK_CNTL 0x254
103#define HHI_NAND_CLK_CNTL 0x25c
104#define HHI_SD_EMMC_CLK_CNTL 0x264
105#define HHI_MPLL_CNTL0 0x278
106#define HHI_MPLL_CNTL1 0x27c
107#define HHI_MPLL_CNTL2 0x280
108#define HHI_MPLL_CNTL3 0x284
109#define HHI_MPLL_CNTL4 0x288
110#define HHI_MPLL_CNTL5 0x28c
111#define HHI_MPLL_CNTL6 0x290
112#define HHI_MPLL_CNTL7 0x294
113#define HHI_MPLL_CNTL8 0x298
114#define HHI_FIX_PLL_CNTL0 0x2a0
115#define HHI_FIX_PLL_CNTL1 0x2a4
116#define HHI_FIX_PLL_CNTL3 0x2ac
117#define HHI_SYS_PLL_CNTL0 0x2f4
118#define HHI_SYS_PLL_CNTL1 0x2f8
119#define HHI_SYS_PLL_CNTL2 0x2fc
120#define HHI_SYS_PLL_CNTL3 0x300
121#define HHI_SYS_PLL_CNTL4 0x304
122#define HHI_SYS_PLL_CNTL5 0x308
123#define HHI_SYS_PLL_CNTL6 0x30c
124#define HHI_HDMI_PLL_CNTL0 0x320
125#define HHI_HDMI_PLL_CNTL1 0x324
126#define HHI_HDMI_PLL_CNTL2 0x328
127#define HHI_HDMI_PLL_CNTL3 0x32c
128#define HHI_HDMI_PLL_CNTL4 0x330
129#define HHI_HDMI_PLL_CNTL5 0x334
130#define HHI_HDMI_PLL_CNTL6 0x338
131#define HHI_SPICC_CLK_CNTL 0x3dc
132#define HHI_SYS1_PLL_CNTL0 0x380
133#define HHI_SYS1_PLL_CNTL1 0x384
134#define HHI_SYS1_PLL_CNTL2 0x388
135#define HHI_SYS1_PLL_CNTL3 0x38c
136#define HHI_SYS1_PLL_CNTL4 0x390
137#define HHI_SYS1_PLL_CNTL5 0x394
138#define HHI_SYS1_PLL_CNTL6 0x398
139
140static struct clk_regmap g12a_fixed_pll_dco = {
141 .data = &(struct meson_clk_pll_data){
142 .en = {
143 .reg_off = HHI_FIX_PLL_CNTL0,
144 .shift = 28,
145 .width = 1,
146 },
147 .m = {
148 .reg_off = HHI_FIX_PLL_CNTL0,
149 .shift = 0,
150 .width = 8,
151 },
152 .n = {
153 .reg_off = HHI_FIX_PLL_CNTL0,
154 .shift = 10,
155 .width = 5,
156 },
157 .frac = {
158 .reg_off = HHI_FIX_PLL_CNTL1,
159 .shift = 0,
160 .width = 17,
161 },
162 .l = {
163 .reg_off = HHI_FIX_PLL_CNTL0,
164 .shift = 31,
165 .width = 1,
166 },
167 .rst = {
168 .reg_off = HHI_FIX_PLL_CNTL0,
169 .shift = 29,
170 .width = 1,
171 },
172 },
173 .hw.init = &(struct clk_init_data){
174 .name = "fixed_pll_dco",
175 .ops = &meson_clk_pll_ro_ops,
176 .parent_data = &(const struct clk_parent_data) {
177 .fw_name = "xtal",
178 },
179 .num_parents = 1,
180 },
181};
182
183static struct clk_regmap g12a_fixed_pll = {
184 .data = &(struct clk_regmap_div_data){
185 .offset = HHI_FIX_PLL_CNTL0,
186 .shift = 16,
187 .width = 2,
188 .flags = CLK_DIVIDER_POWER_OF_TWO,
189 },
190 .hw.init = &(struct clk_init_data){
191 .name = "fixed_pll",
192 .ops = &clk_regmap_divider_ro_ops,
193 .parent_hws = (const struct clk_hw *[]) {
194 &g12a_fixed_pll_dco.hw
195 },
196 .num_parents = 1,
197 /*
198 * This clock won't ever change at runtime so
199 * CLK_SET_RATE_PARENT is not required
200 */
201 },
202};
203
204static const struct pll_mult_range g12a_sys_pll_mult_range = {
205 .min = 128,
206 .max = 250,
207};
208
209static struct clk_regmap g12a_sys_pll_dco = {
210 .data = &(struct meson_clk_pll_data){
211 .en = {
212 .reg_off = HHI_SYS_PLL_CNTL0,
213 .shift = 28,
214 .width = 1,
215 },
216 .m = {
217 .reg_off = HHI_SYS_PLL_CNTL0,
218 .shift = 0,
219 .width = 8,
220 },
221 .n = {
222 .reg_off = HHI_SYS_PLL_CNTL0,
223 .shift = 10,
224 .width = 5,
225 },
226 .l = {
227 .reg_off = HHI_SYS_PLL_CNTL0,
228 .shift = 31,
229 .width = 1,
230 },
231 .rst = {
232 .reg_off = HHI_SYS_PLL_CNTL0,
233 .shift = 29,
234 .width = 1,
235 },
236 .range = &g12a_sys_pll_mult_range,
237 },
238 .hw.init = &(struct clk_init_data){
239 .name = "sys_pll_dco",
240 .ops = &meson_clk_pll_ops,
241 .parent_data = &(const struct clk_parent_data) {
242 .fw_name = "xtal",
243 },
244 .num_parents = 1,
245 /* This clock feeds the CPU, avoid disabling it */
246 .flags = CLK_IS_CRITICAL,
247 },
248};
249
250static struct clk_regmap g12a_sys_pll = {
251 .data = &(struct clk_regmap_div_data){
252 .offset = HHI_SYS_PLL_CNTL0,
253 .shift = 16,
254 .width = 3,
255 .flags = CLK_DIVIDER_POWER_OF_TWO,
256 },
257 .hw.init = &(struct clk_init_data){
258 .name = "sys_pll",
259 .ops = &clk_regmap_divider_ops,
260 .parent_hws = (const struct clk_hw *[]) {
261 &g12a_sys_pll_dco.hw
262 },
263 .num_parents = 1,
264 .flags = CLK_SET_RATE_PARENT,
265 },
266};
267
268static struct clk_regmap g12b_sys1_pll_dco = {
269 .data = &(struct meson_clk_pll_data){
270 .en = {
271 .reg_off = HHI_SYS1_PLL_CNTL0,
272 .shift = 28,
273 .width = 1,
274 },
275 .m = {
276 .reg_off = HHI_SYS1_PLL_CNTL0,
277 .shift = 0,
278 .width = 8,
279 },
280 .n = {
281 .reg_off = HHI_SYS1_PLL_CNTL0,
282 .shift = 10,
283 .width = 5,
284 },
285 .l = {
286 .reg_off = HHI_SYS1_PLL_CNTL0,
287 .shift = 31,
288 .width = 1,
289 },
290 .rst = {
291 .reg_off = HHI_SYS1_PLL_CNTL0,
292 .shift = 29,
293 .width = 1,
294 },
295 .range = &g12a_sys_pll_mult_range,
296 },
297 .hw.init = &(struct clk_init_data){
298 .name = "sys1_pll_dco",
299 .ops = &meson_clk_pll_ops,
300 .parent_data = &(const struct clk_parent_data) {
301 .fw_name = "xtal",
302 },
303 .num_parents = 1,
304 /* This clock feeds the CPU, avoid disabling it */
305 .flags = CLK_IS_CRITICAL,
306 },
307};
308
309static struct clk_regmap g12b_sys1_pll = {
310 .data = &(struct clk_regmap_div_data){
311 .offset = HHI_SYS1_PLL_CNTL0,
312 .shift = 16,
313 .width = 3,
314 .flags = CLK_DIVIDER_POWER_OF_TWO,
315 },
316 .hw.init = &(struct clk_init_data){
317 .name = "sys1_pll",
318 .ops = &clk_regmap_divider_ops,
319 .parent_hws = (const struct clk_hw *[]) {
320 &g12b_sys1_pll_dco.hw
321 },
322 .num_parents = 1,
323 .flags = CLK_SET_RATE_PARENT,
324 },
325};
326
327static struct clk_regmap g12a_sys_pll_div16_en = {
328 .data = &(struct clk_regmap_gate_data){
329 .offset = HHI_SYS_CPU_CLK_CNTL1,
330 .bit_idx = 24,
331 },
332 .hw.init = &(struct clk_init_data) {
333 .name = "sys_pll_div16_en",
334 .ops = &clk_regmap_gate_ro_ops,
335 .parent_hws = (const struct clk_hw *[]) { &g12a_sys_pll.hw },
336 .num_parents = 1,
337 /*
338 * This clock is used to debug the sys_pll range
339 * Linux should not change it at runtime
340 */
341 },
342};
343
344static struct clk_regmap g12b_sys1_pll_div16_en = {
345 .data = &(struct clk_regmap_gate_data){
346 .offset = HHI_SYS_CPUB_CLK_CNTL1,
347 .bit_idx = 24,
348 },
349 .hw.init = &(struct clk_init_data) {
350 .name = "sys1_pll_div16_en",
351 .ops = &clk_regmap_gate_ro_ops,
352 .parent_hws = (const struct clk_hw *[]) {
353 &g12b_sys1_pll.hw
354 },
355 .num_parents = 1,
356 /*
357 * This clock is used to debug the sys_pll range
358 * Linux should not change it at runtime
359 */
360 },
361};
362
363static struct clk_fixed_factor g12a_sys_pll_div16 = {
364 .mult = 1,
365 .div = 16,
366 .hw.init = &(struct clk_init_data){
367 .name = "sys_pll_div16",
368 .ops = &clk_fixed_factor_ops,
369 .parent_hws = (const struct clk_hw *[]) {
370 &g12a_sys_pll_div16_en.hw
371 },
372 .num_parents = 1,
373 },
374};
375
376static struct clk_fixed_factor g12b_sys1_pll_div16 = {
377 .mult = 1,
378 .div = 16,
379 .hw.init = &(struct clk_init_data){
380 .name = "sys1_pll_div16",
381 .ops = &clk_fixed_factor_ops,
382 .parent_hws = (const struct clk_hw *[]) {
383 &g12b_sys1_pll_div16_en.hw
384 },
385 .num_parents = 1,
386 },
387};
388
389static const struct pll_mult_range g12a_gp0_pll_mult_range = {
390 .min = 125,
391 .max = 255,
392};
393
394/*
395 * Internal gp0 pll emulation configuration parameters
396 */
397static const struct reg_sequence g12a_gp0_pll_init_regs[] = {
398 { .reg = HHI_GP0_PLL_CNTL1, .def = 0x00000000 },
399 { .reg = HHI_GP0_PLL_CNTL2, .def = 0x00000000 },
400 { .reg = HHI_GP0_PLL_CNTL3, .def = 0x48681c00 },
401 { .reg = HHI_GP0_PLL_CNTL4, .def = 0x33771290 },
402 { .reg = HHI_GP0_PLL_CNTL5, .def = 0x39272000 },
403 { .reg = HHI_GP0_PLL_CNTL6, .def = 0x56540000 },
404};
405
406static struct clk_regmap g12a_gp0_pll_dco = {
407 .data = &(struct meson_clk_pll_data){
408 .en = {
409 .reg_off = HHI_GP0_PLL_CNTL0,
410 .shift = 28,
411 .width = 1,
412 },
413 .m = {
414 .reg_off = HHI_GP0_PLL_CNTL0,
415 .shift = 0,
416 .width = 8,
417 },
418 .n = {
419 .reg_off = HHI_GP0_PLL_CNTL0,
420 .shift = 10,
421 .width = 5,
422 },
423 .frac = {
424 .reg_off = HHI_GP0_PLL_CNTL1,
425 .shift = 0,
426 .width = 17,
427 },
428 .l = {
429 .reg_off = HHI_GP0_PLL_CNTL0,
430 .shift = 31,
431 .width = 1,
432 },
433 .rst = {
434 .reg_off = HHI_GP0_PLL_CNTL0,
435 .shift = 29,
436 .width = 1,
437 },
438 .range = &g12a_gp0_pll_mult_range,
439 .init_regs = g12a_gp0_pll_init_regs,
440 .init_count = ARRAY_SIZE(g12a_gp0_pll_init_regs),
441 },
442 .hw.init = &(struct clk_init_data){
443 .name = "gp0_pll_dco",
444 .ops = &meson_clk_pll_ops,
445 .parent_data = &(const struct clk_parent_data) {
446 .fw_name = "xtal",
447 },
448 .num_parents = 1,
449 },
450};
451
452static struct clk_regmap g12a_gp0_pll = {
453 .data = &(struct clk_regmap_div_data){
454 .offset = HHI_GP0_PLL_CNTL0,
455 .shift = 16,
456 .width = 3,
457 .flags = (CLK_DIVIDER_POWER_OF_TWO |
458 CLK_DIVIDER_ROUND_CLOSEST),
459 },
460 .hw.init = &(struct clk_init_data){
461 .name = "gp0_pll",
462 .ops = &clk_regmap_divider_ops,
463 .parent_hws = (const struct clk_hw *[]) {
464 &g12a_gp0_pll_dco.hw
465 },
466 .num_parents = 1,
467 .flags = CLK_SET_RATE_PARENT,
468 },
469};
470
471static struct clk_regmap sm1_gp1_pll_dco = {
472 .data = &(struct meson_clk_pll_data){
473 .en = {
474 .reg_off = HHI_GP1_PLL_CNTL0,
475 .shift = 28,
476 .width = 1,
477 },
478 .m = {
479 .reg_off = HHI_GP1_PLL_CNTL0,
480 .shift = 0,
481 .width = 8,
482 },
483 .n = {
484 .reg_off = HHI_GP1_PLL_CNTL0,
485 .shift = 10,
486 .width = 5,
487 },
488 .frac = {
489 .reg_off = HHI_GP1_PLL_CNTL1,
490 .shift = 0,
491 .width = 17,
492 },
493 .l = {
494 .reg_off = HHI_GP1_PLL_CNTL0,
495 .shift = 31,
496 .width = 1,
497 },
498 .rst = {
499 .reg_off = HHI_GP1_PLL_CNTL0,
500 .shift = 29,
501 .width = 1,
502 },
503 },
504 .hw.init = &(struct clk_init_data){
505 .name = "gp1_pll_dco",
506 .ops = &meson_clk_pll_ro_ops,
507 .parent_data = &(const struct clk_parent_data) {
508 .fw_name = "xtal",
509 },
510 .num_parents = 1,
511 /* This clock feeds the DSU, avoid disabling it */
512 .flags = CLK_IS_CRITICAL,
513 },
514};
515
516static struct clk_regmap sm1_gp1_pll = {
517 .data = &(struct clk_regmap_div_data){
518 .offset = HHI_GP1_PLL_CNTL0,
519 .shift = 16,
520 .width = 3,
521 .flags = (CLK_DIVIDER_POWER_OF_TWO |
522 CLK_DIVIDER_ROUND_CLOSEST),
523 },
524 .hw.init = &(struct clk_init_data){
525 .name = "gp1_pll",
526 .ops = &clk_regmap_divider_ro_ops,
527 .parent_hws = (const struct clk_hw *[]) {
528 &sm1_gp1_pll_dco.hw
529 },
530 .num_parents = 1,
531 },
532};
533
534/*
535 * Internal hifi pll emulation configuration parameters
536 */
537static const struct reg_sequence g12a_hifi_pll_init_regs[] = {
538 { .reg = HHI_HIFI_PLL_CNTL1, .def = 0x00000000 },
539 { .reg = HHI_HIFI_PLL_CNTL2, .def = 0x00000000 },
540 { .reg = HHI_HIFI_PLL_CNTL3, .def = 0x6a285c00 },
541 { .reg = HHI_HIFI_PLL_CNTL4, .def = 0x65771290 },
542 { .reg = HHI_HIFI_PLL_CNTL5, .def = 0x39272000 },
543 { .reg = HHI_HIFI_PLL_CNTL6, .def = 0x56540000 },
544};
545
546static struct clk_regmap g12a_hifi_pll_dco = {
547 .data = &(struct meson_clk_pll_data){
548 .en = {
549 .reg_off = HHI_HIFI_PLL_CNTL0,
550 .shift = 28,
551 .width = 1,
552 },
553 .m = {
554 .reg_off = HHI_HIFI_PLL_CNTL0,
555 .shift = 0,
556 .width = 8,
557 },
558 .n = {
559 .reg_off = HHI_HIFI_PLL_CNTL0,
560 .shift = 10,
561 .width = 5,
562 },
563 .frac = {
564 .reg_off = HHI_HIFI_PLL_CNTL1,
565 .shift = 0,
566 .width = 17,
567 },
568 .l = {
569 .reg_off = HHI_HIFI_PLL_CNTL0,
570 .shift = 31,
571 .width = 1,
572 },
573 .rst = {
574 .reg_off = HHI_HIFI_PLL_CNTL0,
575 .shift = 29,
576 .width = 1,
577 },
578 .range = &g12a_gp0_pll_mult_range,
579 .init_regs = g12a_hifi_pll_init_regs,
580 .init_count = ARRAY_SIZE(g12a_hifi_pll_init_regs),
581 .flags = CLK_MESON_PLL_ROUND_CLOSEST,
582 },
583 .hw.init = &(struct clk_init_data){
584 .name = "hifi_pll_dco",
585 .ops = &meson_clk_pll_ops,
586 .parent_data = &(const struct clk_parent_data) {
587 .fw_name = "xtal",
588 },
589 .num_parents = 1,
590 },
591};
592
593static struct clk_regmap g12a_hifi_pll = {
594 .data = &(struct clk_regmap_div_data){
595 .offset = HHI_HIFI_PLL_CNTL0,
596 .shift = 16,
597 .width = 2,
598 .flags = (CLK_DIVIDER_POWER_OF_TWO |
599 CLK_DIVIDER_ROUND_CLOSEST),
600 },
601 .hw.init = &(struct clk_init_data){
602 .name = "hifi_pll",
603 .ops = &clk_regmap_divider_ops,
604 .parent_hws = (const struct clk_hw *[]) {
605 &g12a_hifi_pll_dco.hw
606 },
607 .num_parents = 1,
608 .flags = CLK_SET_RATE_PARENT,
609 },
610};
611
612/*
613 * The Meson G12A PCIE PLL is fined tuned to deliver a very precise
614 * 100MHz reference clock for the PCIe Analog PHY, and thus requires
615 * a strict register sequence to enable the PLL.
616 */
617static const struct reg_sequence g12a_pcie_pll_init_regs[] = {
618 { .reg = HHI_PCIE_PLL_CNTL0, .def = 0x20090496 },
619 { .reg = HHI_PCIE_PLL_CNTL0, .def = 0x30090496 },
620 { .reg = HHI_PCIE_PLL_CNTL1, .def = 0x00000000 },
621 { .reg = HHI_PCIE_PLL_CNTL2, .def = 0x00001100 },
622 { .reg = HHI_PCIE_PLL_CNTL3, .def = 0x10058e00 },
623 { .reg = HHI_PCIE_PLL_CNTL4, .def = 0x000100c0 },
624 { .reg = HHI_PCIE_PLL_CNTL5, .def = 0x68000048 },
625 { .reg = HHI_PCIE_PLL_CNTL5, .def = 0x68000068, .delay_us = 20 },
626 { .reg = HHI_PCIE_PLL_CNTL4, .def = 0x008100c0, .delay_us = 10 },
627 { .reg = HHI_PCIE_PLL_CNTL0, .def = 0x34090496 },
628 { .reg = HHI_PCIE_PLL_CNTL0, .def = 0x14090496, .delay_us = 10 },
629 { .reg = HHI_PCIE_PLL_CNTL2, .def = 0x00001000 },
630};
631
632/* Keep a single entry table for recalc/round_rate() ops */
633static const struct pll_params_table g12a_pcie_pll_table[] = {
634 PLL_PARAMS(150, 1),
635 {0, 0},
636};
637
638static struct clk_regmap g12a_pcie_pll_dco = {
639 .data = &(struct meson_clk_pll_data){
640 .en = {
641 .reg_off = HHI_PCIE_PLL_CNTL0,
642 .shift = 28,
643 .width = 1,
644 },
645 .m = {
646 .reg_off = HHI_PCIE_PLL_CNTL0,
647 .shift = 0,
648 .width = 8,
649 },
650 .n = {
651 .reg_off = HHI_PCIE_PLL_CNTL0,
652 .shift = 10,
653 .width = 5,
654 },
655 .frac = {
656 .reg_off = HHI_PCIE_PLL_CNTL1,
657 .shift = 0,
658 .width = 12,
659 },
660 .l = {
661 .reg_off = HHI_PCIE_PLL_CNTL0,
662 .shift = 31,
663 .width = 1,
664 },
665 .rst = {
666 .reg_off = HHI_PCIE_PLL_CNTL0,
667 .shift = 29,
668 .width = 1,
669 },
670 .table = g12a_pcie_pll_table,
671 .init_regs = g12a_pcie_pll_init_regs,
672 .init_count = ARRAY_SIZE(g12a_pcie_pll_init_regs),
673 },
674 .hw.init = &(struct clk_init_data){
675 .name = "pcie_pll_dco",
676 .ops = &meson_clk_pcie_pll_ops,
677 .parent_data = &(const struct clk_parent_data) {
678 .fw_name = "xtal",
679 },
680 .num_parents = 1,
681 },
682};
683
684static struct clk_fixed_factor g12a_pcie_pll_dco_div2 = {
685 .mult = 1,
686 .div = 2,
687 .hw.init = &(struct clk_init_data){
688 .name = "pcie_pll_dco_div2",
689 .ops = &clk_fixed_factor_ops,
690 .parent_hws = (const struct clk_hw *[]) {
691 &g12a_pcie_pll_dco.hw
692 },
693 .num_parents = 1,
694 .flags = CLK_SET_RATE_PARENT,
695 },
696};
697
698static struct clk_regmap g12a_pcie_pll_od = {
699 .data = &(struct clk_regmap_div_data){
700 .offset = HHI_PCIE_PLL_CNTL0,
701 .shift = 16,
702 .width = 5,
703 .flags = CLK_DIVIDER_ROUND_CLOSEST |
704 CLK_DIVIDER_ONE_BASED |
705 CLK_DIVIDER_ALLOW_ZERO,
706 },
707 .hw.init = &(struct clk_init_data){
708 .name = "pcie_pll_od",
709 .ops = &clk_regmap_divider_ops,
710 .parent_hws = (const struct clk_hw *[]) {
711 &g12a_pcie_pll_dco_div2.hw
712 },
713 .num_parents = 1,
714 .flags = CLK_SET_RATE_PARENT,
715 },
716};
717
718static struct clk_fixed_factor g12a_pcie_pll = {
719 .mult = 1,
720 .div = 2,
721 .hw.init = &(struct clk_init_data){
722 .name = "pcie_pll_pll",
723 .ops = &clk_fixed_factor_ops,
724 .parent_hws = (const struct clk_hw *[]) {
725 &g12a_pcie_pll_od.hw
726 },
727 .num_parents = 1,
728 .flags = CLK_SET_RATE_PARENT,
729 },
730};
731
732static struct clk_regmap g12a_hdmi_pll_dco = {
733 .data = &(struct meson_clk_pll_data){
734 .en = {
735 .reg_off = HHI_HDMI_PLL_CNTL0,
736 .shift = 28,
737 .width = 1,
738 },
739 .m = {
740 .reg_off = HHI_HDMI_PLL_CNTL0,
741 .shift = 0,
742 .width = 8,
743 },
744 .n = {
745 .reg_off = HHI_HDMI_PLL_CNTL0,
746 .shift = 10,
747 .width = 5,
748 },
749 .frac = {
750 .reg_off = HHI_HDMI_PLL_CNTL1,
751 .shift = 0,
752 .width = 16,
753 },
754 .l = {
755 .reg_off = HHI_HDMI_PLL_CNTL0,
756 .shift = 30,
757 .width = 1,
758 },
759 .rst = {
760 .reg_off = HHI_HDMI_PLL_CNTL0,
761 .shift = 29,
762 .width = 1,
763 },
764 },
765 .hw.init = &(struct clk_init_data){
766 .name = "hdmi_pll_dco",
767 .ops = &meson_clk_pll_ro_ops,
768 .parent_data = &(const struct clk_parent_data) {
769 .fw_name = "xtal",
770 },
771 .num_parents = 1,
772 /*
773 * Display directly handle hdmi pll registers ATM, we need
774 * NOCACHE to keep our view of the clock as accurate as possible
775 */
776 .flags = CLK_GET_RATE_NOCACHE,
777 },
778};
779
780/*
781 * G12/SM1 hdmi OD dividers are POWER_OF_TWO dividers but limited to /4.
782 * A divider value of 3 should map to /8 but instead map /4 so ignore it.
783 */
784static const struct clk_div_table g12a_hdmi_pll_od_div_table[] = {
785 { .val = 0, .div = 1 },
786 { .val = 1, .div = 2 },
787 { .val = 2, .div = 4 },
788 { /* sentinel */ }
789};
790
791static struct clk_regmap g12a_hdmi_pll_od = {
792 .data = &(struct clk_regmap_div_data){
793 .offset = HHI_HDMI_PLL_CNTL0,
794 .shift = 16,
795 .width = 2,
796 .table = g12a_hdmi_pll_od_div_table,
797 },
798 .hw.init = &(struct clk_init_data){
799 .name = "hdmi_pll_od",
800 .ops = &clk_regmap_divider_ro_ops,
801 .parent_hws = (const struct clk_hw *[]) {
802 &g12a_hdmi_pll_dco.hw
803 },
804 .num_parents = 1,
805 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
806 },
807};
808
809static struct clk_regmap g12a_hdmi_pll_od2 = {
810 .data = &(struct clk_regmap_div_data){
811 .offset = HHI_HDMI_PLL_CNTL0,
812 .shift = 18,
813 .width = 2,
814 .table = g12a_hdmi_pll_od_div_table,
815 },
816 .hw.init = &(struct clk_init_data){
817 .name = "hdmi_pll_od2",
818 .ops = &clk_regmap_divider_ro_ops,
819 .parent_hws = (const struct clk_hw *[]) {
820 &g12a_hdmi_pll_od.hw
821 },
822 .num_parents = 1,
823 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
824 },
825};
826
827static struct clk_regmap g12a_hdmi_pll = {
828 .data = &(struct clk_regmap_div_data){
829 .offset = HHI_HDMI_PLL_CNTL0,
830 .shift = 20,
831 .width = 2,
832 .table = g12a_hdmi_pll_od_div_table,
833 },
834 .hw.init = &(struct clk_init_data){
835 .name = "hdmi_pll",
836 .ops = &clk_regmap_divider_ro_ops,
837 .parent_hws = (const struct clk_hw *[]) {
838 &g12a_hdmi_pll_od2.hw
839 },
840 .num_parents = 1,
841 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
842 },
843};
844
845static struct clk_fixed_factor g12a_fclk_div2_div = {
846 .mult = 1,
847 .div = 2,
848 .hw.init = &(struct clk_init_data){
849 .name = "fclk_div2_div",
850 .ops = &clk_fixed_factor_ops,
851 .parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },
852 .num_parents = 1,
853 },
854};
855
856static struct clk_regmap g12a_fclk_div2 = {
857 .data = &(struct clk_regmap_gate_data){
858 .offset = HHI_FIX_PLL_CNTL1,
859 .bit_idx = 24,
860 },
861 .hw.init = &(struct clk_init_data){
862 .name = "fclk_div2",
863 .ops = &clk_regmap_gate_ops,
864 .parent_hws = (const struct clk_hw *[]) {
865 &g12a_fclk_div2_div.hw
866 },
867 .num_parents = 1,
868 /*
869 * Similar to fclk_div3, it seems that this clock is used by
870 * the resident firmware and is required by the platform to
871 * operate correctly.
872 * Until the following condition are met, we need this clock to
873 * be marked as critical:
874 * a) Mark the clock used by a firmware resource, if possible
875 * b) CCF has a clock hand-off mechanism to make the sure the
876 * clock stays on until the proper driver comes along
877 */
878 .flags = CLK_IS_CRITICAL,
879 },
880};
881
882static struct clk_fixed_factor g12a_fclk_div3_div = {
883 .mult = 1,
884 .div = 3,
885 .hw.init = &(struct clk_init_data){
886 .name = "fclk_div3_div",
887 .ops = &clk_fixed_factor_ops,
888 .parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },
889 .num_parents = 1,
890 },
891};
892
893static struct clk_regmap g12a_fclk_div3 = {
894 .data = &(struct clk_regmap_gate_data){
895 .offset = HHI_FIX_PLL_CNTL1,
896 .bit_idx = 20,
897 },
898 .hw.init = &(struct clk_init_data){
899 .name = "fclk_div3",
900 .ops = &clk_regmap_gate_ops,
901 .parent_hws = (const struct clk_hw *[]) {
902 &g12a_fclk_div3_div.hw
903 },
904 .num_parents = 1,
905 /*
906 * This clock is used by the resident firmware and is required
907 * by the platform to operate correctly.
908 * Until the following condition are met, we need this clock to
909 * be marked as critical:
910 * a) Mark the clock used by a firmware resource, if possible
911 * b) CCF has a clock hand-off mechanism to make the sure the
912 * clock stays on until the proper driver comes along
913 */
914 .flags = CLK_IS_CRITICAL,
915 },
916};
917
918
919static struct clk_fixed_factor g12a_fclk_div4_div = {
920 .mult = 1,
921 .div = 4,
922 .hw.init = &(struct clk_init_data){
923 .name = "fclk_div4_div",
924 .ops = &clk_fixed_factor_ops,
925 .parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },
926 .num_parents = 1,
927 },
928};
929
930static struct clk_regmap g12a_fclk_div4 = {
931 .data = &(struct clk_regmap_gate_data){
932 .offset = HHI_FIX_PLL_CNTL1,
933 .bit_idx = 21,
934 },
935 .hw.init = &(struct clk_init_data){
936 .name = "fclk_div4",
937 .ops = &clk_regmap_gate_ops,
938 .parent_hws = (const struct clk_hw *[]) {
939 &g12a_fclk_div4_div.hw
940 },
941 .num_parents = 1,
942 },
943};
944
945static struct clk_fixed_factor g12a_fclk_div5_div = {
946 .mult = 1,
947 .div = 5,
948 .hw.init = &(struct clk_init_data){
949 .name = "fclk_div5_div",
950 .ops = &clk_fixed_factor_ops,
951 .parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },
952 .num_parents = 1,
953 },
954};
955
956static struct clk_regmap g12a_fclk_div5 = {
957 .data = &(struct clk_regmap_gate_data){
958 .offset = HHI_FIX_PLL_CNTL1,
959 .bit_idx = 22,
960 },
961 .hw.init = &(struct clk_init_data){
962 .name = "fclk_div5",
963 .ops = &clk_regmap_gate_ops,
964 .parent_hws = (const struct clk_hw *[]) {
965 &g12a_fclk_div5_div.hw
966 },
967 .num_parents = 1,
968 },
969};
970
971static struct clk_fixed_factor g12a_fclk_div7_div = {
972 .mult = 1,
973 .div = 7,
974 .hw.init = &(struct clk_init_data){
975 .name = "fclk_div7_div",
976 .ops = &clk_fixed_factor_ops,
977 .parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },
978 .num_parents = 1,
979 },
980};
981
982static struct clk_regmap g12a_fclk_div7 = {
983 .data = &(struct clk_regmap_gate_data){
984 .offset = HHI_FIX_PLL_CNTL1,
985 .bit_idx = 23,
986 },
987 .hw.init = &(struct clk_init_data){
988 .name = "fclk_div7",
989 .ops = &clk_regmap_gate_ops,
990 .parent_hws = (const struct clk_hw *[]) {
991 &g12a_fclk_div7_div.hw
992 },
993 .num_parents = 1,
994 },
995};
996
997static struct clk_fixed_factor g12a_fclk_div2p5_div = {
998 .mult = 1,
999 .div = 5,
1000 .hw.init = &(struct clk_init_data){
1001 .name = "fclk_div2p5_div",
1002 .ops = &clk_fixed_factor_ops,
1003 .parent_hws = (const struct clk_hw *[]) {
1004 &g12a_fixed_pll_dco.hw
1005 },
1006 .num_parents = 1,
1007 },
1008};
1009
1010static struct clk_regmap g12a_fclk_div2p5 = {
1011 .data = &(struct clk_regmap_gate_data){
1012 .offset = HHI_FIX_PLL_CNTL1,
1013 .bit_idx = 25,
1014 },
1015 .hw.init = &(struct clk_init_data){
1016 .name = "fclk_div2p5",
1017 .ops = &clk_regmap_gate_ops,
1018 .parent_hws = (const struct clk_hw *[]) {
1019 &g12a_fclk_div2p5_div.hw
1020 },
1021 .num_parents = 1,
1022 },
1023};
1024
1025static struct clk_fixed_factor g12a_mpll_50m_div = {
1026 .mult = 1,
1027 .div = 80,
1028 .hw.init = &(struct clk_init_data){
1029 .name = "mpll_50m_div",
1030 .ops = &clk_fixed_factor_ops,
1031 .parent_hws = (const struct clk_hw *[]) {
1032 &g12a_fixed_pll_dco.hw
1033 },
1034 .num_parents = 1,
1035 },
1036};
1037
1038static struct clk_regmap g12a_mpll_50m = {
1039 .data = &(struct clk_regmap_mux_data){
1040 .offset = HHI_FIX_PLL_CNTL3,
1041 .mask = 0x1,
1042 .shift = 5,
1043 },
1044 .hw.init = &(struct clk_init_data){
1045 .name = "mpll_50m",
1046 .ops = &clk_regmap_mux_ro_ops,
1047 .parent_data = (const struct clk_parent_data []) {
1048 { .fw_name = "xtal", },
1049 { .hw = &g12a_mpll_50m_div.hw },
1050 },
1051 .num_parents = 2,
1052 },
1053};
1054
1055static struct clk_fixed_factor g12a_mpll_prediv = {
1056 .mult = 1,
1057 .div = 2,
1058 .hw.init = &(struct clk_init_data){
1059 .name = "mpll_prediv",
1060 .ops = &clk_fixed_factor_ops,
1061 .parent_hws = (const struct clk_hw *[]) {
1062 &g12a_fixed_pll_dco.hw
1063 },
1064 .num_parents = 1,
1065 },
1066};
1067
1068/* Datasheet names this field as "premux0" */
1069static struct clk_regmap g12a_cpu_clk_dyn0_sel = {
1070 .data = &(struct clk_regmap_mux_data){
1071 .offset = HHI_SYS_CPU_CLK_CNTL0,
1072 .mask = 0x3,
1073 .shift = 0,
1074 .flags = CLK_MUX_ROUND_CLOSEST,
1075 },
1076 .hw.init = &(struct clk_init_data){
1077 .name = "cpu_clk_dyn0_sel",
1078 .ops = &clk_regmap_mux_ops,
1079 .parent_data = (const struct clk_parent_data []) {
1080 { .fw_name = "xtal", },
1081 { .hw = &g12a_fclk_div2.hw },
1082 { .hw = &g12a_fclk_div3.hw },
1083 },
1084 .num_parents = 3,
1085 .flags = CLK_SET_RATE_PARENT,
1086 },
1087};
1088
1089/* Datasheet names this field as "mux0_divn_tcnt" */
1090static struct clk_regmap g12a_cpu_clk_dyn0_div = {
1091 .data = &(struct meson_clk_cpu_dyndiv_data){
1092 .div = {
1093 .reg_off = HHI_SYS_CPU_CLK_CNTL0,
1094 .shift = 4,
1095 .width = 6,
1096 },
1097 .dyn = {
1098 .reg_off = HHI_SYS_CPU_CLK_CNTL0,
1099 .shift = 26,
1100 .width = 1,
1101 },
1102 },
1103 .hw.init = &(struct clk_init_data){
1104 .name = "cpu_clk_dyn0_div",
1105 .ops = &meson_clk_cpu_dyndiv_ops,
1106 .parent_hws = (const struct clk_hw *[]) {
1107 &g12a_cpu_clk_dyn0_sel.hw
1108 },
1109 .num_parents = 1,
1110 .flags = CLK_SET_RATE_PARENT,
1111 },
1112};
1113
1114/* Datasheet names this field as "postmux0" */
1115static struct clk_regmap g12a_cpu_clk_dyn0 = {
1116 .data = &(struct clk_regmap_mux_data){
1117 .offset = HHI_SYS_CPU_CLK_CNTL0,
1118 .mask = 0x1,
1119 .shift = 2,
1120 .flags = CLK_MUX_ROUND_CLOSEST,
1121 },
1122 .hw.init = &(struct clk_init_data){
1123 .name = "cpu_clk_dyn0",
1124 .ops = &clk_regmap_mux_ops,
1125 .parent_hws = (const struct clk_hw *[]) {
1126 &g12a_cpu_clk_dyn0_sel.hw,
1127 &g12a_cpu_clk_dyn0_div.hw,
1128 },
1129 .num_parents = 2,
1130 .flags = CLK_SET_RATE_PARENT,
1131 },
1132};
1133
1134/* Datasheet names this field as "premux1" */
1135static struct clk_regmap g12a_cpu_clk_dyn1_sel = {
1136 .data = &(struct clk_regmap_mux_data){
1137 .offset = HHI_SYS_CPU_CLK_CNTL0,
1138 .mask = 0x3,
1139 .shift = 16,
1140 },
1141 .hw.init = &(struct clk_init_data){
1142 .name = "cpu_clk_dyn1_sel",
1143 .ops = &clk_regmap_mux_ops,
1144 .parent_data = (const struct clk_parent_data []) {
1145 { .fw_name = "xtal", },
1146 { .hw = &g12a_fclk_div2.hw },
1147 { .hw = &g12a_fclk_div3.hw },
1148 },
1149 .num_parents = 3,
1150 /* This sub-tree is used a parking clock */
1151 .flags = CLK_SET_RATE_NO_REPARENT
1152 },
1153};
1154
1155/* Datasheet names this field as "Mux1_divn_tcnt" */
1156static struct clk_regmap g12a_cpu_clk_dyn1_div = {
1157 .data = &(struct clk_regmap_div_data){
1158 .offset = HHI_SYS_CPU_CLK_CNTL0,
1159 .shift = 20,
1160 .width = 6,
1161 },
1162 .hw.init = &(struct clk_init_data){
1163 .name = "cpu_clk_dyn1_div",
1164 .ops = &clk_regmap_divider_ro_ops,
1165 .parent_hws = (const struct clk_hw *[]) {
1166 &g12a_cpu_clk_dyn1_sel.hw
1167 },
1168 .num_parents = 1,
1169 },
1170};
1171
1172/* Datasheet names this field as "postmux1" */
1173static struct clk_regmap g12a_cpu_clk_dyn1 = {
1174 .data = &(struct clk_regmap_mux_data){
1175 .offset = HHI_SYS_CPU_CLK_CNTL0,
1176 .mask = 0x1,
1177 .shift = 18,
1178 },
1179 .hw.init = &(struct clk_init_data){
1180 .name = "cpu_clk_dyn1",
1181 .ops = &clk_regmap_mux_ops,
1182 .parent_hws = (const struct clk_hw *[]) {
1183 &g12a_cpu_clk_dyn1_sel.hw,
1184 &g12a_cpu_clk_dyn1_div.hw,
1185 },
1186 .num_parents = 2,
1187 /* This sub-tree is used a parking clock */
1188 .flags = CLK_SET_RATE_NO_REPARENT,
1189 },
1190};
1191
1192/* Datasheet names this field as "Final_dyn_mux_sel" */
1193static struct clk_regmap g12a_cpu_clk_dyn = {
1194 .data = &(struct clk_regmap_mux_data){
1195 .offset = HHI_SYS_CPU_CLK_CNTL0,
1196 .mask = 0x1,
1197 .shift = 10,
1198 .flags = CLK_MUX_ROUND_CLOSEST,
1199 },
1200 .hw.init = &(struct clk_init_data){
1201 .name = "cpu_clk_dyn",
1202 .ops = &clk_regmap_mux_ops,
1203 .parent_hws = (const struct clk_hw *[]) {
1204 &g12a_cpu_clk_dyn0.hw,
1205 &g12a_cpu_clk_dyn1.hw,
1206 },
1207 .num_parents = 2,
1208 .flags = CLK_SET_RATE_PARENT,
1209 },
1210};
1211
1212/* Datasheet names this field as "Final_mux_sel" */
1213static struct clk_regmap g12a_cpu_clk = {
1214 .data = &(struct clk_regmap_mux_data){
1215 .offset = HHI_SYS_CPU_CLK_CNTL0,
1216 .mask = 0x1,
1217 .shift = 11,
1218 .flags = CLK_MUX_ROUND_CLOSEST,
1219 },
1220 .hw.init = &(struct clk_init_data){
1221 .name = "cpu_clk",
1222 .ops = &clk_regmap_mux_ops,
1223 .parent_hws = (const struct clk_hw *[]) {
1224 &g12a_cpu_clk_dyn.hw,
1225 &g12a_sys_pll.hw,
1226 },
1227 .num_parents = 2,
1228 .flags = CLK_SET_RATE_PARENT,
1229 },
1230};
1231
1232/* Datasheet names this field as "Final_mux_sel" */
1233static struct clk_regmap g12b_cpu_clk = {
1234 .data = &(struct clk_regmap_mux_data){
1235 .offset = HHI_SYS_CPU_CLK_CNTL0,
1236 .mask = 0x1,
1237 .shift = 11,
1238 .flags = CLK_MUX_ROUND_CLOSEST,
1239 },
1240 .hw.init = &(struct clk_init_data){
1241 .name = "cpu_clk",
1242 .ops = &clk_regmap_mux_ops,
1243 .parent_hws = (const struct clk_hw *[]) {
1244 &g12a_cpu_clk_dyn.hw,
1245 &g12b_sys1_pll.hw
1246 },
1247 .num_parents = 2,
1248 .flags = CLK_SET_RATE_PARENT,
1249 },
1250};
1251
1252/* Datasheet names this field as "premux0" */
1253static struct clk_regmap g12b_cpub_clk_dyn0_sel = {
1254 .data = &(struct clk_regmap_mux_data){
1255 .offset = HHI_SYS_CPUB_CLK_CNTL,
1256 .mask = 0x3,
1257 .shift = 0,
1258 .flags = CLK_MUX_ROUND_CLOSEST,
1259 },
1260 .hw.init = &(struct clk_init_data){
1261 .name = "cpub_clk_dyn0_sel",
1262 .ops = &clk_regmap_mux_ops,
1263 .parent_data = (const struct clk_parent_data []) {
1264 { .fw_name = "xtal", },
1265 { .hw = &g12a_fclk_div2.hw },
1266 { .hw = &g12a_fclk_div3.hw },
1267 },
1268 .num_parents = 3,
1269 .flags = CLK_SET_RATE_PARENT,
1270 },
1271};
1272
1273/* Datasheet names this field as "mux0_divn_tcnt" */
1274static struct clk_regmap g12b_cpub_clk_dyn0_div = {
1275 .data = &(struct meson_clk_cpu_dyndiv_data){
1276 .div = {
1277 .reg_off = HHI_SYS_CPUB_CLK_CNTL,
1278 .shift = 4,
1279 .width = 6,
1280 },
1281 .dyn = {
1282 .reg_off = HHI_SYS_CPUB_CLK_CNTL,
1283 .shift = 26,
1284 .width = 1,
1285 },
1286 },
1287 .hw.init = &(struct clk_init_data){
1288 .name = "cpub_clk_dyn0_div",
1289 .ops = &meson_clk_cpu_dyndiv_ops,
1290 .parent_hws = (const struct clk_hw *[]) {
1291 &g12b_cpub_clk_dyn0_sel.hw
1292 },
1293 .num_parents = 1,
1294 .flags = CLK_SET_RATE_PARENT,
1295 },
1296};
1297
1298/* Datasheet names this field as "postmux0" */
1299static struct clk_regmap g12b_cpub_clk_dyn0 = {
1300 .data = &(struct clk_regmap_mux_data){
1301 .offset = HHI_SYS_CPUB_CLK_CNTL,
1302 .mask = 0x1,
1303 .shift = 2,
1304 .flags = CLK_MUX_ROUND_CLOSEST,
1305 },
1306 .hw.init = &(struct clk_init_data){
1307 .name = "cpub_clk_dyn0",
1308 .ops = &clk_regmap_mux_ops,
1309 .parent_hws = (const struct clk_hw *[]) {
1310 &g12b_cpub_clk_dyn0_sel.hw,
1311 &g12b_cpub_clk_dyn0_div.hw
1312 },
1313 .num_parents = 2,
1314 .flags = CLK_SET_RATE_PARENT,
1315 },
1316};
1317
1318/* Datasheet names this field as "premux1" */
1319static struct clk_regmap g12b_cpub_clk_dyn1_sel = {
1320 .data = &(struct clk_regmap_mux_data){
1321 .offset = HHI_SYS_CPUB_CLK_CNTL,
1322 .mask = 0x3,
1323 .shift = 16,
1324 },
1325 .hw.init = &(struct clk_init_data){
1326 .name = "cpub_clk_dyn1_sel",
1327 .ops = &clk_regmap_mux_ops,
1328 .parent_data = (const struct clk_parent_data []) {
1329 { .fw_name = "xtal", },
1330 { .hw = &g12a_fclk_div2.hw },
1331 { .hw = &g12a_fclk_div3.hw },
1332 },
1333 .num_parents = 3,
1334 /* This sub-tree is used a parking clock */
1335 .flags = CLK_SET_RATE_NO_REPARENT,
1336 },
1337};
1338
1339/* Datasheet names this field as "Mux1_divn_tcnt" */
1340static struct clk_regmap g12b_cpub_clk_dyn1_div = {
1341 .data = &(struct clk_regmap_div_data){
1342 .offset = HHI_SYS_CPUB_CLK_CNTL,
1343 .shift = 20,
1344 .width = 6,
1345 },
1346 .hw.init = &(struct clk_init_data){
1347 .name = "cpub_clk_dyn1_div",
1348 .ops = &clk_regmap_divider_ro_ops,
1349 .parent_hws = (const struct clk_hw *[]) {
1350 &g12b_cpub_clk_dyn1_sel.hw
1351 },
1352 .num_parents = 1,
1353 },
1354};
1355
1356/* Datasheet names this field as "postmux1" */
1357static struct clk_regmap g12b_cpub_clk_dyn1 = {
1358 .data = &(struct clk_regmap_mux_data){
1359 .offset = HHI_SYS_CPUB_CLK_CNTL,
1360 .mask = 0x1,
1361 .shift = 18,
1362 },
1363 .hw.init = &(struct clk_init_data){
1364 .name = "cpub_clk_dyn1",
1365 .ops = &clk_regmap_mux_ops,
1366 .parent_hws = (const struct clk_hw *[]) {
1367 &g12b_cpub_clk_dyn1_sel.hw,
1368 &g12b_cpub_clk_dyn1_div.hw
1369 },
1370 .num_parents = 2,
1371 /* This sub-tree is used a parking clock */
1372 .flags = CLK_SET_RATE_NO_REPARENT,
1373 },
1374};
1375
1376/* Datasheet names this field as "Final_dyn_mux_sel" */
1377static struct clk_regmap g12b_cpub_clk_dyn = {
1378 .data = &(struct clk_regmap_mux_data){
1379 .offset = HHI_SYS_CPUB_CLK_CNTL,
1380 .mask = 0x1,
1381 .shift = 10,
1382 .flags = CLK_MUX_ROUND_CLOSEST,
1383 },
1384 .hw.init = &(struct clk_init_data){
1385 .name = "cpub_clk_dyn",
1386 .ops = &clk_regmap_mux_ops,
1387 .parent_hws = (const struct clk_hw *[]) {
1388 &g12b_cpub_clk_dyn0.hw,
1389 &g12b_cpub_clk_dyn1.hw
1390 },
1391 .num_parents = 2,
1392 .flags = CLK_SET_RATE_PARENT,
1393 },
1394};
1395
1396/* Datasheet names this field as "Final_mux_sel" */
1397static struct clk_regmap g12b_cpub_clk = {
1398 .data = &(struct clk_regmap_mux_data){
1399 .offset = HHI_SYS_CPUB_CLK_CNTL,
1400 .mask = 0x1,
1401 .shift = 11,
1402 .flags = CLK_MUX_ROUND_CLOSEST,
1403 },
1404 .hw.init = &(struct clk_init_data){
1405 .name = "cpub_clk",
1406 .ops = &clk_regmap_mux_ops,
1407 .parent_hws = (const struct clk_hw *[]) {
1408 &g12b_cpub_clk_dyn.hw,
1409 &g12a_sys_pll.hw
1410 },
1411 .num_parents = 2,
1412 .flags = CLK_SET_RATE_PARENT,
1413 },
1414};
1415
1416/* Datasheet names this field as "premux0" */
1417static struct clk_regmap sm1_dsu_clk_dyn0_sel = {
1418 .data = &(struct clk_regmap_mux_data){
1419 .offset = HHI_SYS_CPU_CLK_CNTL5,
1420 .mask = 0x3,
1421 .shift = 0,
1422 },
1423 .hw.init = &(struct clk_init_data){
1424 .name = "dsu_clk_dyn0_sel",
1425 .ops = &clk_regmap_mux_ro_ops,
1426 .parent_data = (const struct clk_parent_data []) {
1427 { .fw_name = "xtal", },
1428 { .hw = &g12a_fclk_div2.hw },
1429 { .hw = &g12a_fclk_div3.hw },
1430 { .hw = &sm1_gp1_pll.hw },
1431 },
1432 .num_parents = 4,
1433 },
1434};
1435
1436/* Datasheet names this field as "Mux0_divn_tcnt" */
1437static struct clk_regmap sm1_dsu_clk_dyn0_div = {
1438 .data = &(struct clk_regmap_div_data){
1439 .offset = HHI_SYS_CPU_CLK_CNTL5,
1440 .shift = 4,
1441 .width = 6,
1442 },
1443 .hw.init = &(struct clk_init_data){
1444 .name = "dsu_clk_dyn0_div",
1445 .ops = &clk_regmap_divider_ro_ops,
1446 .parent_hws = (const struct clk_hw *[]) {
1447 &sm1_dsu_clk_dyn0_sel.hw
1448 },
1449 .num_parents = 1,
1450 },
1451};
1452
1453/* Datasheet names this field as "postmux0" */
1454static struct clk_regmap sm1_dsu_clk_dyn0 = {
1455 .data = &(struct clk_regmap_mux_data){
1456 .offset = HHI_SYS_CPU_CLK_CNTL5,
1457 .mask = 0x1,
1458 .shift = 2,
1459 },
1460 .hw.init = &(struct clk_init_data){
1461 .name = "dsu_clk_dyn0",
1462 .ops = &clk_regmap_mux_ro_ops,
1463 .parent_hws = (const struct clk_hw *[]) {
1464 &sm1_dsu_clk_dyn0_sel.hw,
1465 &sm1_dsu_clk_dyn0_div.hw,
1466 },
1467 .num_parents = 2,
1468 },
1469};
1470
1471/* Datasheet names this field as "premux1" */
1472static struct clk_regmap sm1_dsu_clk_dyn1_sel = {
1473 .data = &(struct clk_regmap_mux_data){
1474 .offset = HHI_SYS_CPU_CLK_CNTL5,
1475 .mask = 0x3,
1476 .shift = 16,
1477 },
1478 .hw.init = &(struct clk_init_data){
1479 .name = "dsu_clk_dyn1_sel",
1480 .ops = &clk_regmap_mux_ro_ops,
1481 .parent_data = (const struct clk_parent_data []) {
1482 { .fw_name = "xtal", },
1483 { .hw = &g12a_fclk_div2.hw },
1484 { .hw = &g12a_fclk_div3.hw },
1485 { .hw = &sm1_gp1_pll.hw },
1486 },
1487 .num_parents = 4,
1488 },
1489};
1490
1491/* Datasheet names this field as "Mux1_divn_tcnt" */
1492static struct clk_regmap sm1_dsu_clk_dyn1_div = {
1493 .data = &(struct clk_regmap_div_data){
1494 .offset = HHI_SYS_CPU_CLK_CNTL5,
1495 .shift = 20,
1496 .width = 6,
1497 },
1498 .hw.init = &(struct clk_init_data){
1499 .name = "dsu_clk_dyn1_div",
1500 .ops = &clk_regmap_divider_ro_ops,
1501 .parent_hws = (const struct clk_hw *[]) {
1502 &sm1_dsu_clk_dyn1_sel.hw
1503 },
1504 .num_parents = 1,
1505 },
1506};
1507
1508/* Datasheet names this field as "postmux1" */
1509static struct clk_regmap sm1_dsu_clk_dyn1 = {
1510 .data = &(struct clk_regmap_mux_data){
1511 .offset = HHI_SYS_CPU_CLK_CNTL5,
1512 .mask = 0x1,
1513 .shift = 18,
1514 },
1515 .hw.init = &(struct clk_init_data){
1516 .name = "dsu_clk_dyn1",
1517 .ops = &clk_regmap_mux_ro_ops,
1518 .parent_hws = (const struct clk_hw *[]) {
1519 &sm1_dsu_clk_dyn1_sel.hw,
1520 &sm1_dsu_clk_dyn1_div.hw,
1521 },
1522 .num_parents = 2,
1523 },
1524};
1525
1526/* Datasheet names this field as "Final_dyn_mux_sel" */
1527static struct clk_regmap sm1_dsu_clk_dyn = {
1528 .data = &(struct clk_regmap_mux_data){
1529 .offset = HHI_SYS_CPU_CLK_CNTL5,
1530 .mask = 0x1,
1531 .shift = 10,
1532 },
1533 .hw.init = &(struct clk_init_data){
1534 .name = "dsu_clk_dyn",
1535 .ops = &clk_regmap_mux_ro_ops,
1536 .parent_hws = (const struct clk_hw *[]) {
1537 &sm1_dsu_clk_dyn0.hw,
1538 &sm1_dsu_clk_dyn1.hw,
1539 },
1540 .num_parents = 2,
1541 },
1542};
1543
1544/* Datasheet names this field as "Final_mux_sel" */
1545static struct clk_regmap sm1_dsu_final_clk = {
1546 .data = &(struct clk_regmap_mux_data){
1547 .offset = HHI_SYS_CPU_CLK_CNTL5,
1548 .mask = 0x1,
1549 .shift = 11,
1550 },
1551 .hw.init = &(struct clk_init_data){
1552 .name = "dsu_clk_final",
1553 .ops = &clk_regmap_mux_ro_ops,
1554 .parent_hws = (const struct clk_hw *[]) {
1555 &sm1_dsu_clk_dyn.hw,
1556 &g12a_sys_pll.hw,
1557 },
1558 .num_parents = 2,
1559 },
1560};
1561
1562/* Datasheet names this field as "Cpu_clk_sync_mux_sel" bit 0 */
1563static struct clk_regmap sm1_cpu1_clk = {
1564 .data = &(struct clk_regmap_mux_data){
1565 .offset = HHI_SYS_CPU_CLK_CNTL6,
1566 .mask = 0x1,
1567 .shift = 24,
1568 },
1569 .hw.init = &(struct clk_init_data){
1570 .name = "cpu1_clk",
1571 .ops = &clk_regmap_mux_ro_ops,
1572 .parent_hws = (const struct clk_hw *[]) {
1573 &g12a_cpu_clk.hw,
1574 /* This CPU also have a dedicated clock tree */
1575 },
1576 .num_parents = 1,
1577 },
1578};
1579
1580/* Datasheet names this field as "Cpu_clk_sync_mux_sel" bit 1 */
1581static struct clk_regmap sm1_cpu2_clk = {
1582 .data = &(struct clk_regmap_mux_data){
1583 .offset = HHI_SYS_CPU_CLK_CNTL6,
1584 .mask = 0x1,
1585 .shift = 25,
1586 },
1587 .hw.init = &(struct clk_init_data){
1588 .name = "cpu2_clk",
1589 .ops = &clk_regmap_mux_ro_ops,
1590 .parent_hws = (const struct clk_hw *[]) {
1591 &g12a_cpu_clk.hw,
1592 /* This CPU also have a dedicated clock tree */
1593 },
1594 .num_parents = 1,
1595 },
1596};
1597
1598/* Datasheet names this field as "Cpu_clk_sync_mux_sel" bit 2 */
1599static struct clk_regmap sm1_cpu3_clk = {
1600 .data = &(struct clk_regmap_mux_data){
1601 .offset = HHI_SYS_CPU_CLK_CNTL6,
1602 .mask = 0x1,
1603 .shift = 26,
1604 },
1605 .hw.init = &(struct clk_init_data){
1606 .name = "cpu3_clk",
1607 .ops = &clk_regmap_mux_ro_ops,
1608 .parent_hws = (const struct clk_hw *[]) {
1609 &g12a_cpu_clk.hw,
1610 /* This CPU also have a dedicated clock tree */
1611 },
1612 .num_parents = 1,
1613 },
1614};
1615
1616/* Datasheet names this field as "Cpu_clk_sync_mux_sel" bit 4 */
1617static struct clk_regmap sm1_dsu_clk = {
1618 .data = &(struct clk_regmap_mux_data){
1619 .offset = HHI_SYS_CPU_CLK_CNTL6,
1620 .mask = 0x1,
1621 .shift = 27,
1622 },
1623 .hw.init = &(struct clk_init_data){
1624 .name = "dsu_clk",
1625 .ops = &clk_regmap_mux_ro_ops,
1626 .parent_hws = (const struct clk_hw *[]) {
1627 &g12a_cpu_clk.hw,
1628 &sm1_dsu_final_clk.hw,
1629 },
1630 .num_parents = 2,
1631 },
1632};
1633
1634static int g12a_cpu_clk_mux_notifier_cb(struct notifier_block *nb,
1635 unsigned long event, void *data)
1636{
1637 if (event == POST_RATE_CHANGE || event == PRE_RATE_CHANGE) {
1638 /* Wait for clock propagation before/after changing the mux */
1639 udelay(100);
1640 return NOTIFY_OK;
1641 }
1642
1643 return NOTIFY_DONE;
1644}
1645
1646static struct notifier_block g12a_cpu_clk_mux_nb = {
1647 .notifier_call = g12a_cpu_clk_mux_notifier_cb,
1648};
1649
1650struct g12a_cpu_clk_dyn_nb_data {
1651 struct notifier_block nb;
1652 struct clk_hw *xtal;
1653 struct clk_hw *cpu_clk_dyn;
1654 struct clk_hw *cpu_clk_postmux0;
1655 struct clk_hw *cpu_clk_postmux1;
1656 struct clk_hw *cpu_clk_premux1;
1657};
1658
1659static int g12a_cpu_clk_dyn_notifier_cb(struct notifier_block *nb,
1660 unsigned long event, void *data)
1661{
1662 struct g12a_cpu_clk_dyn_nb_data *nb_data =
1663 container_of(nb, struct g12a_cpu_clk_dyn_nb_data, nb);
1664
1665 switch (event) {
1666 case PRE_RATE_CHANGE:
1667 /*
1668 * This notifier means cpu_clk_dyn0 clock will be changed
1669 * to feed cpu_clk, this is the current path :
1670 * cpu_clk
1671 * \- cpu_clk_dyn
1672 * \- cpu_clk_dyn0
1673 * \- cpu_clk_dyn0_div
1674 * \- cpu_clk_dyn0_sel
1675 * \- fclk_div3 or fclk_div2
1676 * OR
1677 * \- cpu_clk_dyn0_sel
1678 * \- fclk_div3 or fclk_div2
1679 */
1680
1681 /* Setup cpu_clk_dyn1_sel to xtal */
1682 clk_hw_set_parent(nb_data->cpu_clk_premux1,
1683 nb_data->xtal);
1684
1685 /* Setup cpu_clk_dyn1 to bypass divider */
1686 clk_hw_set_parent(nb_data->cpu_clk_postmux1,
1687 nb_data->cpu_clk_premux1);
1688
1689 /* Switch to parking clk on cpu_clk_postmux1 */
1690 clk_hw_set_parent(nb_data->cpu_clk_dyn,
1691 nb_data->cpu_clk_postmux1);
1692
1693 /*
1694 * Now, cpu_clk is 24MHz in the current path :
1695 * cpu_clk
1696 * \- cpu_clk_dyn
1697 * \- cpu_clk_dyn1
1698 * \- cpu_clk_dyn1_sel
1699 * \- xtal
1700 */
1701
1702 udelay(100);
1703
1704 return NOTIFY_OK;
1705
1706 case POST_RATE_CHANGE:
1707 /*
1708 * The cpu_clk_dyn0 has ben updated, now switch back
1709 * cpu_clk_dyn to cpu_clk_dyn0 and take the changes
1710 * in account.
1711 */
1712
1713 /* Configure cpu_clk_dyn back to cpu_clk_postmux0 */
1714 clk_hw_set_parent(nb_data->cpu_clk_dyn,
1715 nb_data->cpu_clk_postmux0);
1716
1717 /*
1718 * new path :
1719 * cpu_clk
1720 * \- cpu_clk_dyn
1721 * \- cpu_clk_dyn0
1722 * \- cpu_clk_dyn0_div
1723 * \- cpu_clk_dyn0_sel
1724 * \- fclk_div3 or fclk_div2
1725 * OR
1726 * \- cpu_clk_dyn0_sel
1727 * \- fclk_div3 or fclk_div2
1728 */
1729
1730 udelay(100);
1731
1732 return NOTIFY_OK;
1733
1734 default:
1735 return NOTIFY_DONE;
1736 }
1737}
1738
1739static struct g12a_cpu_clk_dyn_nb_data g12a_cpu_clk_dyn0_nb_data = {
1740 .cpu_clk_dyn = &g12a_cpu_clk_dyn.hw,
1741 .cpu_clk_postmux0 = &g12a_cpu_clk_dyn0.hw,
1742 .cpu_clk_postmux1 = &g12a_cpu_clk_dyn1.hw,
1743 .cpu_clk_premux1 = &g12a_cpu_clk_dyn1_sel.hw,
1744 .nb.notifier_call = g12a_cpu_clk_dyn_notifier_cb,
1745};
1746
1747static struct g12a_cpu_clk_dyn_nb_data g12b_cpub_clk_dyn0_nb_data = {
1748 .cpu_clk_dyn = &g12b_cpub_clk_dyn.hw,
1749 .cpu_clk_postmux0 = &g12b_cpub_clk_dyn0.hw,
1750 .cpu_clk_postmux1 = &g12b_cpub_clk_dyn1.hw,
1751 .cpu_clk_premux1 = &g12b_cpub_clk_dyn1_sel.hw,
1752 .nb.notifier_call = g12a_cpu_clk_dyn_notifier_cb,
1753};
1754
1755struct g12a_sys_pll_nb_data {
1756 struct notifier_block nb;
1757 struct clk_hw *sys_pll;
1758 struct clk_hw *cpu_clk;
1759 struct clk_hw *cpu_clk_dyn;
1760};
1761
1762static int g12a_sys_pll_notifier_cb(struct notifier_block *nb,
1763 unsigned long event, void *data)
1764{
1765 struct g12a_sys_pll_nb_data *nb_data =
1766 container_of(nb, struct g12a_sys_pll_nb_data, nb);
1767
1768 switch (event) {
1769 case PRE_RATE_CHANGE:
1770 /*
1771 * This notifier means sys_pll clock will be changed
1772 * to feed cpu_clk, this the current path :
1773 * cpu_clk
1774 * \- sys_pll
1775 * \- sys_pll_dco
1776 */
1777
1778 /* Configure cpu_clk to use cpu_clk_dyn */
1779 clk_hw_set_parent(nb_data->cpu_clk,
1780 nb_data->cpu_clk_dyn);
1781
1782 /*
1783 * Now, cpu_clk uses the dyn path
1784 * cpu_clk
1785 * \- cpu_clk_dyn
1786 * \- cpu_clk_dynX
1787 * \- cpu_clk_dynX_sel
1788 * \- cpu_clk_dynX_div
1789 * \- xtal/fclk_div2/fclk_div3
1790 * \- xtal/fclk_div2/fclk_div3
1791 */
1792
1793 udelay(100);
1794
1795 return NOTIFY_OK;
1796
1797 case POST_RATE_CHANGE:
1798 /*
1799 * The sys_pll has ben updated, now switch back cpu_clk to
1800 * sys_pll
1801 */
1802
1803 /* Configure cpu_clk to use sys_pll */
1804 clk_hw_set_parent(nb_data->cpu_clk,
1805 nb_data->sys_pll);
1806
1807 udelay(100);
1808
1809 /* new path :
1810 * cpu_clk
1811 * \- sys_pll
1812 * \- sys_pll_dco
1813 */
1814
1815 return NOTIFY_OK;
1816
1817 default:
1818 return NOTIFY_DONE;
1819 }
1820}
1821
1822static struct g12a_sys_pll_nb_data g12a_sys_pll_nb_data = {
1823 .sys_pll = &g12a_sys_pll.hw,
1824 .cpu_clk = &g12a_cpu_clk.hw,
1825 .cpu_clk_dyn = &g12a_cpu_clk_dyn.hw,
1826 .nb.notifier_call = g12a_sys_pll_notifier_cb,
1827};
1828
1829/* G12B first CPU cluster uses sys1_pll */
1830static struct g12a_sys_pll_nb_data g12b_cpu_clk_sys1_pll_nb_data = {
1831 .sys_pll = &g12b_sys1_pll.hw,
1832 .cpu_clk = &g12b_cpu_clk.hw,
1833 .cpu_clk_dyn = &g12a_cpu_clk_dyn.hw,
1834 .nb.notifier_call = g12a_sys_pll_notifier_cb,
1835};
1836
1837/* G12B second CPU cluster uses sys_pll */
1838static struct g12a_sys_pll_nb_data g12b_cpub_clk_sys_pll_nb_data = {
1839 .sys_pll = &g12a_sys_pll.hw,
1840 .cpu_clk = &g12b_cpub_clk.hw,
1841 .cpu_clk_dyn = &g12b_cpub_clk_dyn.hw,
1842 .nb.notifier_call = g12a_sys_pll_notifier_cb,
1843};
1844
1845static struct clk_regmap g12a_cpu_clk_div16_en = {
1846 .data = &(struct clk_regmap_gate_data){
1847 .offset = HHI_SYS_CPU_CLK_CNTL1,
1848 .bit_idx = 1,
1849 },
1850 .hw.init = &(struct clk_init_data) {
1851 .name = "cpu_clk_div16_en",
1852 .ops = &clk_regmap_gate_ro_ops,
1853 .parent_data = &(const struct clk_parent_data) {
1854 /*
1855 * Note:
1856 * G12A and G12B have different cpu clocks (with
1857 * different struct clk_hw). We fallback to the global
1858 * naming string mechanism so this clock picks
1859 * up the appropriate one. Same goes for the other
1860 * clock using cpu cluster A clock output and present
1861 * on both G12 variant.
1862 */
1863 .name = "cpu_clk",
1864 .index = -1,
1865 },
1866 .num_parents = 1,
1867 /*
1868 * This clock is used to debug the cpu_clk range
1869 * Linux should not change it at runtime
1870 */
1871 },
1872};
1873
1874static struct clk_regmap g12b_cpub_clk_div16_en = {
1875 .data = &(struct clk_regmap_gate_data){
1876 .offset = HHI_SYS_CPUB_CLK_CNTL1,
1877 .bit_idx = 1,
1878 },
1879 .hw.init = &(struct clk_init_data) {
1880 .name = "cpub_clk_div16_en",
1881 .ops = &clk_regmap_gate_ro_ops,
1882 .parent_hws = (const struct clk_hw *[]) {
1883 &g12b_cpub_clk.hw
1884 },
1885 .num_parents = 1,
1886 /*
1887 * This clock is used to debug the cpu_clk range
1888 * Linux should not change it at runtime
1889 */
1890 },
1891};
1892
1893static struct clk_fixed_factor g12a_cpu_clk_div16 = {
1894 .mult = 1,
1895 .div = 16,
1896 .hw.init = &(struct clk_init_data){
1897 .name = "cpu_clk_div16",
1898 .ops = &clk_fixed_factor_ops,
1899 .parent_hws = (const struct clk_hw *[]) {
1900 &g12a_cpu_clk_div16_en.hw
1901 },
1902 .num_parents = 1,
1903 },
1904};
1905
1906static struct clk_fixed_factor g12b_cpub_clk_div16 = {
1907 .mult = 1,
1908 .div = 16,
1909 .hw.init = &(struct clk_init_data){
1910 .name = "cpub_clk_div16",
1911 .ops = &clk_fixed_factor_ops,
1912 .parent_hws = (const struct clk_hw *[]) {
1913 &g12b_cpub_clk_div16_en.hw
1914 },
1915 .num_parents = 1,
1916 },
1917};
1918
1919static struct clk_regmap g12a_cpu_clk_apb_div = {
1920 .data = &(struct clk_regmap_div_data){
1921 .offset = HHI_SYS_CPU_CLK_CNTL1,
1922 .shift = 3,
1923 .width = 3,
1924 .flags = CLK_DIVIDER_POWER_OF_TWO,
1925 },
1926 .hw.init = &(struct clk_init_data){
1927 .name = "cpu_clk_apb_div",
1928 .ops = &clk_regmap_divider_ro_ops,
1929 .parent_data = &(const struct clk_parent_data) {
1930 .name = "cpu_clk",
1931 .index = -1,
1932 },
1933 .num_parents = 1,
1934 },
1935};
1936
1937static struct clk_regmap g12a_cpu_clk_apb = {
1938 .data = &(struct clk_regmap_gate_data){
1939 .offset = HHI_SYS_CPU_CLK_CNTL1,
1940 .bit_idx = 1,
1941 },
1942 .hw.init = &(struct clk_init_data) {
1943 .name = "cpu_clk_apb",
1944 .ops = &clk_regmap_gate_ro_ops,
1945 .parent_hws = (const struct clk_hw *[]) {
1946 &g12a_cpu_clk_apb_div.hw
1947 },
1948 .num_parents = 1,
1949 /*
1950 * This clock is set by the ROM monitor code,
1951 * Linux should not change it at runtime
1952 */
1953 },
1954};
1955
1956static struct clk_regmap g12a_cpu_clk_atb_div = {
1957 .data = &(struct clk_regmap_div_data){
1958 .offset = HHI_SYS_CPU_CLK_CNTL1,
1959 .shift = 6,
1960 .width = 3,
1961 .flags = CLK_DIVIDER_POWER_OF_TWO,
1962 },
1963 .hw.init = &(struct clk_init_data){
1964 .name = "cpu_clk_atb_div",
1965 .ops = &clk_regmap_divider_ro_ops,
1966 .parent_data = &(const struct clk_parent_data) {
1967 .name = "cpu_clk",
1968 .index = -1,
1969 },
1970 .num_parents = 1,
1971 },
1972};
1973
1974static struct clk_regmap g12a_cpu_clk_atb = {
1975 .data = &(struct clk_regmap_gate_data){
1976 .offset = HHI_SYS_CPU_CLK_CNTL1,
1977 .bit_idx = 17,
1978 },
1979 .hw.init = &(struct clk_init_data) {
1980 .name = "cpu_clk_atb",
1981 .ops = &clk_regmap_gate_ro_ops,
1982 .parent_hws = (const struct clk_hw *[]) {
1983 &g12a_cpu_clk_atb_div.hw
1984 },
1985 .num_parents = 1,
1986 /*
1987 * This clock is set by the ROM monitor code,
1988 * Linux should not change it at runtime
1989 */
1990 },
1991};
1992
1993static struct clk_regmap g12a_cpu_clk_axi_div = {
1994 .data = &(struct clk_regmap_div_data){
1995 .offset = HHI_SYS_CPU_CLK_CNTL1,
1996 .shift = 9,
1997 .width = 3,
1998 .flags = CLK_DIVIDER_POWER_OF_TWO,
1999 },
2000 .hw.init = &(struct clk_init_data){
2001 .name = "cpu_clk_axi_div",
2002 .ops = &clk_regmap_divider_ro_ops,
2003 .parent_data = &(const struct clk_parent_data) {
2004 .name = "cpu_clk",
2005 .index = -1,
2006 },
2007 .num_parents = 1,
2008 },
2009};
2010
2011static struct clk_regmap g12a_cpu_clk_axi = {
2012 .data = &(struct clk_regmap_gate_data){
2013 .offset = HHI_SYS_CPU_CLK_CNTL1,
2014 .bit_idx = 18,
2015 },
2016 .hw.init = &(struct clk_init_data) {
2017 .name = "cpu_clk_axi",
2018 .ops = &clk_regmap_gate_ro_ops,
2019 .parent_hws = (const struct clk_hw *[]) {
2020 &g12a_cpu_clk_axi_div.hw
2021 },
2022 .num_parents = 1,
2023 /*
2024 * This clock is set by the ROM monitor code,
2025 * Linux should not change it at runtime
2026 */
2027 },
2028};
2029
2030static struct clk_regmap g12a_cpu_clk_trace_div = {
2031 .data = &(struct clk_regmap_div_data){
2032 .offset = HHI_SYS_CPU_CLK_CNTL1,
2033 .shift = 20,
2034 .width = 3,
2035 .flags = CLK_DIVIDER_POWER_OF_TWO,
2036 },
2037 .hw.init = &(struct clk_init_data){
2038 .name = "cpu_clk_trace_div",
2039 .ops = &clk_regmap_divider_ro_ops,
2040 .parent_data = &(const struct clk_parent_data) {
2041 .name = "cpu_clk",
2042 .index = -1,
2043 },
2044 .num_parents = 1,
2045 },
2046};
2047
2048static struct clk_regmap g12a_cpu_clk_trace = {
2049 .data = &(struct clk_regmap_gate_data){
2050 .offset = HHI_SYS_CPU_CLK_CNTL1,
2051 .bit_idx = 23,
2052 },
2053 .hw.init = &(struct clk_init_data) {
2054 .name = "cpu_clk_trace",
2055 .ops = &clk_regmap_gate_ro_ops,
2056 .parent_hws = (const struct clk_hw *[]) {
2057 &g12a_cpu_clk_trace_div.hw
2058 },
2059 .num_parents = 1,
2060 /*
2061 * This clock is set by the ROM monitor code,
2062 * Linux should not change it at runtime
2063 */
2064 },
2065};
2066
2067static struct clk_fixed_factor g12b_cpub_clk_div2 = {
2068 .mult = 1,
2069 .div = 2,
2070 .hw.init = &(struct clk_init_data){
2071 .name = "cpub_clk_div2",
2072 .ops = &clk_fixed_factor_ops,
2073 .parent_hws = (const struct clk_hw *[]) {
2074 &g12b_cpub_clk.hw
2075 },
2076 .num_parents = 1,
2077 },
2078};
2079
2080static struct clk_fixed_factor g12b_cpub_clk_div3 = {
2081 .mult = 1,
2082 .div = 3,
2083 .hw.init = &(struct clk_init_data){
2084 .name = "cpub_clk_div3",
2085 .ops = &clk_fixed_factor_ops,
2086 .parent_hws = (const struct clk_hw *[]) {
2087 &g12b_cpub_clk.hw
2088 },
2089 .num_parents = 1,
2090 },
2091};
2092
2093static struct clk_fixed_factor g12b_cpub_clk_div4 = {
2094 .mult = 1,
2095 .div = 4,
2096 .hw.init = &(struct clk_init_data){
2097 .name = "cpub_clk_div4",
2098 .ops = &clk_fixed_factor_ops,
2099 .parent_hws = (const struct clk_hw *[]) {
2100 &g12b_cpub_clk.hw
2101 },
2102 .num_parents = 1,
2103 },
2104};
2105
2106static struct clk_fixed_factor g12b_cpub_clk_div5 = {
2107 .mult = 1,
2108 .div = 5,
2109 .hw.init = &(struct clk_init_data){
2110 .name = "cpub_clk_div5",
2111 .ops = &clk_fixed_factor_ops,
2112 .parent_hws = (const struct clk_hw *[]) {
2113 &g12b_cpub_clk.hw
2114 },
2115 .num_parents = 1,
2116 },
2117};
2118
2119static struct clk_fixed_factor g12b_cpub_clk_div6 = {
2120 .mult = 1,
2121 .div = 6,
2122 .hw.init = &(struct clk_init_data){
2123 .name = "cpub_clk_div6",
2124 .ops = &clk_fixed_factor_ops,
2125 .parent_hws = (const struct clk_hw *[]) {
2126 &g12b_cpub_clk.hw
2127 },
2128 .num_parents = 1,
2129 },
2130};
2131
2132static struct clk_fixed_factor g12b_cpub_clk_div7 = {
2133 .mult = 1,
2134 .div = 7,
2135 .hw.init = &(struct clk_init_data){
2136 .name = "cpub_clk_div7",
2137 .ops = &clk_fixed_factor_ops,
2138 .parent_hws = (const struct clk_hw *[]) {
2139 &g12b_cpub_clk.hw
2140 },
2141 .num_parents = 1,
2142 },
2143};
2144
2145static struct clk_fixed_factor g12b_cpub_clk_div8 = {
2146 .mult = 1,
2147 .div = 8,
2148 .hw.init = &(struct clk_init_data){
2149 .name = "cpub_clk_div8",
2150 .ops = &clk_fixed_factor_ops,
2151 .parent_hws = (const struct clk_hw *[]) {
2152 &g12b_cpub_clk.hw
2153 },
2154 .num_parents = 1,
2155 },
2156};
2157
2158static u32 g12b_cpub_clk_if_parents_val_table[] = { 1, 2, 3, 4, 5, 6, 7 };
2159static const struct clk_hw *g12b_cpub_clk_if_parents[] = {
2160 &g12b_cpub_clk_div2.hw,
2161 &g12b_cpub_clk_div3.hw,
2162 &g12b_cpub_clk_div4.hw,
2163 &g12b_cpub_clk_div5.hw,
2164 &g12b_cpub_clk_div6.hw,
2165 &g12b_cpub_clk_div7.hw,
2166 &g12b_cpub_clk_div8.hw,
2167};
2168
2169static struct clk_regmap g12b_cpub_clk_apb_sel = {
2170 .data = &(struct clk_regmap_mux_data){
2171 .offset = HHI_SYS_CPUB_CLK_CNTL1,
2172 .mask = 7,
2173 .shift = 3,
2174 .table = g12b_cpub_clk_if_parents_val_table,
2175 },
2176 .hw.init = &(struct clk_init_data){
2177 .name = "cpub_clk_apb_sel",
2178 .ops = &clk_regmap_mux_ro_ops,
2179 .parent_hws = g12b_cpub_clk_if_parents,
2180 .num_parents = ARRAY_SIZE(g12b_cpub_clk_if_parents),
2181 },
2182};
2183
2184static struct clk_regmap g12b_cpub_clk_apb = {
2185 .data = &(struct clk_regmap_gate_data){
2186 .offset = HHI_SYS_CPUB_CLK_CNTL1,
2187 .bit_idx = 16,
2188 .flags = CLK_GATE_SET_TO_DISABLE,
2189 },
2190 .hw.init = &(struct clk_init_data) {
2191 .name = "cpub_clk_apb",
2192 .ops = &clk_regmap_gate_ro_ops,
2193 .parent_hws = (const struct clk_hw *[]) {
2194 &g12b_cpub_clk_apb_sel.hw
2195 },
2196 .num_parents = 1,
2197 /*
2198 * This clock is set by the ROM monitor code,
2199 * Linux should not change it at runtime
2200 */
2201 },
2202};
2203
2204static struct clk_regmap g12b_cpub_clk_atb_sel = {
2205 .data = &(struct clk_regmap_mux_data){
2206 .offset = HHI_SYS_CPUB_CLK_CNTL1,
2207 .mask = 7,
2208 .shift = 6,
2209 .table = g12b_cpub_clk_if_parents_val_table,
2210 },
2211 .hw.init = &(struct clk_init_data){
2212 .name = "cpub_clk_atb_sel",
2213 .ops = &clk_regmap_mux_ro_ops,
2214 .parent_hws = g12b_cpub_clk_if_parents,
2215 .num_parents = ARRAY_SIZE(g12b_cpub_clk_if_parents),
2216 },
2217};
2218
2219static struct clk_regmap g12b_cpub_clk_atb = {
2220 .data = &(struct clk_regmap_gate_data){
2221 .offset = HHI_SYS_CPUB_CLK_CNTL1,
2222 .bit_idx = 17,
2223 .flags = CLK_GATE_SET_TO_DISABLE,
2224 },
2225 .hw.init = &(struct clk_init_data) {
2226 .name = "cpub_clk_atb",
2227 .ops = &clk_regmap_gate_ro_ops,
2228 .parent_hws = (const struct clk_hw *[]) {
2229 &g12b_cpub_clk_atb_sel.hw
2230 },
2231 .num_parents = 1,
2232 /*
2233 * This clock is set by the ROM monitor code,
2234 * Linux should not change it at runtime
2235 */
2236 },
2237};
2238
2239static struct clk_regmap g12b_cpub_clk_axi_sel = {
2240 .data = &(struct clk_regmap_mux_data){
2241 .offset = HHI_SYS_CPUB_CLK_CNTL1,
2242 .mask = 7,
2243 .shift = 9,
2244 .table = g12b_cpub_clk_if_parents_val_table,
2245 },
2246 .hw.init = &(struct clk_init_data){
2247 .name = "cpub_clk_axi_sel",
2248 .ops = &clk_regmap_mux_ro_ops,
2249 .parent_hws = g12b_cpub_clk_if_parents,
2250 .num_parents = ARRAY_SIZE(g12b_cpub_clk_if_parents),
2251 },
2252};
2253
2254static struct clk_regmap g12b_cpub_clk_axi = {
2255 .data = &(struct clk_regmap_gate_data){
2256 .offset = HHI_SYS_CPUB_CLK_CNTL1,
2257 .bit_idx = 18,
2258 .flags = CLK_GATE_SET_TO_DISABLE,
2259 },
2260 .hw.init = &(struct clk_init_data) {
2261 .name = "cpub_clk_axi",
2262 .ops = &clk_regmap_gate_ro_ops,
2263 .parent_hws = (const struct clk_hw *[]) {
2264 &g12b_cpub_clk_axi_sel.hw
2265 },
2266 .num_parents = 1,
2267 /*
2268 * This clock is set by the ROM monitor code,
2269 * Linux should not change it at runtime
2270 */
2271 },
2272};
2273
2274static struct clk_regmap g12b_cpub_clk_trace_sel = {
2275 .data = &(struct clk_regmap_mux_data){
2276 .offset = HHI_SYS_CPUB_CLK_CNTL1,
2277 .mask = 7,
2278 .shift = 20,
2279 .table = g12b_cpub_clk_if_parents_val_table,
2280 },
2281 .hw.init = &(struct clk_init_data){
2282 .name = "cpub_clk_trace_sel",
2283 .ops = &clk_regmap_mux_ro_ops,
2284 .parent_hws = g12b_cpub_clk_if_parents,
2285 .num_parents = ARRAY_SIZE(g12b_cpub_clk_if_parents),
2286 },
2287};
2288
2289static struct clk_regmap g12b_cpub_clk_trace = {
2290 .data = &(struct clk_regmap_gate_data){
2291 .offset = HHI_SYS_CPUB_CLK_CNTL1,
2292 .bit_idx = 23,
2293 .flags = CLK_GATE_SET_TO_DISABLE,
2294 },
2295 .hw.init = &(struct clk_init_data) {
2296 .name = "cpub_clk_trace",
2297 .ops = &clk_regmap_gate_ro_ops,
2298 .parent_hws = (const struct clk_hw *[]) {
2299 &g12b_cpub_clk_trace_sel.hw
2300 },
2301 .num_parents = 1,
2302 /*
2303 * This clock is set by the ROM monitor code,
2304 * Linux should not change it at runtime
2305 */
2306 },
2307};
2308
2309static const struct reg_sequence g12a_mpll0_init_regs[] = {
2310 { .reg = HHI_MPLL_CNTL2, .def = 0x40000033 },
2311};
2312
2313static struct clk_regmap g12a_mpll0_div = {
2314 .data = &(struct meson_clk_mpll_data){
2315 .sdm = {
2316 .reg_off = HHI_MPLL_CNTL1,
2317 .shift = 0,
2318 .width = 14,
2319 },
2320 .sdm_en = {
2321 .reg_off = HHI_MPLL_CNTL1,
2322 .shift = 30,
2323 .width = 1,
2324 },
2325 .n2 = {
2326 .reg_off = HHI_MPLL_CNTL1,
2327 .shift = 20,
2328 .width = 9,
2329 },
2330 .ssen = {
2331 .reg_off = HHI_MPLL_CNTL1,
2332 .shift = 29,
2333 .width = 1,
2334 },
2335 .init_regs = g12a_mpll0_init_regs,
2336 .init_count = ARRAY_SIZE(g12a_mpll0_init_regs),
2337 },
2338 .hw.init = &(struct clk_init_data){
2339 .name = "mpll0_div",
2340 .ops = &meson_clk_mpll_ops,
2341 .parent_hws = (const struct clk_hw *[]) {
2342 &g12a_mpll_prediv.hw
2343 },
2344 .num_parents = 1,
2345 },
2346};
2347
2348static struct clk_regmap g12a_mpll0 = {
2349 .data = &(struct clk_regmap_gate_data){
2350 .offset = HHI_MPLL_CNTL1,
2351 .bit_idx = 31,
2352 },
2353 .hw.init = &(struct clk_init_data){
2354 .name = "mpll0",
2355 .ops = &clk_regmap_gate_ops,
2356 .parent_hws = (const struct clk_hw *[]) { &g12a_mpll0_div.hw },
2357 .num_parents = 1,
2358 .flags = CLK_SET_RATE_PARENT,
2359 },
2360};
2361
2362static const struct reg_sequence g12a_mpll1_init_regs[] = {
2363 { .reg = HHI_MPLL_CNTL4, .def = 0x40000033 },
2364};
2365
2366static struct clk_regmap g12a_mpll1_div = {
2367 .data = &(struct meson_clk_mpll_data){
2368 .sdm = {
2369 .reg_off = HHI_MPLL_CNTL3,
2370 .shift = 0,
2371 .width = 14,
2372 },
2373 .sdm_en = {
2374 .reg_off = HHI_MPLL_CNTL3,
2375 .shift = 30,
2376 .width = 1,
2377 },
2378 .n2 = {
2379 .reg_off = HHI_MPLL_CNTL3,
2380 .shift = 20,
2381 .width = 9,
2382 },
2383 .ssen = {
2384 .reg_off = HHI_MPLL_CNTL3,
2385 .shift = 29,
2386 .width = 1,
2387 },
2388 .init_regs = g12a_mpll1_init_regs,
2389 .init_count = ARRAY_SIZE(g12a_mpll1_init_regs),
2390 },
2391 .hw.init = &(struct clk_init_data){
2392 .name = "mpll1_div",
2393 .ops = &meson_clk_mpll_ops,
2394 .parent_hws = (const struct clk_hw *[]) {
2395 &g12a_mpll_prediv.hw
2396 },
2397 .num_parents = 1,
2398 },
2399};
2400
2401static struct clk_regmap g12a_mpll1 = {
2402 .data = &(struct clk_regmap_gate_data){
2403 .offset = HHI_MPLL_CNTL3,
2404 .bit_idx = 31,
2405 },
2406 .hw.init = &(struct clk_init_data){
2407 .name = "mpll1",
2408 .ops = &clk_regmap_gate_ops,
2409 .parent_hws = (const struct clk_hw *[]) { &g12a_mpll1_div.hw },
2410 .num_parents = 1,
2411 .flags = CLK_SET_RATE_PARENT,
2412 },
2413};
2414
2415static const struct reg_sequence g12a_mpll2_init_regs[] = {
2416 { .reg = HHI_MPLL_CNTL6, .def = 0x40000033 },
2417};
2418
2419static struct clk_regmap g12a_mpll2_div = {
2420 .data = &(struct meson_clk_mpll_data){
2421 .sdm = {
2422 .reg_off = HHI_MPLL_CNTL5,
2423 .shift = 0,
2424 .width = 14,
2425 },
2426 .sdm_en = {
2427 .reg_off = HHI_MPLL_CNTL5,
2428 .shift = 30,
2429 .width = 1,
2430 },
2431 .n2 = {
2432 .reg_off = HHI_MPLL_CNTL5,
2433 .shift = 20,
2434 .width = 9,
2435 },
2436 .ssen = {
2437 .reg_off = HHI_MPLL_CNTL5,
2438 .shift = 29,
2439 .width = 1,
2440 },
2441 .init_regs = g12a_mpll2_init_regs,
2442 .init_count = ARRAY_SIZE(g12a_mpll2_init_regs),
2443 },
2444 .hw.init = &(struct clk_init_data){
2445 .name = "mpll2_div",
2446 .ops = &meson_clk_mpll_ops,
2447 .parent_hws = (const struct clk_hw *[]) {
2448 &g12a_mpll_prediv.hw
2449 },
2450 .num_parents = 1,
2451 },
2452};
2453
2454static struct clk_regmap g12a_mpll2 = {
2455 .data = &(struct clk_regmap_gate_data){
2456 .offset = HHI_MPLL_CNTL5,
2457 .bit_idx = 31,
2458 },
2459 .hw.init = &(struct clk_init_data){
2460 .name = "mpll2",
2461 .ops = &clk_regmap_gate_ops,
2462 .parent_hws = (const struct clk_hw *[]) { &g12a_mpll2_div.hw },
2463 .num_parents = 1,
2464 .flags = CLK_SET_RATE_PARENT,
2465 },
2466};
2467
2468static const struct reg_sequence g12a_mpll3_init_regs[] = {
2469 { .reg = HHI_MPLL_CNTL8, .def = 0x40000033 },
2470};
2471
2472static struct clk_regmap g12a_mpll3_div = {
2473 .data = &(struct meson_clk_mpll_data){
2474 .sdm = {
2475 .reg_off = HHI_MPLL_CNTL7,
2476 .shift = 0,
2477 .width = 14,
2478 },
2479 .sdm_en = {
2480 .reg_off = HHI_MPLL_CNTL7,
2481 .shift = 30,
2482 .width = 1,
2483 },
2484 .n2 = {
2485 .reg_off = HHI_MPLL_CNTL7,
2486 .shift = 20,
2487 .width = 9,
2488 },
2489 .ssen = {
2490 .reg_off = HHI_MPLL_CNTL7,
2491 .shift = 29,
2492 .width = 1,
2493 },
2494 .init_regs = g12a_mpll3_init_regs,
2495 .init_count = ARRAY_SIZE(g12a_mpll3_init_regs),
2496 },
2497 .hw.init = &(struct clk_init_data){
2498 .name = "mpll3_div",
2499 .ops = &meson_clk_mpll_ops,
2500 .parent_hws = (const struct clk_hw *[]) {
2501 &g12a_mpll_prediv.hw
2502 },
2503 .num_parents = 1,
2504 },
2505};
2506
2507static struct clk_regmap g12a_mpll3 = {
2508 .data = &(struct clk_regmap_gate_data){
2509 .offset = HHI_MPLL_CNTL7,
2510 .bit_idx = 31,
2511 },
2512 .hw.init = &(struct clk_init_data){
2513 .name = "mpll3",
2514 .ops = &clk_regmap_gate_ops,
2515 .parent_hws = (const struct clk_hw *[]) { &g12a_mpll3_div.hw },
2516 .num_parents = 1,
2517 .flags = CLK_SET_RATE_PARENT,
2518 },
2519};
2520
2521/* clk81 is often referred as "mpeg_clk" */
2522static u32 g12a_clk81_parents_val_table[] = { 0, 2, 3, 4, 5, 6, 7 };
2523static const struct clk_parent_data g12a_clk81_parents[] = {
2524 { .fw_name = "xtal", },
2525 { .hw = &g12a_fclk_div7.hw },
2526 { .hw = &g12a_mpll1.hw },
2527 { .hw = &g12a_mpll2.hw },
2528 { .hw = &g12a_fclk_div4.hw },
2529 { .hw = &g12a_fclk_div3.hw },
2530 { .hw = &g12a_fclk_div5.hw },
2531};
2532
2533static struct clk_regmap g12a_clk81_sel = {
2534 .data = &(struct clk_regmap_mux_data){
2535 .offset = HHI_MPEG_CLK_CNTL,
2536 .mask = 0x7,
2537 .shift = 12,
2538 .table = g12a_clk81_parents_val_table,
2539 },
2540 .hw.init = &(struct clk_init_data){
2541 .name = "clk81_sel",
2542 .ops = &clk_regmap_mux_ro_ops,
2543 .parent_data = g12a_clk81_parents,
2544 .num_parents = ARRAY_SIZE(g12a_clk81_parents),
2545 },
2546};
2547
2548static struct clk_regmap g12a_clk81_div = {
2549 .data = &(struct clk_regmap_div_data){
2550 .offset = HHI_MPEG_CLK_CNTL,
2551 .shift = 0,
2552 .width = 7,
2553 },
2554 .hw.init = &(struct clk_init_data){
2555 .name = "clk81_div",
2556 .ops = &clk_regmap_divider_ops,
2557 .parent_hws = (const struct clk_hw *[]) {
2558 &g12a_clk81_sel.hw
2559 },
2560 .num_parents = 1,
2561 .flags = CLK_SET_RATE_PARENT,
2562 },
2563};
2564
2565static struct clk_regmap g12a_clk81 = {
2566 .data = &(struct clk_regmap_gate_data){
2567 .offset = HHI_MPEG_CLK_CNTL,
2568 .bit_idx = 7,
2569 },
2570 .hw.init = &(struct clk_init_data){
2571 .name = "clk81",
2572 .ops = &clk_regmap_gate_ops,
2573 .parent_hws = (const struct clk_hw *[]) {
2574 &g12a_clk81_div.hw
2575 },
2576 .num_parents = 1,
2577 .flags = (CLK_SET_RATE_PARENT | CLK_IS_CRITICAL),
2578 },
2579};
2580
2581static const struct clk_parent_data g12a_sd_emmc_clk0_parents[] = {
2582 { .fw_name = "xtal", },
2583 { .hw = &g12a_fclk_div2.hw },
2584 { .hw = &g12a_fclk_div3.hw },
2585 { .hw = &g12a_fclk_div5.hw },
2586 { .hw = &g12a_fclk_div7.hw },
2587 /*
2588 * Following these parent clocks, we should also have had mpll2, mpll3
2589 * and gp0_pll but these clocks are too precious to be used here. All
2590 * the necessary rates for MMC and NAND operation can be achieved using
2591 * g12a_ee_core or fclk_div clocks
2592 */
2593};
2594
2595/* SDIO clock */
2596static struct clk_regmap g12a_sd_emmc_a_clk0_sel = {
2597 .data = &(struct clk_regmap_mux_data){
2598 .offset = HHI_SD_EMMC_CLK_CNTL,
2599 .mask = 0x7,
2600 .shift = 9,
2601 },
2602 .hw.init = &(struct clk_init_data) {
2603 .name = "sd_emmc_a_clk0_sel",
2604 .ops = &clk_regmap_mux_ops,
2605 .parent_data = g12a_sd_emmc_clk0_parents,
2606 .num_parents = ARRAY_SIZE(g12a_sd_emmc_clk0_parents),
2607 .flags = CLK_SET_RATE_PARENT,
2608 },
2609};
2610
2611static struct clk_regmap g12a_sd_emmc_a_clk0_div = {
2612 .data = &(struct clk_regmap_div_data){
2613 .offset = HHI_SD_EMMC_CLK_CNTL,
2614 .shift = 0,
2615 .width = 7,
2616 },
2617 .hw.init = &(struct clk_init_data) {
2618 .name = "sd_emmc_a_clk0_div",
2619 .ops = &clk_regmap_divider_ops,
2620 .parent_hws = (const struct clk_hw *[]) {
2621 &g12a_sd_emmc_a_clk0_sel.hw
2622 },
2623 .num_parents = 1,
2624 .flags = CLK_SET_RATE_PARENT,
2625 },
2626};
2627
2628static struct clk_regmap g12a_sd_emmc_a_clk0 = {
2629 .data = &(struct clk_regmap_gate_data){
2630 .offset = HHI_SD_EMMC_CLK_CNTL,
2631 .bit_idx = 7,
2632 },
2633 .hw.init = &(struct clk_init_data){
2634 .name = "sd_emmc_a_clk0",
2635 .ops = &clk_regmap_gate_ops,
2636 .parent_hws = (const struct clk_hw *[]) {
2637 &g12a_sd_emmc_a_clk0_div.hw
2638 },
2639 .num_parents = 1,
2640 .flags = CLK_SET_RATE_PARENT,
2641 },
2642};
2643
2644/* SDcard clock */
2645static struct clk_regmap g12a_sd_emmc_b_clk0_sel = {
2646 .data = &(struct clk_regmap_mux_data){
2647 .offset = HHI_SD_EMMC_CLK_CNTL,
2648 .mask = 0x7,
2649 .shift = 25,
2650 },
2651 .hw.init = &(struct clk_init_data) {
2652 .name = "sd_emmc_b_clk0_sel",
2653 .ops = &clk_regmap_mux_ops,
2654 .parent_data = g12a_sd_emmc_clk0_parents,
2655 .num_parents = ARRAY_SIZE(g12a_sd_emmc_clk0_parents),
2656 .flags = CLK_SET_RATE_PARENT,
2657 },
2658};
2659
2660static struct clk_regmap g12a_sd_emmc_b_clk0_div = {
2661 .data = &(struct clk_regmap_div_data){
2662 .offset = HHI_SD_EMMC_CLK_CNTL,
2663 .shift = 16,
2664 .width = 7,
2665 },
2666 .hw.init = &(struct clk_init_data) {
2667 .name = "sd_emmc_b_clk0_div",
2668 .ops = &clk_regmap_divider_ops,
2669 .parent_hws = (const struct clk_hw *[]) {
2670 &g12a_sd_emmc_b_clk0_sel.hw
2671 },
2672 .num_parents = 1,
2673 .flags = CLK_SET_RATE_PARENT,
2674 },
2675};
2676
2677static struct clk_regmap g12a_sd_emmc_b_clk0 = {
2678 .data = &(struct clk_regmap_gate_data){
2679 .offset = HHI_SD_EMMC_CLK_CNTL,
2680 .bit_idx = 23,
2681 },
2682 .hw.init = &(struct clk_init_data){
2683 .name = "sd_emmc_b_clk0",
2684 .ops = &clk_regmap_gate_ops,
2685 .parent_hws = (const struct clk_hw *[]) {
2686 &g12a_sd_emmc_b_clk0_div.hw
2687 },
2688 .num_parents = 1,
2689 .flags = CLK_SET_RATE_PARENT,
2690 },
2691};
2692
2693/* EMMC/NAND clock */
2694static struct clk_regmap g12a_sd_emmc_c_clk0_sel = {
2695 .data = &(struct clk_regmap_mux_data){
2696 .offset = HHI_NAND_CLK_CNTL,
2697 .mask = 0x7,
2698 .shift = 9,
2699 },
2700 .hw.init = &(struct clk_init_data) {
2701 .name = "sd_emmc_c_clk0_sel",
2702 .ops = &clk_regmap_mux_ops,
2703 .parent_data = g12a_sd_emmc_clk0_parents,
2704 .num_parents = ARRAY_SIZE(g12a_sd_emmc_clk0_parents),
2705 .flags = CLK_SET_RATE_PARENT,
2706 },
2707};
2708
2709static struct clk_regmap g12a_sd_emmc_c_clk0_div = {
2710 .data = &(struct clk_regmap_div_data){
2711 .offset = HHI_NAND_CLK_CNTL,
2712 .shift = 0,
2713 .width = 7,
2714 },
2715 .hw.init = &(struct clk_init_data) {
2716 .name = "sd_emmc_c_clk0_div",
2717 .ops = &clk_regmap_divider_ops,
2718 .parent_hws = (const struct clk_hw *[]) {
2719 &g12a_sd_emmc_c_clk0_sel.hw
2720 },
2721 .num_parents = 1,
2722 .flags = CLK_SET_RATE_PARENT,
2723 },
2724};
2725
2726static struct clk_regmap g12a_sd_emmc_c_clk0 = {
2727 .data = &(struct clk_regmap_gate_data){
2728 .offset = HHI_NAND_CLK_CNTL,
2729 .bit_idx = 7,
2730 },
2731 .hw.init = &(struct clk_init_data){
2732 .name = "sd_emmc_c_clk0",
2733 .ops = &clk_regmap_gate_ops,
2734 .parent_hws = (const struct clk_hw *[]) {
2735 &g12a_sd_emmc_c_clk0_div.hw
2736 },
2737 .num_parents = 1,
2738 .flags = CLK_SET_RATE_PARENT,
2739 },
2740};
2741
2742/* Video Clocks */
2743
2744static struct clk_regmap g12a_vid_pll_div = {
2745 .data = &(struct meson_vid_pll_div_data){
2746 .val = {
2747 .reg_off = HHI_VID_PLL_CLK_DIV,
2748 .shift = 0,
2749 .width = 15,
2750 },
2751 .sel = {
2752 .reg_off = HHI_VID_PLL_CLK_DIV,
2753 .shift = 16,
2754 .width = 2,
2755 },
2756 },
2757 .hw.init = &(struct clk_init_data) {
2758 .name = "vid_pll_div",
2759 .ops = &meson_vid_pll_div_ro_ops,
2760 .parent_hws = (const struct clk_hw *[]) { &g12a_hdmi_pll.hw },
2761 .num_parents = 1,
2762 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
2763 },
2764};
2765
2766static const struct clk_hw *g12a_vid_pll_parents[] = {
2767 &g12a_vid_pll_div.hw,
2768 &g12a_hdmi_pll.hw,
2769};
2770
2771static struct clk_regmap g12a_vid_pll_sel = {
2772 .data = &(struct clk_regmap_mux_data){
2773 .offset = HHI_VID_PLL_CLK_DIV,
2774 .mask = 0x1,
2775 .shift = 18,
2776 },
2777 .hw.init = &(struct clk_init_data){
2778 .name = "vid_pll_sel",
2779 .ops = &clk_regmap_mux_ops,
2780 /*
2781 * bit 18 selects from 2 possible parents:
2782 * vid_pll_div or hdmi_pll
2783 */
2784 .parent_hws = g12a_vid_pll_parents,
2785 .num_parents = ARRAY_SIZE(g12a_vid_pll_parents),
2786 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
2787 },
2788};
2789
2790static struct clk_regmap g12a_vid_pll = {
2791 .data = &(struct clk_regmap_gate_data){
2792 .offset = HHI_VID_PLL_CLK_DIV,
2793 .bit_idx = 19,
2794 },
2795 .hw.init = &(struct clk_init_data) {
2796 .name = "vid_pll",
2797 .ops = &clk_regmap_gate_ops,
2798 .parent_hws = (const struct clk_hw *[]) {
2799 &g12a_vid_pll_sel.hw
2800 },
2801 .num_parents = 1,
2802 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2803 },
2804};
2805
2806/* VPU Clock */
2807
2808static const struct clk_hw *g12a_vpu_parents[] = {
2809 &g12a_fclk_div3.hw,
2810 &g12a_fclk_div4.hw,
2811 &g12a_fclk_div5.hw,
2812 &g12a_fclk_div7.hw,
2813 &g12a_mpll1.hw,
2814 &g12a_vid_pll.hw,
2815 &g12a_hifi_pll.hw,
2816 &g12a_gp0_pll.hw,
2817};
2818
2819static struct clk_regmap g12a_vpu_0_sel = {
2820 .data = &(struct clk_regmap_mux_data){
2821 .offset = HHI_VPU_CLK_CNTL,
2822 .mask = 0x7,
2823 .shift = 9,
2824 },
2825 .hw.init = &(struct clk_init_data){
2826 .name = "vpu_0_sel",
2827 .ops = &clk_regmap_mux_ops,
2828 .parent_hws = g12a_vpu_parents,
2829 .num_parents = ARRAY_SIZE(g12a_vpu_parents),
2830 .flags = CLK_SET_RATE_NO_REPARENT,
2831 },
2832};
2833
2834static struct clk_regmap g12a_vpu_0_div = {
2835 .data = &(struct clk_regmap_div_data){
2836 .offset = HHI_VPU_CLK_CNTL,
2837 .shift = 0,
2838 .width = 7,
2839 },
2840 .hw.init = &(struct clk_init_data){
2841 .name = "vpu_0_div",
2842 .ops = &clk_regmap_divider_ops,
2843 .parent_hws = (const struct clk_hw *[]) { &g12a_vpu_0_sel.hw },
2844 .num_parents = 1,
2845 .flags = CLK_SET_RATE_PARENT,
2846 },
2847};
2848
2849static struct clk_regmap g12a_vpu_0 = {
2850 .data = &(struct clk_regmap_gate_data){
2851 .offset = HHI_VPU_CLK_CNTL,
2852 .bit_idx = 8,
2853 },
2854 .hw.init = &(struct clk_init_data) {
2855 .name = "vpu_0",
2856 .ops = &clk_regmap_gate_ops,
2857 .parent_hws = (const struct clk_hw *[]) { &g12a_vpu_0_div.hw },
2858 .num_parents = 1,
2859 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2860 },
2861};
2862
2863static struct clk_regmap g12a_vpu_1_sel = {
2864 .data = &(struct clk_regmap_mux_data){
2865 .offset = HHI_VPU_CLK_CNTL,
2866 .mask = 0x7,
2867 .shift = 25,
2868 },
2869 .hw.init = &(struct clk_init_data){
2870 .name = "vpu_1_sel",
2871 .ops = &clk_regmap_mux_ops,
2872 .parent_hws = g12a_vpu_parents,
2873 .num_parents = ARRAY_SIZE(g12a_vpu_parents),
2874 .flags = CLK_SET_RATE_NO_REPARENT,
2875 },
2876};
2877
2878static struct clk_regmap g12a_vpu_1_div = {
2879 .data = &(struct clk_regmap_div_data){
2880 .offset = HHI_VPU_CLK_CNTL,
2881 .shift = 16,
2882 .width = 7,
2883 },
2884 .hw.init = &(struct clk_init_data){
2885 .name = "vpu_1_div",
2886 .ops = &clk_regmap_divider_ops,
2887 .parent_hws = (const struct clk_hw *[]) { &g12a_vpu_1_sel.hw },
2888 .num_parents = 1,
2889 .flags = CLK_SET_RATE_PARENT,
2890 },
2891};
2892
2893static struct clk_regmap g12a_vpu_1 = {
2894 .data = &(struct clk_regmap_gate_data){
2895 .offset = HHI_VPU_CLK_CNTL,
2896 .bit_idx = 24,
2897 },
2898 .hw.init = &(struct clk_init_data) {
2899 .name = "vpu_1",
2900 .ops = &clk_regmap_gate_ops,
2901 .parent_hws = (const struct clk_hw *[]) { &g12a_vpu_1_div.hw },
2902 .num_parents = 1,
2903 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2904 },
2905};
2906
2907static struct clk_regmap g12a_vpu = {
2908 .data = &(struct clk_regmap_mux_data){
2909 .offset = HHI_VPU_CLK_CNTL,
2910 .mask = 1,
2911 .shift = 31,
2912 },
2913 .hw.init = &(struct clk_init_data){
2914 .name = "vpu",
2915 .ops = &clk_regmap_mux_ops,
2916 /*
2917 * bit 31 selects from 2 possible parents:
2918 * vpu_0 or vpu_1
2919 */
2920 .parent_hws = (const struct clk_hw *[]) {
2921 &g12a_vpu_0.hw,
2922 &g12a_vpu_1.hw,
2923 },
2924 .num_parents = 2,
2925 .flags = CLK_SET_RATE_NO_REPARENT,
2926 },
2927};
2928
2929/* VDEC clocks */
2930
2931static const struct clk_hw *g12a_vdec_parents[] = {
2932 &g12a_fclk_div2p5.hw,
2933 &g12a_fclk_div3.hw,
2934 &g12a_fclk_div4.hw,
2935 &g12a_fclk_div5.hw,
2936 &g12a_fclk_div7.hw,
2937 &g12a_hifi_pll.hw,
2938 &g12a_gp0_pll.hw,
2939};
2940
2941static struct clk_regmap g12a_vdec_1_sel = {
2942 .data = &(struct clk_regmap_mux_data){
2943 .offset = HHI_VDEC_CLK_CNTL,
2944 .mask = 0x7,
2945 .shift = 9,
2946 .flags = CLK_MUX_ROUND_CLOSEST,
2947 },
2948 .hw.init = &(struct clk_init_data){
2949 .name = "vdec_1_sel",
2950 .ops = &clk_regmap_mux_ops,
2951 .parent_hws = g12a_vdec_parents,
2952 .num_parents = ARRAY_SIZE(g12a_vdec_parents),
2953 .flags = CLK_SET_RATE_PARENT,
2954 },
2955};
2956
2957static struct clk_regmap g12a_vdec_1_div = {
2958 .data = &(struct clk_regmap_div_data){
2959 .offset = HHI_VDEC_CLK_CNTL,
2960 .shift = 0,
2961 .width = 7,
2962 .flags = CLK_DIVIDER_ROUND_CLOSEST,
2963 },
2964 .hw.init = &(struct clk_init_data){
2965 .name = "vdec_1_div",
2966 .ops = &clk_regmap_divider_ops,
2967 .parent_hws = (const struct clk_hw *[]) {
2968 &g12a_vdec_1_sel.hw
2969 },
2970 .num_parents = 1,
2971 .flags = CLK_SET_RATE_PARENT,
2972 },
2973};
2974
2975static struct clk_regmap g12a_vdec_1 = {
2976 .data = &(struct clk_regmap_gate_data){
2977 .offset = HHI_VDEC_CLK_CNTL,
2978 .bit_idx = 8,
2979 },
2980 .hw.init = &(struct clk_init_data) {
2981 .name = "vdec_1",
2982 .ops = &clk_regmap_gate_ops,
2983 .parent_hws = (const struct clk_hw *[]) {
2984 &g12a_vdec_1_div.hw
2985 },
2986 .num_parents = 1,
2987 .flags = CLK_SET_RATE_PARENT,
2988 },
2989};
2990
2991static struct clk_regmap g12a_vdec_hevcf_sel = {
2992 .data = &(struct clk_regmap_mux_data){
2993 .offset = HHI_VDEC2_CLK_CNTL,
2994 .mask = 0x7,
2995 .shift = 9,
2996 .flags = CLK_MUX_ROUND_CLOSEST,
2997 },
2998 .hw.init = &(struct clk_init_data){
2999 .name = "vdec_hevcf_sel",
3000 .ops = &clk_regmap_mux_ops,
3001 .parent_hws = g12a_vdec_parents,
3002 .num_parents = ARRAY_SIZE(g12a_vdec_parents),
3003 .flags = CLK_SET_RATE_PARENT,
3004 },
3005};
3006
3007static struct clk_regmap g12a_vdec_hevcf_div = {
3008 .data = &(struct clk_regmap_div_data){
3009 .offset = HHI_VDEC2_CLK_CNTL,
3010 .shift = 0,
3011 .width = 7,
3012 .flags = CLK_DIVIDER_ROUND_CLOSEST,
3013 },
3014 .hw.init = &(struct clk_init_data){
3015 .name = "vdec_hevcf_div",
3016 .ops = &clk_regmap_divider_ops,
3017 .parent_hws = (const struct clk_hw *[]) {
3018 &g12a_vdec_hevcf_sel.hw
3019 },
3020 .num_parents = 1,
3021 .flags = CLK_SET_RATE_PARENT,
3022 },
3023};
3024
3025static struct clk_regmap g12a_vdec_hevcf = {
3026 .data = &(struct clk_regmap_gate_data){
3027 .offset = HHI_VDEC2_CLK_CNTL,
3028 .bit_idx = 8,
3029 },
3030 .hw.init = &(struct clk_init_data) {
3031 .name = "vdec_hevcf",
3032 .ops = &clk_regmap_gate_ops,
3033 .parent_hws = (const struct clk_hw *[]) {
3034 &g12a_vdec_hevcf_div.hw
3035 },
3036 .num_parents = 1,
3037 .flags = CLK_SET_RATE_PARENT,
3038 },
3039};
3040
3041static struct clk_regmap g12a_vdec_hevc_sel = {
3042 .data = &(struct clk_regmap_mux_data){
3043 .offset = HHI_VDEC2_CLK_CNTL,
3044 .mask = 0x7,
3045 .shift = 25,
3046 .flags = CLK_MUX_ROUND_CLOSEST,
3047 },
3048 .hw.init = &(struct clk_init_data){
3049 .name = "vdec_hevc_sel",
3050 .ops = &clk_regmap_mux_ops,
3051 .parent_hws = g12a_vdec_parents,
3052 .num_parents = ARRAY_SIZE(g12a_vdec_parents),
3053 .flags = CLK_SET_RATE_PARENT,
3054 },
3055};
3056
3057static struct clk_regmap g12a_vdec_hevc_div = {
3058 .data = &(struct clk_regmap_div_data){
3059 .offset = HHI_VDEC2_CLK_CNTL,
3060 .shift = 16,
3061 .width = 7,
3062 .flags = CLK_DIVIDER_ROUND_CLOSEST,
3063 },
3064 .hw.init = &(struct clk_init_data){
3065 .name = "vdec_hevc_div",
3066 .ops = &clk_regmap_divider_ops,
3067 .parent_hws = (const struct clk_hw *[]) {
3068 &g12a_vdec_hevc_sel.hw
3069 },
3070 .num_parents = 1,
3071 .flags = CLK_SET_RATE_PARENT,
3072 },
3073};
3074
3075static struct clk_regmap g12a_vdec_hevc = {
3076 .data = &(struct clk_regmap_gate_data){
3077 .offset = HHI_VDEC2_CLK_CNTL,
3078 .bit_idx = 24,
3079 },
3080 .hw.init = &(struct clk_init_data) {
3081 .name = "vdec_hevc",
3082 .ops = &clk_regmap_gate_ops,
3083 .parent_hws = (const struct clk_hw *[]) {
3084 &g12a_vdec_hevc_div.hw
3085 },
3086 .num_parents = 1,
3087 .flags = CLK_SET_RATE_PARENT,
3088 },
3089};
3090
3091/* VAPB Clock */
3092
3093static const struct clk_hw *g12a_vapb_parents[] = {
3094 &g12a_fclk_div4.hw,
3095 &g12a_fclk_div3.hw,
3096 &g12a_fclk_div5.hw,
3097 &g12a_fclk_div7.hw,
3098 &g12a_mpll1.hw,
3099 &g12a_vid_pll.hw,
3100 &g12a_mpll2.hw,
3101 &g12a_fclk_div2p5.hw,
3102};
3103
3104static struct clk_regmap g12a_vapb_0_sel = {
3105 .data = &(struct clk_regmap_mux_data){
3106 .offset = HHI_VAPBCLK_CNTL,
3107 .mask = 0x3,
3108 .shift = 9,
3109 },
3110 .hw.init = &(struct clk_init_data){
3111 .name = "vapb_0_sel",
3112 .ops = &clk_regmap_mux_ops,
3113 .parent_hws = g12a_vapb_parents,
3114 .num_parents = ARRAY_SIZE(g12a_vapb_parents),
3115 .flags = CLK_SET_RATE_NO_REPARENT,
3116 },
3117};
3118
3119static struct clk_regmap g12a_vapb_0_div = {
3120 .data = &(struct clk_regmap_div_data){
3121 .offset = HHI_VAPBCLK_CNTL,
3122 .shift = 0,
3123 .width = 7,
3124 },
3125 .hw.init = &(struct clk_init_data){
3126 .name = "vapb_0_div",
3127 .ops = &clk_regmap_divider_ops,
3128 .parent_hws = (const struct clk_hw *[]) {
3129 &g12a_vapb_0_sel.hw
3130 },
3131 .num_parents = 1,
3132 .flags = CLK_SET_RATE_PARENT,
3133 },
3134};
3135
3136static struct clk_regmap g12a_vapb_0 = {
3137 .data = &(struct clk_regmap_gate_data){
3138 .offset = HHI_VAPBCLK_CNTL,
3139 .bit_idx = 8,
3140 },
3141 .hw.init = &(struct clk_init_data) {
3142 .name = "vapb_0",
3143 .ops = &clk_regmap_gate_ops,
3144 .parent_hws = (const struct clk_hw *[]) {
3145 &g12a_vapb_0_div.hw
3146 },
3147 .num_parents = 1,
3148 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3149 },
3150};
3151
3152static struct clk_regmap g12a_vapb_1_sel = {
3153 .data = &(struct clk_regmap_mux_data){
3154 .offset = HHI_VAPBCLK_CNTL,
3155 .mask = 0x3,
3156 .shift = 25,
3157 },
3158 .hw.init = &(struct clk_init_data){
3159 .name = "vapb_1_sel",
3160 .ops = &clk_regmap_mux_ops,
3161 .parent_hws = g12a_vapb_parents,
3162 .num_parents = ARRAY_SIZE(g12a_vapb_parents),
3163 .flags = CLK_SET_RATE_NO_REPARENT,
3164 },
3165};
3166
3167static struct clk_regmap g12a_vapb_1_div = {
3168 .data = &(struct clk_regmap_div_data){
3169 .offset = HHI_VAPBCLK_CNTL,
3170 .shift = 16,
3171 .width = 7,
3172 },
3173 .hw.init = &(struct clk_init_data){
3174 .name = "vapb_1_div",
3175 .ops = &clk_regmap_divider_ops,
3176 .parent_hws = (const struct clk_hw *[]) {
3177 &g12a_vapb_1_sel.hw
3178 },
3179 .num_parents = 1,
3180 .flags = CLK_SET_RATE_PARENT,
3181 },
3182};
3183
3184static struct clk_regmap g12a_vapb_1 = {
3185 .data = &(struct clk_regmap_gate_data){
3186 .offset = HHI_VAPBCLK_CNTL,
3187 .bit_idx = 24,
3188 },
3189 .hw.init = &(struct clk_init_data) {
3190 .name = "vapb_1",
3191 .ops = &clk_regmap_gate_ops,
3192 .parent_hws = (const struct clk_hw *[]) {
3193 &g12a_vapb_1_div.hw
3194 },
3195 .num_parents = 1,
3196 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3197 },
3198};
3199
3200static struct clk_regmap g12a_vapb_sel = {
3201 .data = &(struct clk_regmap_mux_data){
3202 .offset = HHI_VAPBCLK_CNTL,
3203 .mask = 1,
3204 .shift = 31,
3205 },
3206 .hw.init = &(struct clk_init_data){
3207 .name = "vapb_sel",
3208 .ops = &clk_regmap_mux_ops,
3209 /*
3210 * bit 31 selects from 2 possible parents:
3211 * vapb_0 or vapb_1
3212 */
3213 .parent_hws = (const struct clk_hw *[]) {
3214 &g12a_vapb_0.hw,
3215 &g12a_vapb_1.hw,
3216 },
3217 .num_parents = 2,
3218 .flags = CLK_SET_RATE_NO_REPARENT,
3219 },
3220};
3221
3222static struct clk_regmap g12a_vapb = {
3223 .data = &(struct clk_regmap_gate_data){
3224 .offset = HHI_VAPBCLK_CNTL,
3225 .bit_idx = 30,
3226 },
3227 .hw.init = &(struct clk_init_data) {
3228 .name = "vapb",
3229 .ops = &clk_regmap_gate_ops,
3230 .parent_hws = (const struct clk_hw *[]) { &g12a_vapb_sel.hw },
3231 .num_parents = 1,
3232 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3233 },
3234};
3235
3236static const struct clk_hw *g12a_vclk_parents[] = {
3237 &g12a_vid_pll.hw,
3238 &g12a_gp0_pll.hw,
3239 &g12a_hifi_pll.hw,
3240 &g12a_mpll1.hw,
3241 &g12a_fclk_div3.hw,
3242 &g12a_fclk_div4.hw,
3243 &g12a_fclk_div5.hw,
3244 &g12a_fclk_div7.hw,
3245};
3246
3247static struct clk_regmap g12a_vclk_sel = {
3248 .data = &(struct clk_regmap_mux_data){
3249 .offset = HHI_VID_CLK_CNTL,
3250 .mask = 0x7,
3251 .shift = 16,
3252 },
3253 .hw.init = &(struct clk_init_data){
3254 .name = "vclk_sel",
3255 .ops = &clk_regmap_mux_ops,
3256 .parent_hws = g12a_vclk_parents,
3257 .num_parents = ARRAY_SIZE(g12a_vclk_parents),
3258 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
3259 },
3260};
3261
3262static struct clk_regmap g12a_vclk2_sel = {
3263 .data = &(struct clk_regmap_mux_data){
3264 .offset = HHI_VIID_CLK_CNTL,
3265 .mask = 0x7,
3266 .shift = 16,
3267 },
3268 .hw.init = &(struct clk_init_data){
3269 .name = "vclk2_sel",
3270 .ops = &clk_regmap_mux_ops,
3271 .parent_hws = g12a_vclk_parents,
3272 .num_parents = ARRAY_SIZE(g12a_vclk_parents),
3273 .flags = CLK_SET_RATE_NO_REPARENT,
3274 },
3275};
3276
3277static struct clk_regmap g12a_vclk_input = {
3278 .data = &(struct clk_regmap_gate_data){
3279 .offset = HHI_VID_CLK_DIV,
3280 .bit_idx = 16,
3281 },
3282 .hw.init = &(struct clk_init_data) {
3283 .name = "vclk_input",
3284 .ops = &clk_regmap_gate_ops,
3285 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk_sel.hw },
3286 .num_parents = 1,
3287 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3288 },
3289};
3290
3291static struct clk_regmap g12a_vclk2_input = {
3292 .data = &(struct clk_regmap_gate_data){
3293 .offset = HHI_VIID_CLK_DIV,
3294 .bit_idx = 16,
3295 },
3296 .hw.init = &(struct clk_init_data) {
3297 .name = "vclk2_input",
3298 .ops = &clk_regmap_gate_ops,
3299 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2_sel.hw },
3300 .num_parents = 1,
3301 },
3302};
3303
3304static struct clk_regmap g12a_vclk_div = {
3305 .data = &(struct clk_regmap_div_data){
3306 .offset = HHI_VID_CLK_DIV,
3307 .shift = 0,
3308 .width = 8,
3309 },
3310 .hw.init = &(struct clk_init_data){
3311 .name = "vclk_div",
3312 .ops = &clk_regmap_divider_ops,
3313 .parent_hws = (const struct clk_hw *[]) {
3314 &g12a_vclk_input.hw
3315 },
3316 .num_parents = 1,
3317 .flags = CLK_GET_RATE_NOCACHE,
3318 },
3319};
3320
3321static struct clk_regmap g12a_vclk2_div = {
3322 .data = &(struct meson_vclk_div_data){
3323 .div = {
3324 .reg_off = HHI_VIID_CLK_DIV,
3325 .shift = 0,
3326 .width = 8,
3327 },
3328 .enable = {
3329 .reg_off = HHI_VIID_CLK_DIV,
3330 .shift = 16,
3331 .width = 1,
3332 },
3333 .reset = {
3334 .reg_off = HHI_VIID_CLK_DIV,
3335 .shift = 17,
3336 .width = 1,
3337 },
3338 .flags = CLK_DIVIDER_ROUND_CLOSEST,
3339 },
3340 .hw.init = &(struct clk_init_data){
3341 .name = "vclk2_div",
3342 .ops = &meson_vclk_div_ops,
3343 .parent_hws = (const struct clk_hw *[]) {
3344 &g12a_vclk2_input.hw
3345 },
3346 .num_parents = 1,
3347 .flags = CLK_SET_RATE_GATE,
3348 },
3349};
3350
3351static struct clk_regmap g12a_vclk = {
3352 .data = &(struct clk_regmap_gate_data){
3353 .offset = HHI_VID_CLK_CNTL,
3354 .bit_idx = 19,
3355 },
3356 .hw.init = &(struct clk_init_data) {
3357 .name = "vclk",
3358 .ops = &clk_regmap_gate_ops,
3359 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk_div.hw },
3360 .num_parents = 1,
3361 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3362 },
3363};
3364
3365static struct clk_regmap g12a_vclk2 = {
3366 .data = &(struct meson_vclk_gate_data){
3367 .enable = {
3368 .reg_off = HHI_VIID_CLK_CNTL,
3369 .shift = 19,
3370 .width = 1,
3371 },
3372 .reset = {
3373 .reg_off = HHI_VIID_CLK_CNTL,
3374 .shift = 15,
3375 .width = 1,
3376 },
3377 },
3378 .hw.init = &(struct clk_init_data) {
3379 .name = "vclk2",
3380 .ops = &meson_vclk_gate_ops,
3381 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2_div.hw },
3382 .num_parents = 1,
3383 .flags = CLK_SET_RATE_PARENT,
3384 },
3385};
3386
3387static struct clk_regmap g12a_vclk_div1 = {
3388 .data = &(struct clk_regmap_gate_data){
3389 .offset = HHI_VID_CLK_CNTL,
3390 .bit_idx = 0,
3391 },
3392 .hw.init = &(struct clk_init_data) {
3393 .name = "vclk_div1",
3394 .ops = &clk_regmap_gate_ops,
3395 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk.hw },
3396 .num_parents = 1,
3397 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3398 },
3399};
3400
3401static struct clk_regmap g12a_vclk_div2_en = {
3402 .data = &(struct clk_regmap_gate_data){
3403 .offset = HHI_VID_CLK_CNTL,
3404 .bit_idx = 1,
3405 },
3406 .hw.init = &(struct clk_init_data) {
3407 .name = "vclk_div2_en",
3408 .ops = &clk_regmap_gate_ops,
3409 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk.hw },
3410 .num_parents = 1,
3411 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3412 },
3413};
3414
3415static struct clk_regmap g12a_vclk_div4_en = {
3416 .data = &(struct clk_regmap_gate_data){
3417 .offset = HHI_VID_CLK_CNTL,
3418 .bit_idx = 2,
3419 },
3420 .hw.init = &(struct clk_init_data) {
3421 .name = "vclk_div4_en",
3422 .ops = &clk_regmap_gate_ops,
3423 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk.hw },
3424 .num_parents = 1,
3425 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3426 },
3427};
3428
3429static struct clk_regmap g12a_vclk_div6_en = {
3430 .data = &(struct clk_regmap_gate_data){
3431 .offset = HHI_VID_CLK_CNTL,
3432 .bit_idx = 3,
3433 },
3434 .hw.init = &(struct clk_init_data) {
3435 .name = "vclk_div6_en",
3436 .ops = &clk_regmap_gate_ops,
3437 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk.hw },
3438 .num_parents = 1,
3439 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3440 },
3441};
3442
3443static struct clk_regmap g12a_vclk_div12_en = {
3444 .data = &(struct clk_regmap_gate_data){
3445 .offset = HHI_VID_CLK_CNTL,
3446 .bit_idx = 4,
3447 },
3448 .hw.init = &(struct clk_init_data) {
3449 .name = "vclk_div12_en",
3450 .ops = &clk_regmap_gate_ops,
3451 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk.hw },
3452 .num_parents = 1,
3453 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3454 },
3455};
3456
3457static struct clk_regmap g12a_vclk2_div1 = {
3458 .data = &(struct clk_regmap_gate_data){
3459 .offset = HHI_VIID_CLK_CNTL,
3460 .bit_idx = 0,
3461 },
3462 .hw.init = &(struct clk_init_data) {
3463 .name = "vclk2_div1",
3464 .ops = &clk_regmap_gate_ops,
3465 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
3466 .num_parents = 1,
3467 .flags = CLK_SET_RATE_PARENT,
3468 },
3469};
3470
3471static struct clk_regmap g12a_vclk2_div2_en = {
3472 .data = &(struct clk_regmap_gate_data){
3473 .offset = HHI_VIID_CLK_CNTL,
3474 .bit_idx = 1,
3475 },
3476 .hw.init = &(struct clk_init_data) {
3477 .name = "vclk2_div2_en",
3478 .ops = &clk_regmap_gate_ops,
3479 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
3480 .num_parents = 1,
3481 .flags = CLK_SET_RATE_PARENT,
3482 },
3483};
3484
3485static struct clk_regmap g12a_vclk2_div4_en = {
3486 .data = &(struct clk_regmap_gate_data){
3487 .offset = HHI_VIID_CLK_CNTL,
3488 .bit_idx = 2,
3489 },
3490 .hw.init = &(struct clk_init_data) {
3491 .name = "vclk2_div4_en",
3492 .ops = &clk_regmap_gate_ops,
3493 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
3494 .num_parents = 1,
3495 .flags = CLK_SET_RATE_PARENT,
3496 },
3497};
3498
3499static struct clk_regmap g12a_vclk2_div6_en = {
3500 .data = &(struct clk_regmap_gate_data){
3501 .offset = HHI_VIID_CLK_CNTL,
3502 .bit_idx = 3,
3503 },
3504 .hw.init = &(struct clk_init_data) {
3505 .name = "vclk2_div6_en",
3506 .ops = &clk_regmap_gate_ops,
3507 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
3508 .num_parents = 1,
3509 .flags = CLK_SET_RATE_PARENT,
3510 },
3511};
3512
3513static struct clk_regmap g12a_vclk2_div12_en = {
3514 .data = &(struct clk_regmap_gate_data){
3515 .offset = HHI_VIID_CLK_CNTL,
3516 .bit_idx = 4,
3517 },
3518 .hw.init = &(struct clk_init_data) {
3519 .name = "vclk2_div12_en",
3520 .ops = &clk_regmap_gate_ops,
3521 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
3522 .num_parents = 1,
3523 .flags = CLK_SET_RATE_PARENT,
3524 },
3525};
3526
3527static struct clk_fixed_factor g12a_vclk_div2 = {
3528 .mult = 1,
3529 .div = 2,
3530 .hw.init = &(struct clk_init_data){
3531 .name = "vclk_div2",
3532 .ops = &clk_fixed_factor_ops,
3533 .parent_hws = (const struct clk_hw *[]) {
3534 &g12a_vclk_div2_en.hw
3535 },
3536 .num_parents = 1,
3537 },
3538};
3539
3540static struct clk_fixed_factor g12a_vclk_div4 = {
3541 .mult = 1,
3542 .div = 4,
3543 .hw.init = &(struct clk_init_data){
3544 .name = "vclk_div4",
3545 .ops = &clk_fixed_factor_ops,
3546 .parent_hws = (const struct clk_hw *[]) {
3547 &g12a_vclk_div4_en.hw
3548 },
3549 .num_parents = 1,
3550 },
3551};
3552
3553static struct clk_fixed_factor g12a_vclk_div6 = {
3554 .mult = 1,
3555 .div = 6,
3556 .hw.init = &(struct clk_init_data){
3557 .name = "vclk_div6",
3558 .ops = &clk_fixed_factor_ops,
3559 .parent_hws = (const struct clk_hw *[]) {
3560 &g12a_vclk_div6_en.hw
3561 },
3562 .num_parents = 1,
3563 },
3564};
3565
3566static struct clk_fixed_factor g12a_vclk_div12 = {
3567 .mult = 1,
3568 .div = 12,
3569 .hw.init = &(struct clk_init_data){
3570 .name = "vclk_div12",
3571 .ops = &clk_fixed_factor_ops,
3572 .parent_hws = (const struct clk_hw *[]) {
3573 &g12a_vclk_div12_en.hw
3574 },
3575 .num_parents = 1,
3576 },
3577};
3578
3579static struct clk_fixed_factor g12a_vclk2_div2 = {
3580 .mult = 1,
3581 .div = 2,
3582 .hw.init = &(struct clk_init_data){
3583 .name = "vclk2_div2",
3584 .ops = &clk_fixed_factor_ops,
3585 .parent_hws = (const struct clk_hw *[]) {
3586 &g12a_vclk2_div2_en.hw
3587 },
3588 .num_parents = 1,
3589 .flags = CLK_SET_RATE_PARENT,
3590 },
3591};
3592
3593static struct clk_fixed_factor g12a_vclk2_div4 = {
3594 .mult = 1,
3595 .div = 4,
3596 .hw.init = &(struct clk_init_data){
3597 .name = "vclk2_div4",
3598 .ops = &clk_fixed_factor_ops,
3599 .parent_hws = (const struct clk_hw *[]) {
3600 &g12a_vclk2_div4_en.hw
3601 },
3602 .num_parents = 1,
3603 .flags = CLK_SET_RATE_PARENT,
3604 },
3605};
3606
3607static struct clk_fixed_factor g12a_vclk2_div6 = {
3608 .mult = 1,
3609 .div = 6,
3610 .hw.init = &(struct clk_init_data){
3611 .name = "vclk2_div6",
3612 .ops = &clk_fixed_factor_ops,
3613 .parent_hws = (const struct clk_hw *[]) {
3614 &g12a_vclk2_div6_en.hw
3615 },
3616 .num_parents = 1,
3617 .flags = CLK_SET_RATE_PARENT,
3618 },
3619};
3620
3621static struct clk_fixed_factor g12a_vclk2_div12 = {
3622 .mult = 1,
3623 .div = 12,
3624 .hw.init = &(struct clk_init_data){
3625 .name = "vclk2_div12",
3626 .ops = &clk_fixed_factor_ops,
3627 .parent_hws = (const struct clk_hw *[]) {
3628 &g12a_vclk2_div12_en.hw
3629 },
3630 .num_parents = 1,
3631 .flags = CLK_SET_RATE_PARENT,
3632 },
3633};
3634
3635static u32 g12a_cts_parents_val_table[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
3636static const struct clk_hw *g12a_cts_parents[] = {
3637 &g12a_vclk_div1.hw,
3638 &g12a_vclk_div2.hw,
3639 &g12a_vclk_div4.hw,
3640 &g12a_vclk_div6.hw,
3641 &g12a_vclk_div12.hw,
3642 &g12a_vclk2_div1.hw,
3643 &g12a_vclk2_div2.hw,
3644 &g12a_vclk2_div4.hw,
3645 &g12a_vclk2_div6.hw,
3646 &g12a_vclk2_div12.hw,
3647};
3648
3649static struct clk_regmap g12a_cts_enci_sel = {
3650 .data = &(struct clk_regmap_mux_data){
3651 .offset = HHI_VID_CLK_DIV,
3652 .mask = 0xf,
3653 .shift = 28,
3654 .table = g12a_cts_parents_val_table,
3655 },
3656 .hw.init = &(struct clk_init_data){
3657 .name = "cts_enci_sel",
3658 .ops = &clk_regmap_mux_ops,
3659 .parent_hws = g12a_cts_parents,
3660 .num_parents = ARRAY_SIZE(g12a_cts_parents),
3661 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
3662 },
3663};
3664
3665static struct clk_regmap g12a_cts_encp_sel = {
3666 .data = &(struct clk_regmap_mux_data){
3667 .offset = HHI_VID_CLK_DIV,
3668 .mask = 0xf,
3669 .shift = 20,
3670 .table = g12a_cts_parents_val_table,
3671 },
3672 .hw.init = &(struct clk_init_data){
3673 .name = "cts_encp_sel",
3674 .ops = &clk_regmap_mux_ops,
3675 .parent_hws = g12a_cts_parents,
3676 .num_parents = ARRAY_SIZE(g12a_cts_parents),
3677 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
3678 },
3679};
3680
3681static struct clk_regmap g12a_cts_encl_sel = {
3682 .data = &(struct clk_regmap_mux_data){
3683 .offset = HHI_VIID_CLK_DIV,
3684 .mask = 0xf,
3685 .shift = 12,
3686 .table = g12a_cts_parents_val_table,
3687 },
3688 .hw.init = &(struct clk_init_data){
3689 .name = "cts_encl_sel",
3690 .ops = &clk_regmap_mux_ops,
3691 .parent_hws = g12a_cts_parents,
3692 .num_parents = ARRAY_SIZE(g12a_cts_parents),
3693 .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
3694 },
3695};
3696
3697static struct clk_regmap g12a_cts_vdac_sel = {
3698 .data = &(struct clk_regmap_mux_data){
3699 .offset = HHI_VIID_CLK_DIV,
3700 .mask = 0xf,
3701 .shift = 28,
3702 .table = g12a_cts_parents_val_table,
3703 },
3704 .hw.init = &(struct clk_init_data){
3705 .name = "cts_vdac_sel",
3706 .ops = &clk_regmap_mux_ops,
3707 .parent_hws = g12a_cts_parents,
3708 .num_parents = ARRAY_SIZE(g12a_cts_parents),
3709 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
3710 },
3711};
3712
3713/* TOFIX: add support for cts_tcon */
3714static u32 g12a_hdmi_tx_parents_val_table[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
3715static const struct clk_hw *g12a_hdmi_tx_parents[] = {
3716 &g12a_vclk_div1.hw,
3717 &g12a_vclk_div2.hw,
3718 &g12a_vclk_div4.hw,
3719 &g12a_vclk_div6.hw,
3720 &g12a_vclk_div12.hw,
3721 &g12a_vclk2_div1.hw,
3722 &g12a_vclk2_div2.hw,
3723 &g12a_vclk2_div4.hw,
3724 &g12a_vclk2_div6.hw,
3725 &g12a_vclk2_div12.hw,
3726};
3727
3728static struct clk_regmap g12a_hdmi_tx_sel = {
3729 .data = &(struct clk_regmap_mux_data){
3730 .offset = HHI_HDMI_CLK_CNTL,
3731 .mask = 0xf,
3732 .shift = 16,
3733 .table = g12a_hdmi_tx_parents_val_table,
3734 },
3735 .hw.init = &(struct clk_init_data){
3736 .name = "hdmi_tx_sel",
3737 .ops = &clk_regmap_mux_ops,
3738 .parent_hws = g12a_hdmi_tx_parents,
3739 .num_parents = ARRAY_SIZE(g12a_hdmi_tx_parents),
3740 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
3741 },
3742};
3743
3744static struct clk_regmap g12a_cts_enci = {
3745 .data = &(struct clk_regmap_gate_data){
3746 .offset = HHI_VID_CLK_CNTL2,
3747 .bit_idx = 0,
3748 },
3749 .hw.init = &(struct clk_init_data) {
3750 .name = "cts_enci",
3751 .ops = &clk_regmap_gate_ops,
3752 .parent_hws = (const struct clk_hw *[]) {
3753 &g12a_cts_enci_sel.hw
3754 },
3755 .num_parents = 1,
3756 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3757 },
3758};
3759
3760static struct clk_regmap g12a_cts_encp = {
3761 .data = &(struct clk_regmap_gate_data){
3762 .offset = HHI_VID_CLK_CNTL2,
3763 .bit_idx = 2,
3764 },
3765 .hw.init = &(struct clk_init_data) {
3766 .name = "cts_encp",
3767 .ops = &clk_regmap_gate_ops,
3768 .parent_hws = (const struct clk_hw *[]) {
3769 &g12a_cts_encp_sel.hw
3770 },
3771 .num_parents = 1,
3772 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3773 },
3774};
3775
3776static struct clk_regmap g12a_cts_encl = {
3777 .data = &(struct clk_regmap_gate_data){
3778 .offset = HHI_VID_CLK_CNTL2,
3779 .bit_idx = 3,
3780 },
3781 .hw.init = &(struct clk_init_data) {
3782 .name = "cts_encl",
3783 .ops = &clk_regmap_gate_ops,
3784 .parent_hws = (const struct clk_hw *[]) {
3785 &g12a_cts_encl_sel.hw
3786 },
3787 .num_parents = 1,
3788 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3789 },
3790};
3791
3792static struct clk_regmap g12a_cts_vdac = {
3793 .data = &(struct clk_regmap_gate_data){
3794 .offset = HHI_VID_CLK_CNTL2,
3795 .bit_idx = 4,
3796 },
3797 .hw.init = &(struct clk_init_data) {
3798 .name = "cts_vdac",
3799 .ops = &clk_regmap_gate_ops,
3800 .parent_hws = (const struct clk_hw *[]) {
3801 &g12a_cts_vdac_sel.hw
3802 },
3803 .num_parents = 1,
3804 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3805 },
3806};
3807
3808static struct clk_regmap g12a_hdmi_tx = {
3809 .data = &(struct clk_regmap_gate_data){
3810 .offset = HHI_VID_CLK_CNTL2,
3811 .bit_idx = 5,
3812 },
3813 .hw.init = &(struct clk_init_data) {
3814 .name = "hdmi_tx",
3815 .ops = &clk_regmap_gate_ops,
3816 .parent_hws = (const struct clk_hw *[]) {
3817 &g12a_hdmi_tx_sel.hw
3818 },
3819 .num_parents = 1,
3820 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3821 },
3822};
3823
3824/* MIPI DSI Host Clocks */
3825
3826static const struct clk_hw *g12a_mipi_dsi_pxclk_parents[] = {
3827 &g12a_vid_pll.hw,
3828 &g12a_gp0_pll.hw,
3829 &g12a_hifi_pll.hw,
3830 &g12a_mpll1.hw,
3831 &g12a_fclk_div2.hw,
3832 &g12a_fclk_div2p5.hw,
3833 &g12a_fclk_div3.hw,
3834 &g12a_fclk_div7.hw,
3835};
3836
3837static struct clk_regmap g12a_mipi_dsi_pxclk_sel = {
3838 .data = &(struct clk_regmap_mux_data){
3839 .offset = HHI_MIPIDSI_PHY_CLK_CNTL,
3840 .mask = 0x7,
3841 .shift = 12,
3842 .flags = CLK_MUX_ROUND_CLOSEST,
3843 },
3844 .hw.init = &(struct clk_init_data){
3845 .name = "mipi_dsi_pxclk_sel",
3846 .ops = &clk_regmap_mux_ops,
3847 .parent_hws = g12a_mipi_dsi_pxclk_parents,
3848 .num_parents = ARRAY_SIZE(g12a_mipi_dsi_pxclk_parents),
3849 .flags = CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT,
3850 },
3851};
3852
3853/*
3854 * FIXME: Force as bypass by forcing a single /1 table entry, and doesn't on boot value
3855 * when setting a clock with this node in the clock path, but doesn't guarantee the divider
3856 * is at /1 at boot until a rate is set.
3857 */
3858static const struct clk_div_table g12a_mipi_dsi_pxclk_div_table[] = {
3859 { .val = 0, .div = 1 },
3860 { /* sentinel */ },
3861};
3862
3863static struct clk_regmap g12a_mipi_dsi_pxclk_div = {
3864 .data = &(struct clk_regmap_div_data){
3865 .offset = HHI_MIPIDSI_PHY_CLK_CNTL,
3866 .shift = 0,
3867 .width = 7,
3868 .table = g12a_mipi_dsi_pxclk_div_table,
3869 },
3870 .hw.init = &(struct clk_init_data){
3871 .name = "mipi_dsi_pxclk_div",
3872 .ops = &clk_regmap_divider_ops,
3873 .parent_hws = (const struct clk_hw *[]) {
3874 &g12a_mipi_dsi_pxclk_sel.hw
3875 },
3876 .num_parents = 1,
3877 .flags = CLK_SET_RATE_PARENT,
3878 },
3879};
3880
3881static struct clk_regmap g12a_mipi_dsi_pxclk = {
3882 .data = &(struct clk_regmap_gate_data){
3883 .offset = HHI_MIPIDSI_PHY_CLK_CNTL,
3884 .bit_idx = 8,
3885 },
3886 .hw.init = &(struct clk_init_data) {
3887 .name = "mipi_dsi_pxclk",
3888 .ops = &clk_regmap_gate_ops,
3889 .parent_hws = (const struct clk_hw *[]) {
3890 &g12a_mipi_dsi_pxclk_div.hw
3891 },
3892 .num_parents = 1,
3893 .flags = CLK_SET_RATE_PARENT,
3894 },
3895};
3896
3897/* MIPI ISP Clocks */
3898
3899static const struct clk_parent_data g12b_mipi_isp_parents[] = {
3900 { .fw_name = "xtal", },
3901 { .hw = &g12a_gp0_pll.hw },
3902 { .hw = &g12a_hifi_pll.hw },
3903 { .hw = &g12a_fclk_div2p5.hw },
3904 { .hw = &g12a_fclk_div3.hw },
3905 { .hw = &g12a_fclk_div4.hw },
3906 { .hw = &g12a_fclk_div5.hw },
3907 { .hw = &g12a_fclk_div7.hw },
3908};
3909
3910static struct clk_regmap g12b_mipi_isp_sel = {
3911 .data = &(struct clk_regmap_mux_data){
3912 .offset = HHI_ISP_CLK_CNTL,
3913 .mask = 7,
3914 .shift = 9,
3915 },
3916 .hw.init = &(struct clk_init_data){
3917 .name = "mipi_isp_sel",
3918 .ops = &clk_regmap_mux_ops,
3919 .parent_data = g12b_mipi_isp_parents,
3920 .num_parents = ARRAY_SIZE(g12b_mipi_isp_parents),
3921 },
3922};
3923
3924static struct clk_regmap g12b_mipi_isp_div = {
3925 .data = &(struct clk_regmap_div_data){
3926 .offset = HHI_ISP_CLK_CNTL,
3927 .shift = 0,
3928 .width = 7,
3929 },
3930 .hw.init = &(struct clk_init_data){
3931 .name = "mipi_isp_div",
3932 .ops = &clk_regmap_divider_ops,
3933 .parent_hws = (const struct clk_hw *[]) {
3934 &g12b_mipi_isp_sel.hw
3935 },
3936 .num_parents = 1,
3937 .flags = CLK_SET_RATE_PARENT,
3938 },
3939};
3940
3941static struct clk_regmap g12b_mipi_isp = {
3942 .data = &(struct clk_regmap_gate_data){
3943 .offset = HHI_ISP_CLK_CNTL,
3944 .bit_idx = 8,
3945 },
3946 .hw.init = &(struct clk_init_data) {
3947 .name = "mipi_isp",
3948 .ops = &clk_regmap_gate_ops,
3949 .parent_hws = (const struct clk_hw *[]) {
3950 &g12b_mipi_isp_div.hw
3951 },
3952 .num_parents = 1,
3953 .flags = CLK_SET_RATE_PARENT,
3954 },
3955};
3956
3957/* HDMI Clocks */
3958
3959static const struct clk_parent_data g12a_hdmi_parents[] = {
3960 { .fw_name = "xtal", },
3961 { .hw = &g12a_fclk_div4.hw },
3962 { .hw = &g12a_fclk_div3.hw },
3963 { .hw = &g12a_fclk_div5.hw },
3964};
3965
3966static struct clk_regmap g12a_hdmi_sel = {
3967 .data = &(struct clk_regmap_mux_data){
3968 .offset = HHI_HDMI_CLK_CNTL,
3969 .mask = 0x3,
3970 .shift = 9,
3971 .flags = CLK_MUX_ROUND_CLOSEST,
3972 },
3973 .hw.init = &(struct clk_init_data){
3974 .name = "hdmi_sel",
3975 .ops = &clk_regmap_mux_ops,
3976 .parent_data = g12a_hdmi_parents,
3977 .num_parents = ARRAY_SIZE(g12a_hdmi_parents),
3978 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
3979 },
3980};
3981
3982static struct clk_regmap g12a_hdmi_div = {
3983 .data = &(struct clk_regmap_div_data){
3984 .offset = HHI_HDMI_CLK_CNTL,
3985 .shift = 0,
3986 .width = 7,
3987 },
3988 .hw.init = &(struct clk_init_data){
3989 .name = "hdmi_div",
3990 .ops = &clk_regmap_divider_ops,
3991 .parent_hws = (const struct clk_hw *[]) { &g12a_hdmi_sel.hw },
3992 .num_parents = 1,
3993 .flags = CLK_GET_RATE_NOCACHE,
3994 },
3995};
3996
3997static struct clk_regmap g12a_hdmi = {
3998 .data = &(struct clk_regmap_gate_data){
3999 .offset = HHI_HDMI_CLK_CNTL,
4000 .bit_idx = 8,
4001 },
4002 .hw.init = &(struct clk_init_data) {
4003 .name = "hdmi",
4004 .ops = &clk_regmap_gate_ops,
4005 .parent_hws = (const struct clk_hw *[]) { &g12a_hdmi_div.hw },
4006 .num_parents = 1,
4007 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
4008 },
4009};
4010
4011/*
4012 * The MALI IP is clocked by two identical clocks (mali_0 and mali_1)
4013 * muxed by a glitch-free switch. The CCF can manage this glitch-free
4014 * mux because it does top-to-bottom updates the each clock tree and
4015 * switches to the "inactive" one when CLK_SET_RATE_GATE is set.
4016 */
4017static const struct clk_parent_data g12a_mali_parents[] = {
4018 { .fw_name = "xtal", },
4019 { .hw = &g12a_gp0_pll.hw },
4020 { .hw = &g12a_hifi_pll.hw },
4021 { .hw = &g12a_fclk_div2p5.hw },
4022 { .hw = &g12a_fclk_div3.hw },
4023 { .hw = &g12a_fclk_div4.hw },
4024 { .hw = &g12a_fclk_div5.hw },
4025 { .hw = &g12a_fclk_div7.hw },
4026};
4027
4028static struct clk_regmap g12a_mali_0_sel = {
4029 .data = &(struct clk_regmap_mux_data){
4030 .offset = HHI_MALI_CLK_CNTL,
4031 .mask = 0x7,
4032 .shift = 9,
4033 },
4034 .hw.init = &(struct clk_init_data){
4035 .name = "mali_0_sel",
4036 .ops = &clk_regmap_mux_ops,
4037 .parent_data = g12a_mali_parents,
4038 .num_parents = ARRAY_SIZE(g12a_mali_parents),
4039 /*
4040 * Don't request the parent to change the rate because
4041 * all GPU frequencies can be derived from the fclk_*
4042 * clocks and one special GP0_PLL setting. This is
4043 * important because we need the MPLL clocks for audio.
4044 */
4045 .flags = 0,
4046 },
4047};
4048
4049static struct clk_regmap g12a_mali_0_div = {
4050 .data = &(struct clk_regmap_div_data){
4051 .offset = HHI_MALI_CLK_CNTL,
4052 .shift = 0,
4053 .width = 7,
4054 },
4055 .hw.init = &(struct clk_init_data){
4056 .name = "mali_0_div",
4057 .ops = &clk_regmap_divider_ops,
4058 .parent_hws = (const struct clk_hw *[]) {
4059 &g12a_mali_0_sel.hw
4060 },
4061 .num_parents = 1,
4062 .flags = CLK_SET_RATE_PARENT,
4063 },
4064};
4065
4066static struct clk_regmap g12a_mali_0 = {
4067 .data = &(struct clk_regmap_gate_data){
4068 .offset = HHI_MALI_CLK_CNTL,
4069 .bit_idx = 8,
4070 },
4071 .hw.init = &(struct clk_init_data){
4072 .name = "mali_0",
4073 .ops = &clk_regmap_gate_ops,
4074 .parent_hws = (const struct clk_hw *[]) {
4075 &g12a_mali_0_div.hw
4076 },
4077 .num_parents = 1,
4078 .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
4079 },
4080};
4081
4082static struct clk_regmap g12a_mali_1_sel = {
4083 .data = &(struct clk_regmap_mux_data){
4084 .offset = HHI_MALI_CLK_CNTL,
4085 .mask = 0x7,
4086 .shift = 25,
4087 },
4088 .hw.init = &(struct clk_init_data){
4089 .name = "mali_1_sel",
4090 .ops = &clk_regmap_mux_ops,
4091 .parent_data = g12a_mali_parents,
4092 .num_parents = ARRAY_SIZE(g12a_mali_parents),
4093 /*
4094 * Don't request the parent to change the rate because
4095 * all GPU frequencies can be derived from the fclk_*
4096 * clocks and one special GP0_PLL setting. This is
4097 * important because we need the MPLL clocks for audio.
4098 */
4099 .flags = 0,
4100 },
4101};
4102
4103static struct clk_regmap g12a_mali_1_div = {
4104 .data = &(struct clk_regmap_div_data){
4105 .offset = HHI_MALI_CLK_CNTL,
4106 .shift = 16,
4107 .width = 7,
4108 },
4109 .hw.init = &(struct clk_init_data){
4110 .name = "mali_1_div",
4111 .ops = &clk_regmap_divider_ops,
4112 .parent_hws = (const struct clk_hw *[]) {
4113 &g12a_mali_1_sel.hw
4114 },
4115 .num_parents = 1,
4116 .flags = CLK_SET_RATE_PARENT,
4117 },
4118};
4119
4120static struct clk_regmap g12a_mali_1 = {
4121 .data = &(struct clk_regmap_gate_data){
4122 .offset = HHI_MALI_CLK_CNTL,
4123 .bit_idx = 24,
4124 },
4125 .hw.init = &(struct clk_init_data){
4126 .name = "mali_1",
4127 .ops = &clk_regmap_gate_ops,
4128 .parent_hws = (const struct clk_hw *[]) {
4129 &g12a_mali_1_div.hw
4130 },
4131 .num_parents = 1,
4132 .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
4133 },
4134};
4135
4136static struct clk_regmap g12a_mali = {
4137 .data = &(struct clk_regmap_mux_data){
4138 .offset = HHI_MALI_CLK_CNTL,
4139 .mask = 1,
4140 .shift = 31,
4141 },
4142 .hw.init = &(struct clk_init_data){
4143 .name = "mali",
4144 .ops = &clk_regmap_mux_ops,
4145 .parent_hws = (const struct clk_hw *[]) {
4146 &g12a_mali_0.hw,
4147 &g12a_mali_1.hw,
4148 },
4149 .num_parents = 2,
4150 .flags = CLK_SET_RATE_PARENT,
4151 },
4152};
4153
4154static struct clk_regmap g12a_ts_div = {
4155 .data = &(struct clk_regmap_div_data){
4156 .offset = HHI_TS_CLK_CNTL,
4157 .shift = 0,
4158 .width = 8,
4159 },
4160 .hw.init = &(struct clk_init_data){
4161 .name = "ts_div",
4162 .ops = &clk_regmap_divider_ro_ops,
4163 .parent_data = &(const struct clk_parent_data) {
4164 .fw_name = "xtal",
4165 },
4166 .num_parents = 1,
4167 },
4168};
4169
4170static struct clk_regmap g12a_ts = {
4171 .data = &(struct clk_regmap_gate_data){
4172 .offset = HHI_TS_CLK_CNTL,
4173 .bit_idx = 8,
4174 },
4175 .hw.init = &(struct clk_init_data){
4176 .name = "ts",
4177 .ops = &clk_regmap_gate_ops,
4178 .parent_hws = (const struct clk_hw *[]) {
4179 &g12a_ts_div.hw
4180 },
4181 .num_parents = 1,
4182 },
4183};
4184
4185/* SPICC SCLK source clock */
4186
4187static const struct clk_parent_data g12a_spicc_sclk_parents[] = {
4188 { .fw_name = "xtal", },
4189 { .hw = &g12a_clk81.hw },
4190 { .hw = &g12a_fclk_div4.hw },
4191 { .hw = &g12a_fclk_div3.hw },
4192 { .hw = &g12a_fclk_div2.hw },
4193 { .hw = &g12a_fclk_div5.hw },
4194 { .hw = &g12a_fclk_div7.hw },
4195};
4196
4197static struct clk_regmap g12a_spicc0_sclk_sel = {
4198 .data = &(struct clk_regmap_mux_data){
4199 .offset = HHI_SPICC_CLK_CNTL,
4200 .mask = 7,
4201 .shift = 7,
4202 },
4203 .hw.init = &(struct clk_init_data){
4204 .name = "spicc0_sclk_sel",
4205 .ops = &clk_regmap_mux_ops,
4206 .parent_data = g12a_spicc_sclk_parents,
4207 .num_parents = ARRAY_SIZE(g12a_spicc_sclk_parents),
4208 },
4209};
4210
4211static struct clk_regmap g12a_spicc0_sclk_div = {
4212 .data = &(struct clk_regmap_div_data){
4213 .offset = HHI_SPICC_CLK_CNTL,
4214 .shift = 0,
4215 .width = 6,
4216 },
4217 .hw.init = &(struct clk_init_data){
4218 .name = "spicc0_sclk_div",
4219 .ops = &clk_regmap_divider_ops,
4220 .parent_hws = (const struct clk_hw *[]) {
4221 &g12a_spicc0_sclk_sel.hw
4222 },
4223 .num_parents = 1,
4224 .flags = CLK_SET_RATE_PARENT,
4225 },
4226};
4227
4228static struct clk_regmap g12a_spicc0_sclk = {
4229 .data = &(struct clk_regmap_gate_data){
4230 .offset = HHI_SPICC_CLK_CNTL,
4231 .bit_idx = 6,
4232 },
4233 .hw.init = &(struct clk_init_data){
4234 .name = "spicc0_sclk",
4235 .ops = &clk_regmap_gate_ops,
4236 .parent_hws = (const struct clk_hw *[]) {
4237 &g12a_spicc0_sclk_div.hw
4238 },
4239 .num_parents = 1,
4240 .flags = CLK_SET_RATE_PARENT,
4241 },
4242};
4243
4244static struct clk_regmap g12a_spicc1_sclk_sel = {
4245 .data = &(struct clk_regmap_mux_data){
4246 .offset = HHI_SPICC_CLK_CNTL,
4247 .mask = 7,
4248 .shift = 23,
4249 },
4250 .hw.init = &(struct clk_init_data){
4251 .name = "spicc1_sclk_sel",
4252 .ops = &clk_regmap_mux_ops,
4253 .parent_data = g12a_spicc_sclk_parents,
4254 .num_parents = ARRAY_SIZE(g12a_spicc_sclk_parents),
4255 },
4256};
4257
4258static struct clk_regmap g12a_spicc1_sclk_div = {
4259 .data = &(struct clk_regmap_div_data){
4260 .offset = HHI_SPICC_CLK_CNTL,
4261 .shift = 16,
4262 .width = 6,
4263 },
4264 .hw.init = &(struct clk_init_data){
4265 .name = "spicc1_sclk_div",
4266 .ops = &clk_regmap_divider_ops,
4267 .parent_hws = (const struct clk_hw *[]) {
4268 &g12a_spicc1_sclk_sel.hw
4269 },
4270 .num_parents = 1,
4271 .flags = CLK_SET_RATE_PARENT,
4272 },
4273};
4274
4275static struct clk_regmap g12a_spicc1_sclk = {
4276 .data = &(struct clk_regmap_gate_data){
4277 .offset = HHI_SPICC_CLK_CNTL,
4278 .bit_idx = 22,
4279 },
4280 .hw.init = &(struct clk_init_data){
4281 .name = "spicc1_sclk",
4282 .ops = &clk_regmap_gate_ops,
4283 .parent_hws = (const struct clk_hw *[]) {
4284 &g12a_spicc1_sclk_div.hw
4285 },
4286 .num_parents = 1,
4287 .flags = CLK_SET_RATE_PARENT,
4288 },
4289};
4290
4291/* Neural Network Accelerator source clock */
4292
4293static const struct clk_parent_data sm1_nna_clk_parents[] = {
4294 { .fw_name = "xtal", },
4295 { .hw = &g12a_gp0_pll.hw, },
4296 { .hw = &g12a_hifi_pll.hw, },
4297 { .hw = &g12a_fclk_div2p5.hw, },
4298 { .hw = &g12a_fclk_div3.hw, },
4299 { .hw = &g12a_fclk_div4.hw, },
4300 { .hw = &g12a_fclk_div5.hw, },
4301 { .hw = &g12a_fclk_div7.hw },
4302};
4303
4304static struct clk_regmap sm1_nna_axi_clk_sel = {
4305 .data = &(struct clk_regmap_mux_data){
4306 .offset = HHI_NNA_CLK_CNTL,
4307 .mask = 7,
4308 .shift = 9,
4309 },
4310 .hw.init = &(struct clk_init_data){
4311 .name = "nna_axi_clk_sel",
4312 .ops = &clk_regmap_mux_ops,
4313 .parent_data = sm1_nna_clk_parents,
4314 .num_parents = ARRAY_SIZE(sm1_nna_clk_parents),
4315 },
4316};
4317
4318static struct clk_regmap sm1_nna_axi_clk_div = {
4319 .data = &(struct clk_regmap_div_data){
4320 .offset = HHI_NNA_CLK_CNTL,
4321 .shift = 0,
4322 .width = 7,
4323 },
4324 .hw.init = &(struct clk_init_data){
4325 .name = "nna_axi_clk_div",
4326 .ops = &clk_regmap_divider_ops,
4327 .parent_hws = (const struct clk_hw *[]) {
4328 &sm1_nna_axi_clk_sel.hw
4329 },
4330 .num_parents = 1,
4331 .flags = CLK_SET_RATE_PARENT,
4332 },
4333};
4334
4335static struct clk_regmap sm1_nna_axi_clk = {
4336 .data = &(struct clk_regmap_gate_data){
4337 .offset = HHI_NNA_CLK_CNTL,
4338 .bit_idx = 8,
4339 },
4340 .hw.init = &(struct clk_init_data){
4341 .name = "nna_axi_clk",
4342 .ops = &clk_regmap_gate_ops,
4343 .parent_hws = (const struct clk_hw *[]) {
4344 &sm1_nna_axi_clk_div.hw
4345 },
4346 .num_parents = 1,
4347 .flags = CLK_SET_RATE_PARENT,
4348 },
4349};
4350
4351static struct clk_regmap sm1_nna_core_clk_sel = {
4352 .data = &(struct clk_regmap_mux_data){
4353 .offset = HHI_NNA_CLK_CNTL,
4354 .mask = 7,
4355 .shift = 25,
4356 },
4357 .hw.init = &(struct clk_init_data){
4358 .name = "nna_core_clk_sel",
4359 .ops = &clk_regmap_mux_ops,
4360 .parent_data = sm1_nna_clk_parents,
4361 .num_parents = ARRAY_SIZE(sm1_nna_clk_parents),
4362 },
4363};
4364
4365static struct clk_regmap sm1_nna_core_clk_div = {
4366 .data = &(struct clk_regmap_div_data){
4367 .offset = HHI_NNA_CLK_CNTL,
4368 .shift = 16,
4369 .width = 7,
4370 },
4371 .hw.init = &(struct clk_init_data){
4372 .name = "nna_core_clk_div",
4373 .ops = &clk_regmap_divider_ops,
4374 .parent_hws = (const struct clk_hw *[]) {
4375 &sm1_nna_core_clk_sel.hw
4376 },
4377 .num_parents = 1,
4378 .flags = CLK_SET_RATE_PARENT,
4379 },
4380};
4381
4382static struct clk_regmap sm1_nna_core_clk = {
4383 .data = &(struct clk_regmap_gate_data){
4384 .offset = HHI_NNA_CLK_CNTL,
4385 .bit_idx = 24,
4386 },
4387 .hw.init = &(struct clk_init_data){
4388 .name = "nna_core_clk",
4389 .ops = &clk_regmap_gate_ops,
4390 .parent_hws = (const struct clk_hw *[]) {
4391 &sm1_nna_core_clk_div.hw
4392 },
4393 .num_parents = 1,
4394 .flags = CLK_SET_RATE_PARENT,
4395 },
4396};
4397
4398static const struct clk_parent_data g12a_pclk_parents = { .hw = &g12a_clk81.hw };
4399
4400#define G12A_PCLK(_name, _reg, _bit, _flags) \
4401 MESON_PCLK(_name, _reg, _bit, &g12a_pclk_parents, _flags)
4402
4403#define G12A_PCLK_RO(_name, _reg, _bit, _flags) \
4404 MESON_PCLK_RO(_name, _reg, _bit, &g12a_pclk_parents, _flags)
4405
4406/*
4407 * Everything Else (EE) domain gates
4408 *
4409 * NOTE: The gates below are marked with CLK_IGNORE_UNUSED for historic reasons
4410 * Users are encouraged to test without it and submit changes to:
4411 * - remove the flag if not necessary
4412 * - replace the flag with something more adequate, such as CLK_IS_CRITICAL,
4413 * if appropriate.
4414 * - add a comment explaining why the use of CLK_IGNORE_UNUSED is desirable
4415 * for a particular clock.
4416 */
4417static G12A_PCLK(g12a_ddr, HHI_GCLK_MPEG0, 0, CLK_IGNORE_UNUSED);
4418static G12A_PCLK(g12a_dos, HHI_GCLK_MPEG0, 1, CLK_IGNORE_UNUSED);
4419static G12A_PCLK(g12a_audio_locker, HHI_GCLK_MPEG0, 2, CLK_IGNORE_UNUSED);
4420static G12A_PCLK(g12a_mipi_dsi_host, HHI_GCLK_MPEG0, 3, CLK_IGNORE_UNUSED);
4421static G12A_PCLK(g12a_eth_phy, HHI_GCLK_MPEG0, 4, CLK_IGNORE_UNUSED);
4422static G12A_PCLK(g12a_isa, HHI_GCLK_MPEG0, 5, CLK_IGNORE_UNUSED);
4423static G12A_PCLK(g12a_pl301, HHI_GCLK_MPEG0, 6, CLK_IGNORE_UNUSED);
4424static G12A_PCLK(g12a_periphs, HHI_GCLK_MPEG0, 7, CLK_IGNORE_UNUSED);
4425static G12A_PCLK(g12a_spicc_0, HHI_GCLK_MPEG0, 8, CLK_IGNORE_UNUSED);
4426static G12A_PCLK(g12a_i2c, HHI_GCLK_MPEG0, 9, CLK_IGNORE_UNUSED);
4427static G12A_PCLK(g12a_sana, HHI_GCLK_MPEG0, 10, CLK_IGNORE_UNUSED);
4428static G12A_PCLK(g12a_sd, HHI_GCLK_MPEG0, 11, CLK_IGNORE_UNUSED);
4429static G12A_PCLK(g12a_rng0, HHI_GCLK_MPEG0, 12, CLK_IGNORE_UNUSED);
4430static G12A_PCLK(g12a_uart0, HHI_GCLK_MPEG0, 13, CLK_IGNORE_UNUSED);
4431static G12A_PCLK(g12a_spicc_1, HHI_GCLK_MPEG0, 14, CLK_IGNORE_UNUSED);
4432static G12A_PCLK(g12a_hiu_reg, HHI_GCLK_MPEG0, 19, CLK_IGNORE_UNUSED);
4433static G12A_PCLK(g12a_mipi_dsi_phy, HHI_GCLK_MPEG0, 20, CLK_IGNORE_UNUSED);
4434static G12A_PCLK(g12a_assist_misc, HHI_GCLK_MPEG0, 23, CLK_IGNORE_UNUSED);
4435static G12A_PCLK(g12a_emmc_a, HHI_GCLK_MPEG0, 24, CLK_IGNORE_UNUSED);
4436static G12A_PCLK(g12a_emmc_b, HHI_GCLK_MPEG0, 25, CLK_IGNORE_UNUSED);
4437static G12A_PCLK(g12a_emmc_c, HHI_GCLK_MPEG0, 26, CLK_IGNORE_UNUSED);
4438static G12A_PCLK(g12a_audio_codec, HHI_GCLK_MPEG0, 28, CLK_IGNORE_UNUSED);
4439
4440static G12A_PCLK(g12a_audio, HHI_GCLK_MPEG1, 0, CLK_IGNORE_UNUSED);
4441static G12A_PCLK(g12a_eth_core, HHI_GCLK_MPEG1, 3, CLK_IGNORE_UNUSED);
4442static G12A_PCLK(g12a_demux, HHI_GCLK_MPEG1, 4, CLK_IGNORE_UNUSED);
4443static G12A_PCLK(g12a_audio_ififo, HHI_GCLK_MPEG1, 11, CLK_IGNORE_UNUSED);
4444static G12A_PCLK(g12a_adc, HHI_GCLK_MPEG1, 13, CLK_IGNORE_UNUSED);
4445static G12A_PCLK(g12a_uart1, HHI_GCLK_MPEG1, 16, CLK_IGNORE_UNUSED);
4446static G12A_PCLK(g12a_g2d, HHI_GCLK_MPEG1, 20, CLK_IGNORE_UNUSED);
4447static G12A_PCLK(g12a_reset, HHI_GCLK_MPEG1, 23, CLK_IGNORE_UNUSED);
4448static G12A_PCLK(g12a_pcie_comb, HHI_GCLK_MPEG1, 24, CLK_IGNORE_UNUSED);
4449static G12A_PCLK(g12a_parser, HHI_GCLK_MPEG1, 25, CLK_IGNORE_UNUSED);
4450static G12A_PCLK(g12a_usb_general, HHI_GCLK_MPEG1, 26, CLK_IGNORE_UNUSED);
4451static G12A_PCLK(g12a_pcie_phy, HHI_GCLK_MPEG1, 27, CLK_IGNORE_UNUSED);
4452static G12A_PCLK(g12a_ahb_arb0, HHI_GCLK_MPEG1, 29, CLK_IGNORE_UNUSED);
4453
4454static G12A_PCLK(g12a_ahb_data_bus, HHI_GCLK_MPEG2, 1, CLK_IGNORE_UNUSED);
4455static G12A_PCLK(g12a_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2, CLK_IGNORE_UNUSED);
4456static G12A_PCLK(g12a_htx_hdcp22, HHI_GCLK_MPEG2, 3, CLK_IGNORE_UNUSED);
4457static G12A_PCLK(g12a_htx_pclk, HHI_GCLK_MPEG2, 4, CLK_IGNORE_UNUSED);
4458static G12A_PCLK(g12a_bt656, HHI_GCLK_MPEG2, 6, CLK_IGNORE_UNUSED);
4459static G12A_PCLK(g12a_usb1_to_ddr, HHI_GCLK_MPEG2, 8, CLK_IGNORE_UNUSED);
4460static G12A_PCLK(g12b_mipi_isp_gate, HHI_GCLK_MPEG2, 17, CLK_IGNORE_UNUSED);
4461static G12A_PCLK(g12a_mmc_pclk, HHI_GCLK_MPEG2, 11, CLK_IGNORE_UNUSED);
4462static G12A_PCLK(g12a_uart2, HHI_GCLK_MPEG2, 15, CLK_IGNORE_UNUSED);
4463static G12A_PCLK(g12a_vpu_intr, HHI_GCLK_MPEG2, 25, CLK_IGNORE_UNUSED);
4464static G12A_PCLK(g12b_csi_phy1, HHI_GCLK_MPEG2, 28, CLK_IGNORE_UNUSED);
4465static G12A_PCLK(g12b_csi_phy0, HHI_GCLK_MPEG2, 29, CLK_IGNORE_UNUSED);
4466static G12A_PCLK(g12a_gic, HHI_GCLK_MPEG2, 30, CLK_IGNORE_UNUSED);
4467
4468static G12A_PCLK(g12a_vclk2_venci0, HHI_GCLK_OTHER, 1, CLK_IGNORE_UNUSED);
4469static G12A_PCLK(g12a_vclk2_venci1, HHI_GCLK_OTHER, 2, CLK_IGNORE_UNUSED);
4470static G12A_PCLK(g12a_vclk2_vencp0, HHI_GCLK_OTHER, 3, CLK_IGNORE_UNUSED);
4471static G12A_PCLK(g12a_vclk2_vencp1, HHI_GCLK_OTHER, 4, CLK_IGNORE_UNUSED);
4472static G12A_PCLK(g12a_vclk2_venct0, HHI_GCLK_OTHER, 5, CLK_IGNORE_UNUSED);
4473static G12A_PCLK(g12a_vclk2_venct1, HHI_GCLK_OTHER, 6, CLK_IGNORE_UNUSED);
4474static G12A_PCLK(g12a_vclk2_other, HHI_GCLK_OTHER, 7, CLK_IGNORE_UNUSED);
4475static G12A_PCLK(g12a_vclk2_enci, HHI_GCLK_OTHER, 8, CLK_IGNORE_UNUSED);
4476static G12A_PCLK(g12a_vclk2_encp, HHI_GCLK_OTHER, 9, CLK_IGNORE_UNUSED);
4477static G12A_PCLK(g12a_dac_clk, HHI_GCLK_OTHER, 10, CLK_IGNORE_UNUSED);
4478static G12A_PCLK(g12a_aoclk_gate, HHI_GCLK_OTHER, 14, CLK_IGNORE_UNUSED);
4479static G12A_PCLK(g12a_iec958_gate, HHI_GCLK_OTHER, 16, CLK_IGNORE_UNUSED);
4480static G12A_PCLK(g12a_enc480p, HHI_GCLK_OTHER, 20, CLK_IGNORE_UNUSED);
4481static G12A_PCLK(g12a_rng1, HHI_GCLK_OTHER, 21, CLK_IGNORE_UNUSED);
4482static G12A_PCLK(g12a_vclk2_enct, HHI_GCLK_OTHER, 22, CLK_IGNORE_UNUSED);
4483static G12A_PCLK(g12a_vclk2_encl, HHI_GCLK_OTHER, 23, CLK_IGNORE_UNUSED);
4484static G12A_PCLK(g12a_vclk2_venclmmc, HHI_GCLK_OTHER, 24, CLK_IGNORE_UNUSED);
4485static G12A_PCLK(g12a_vclk2_vencl, HHI_GCLK_OTHER, 25, CLK_IGNORE_UNUSED);
4486static G12A_PCLK(g12a_vclk2_other1, HHI_GCLK_OTHER, 26, CLK_IGNORE_UNUSED);
4487
4488static G12A_PCLK_RO(g12a_dma, HHI_GCLK_OTHER2, 0, 0);
4489static G12A_PCLK_RO(g12a_efuse, HHI_GCLK_OTHER2, 1, 0);
4490static G12A_PCLK_RO(g12a_rom_boot, HHI_GCLK_OTHER2, 2, 0);
4491static G12A_PCLK_RO(g12a_reset_sec, HHI_GCLK_OTHER2, 3, 0);
4492static G12A_PCLK_RO(g12a_sec_ahb_apb3, HHI_GCLK_OTHER2, 4, 0);
4493
4494/* Array of all clocks provided by this provider */
4495static struct clk_hw *g12a_hw_clks[] = {
4496 [CLKID_SYS_PLL] = &g12a_sys_pll.hw,
4497 [CLKID_FIXED_PLL] = &g12a_fixed_pll.hw,
4498 [CLKID_FCLK_DIV2] = &g12a_fclk_div2.hw,
4499 [CLKID_FCLK_DIV3] = &g12a_fclk_div3.hw,
4500 [CLKID_FCLK_DIV4] = &g12a_fclk_div4.hw,
4501 [CLKID_FCLK_DIV5] = &g12a_fclk_div5.hw,
4502 [CLKID_FCLK_DIV7] = &g12a_fclk_div7.hw,
4503 [CLKID_FCLK_DIV2P5] = &g12a_fclk_div2p5.hw,
4504 [CLKID_GP0_PLL] = &g12a_gp0_pll.hw,
4505 [CLKID_MPEG_SEL] = &g12a_clk81_sel.hw,
4506 [CLKID_MPEG_DIV] = &g12a_clk81_div.hw,
4507 [CLKID_CLK81] = &g12a_clk81.hw,
4508 [CLKID_MPLL0] = &g12a_mpll0.hw,
4509 [CLKID_MPLL1] = &g12a_mpll1.hw,
4510 [CLKID_MPLL2] = &g12a_mpll2.hw,
4511 [CLKID_MPLL3] = &g12a_mpll3.hw,
4512 [CLKID_DDR] = &g12a_ddr.hw,
4513 [CLKID_DOS] = &g12a_dos.hw,
4514 [CLKID_AUDIO_LOCKER] = &g12a_audio_locker.hw,
4515 [CLKID_MIPI_DSI_HOST] = &g12a_mipi_dsi_host.hw,
4516 [CLKID_ETH_PHY] = &g12a_eth_phy.hw,
4517 [CLKID_ISA] = &g12a_isa.hw,
4518 [CLKID_PL301] = &g12a_pl301.hw,
4519 [CLKID_PERIPHS] = &g12a_periphs.hw,
4520 [CLKID_SPICC0] = &g12a_spicc_0.hw,
4521 [CLKID_I2C] = &g12a_i2c.hw,
4522 [CLKID_SANA] = &g12a_sana.hw,
4523 [CLKID_SD] = &g12a_sd.hw,
4524 [CLKID_RNG0] = &g12a_rng0.hw,
4525 [CLKID_UART0] = &g12a_uart0.hw,
4526 [CLKID_SPICC1] = &g12a_spicc_1.hw,
4527 [CLKID_HIU_IFACE] = &g12a_hiu_reg.hw,
4528 [CLKID_MIPI_DSI_PHY] = &g12a_mipi_dsi_phy.hw,
4529 [CLKID_ASSIST_MISC] = &g12a_assist_misc.hw,
4530 [CLKID_SD_EMMC_A] = &g12a_emmc_a.hw,
4531 [CLKID_SD_EMMC_B] = &g12a_emmc_b.hw,
4532 [CLKID_SD_EMMC_C] = &g12a_emmc_c.hw,
4533 [CLKID_AUDIO_CODEC] = &g12a_audio_codec.hw,
4534 [CLKID_AUDIO] = &g12a_audio.hw,
4535 [CLKID_ETH] = &g12a_eth_core.hw,
4536 [CLKID_DEMUX] = &g12a_demux.hw,
4537 [CLKID_AUDIO_IFIFO] = &g12a_audio_ififo.hw,
4538 [CLKID_ADC] = &g12a_adc.hw,
4539 [CLKID_UART1] = &g12a_uart1.hw,
4540 [CLKID_G2D] = &g12a_g2d.hw,
4541 [CLKID_RESET] = &g12a_reset.hw,
4542 [CLKID_PCIE_COMB] = &g12a_pcie_comb.hw,
4543 [CLKID_PARSER] = &g12a_parser.hw,
4544 [CLKID_USB] = &g12a_usb_general.hw,
4545 [CLKID_PCIE_PHY] = &g12a_pcie_phy.hw,
4546 [CLKID_AHB_ARB0] = &g12a_ahb_arb0.hw,
4547 [CLKID_AHB_DATA_BUS] = &g12a_ahb_data_bus.hw,
4548 [CLKID_AHB_CTRL_BUS] = &g12a_ahb_ctrl_bus.hw,
4549 [CLKID_HTX_HDCP22] = &g12a_htx_hdcp22.hw,
4550 [CLKID_HTX_PCLK] = &g12a_htx_pclk.hw,
4551 [CLKID_BT656] = &g12a_bt656.hw,
4552 [CLKID_USB1_DDR_BRIDGE] = &g12a_usb1_to_ddr.hw,
4553 [CLKID_MMC_PCLK] = &g12a_mmc_pclk.hw,
4554 [CLKID_UART2] = &g12a_uart2.hw,
4555 [CLKID_VPU_INTR] = &g12a_vpu_intr.hw,
4556 [CLKID_GIC] = &g12a_gic.hw,
4557 [CLKID_SD_EMMC_A_CLK0_SEL] = &g12a_sd_emmc_a_clk0_sel.hw,
4558 [CLKID_SD_EMMC_A_CLK0_DIV] = &g12a_sd_emmc_a_clk0_div.hw,
4559 [CLKID_SD_EMMC_A_CLK0] = &g12a_sd_emmc_a_clk0.hw,
4560 [CLKID_SD_EMMC_B_CLK0_SEL] = &g12a_sd_emmc_b_clk0_sel.hw,
4561 [CLKID_SD_EMMC_B_CLK0_DIV] = &g12a_sd_emmc_b_clk0_div.hw,
4562 [CLKID_SD_EMMC_B_CLK0] = &g12a_sd_emmc_b_clk0.hw,
4563 [CLKID_SD_EMMC_C_CLK0_SEL] = &g12a_sd_emmc_c_clk0_sel.hw,
4564 [CLKID_SD_EMMC_C_CLK0_DIV] = &g12a_sd_emmc_c_clk0_div.hw,
4565 [CLKID_SD_EMMC_C_CLK0] = &g12a_sd_emmc_c_clk0.hw,
4566 [CLKID_MPLL0_DIV] = &g12a_mpll0_div.hw,
4567 [CLKID_MPLL1_DIV] = &g12a_mpll1_div.hw,
4568 [CLKID_MPLL2_DIV] = &g12a_mpll2_div.hw,
4569 [CLKID_MPLL3_DIV] = &g12a_mpll3_div.hw,
4570 [CLKID_FCLK_DIV2_DIV] = &g12a_fclk_div2_div.hw,
4571 [CLKID_FCLK_DIV3_DIV] = &g12a_fclk_div3_div.hw,
4572 [CLKID_FCLK_DIV4_DIV] = &g12a_fclk_div4_div.hw,
4573 [CLKID_FCLK_DIV5_DIV] = &g12a_fclk_div5_div.hw,
4574 [CLKID_FCLK_DIV7_DIV] = &g12a_fclk_div7_div.hw,
4575 [CLKID_FCLK_DIV2P5_DIV] = &g12a_fclk_div2p5_div.hw,
4576 [CLKID_HIFI_PLL] = &g12a_hifi_pll.hw,
4577 [CLKID_VCLK2_VENCI0] = &g12a_vclk2_venci0.hw,
4578 [CLKID_VCLK2_VENCI1] = &g12a_vclk2_venci1.hw,
4579 [CLKID_VCLK2_VENCP0] = &g12a_vclk2_vencp0.hw,
4580 [CLKID_VCLK2_VENCP1] = &g12a_vclk2_vencp1.hw,
4581 [CLKID_VCLK2_VENCT0] = &g12a_vclk2_venct0.hw,
4582 [CLKID_VCLK2_VENCT1] = &g12a_vclk2_venct1.hw,
4583 [CLKID_VCLK2_OTHER] = &g12a_vclk2_other.hw,
4584 [CLKID_VCLK2_ENCI] = &g12a_vclk2_enci.hw,
4585 [CLKID_VCLK2_ENCP] = &g12a_vclk2_encp.hw,
4586 [CLKID_DAC_CLK] = &g12a_dac_clk.hw,
4587 [CLKID_AOCLK] = &g12a_aoclk_gate.hw,
4588 [CLKID_IEC958] = &g12a_iec958_gate.hw,
4589 [CLKID_ENC480P] = &g12a_enc480p.hw,
4590 [CLKID_RNG1] = &g12a_rng1.hw,
4591 [CLKID_VCLK2_ENCT] = &g12a_vclk2_enct.hw,
4592 [CLKID_VCLK2_ENCL] = &g12a_vclk2_encl.hw,
4593 [CLKID_VCLK2_VENCLMMC] = &g12a_vclk2_venclmmc.hw,
4594 [CLKID_VCLK2_VENCL] = &g12a_vclk2_vencl.hw,
4595 [CLKID_VCLK2_OTHER1] = &g12a_vclk2_other1.hw,
4596 [CLKID_FIXED_PLL_DCO] = &g12a_fixed_pll_dco.hw,
4597 [CLKID_SYS_PLL_DCO] = &g12a_sys_pll_dco.hw,
4598 [CLKID_GP0_PLL_DCO] = &g12a_gp0_pll_dco.hw,
4599 [CLKID_HIFI_PLL_DCO] = &g12a_hifi_pll_dco.hw,
4600 [CLKID_DMA] = &g12a_dma.hw,
4601 [CLKID_EFUSE] = &g12a_efuse.hw,
4602 [CLKID_ROM_BOOT] = &g12a_rom_boot.hw,
4603 [CLKID_RESET_SEC] = &g12a_reset_sec.hw,
4604 [CLKID_SEC_AHB_APB3] = &g12a_sec_ahb_apb3.hw,
4605 [CLKID_MPLL_PREDIV] = &g12a_mpll_prediv.hw,
4606 [CLKID_VPU_0_SEL] = &g12a_vpu_0_sel.hw,
4607 [CLKID_VPU_0_DIV] = &g12a_vpu_0_div.hw,
4608 [CLKID_VPU_0] = &g12a_vpu_0.hw,
4609 [CLKID_VPU_1_SEL] = &g12a_vpu_1_sel.hw,
4610 [CLKID_VPU_1_DIV] = &g12a_vpu_1_div.hw,
4611 [CLKID_VPU_1] = &g12a_vpu_1.hw,
4612 [CLKID_VPU] = &g12a_vpu.hw,
4613 [CLKID_VAPB_0_SEL] = &g12a_vapb_0_sel.hw,
4614 [CLKID_VAPB_0_DIV] = &g12a_vapb_0_div.hw,
4615 [CLKID_VAPB_0] = &g12a_vapb_0.hw,
4616 [CLKID_VAPB_1_SEL] = &g12a_vapb_1_sel.hw,
4617 [CLKID_VAPB_1_DIV] = &g12a_vapb_1_div.hw,
4618 [CLKID_VAPB_1] = &g12a_vapb_1.hw,
4619 [CLKID_VAPB_SEL] = &g12a_vapb_sel.hw,
4620 [CLKID_VAPB] = &g12a_vapb.hw,
4621 [CLKID_HDMI_PLL_DCO] = &g12a_hdmi_pll_dco.hw,
4622 [CLKID_HDMI_PLL_OD] = &g12a_hdmi_pll_od.hw,
4623 [CLKID_HDMI_PLL_OD2] = &g12a_hdmi_pll_od2.hw,
4624 [CLKID_HDMI_PLL] = &g12a_hdmi_pll.hw,
4625 [CLKID_VID_PLL] = &g12a_vid_pll_div.hw,
4626 [CLKID_VID_PLL_SEL] = &g12a_vid_pll_sel.hw,
4627 [CLKID_VID_PLL_DIV] = &g12a_vid_pll.hw,
4628 [CLKID_VCLK_SEL] = &g12a_vclk_sel.hw,
4629 [CLKID_VCLK2_SEL] = &g12a_vclk2_sel.hw,
4630 [CLKID_VCLK_INPUT] = &g12a_vclk_input.hw,
4631 [CLKID_VCLK2_INPUT] = &g12a_vclk2_input.hw,
4632 [CLKID_VCLK_DIV] = &g12a_vclk_div.hw,
4633 [CLKID_VCLK2_DIV] = &g12a_vclk2_div.hw,
4634 [CLKID_VCLK] = &g12a_vclk.hw,
4635 [CLKID_VCLK2] = &g12a_vclk2.hw,
4636 [CLKID_VCLK_DIV1] = &g12a_vclk_div1.hw,
4637 [CLKID_VCLK_DIV2_EN] = &g12a_vclk_div2_en.hw,
4638 [CLKID_VCLK_DIV4_EN] = &g12a_vclk_div4_en.hw,
4639 [CLKID_VCLK_DIV6_EN] = &g12a_vclk_div6_en.hw,
4640 [CLKID_VCLK_DIV12_EN] = &g12a_vclk_div12_en.hw,
4641 [CLKID_VCLK2_DIV1] = &g12a_vclk2_div1.hw,
4642 [CLKID_VCLK2_DIV2_EN] = &g12a_vclk2_div2_en.hw,
4643 [CLKID_VCLK2_DIV4_EN] = &g12a_vclk2_div4_en.hw,
4644 [CLKID_VCLK2_DIV6_EN] = &g12a_vclk2_div6_en.hw,
4645 [CLKID_VCLK2_DIV12_EN] = &g12a_vclk2_div12_en.hw,
4646 [CLKID_VCLK_DIV2] = &g12a_vclk_div2.hw,
4647 [CLKID_VCLK_DIV4] = &g12a_vclk_div4.hw,
4648 [CLKID_VCLK_DIV6] = &g12a_vclk_div6.hw,
4649 [CLKID_VCLK_DIV12] = &g12a_vclk_div12.hw,
4650 [CLKID_VCLK2_DIV2] = &g12a_vclk2_div2.hw,
4651 [CLKID_VCLK2_DIV4] = &g12a_vclk2_div4.hw,
4652 [CLKID_VCLK2_DIV6] = &g12a_vclk2_div6.hw,
4653 [CLKID_VCLK2_DIV12] = &g12a_vclk2_div12.hw,
4654 [CLKID_CTS_ENCI_SEL] = &g12a_cts_enci_sel.hw,
4655 [CLKID_CTS_ENCP_SEL] = &g12a_cts_encp_sel.hw,
4656 [CLKID_CTS_ENCL_SEL] = &g12a_cts_encl_sel.hw,
4657 [CLKID_CTS_VDAC_SEL] = &g12a_cts_vdac_sel.hw,
4658 [CLKID_HDMI_TX_SEL] = &g12a_hdmi_tx_sel.hw,
4659 [CLKID_CTS_ENCI] = &g12a_cts_enci.hw,
4660 [CLKID_CTS_ENCP] = &g12a_cts_encp.hw,
4661 [CLKID_CTS_ENCL] = &g12a_cts_encl.hw,
4662 [CLKID_CTS_VDAC] = &g12a_cts_vdac.hw,
4663 [CLKID_HDMI_TX] = &g12a_hdmi_tx.hw,
4664 [CLKID_HDMI_SEL] = &g12a_hdmi_sel.hw,
4665 [CLKID_HDMI_DIV] = &g12a_hdmi_div.hw,
4666 [CLKID_HDMI] = &g12a_hdmi.hw,
4667 [CLKID_MALI_0_SEL] = &g12a_mali_0_sel.hw,
4668 [CLKID_MALI_0_DIV] = &g12a_mali_0_div.hw,
4669 [CLKID_MALI_0] = &g12a_mali_0.hw,
4670 [CLKID_MALI_1_SEL] = &g12a_mali_1_sel.hw,
4671 [CLKID_MALI_1_DIV] = &g12a_mali_1_div.hw,
4672 [CLKID_MALI_1] = &g12a_mali_1.hw,
4673 [CLKID_MALI] = &g12a_mali.hw,
4674 [CLKID_MPLL_50M_DIV] = &g12a_mpll_50m_div.hw,
4675 [CLKID_MPLL_50M] = &g12a_mpll_50m.hw,
4676 [CLKID_SYS_PLL_DIV16_EN] = &g12a_sys_pll_div16_en.hw,
4677 [CLKID_SYS_PLL_DIV16] = &g12a_sys_pll_div16.hw,
4678 [CLKID_CPU_CLK_DYN0_SEL] = &g12a_cpu_clk_dyn0_sel.hw,
4679 [CLKID_CPU_CLK_DYN0_DIV] = &g12a_cpu_clk_dyn0_div.hw,
4680 [CLKID_CPU_CLK_DYN0] = &g12a_cpu_clk_dyn0.hw,
4681 [CLKID_CPU_CLK_DYN1_SEL] = &g12a_cpu_clk_dyn1_sel.hw,
4682 [CLKID_CPU_CLK_DYN1_DIV] = &g12a_cpu_clk_dyn1_div.hw,
4683 [CLKID_CPU_CLK_DYN1] = &g12a_cpu_clk_dyn1.hw,
4684 [CLKID_CPU_CLK_DYN] = &g12a_cpu_clk_dyn.hw,
4685 [CLKID_CPU_CLK] = &g12a_cpu_clk.hw,
4686 [CLKID_CPU_CLK_DIV16_EN] = &g12a_cpu_clk_div16_en.hw,
4687 [CLKID_CPU_CLK_DIV16] = &g12a_cpu_clk_div16.hw,
4688 [CLKID_CPU_CLK_APB_DIV] = &g12a_cpu_clk_apb_div.hw,
4689 [CLKID_CPU_CLK_APB] = &g12a_cpu_clk_apb.hw,
4690 [CLKID_CPU_CLK_ATB_DIV] = &g12a_cpu_clk_atb_div.hw,
4691 [CLKID_CPU_CLK_ATB] = &g12a_cpu_clk_atb.hw,
4692 [CLKID_CPU_CLK_AXI_DIV] = &g12a_cpu_clk_axi_div.hw,
4693 [CLKID_CPU_CLK_AXI] = &g12a_cpu_clk_axi.hw,
4694 [CLKID_CPU_CLK_TRACE_DIV] = &g12a_cpu_clk_trace_div.hw,
4695 [CLKID_CPU_CLK_TRACE] = &g12a_cpu_clk_trace.hw,
4696 [CLKID_PCIE_PLL_DCO] = &g12a_pcie_pll_dco.hw,
4697 [CLKID_PCIE_PLL_DCO_DIV2] = &g12a_pcie_pll_dco_div2.hw,
4698 [CLKID_PCIE_PLL_OD] = &g12a_pcie_pll_od.hw,
4699 [CLKID_PCIE_PLL] = &g12a_pcie_pll.hw,
4700 [CLKID_VDEC_1_SEL] = &g12a_vdec_1_sel.hw,
4701 [CLKID_VDEC_1_DIV] = &g12a_vdec_1_div.hw,
4702 [CLKID_VDEC_1] = &g12a_vdec_1.hw,
4703 [CLKID_VDEC_HEVC_SEL] = &g12a_vdec_hevc_sel.hw,
4704 [CLKID_VDEC_HEVC_DIV] = &g12a_vdec_hevc_div.hw,
4705 [CLKID_VDEC_HEVC] = &g12a_vdec_hevc.hw,
4706 [CLKID_VDEC_HEVCF_SEL] = &g12a_vdec_hevcf_sel.hw,
4707 [CLKID_VDEC_HEVCF_DIV] = &g12a_vdec_hevcf_div.hw,
4708 [CLKID_VDEC_HEVCF] = &g12a_vdec_hevcf.hw,
4709 [CLKID_TS_DIV] = &g12a_ts_div.hw,
4710 [CLKID_TS] = &g12a_ts.hw,
4711 [CLKID_SPICC0_SCLK_SEL] = &g12a_spicc0_sclk_sel.hw,
4712 [CLKID_SPICC0_SCLK_DIV] = &g12a_spicc0_sclk_div.hw,
4713 [CLKID_SPICC0_SCLK] = &g12a_spicc0_sclk.hw,
4714 [CLKID_SPICC1_SCLK_SEL] = &g12a_spicc1_sclk_sel.hw,
4715 [CLKID_SPICC1_SCLK_DIV] = &g12a_spicc1_sclk_div.hw,
4716 [CLKID_SPICC1_SCLK] = &g12a_spicc1_sclk.hw,
4717 [CLKID_MIPI_DSI_PXCLK_SEL] = &g12a_mipi_dsi_pxclk_sel.hw,
4718 [CLKID_MIPI_DSI_PXCLK_DIV] = &g12a_mipi_dsi_pxclk_div.hw,
4719 [CLKID_MIPI_DSI_PXCLK] = &g12a_mipi_dsi_pxclk.hw,
4720};
4721
4722static struct clk_hw *g12b_hw_clks[] = {
4723 [CLKID_SYS_PLL] = &g12a_sys_pll.hw,
4724 [CLKID_FIXED_PLL] = &g12a_fixed_pll.hw,
4725 [CLKID_FCLK_DIV2] = &g12a_fclk_div2.hw,
4726 [CLKID_FCLK_DIV3] = &g12a_fclk_div3.hw,
4727 [CLKID_FCLK_DIV4] = &g12a_fclk_div4.hw,
4728 [CLKID_FCLK_DIV5] = &g12a_fclk_div5.hw,
4729 [CLKID_FCLK_DIV7] = &g12a_fclk_div7.hw,
4730 [CLKID_FCLK_DIV2P5] = &g12a_fclk_div2p5.hw,
4731 [CLKID_GP0_PLL] = &g12a_gp0_pll.hw,
4732 [CLKID_MPEG_SEL] = &g12a_clk81_sel.hw,
4733 [CLKID_MPEG_DIV] = &g12a_clk81_div.hw,
4734 [CLKID_CLK81] = &g12a_clk81.hw,
4735 [CLKID_MPLL0] = &g12a_mpll0.hw,
4736 [CLKID_MPLL1] = &g12a_mpll1.hw,
4737 [CLKID_MPLL2] = &g12a_mpll2.hw,
4738 [CLKID_MPLL3] = &g12a_mpll3.hw,
4739 [CLKID_DDR] = &g12a_ddr.hw,
4740 [CLKID_DOS] = &g12a_dos.hw,
4741 [CLKID_AUDIO_LOCKER] = &g12a_audio_locker.hw,
4742 [CLKID_MIPI_DSI_HOST] = &g12a_mipi_dsi_host.hw,
4743 [CLKID_ETH_PHY] = &g12a_eth_phy.hw,
4744 [CLKID_ISA] = &g12a_isa.hw,
4745 [CLKID_PL301] = &g12a_pl301.hw,
4746 [CLKID_PERIPHS] = &g12a_periphs.hw,
4747 [CLKID_SPICC0] = &g12a_spicc_0.hw,
4748 [CLKID_I2C] = &g12a_i2c.hw,
4749 [CLKID_SANA] = &g12a_sana.hw,
4750 [CLKID_SD] = &g12a_sd.hw,
4751 [CLKID_RNG0] = &g12a_rng0.hw,
4752 [CLKID_UART0] = &g12a_uart0.hw,
4753 [CLKID_SPICC1] = &g12a_spicc_1.hw,
4754 [CLKID_HIU_IFACE] = &g12a_hiu_reg.hw,
4755 [CLKID_MIPI_DSI_PHY] = &g12a_mipi_dsi_phy.hw,
4756 [CLKID_ASSIST_MISC] = &g12a_assist_misc.hw,
4757 [CLKID_SD_EMMC_A] = &g12a_emmc_a.hw,
4758 [CLKID_SD_EMMC_B] = &g12a_emmc_b.hw,
4759 [CLKID_SD_EMMC_C] = &g12a_emmc_c.hw,
4760 [CLKID_AUDIO_CODEC] = &g12a_audio_codec.hw,
4761 [CLKID_AUDIO] = &g12a_audio.hw,
4762 [CLKID_ETH] = &g12a_eth_core.hw,
4763 [CLKID_DEMUX] = &g12a_demux.hw,
4764 [CLKID_AUDIO_IFIFO] = &g12a_audio_ififo.hw,
4765 [CLKID_ADC] = &g12a_adc.hw,
4766 [CLKID_UART1] = &g12a_uart1.hw,
4767 [CLKID_G2D] = &g12a_g2d.hw,
4768 [CLKID_RESET] = &g12a_reset.hw,
4769 [CLKID_PCIE_COMB] = &g12a_pcie_comb.hw,
4770 [CLKID_PARSER] = &g12a_parser.hw,
4771 [CLKID_USB] = &g12a_usb_general.hw,
4772 [CLKID_PCIE_PHY] = &g12a_pcie_phy.hw,
4773 [CLKID_AHB_ARB0] = &g12a_ahb_arb0.hw,
4774 [CLKID_AHB_DATA_BUS] = &g12a_ahb_data_bus.hw,
4775 [CLKID_AHB_CTRL_BUS] = &g12a_ahb_ctrl_bus.hw,
4776 [CLKID_HTX_HDCP22] = &g12a_htx_hdcp22.hw,
4777 [CLKID_HTX_PCLK] = &g12a_htx_pclk.hw,
4778 [CLKID_BT656] = &g12a_bt656.hw,
4779 [CLKID_USB1_DDR_BRIDGE] = &g12a_usb1_to_ddr.hw,
4780 [CLKID_MMC_PCLK] = &g12a_mmc_pclk.hw,
4781 [CLKID_UART2] = &g12a_uart2.hw,
4782 [CLKID_VPU_INTR] = &g12a_vpu_intr.hw,
4783 [CLKID_GIC] = &g12a_gic.hw,
4784 [CLKID_SD_EMMC_A_CLK0_SEL] = &g12a_sd_emmc_a_clk0_sel.hw,
4785 [CLKID_SD_EMMC_A_CLK0_DIV] = &g12a_sd_emmc_a_clk0_div.hw,
4786 [CLKID_SD_EMMC_A_CLK0] = &g12a_sd_emmc_a_clk0.hw,
4787 [CLKID_SD_EMMC_B_CLK0_SEL] = &g12a_sd_emmc_b_clk0_sel.hw,
4788 [CLKID_SD_EMMC_B_CLK0_DIV] = &g12a_sd_emmc_b_clk0_div.hw,
4789 [CLKID_SD_EMMC_B_CLK0] = &g12a_sd_emmc_b_clk0.hw,
4790 [CLKID_SD_EMMC_C_CLK0_SEL] = &g12a_sd_emmc_c_clk0_sel.hw,
4791 [CLKID_SD_EMMC_C_CLK0_DIV] = &g12a_sd_emmc_c_clk0_div.hw,
4792 [CLKID_SD_EMMC_C_CLK0] = &g12a_sd_emmc_c_clk0.hw,
4793 [CLKID_MPLL0_DIV] = &g12a_mpll0_div.hw,
4794 [CLKID_MPLL1_DIV] = &g12a_mpll1_div.hw,
4795 [CLKID_MPLL2_DIV] = &g12a_mpll2_div.hw,
4796 [CLKID_MPLL3_DIV] = &g12a_mpll3_div.hw,
4797 [CLKID_FCLK_DIV2_DIV] = &g12a_fclk_div2_div.hw,
4798 [CLKID_FCLK_DIV3_DIV] = &g12a_fclk_div3_div.hw,
4799 [CLKID_FCLK_DIV4_DIV] = &g12a_fclk_div4_div.hw,
4800 [CLKID_FCLK_DIV5_DIV] = &g12a_fclk_div5_div.hw,
4801 [CLKID_FCLK_DIV7_DIV] = &g12a_fclk_div7_div.hw,
4802 [CLKID_FCLK_DIV2P5_DIV] = &g12a_fclk_div2p5_div.hw,
4803 [CLKID_HIFI_PLL] = &g12a_hifi_pll.hw,
4804 [CLKID_VCLK2_VENCI0] = &g12a_vclk2_venci0.hw,
4805 [CLKID_VCLK2_VENCI1] = &g12a_vclk2_venci1.hw,
4806 [CLKID_VCLK2_VENCP0] = &g12a_vclk2_vencp0.hw,
4807 [CLKID_VCLK2_VENCP1] = &g12a_vclk2_vencp1.hw,
4808 [CLKID_VCLK2_VENCT0] = &g12a_vclk2_venct0.hw,
4809 [CLKID_VCLK2_VENCT1] = &g12a_vclk2_venct1.hw,
4810 [CLKID_VCLK2_OTHER] = &g12a_vclk2_other.hw,
4811 [CLKID_VCLK2_ENCI] = &g12a_vclk2_enci.hw,
4812 [CLKID_VCLK2_ENCP] = &g12a_vclk2_encp.hw,
4813 [CLKID_DAC_CLK] = &g12a_dac_clk.hw,
4814 [CLKID_AOCLK] = &g12a_aoclk_gate.hw,
4815 [CLKID_IEC958] = &g12a_iec958_gate.hw,
4816 [CLKID_ENC480P] = &g12a_enc480p.hw,
4817 [CLKID_RNG1] = &g12a_rng1.hw,
4818 [CLKID_VCLK2_ENCT] = &g12a_vclk2_enct.hw,
4819 [CLKID_VCLK2_ENCL] = &g12a_vclk2_encl.hw,
4820 [CLKID_VCLK2_VENCLMMC] = &g12a_vclk2_venclmmc.hw,
4821 [CLKID_VCLK2_VENCL] = &g12a_vclk2_vencl.hw,
4822 [CLKID_VCLK2_OTHER1] = &g12a_vclk2_other1.hw,
4823 [CLKID_FIXED_PLL_DCO] = &g12a_fixed_pll_dco.hw,
4824 [CLKID_SYS_PLL_DCO] = &g12a_sys_pll_dco.hw,
4825 [CLKID_GP0_PLL_DCO] = &g12a_gp0_pll_dco.hw,
4826 [CLKID_HIFI_PLL_DCO] = &g12a_hifi_pll_dco.hw,
4827 [CLKID_DMA] = &g12a_dma.hw,
4828 [CLKID_EFUSE] = &g12a_efuse.hw,
4829 [CLKID_ROM_BOOT] = &g12a_rom_boot.hw,
4830 [CLKID_RESET_SEC] = &g12a_reset_sec.hw,
4831 [CLKID_SEC_AHB_APB3] = &g12a_sec_ahb_apb3.hw,
4832 [CLKID_MPLL_PREDIV] = &g12a_mpll_prediv.hw,
4833 [CLKID_VPU_0_SEL] = &g12a_vpu_0_sel.hw,
4834 [CLKID_VPU_0_DIV] = &g12a_vpu_0_div.hw,
4835 [CLKID_VPU_0] = &g12a_vpu_0.hw,
4836 [CLKID_VPU_1_SEL] = &g12a_vpu_1_sel.hw,
4837 [CLKID_VPU_1_DIV] = &g12a_vpu_1_div.hw,
4838 [CLKID_VPU_1] = &g12a_vpu_1.hw,
4839 [CLKID_VPU] = &g12a_vpu.hw,
4840 [CLKID_VAPB_0_SEL] = &g12a_vapb_0_sel.hw,
4841 [CLKID_VAPB_0_DIV] = &g12a_vapb_0_div.hw,
4842 [CLKID_VAPB_0] = &g12a_vapb_0.hw,
4843 [CLKID_VAPB_1_SEL] = &g12a_vapb_1_sel.hw,
4844 [CLKID_VAPB_1_DIV] = &g12a_vapb_1_div.hw,
4845 [CLKID_VAPB_1] = &g12a_vapb_1.hw,
4846 [CLKID_VAPB_SEL] = &g12a_vapb_sel.hw,
4847 [CLKID_VAPB] = &g12a_vapb.hw,
4848 [CLKID_HDMI_PLL_DCO] = &g12a_hdmi_pll_dco.hw,
4849 [CLKID_HDMI_PLL_OD] = &g12a_hdmi_pll_od.hw,
4850 [CLKID_HDMI_PLL_OD2] = &g12a_hdmi_pll_od2.hw,
4851 [CLKID_HDMI_PLL] = &g12a_hdmi_pll.hw,
4852 [CLKID_VID_PLL] = &g12a_vid_pll_div.hw,
4853 [CLKID_VID_PLL_SEL] = &g12a_vid_pll_sel.hw,
4854 [CLKID_VID_PLL_DIV] = &g12a_vid_pll.hw,
4855 [CLKID_VCLK_SEL] = &g12a_vclk_sel.hw,
4856 [CLKID_VCLK2_SEL] = &g12a_vclk2_sel.hw,
4857 [CLKID_VCLK_INPUT] = &g12a_vclk_input.hw,
4858 [CLKID_VCLK2_INPUT] = &g12a_vclk2_input.hw,
4859 [CLKID_VCLK_DIV] = &g12a_vclk_div.hw,
4860 [CLKID_VCLK2_DIV] = &g12a_vclk2_div.hw,
4861 [CLKID_VCLK] = &g12a_vclk.hw,
4862 [CLKID_VCLK2] = &g12a_vclk2.hw,
4863 [CLKID_VCLK_DIV1] = &g12a_vclk_div1.hw,
4864 [CLKID_VCLK_DIV2_EN] = &g12a_vclk_div2_en.hw,
4865 [CLKID_VCLK_DIV4_EN] = &g12a_vclk_div4_en.hw,
4866 [CLKID_VCLK_DIV6_EN] = &g12a_vclk_div6_en.hw,
4867 [CLKID_VCLK_DIV12_EN] = &g12a_vclk_div12_en.hw,
4868 [CLKID_VCLK2_DIV1] = &g12a_vclk2_div1.hw,
4869 [CLKID_VCLK2_DIV2_EN] = &g12a_vclk2_div2_en.hw,
4870 [CLKID_VCLK2_DIV4_EN] = &g12a_vclk2_div4_en.hw,
4871 [CLKID_VCLK2_DIV6_EN] = &g12a_vclk2_div6_en.hw,
4872 [CLKID_VCLK2_DIV12_EN] = &g12a_vclk2_div12_en.hw,
4873 [CLKID_VCLK_DIV2] = &g12a_vclk_div2.hw,
4874 [CLKID_VCLK_DIV4] = &g12a_vclk_div4.hw,
4875 [CLKID_VCLK_DIV6] = &g12a_vclk_div6.hw,
4876 [CLKID_VCLK_DIV12] = &g12a_vclk_div12.hw,
4877 [CLKID_VCLK2_DIV2] = &g12a_vclk2_div2.hw,
4878 [CLKID_VCLK2_DIV4] = &g12a_vclk2_div4.hw,
4879 [CLKID_VCLK2_DIV6] = &g12a_vclk2_div6.hw,
4880 [CLKID_VCLK2_DIV12] = &g12a_vclk2_div12.hw,
4881 [CLKID_CTS_ENCI_SEL] = &g12a_cts_enci_sel.hw,
4882 [CLKID_CTS_ENCP_SEL] = &g12a_cts_encp_sel.hw,
4883 [CLKID_CTS_ENCL_SEL] = &g12a_cts_encl_sel.hw,
4884 [CLKID_CTS_VDAC_SEL] = &g12a_cts_vdac_sel.hw,
4885 [CLKID_HDMI_TX_SEL] = &g12a_hdmi_tx_sel.hw,
4886 [CLKID_CTS_ENCI] = &g12a_cts_enci.hw,
4887 [CLKID_CTS_ENCP] = &g12a_cts_encp.hw,
4888 [CLKID_CTS_ENCL] = &g12a_cts_encl.hw,
4889 [CLKID_CTS_VDAC] = &g12a_cts_vdac.hw,
4890 [CLKID_HDMI_TX] = &g12a_hdmi_tx.hw,
4891 [CLKID_HDMI_SEL] = &g12a_hdmi_sel.hw,
4892 [CLKID_HDMI_DIV] = &g12a_hdmi_div.hw,
4893 [CLKID_HDMI] = &g12a_hdmi.hw,
4894 [CLKID_MALI_0_SEL] = &g12a_mali_0_sel.hw,
4895 [CLKID_MALI_0_DIV] = &g12a_mali_0_div.hw,
4896 [CLKID_MALI_0] = &g12a_mali_0.hw,
4897 [CLKID_MALI_1_SEL] = &g12a_mali_1_sel.hw,
4898 [CLKID_MALI_1_DIV] = &g12a_mali_1_div.hw,
4899 [CLKID_MALI_1] = &g12a_mali_1.hw,
4900 [CLKID_MALI] = &g12a_mali.hw,
4901 [CLKID_MPLL_50M_DIV] = &g12a_mpll_50m_div.hw,
4902 [CLKID_MPLL_50M] = &g12a_mpll_50m.hw,
4903 [CLKID_SYS_PLL_DIV16_EN] = &g12a_sys_pll_div16_en.hw,
4904 [CLKID_SYS_PLL_DIV16] = &g12a_sys_pll_div16.hw,
4905 [CLKID_CPU_CLK_DYN0_SEL] = &g12a_cpu_clk_dyn0_sel.hw,
4906 [CLKID_CPU_CLK_DYN0_DIV] = &g12a_cpu_clk_dyn0_div.hw,
4907 [CLKID_CPU_CLK_DYN0] = &g12a_cpu_clk_dyn0.hw,
4908 [CLKID_CPU_CLK_DYN1_SEL] = &g12a_cpu_clk_dyn1_sel.hw,
4909 [CLKID_CPU_CLK_DYN1_DIV] = &g12a_cpu_clk_dyn1_div.hw,
4910 [CLKID_CPU_CLK_DYN1] = &g12a_cpu_clk_dyn1.hw,
4911 [CLKID_CPU_CLK_DYN] = &g12a_cpu_clk_dyn.hw,
4912 [CLKID_CPU_CLK] = &g12b_cpu_clk.hw,
4913 [CLKID_CPU_CLK_DIV16_EN] = &g12a_cpu_clk_div16_en.hw,
4914 [CLKID_CPU_CLK_DIV16] = &g12a_cpu_clk_div16.hw,
4915 [CLKID_CPU_CLK_APB_DIV] = &g12a_cpu_clk_apb_div.hw,
4916 [CLKID_CPU_CLK_APB] = &g12a_cpu_clk_apb.hw,
4917 [CLKID_CPU_CLK_ATB_DIV] = &g12a_cpu_clk_atb_div.hw,
4918 [CLKID_CPU_CLK_ATB] = &g12a_cpu_clk_atb.hw,
4919 [CLKID_CPU_CLK_AXI_DIV] = &g12a_cpu_clk_axi_div.hw,
4920 [CLKID_CPU_CLK_AXI] = &g12a_cpu_clk_axi.hw,
4921 [CLKID_CPU_CLK_TRACE_DIV] = &g12a_cpu_clk_trace_div.hw,
4922 [CLKID_CPU_CLK_TRACE] = &g12a_cpu_clk_trace.hw,
4923 [CLKID_PCIE_PLL_DCO] = &g12a_pcie_pll_dco.hw,
4924 [CLKID_PCIE_PLL_DCO_DIV2] = &g12a_pcie_pll_dco_div2.hw,
4925 [CLKID_PCIE_PLL_OD] = &g12a_pcie_pll_od.hw,
4926 [CLKID_PCIE_PLL] = &g12a_pcie_pll.hw,
4927 [CLKID_VDEC_1_SEL] = &g12a_vdec_1_sel.hw,
4928 [CLKID_VDEC_1_DIV] = &g12a_vdec_1_div.hw,
4929 [CLKID_VDEC_1] = &g12a_vdec_1.hw,
4930 [CLKID_VDEC_HEVC_SEL] = &g12a_vdec_hevc_sel.hw,
4931 [CLKID_VDEC_HEVC_DIV] = &g12a_vdec_hevc_div.hw,
4932 [CLKID_VDEC_HEVC] = &g12a_vdec_hevc.hw,
4933 [CLKID_VDEC_HEVCF_SEL] = &g12a_vdec_hevcf_sel.hw,
4934 [CLKID_VDEC_HEVCF_DIV] = &g12a_vdec_hevcf_div.hw,
4935 [CLKID_VDEC_HEVCF] = &g12a_vdec_hevcf.hw,
4936 [CLKID_TS_DIV] = &g12a_ts_div.hw,
4937 [CLKID_TS] = &g12a_ts.hw,
4938 [CLKID_SYS1_PLL_DCO] = &g12b_sys1_pll_dco.hw,
4939 [CLKID_SYS1_PLL] = &g12b_sys1_pll.hw,
4940 [CLKID_SYS1_PLL_DIV16_EN] = &g12b_sys1_pll_div16_en.hw,
4941 [CLKID_SYS1_PLL_DIV16] = &g12b_sys1_pll_div16.hw,
4942 [CLKID_CPUB_CLK_DYN0_SEL] = &g12b_cpub_clk_dyn0_sel.hw,
4943 [CLKID_CPUB_CLK_DYN0_DIV] = &g12b_cpub_clk_dyn0_div.hw,
4944 [CLKID_CPUB_CLK_DYN0] = &g12b_cpub_clk_dyn0.hw,
4945 [CLKID_CPUB_CLK_DYN1_SEL] = &g12b_cpub_clk_dyn1_sel.hw,
4946 [CLKID_CPUB_CLK_DYN1_DIV] = &g12b_cpub_clk_dyn1_div.hw,
4947 [CLKID_CPUB_CLK_DYN1] = &g12b_cpub_clk_dyn1.hw,
4948 [CLKID_CPUB_CLK_DYN] = &g12b_cpub_clk_dyn.hw,
4949 [CLKID_CPUB_CLK] = &g12b_cpub_clk.hw,
4950 [CLKID_CPUB_CLK_DIV16_EN] = &g12b_cpub_clk_div16_en.hw,
4951 [CLKID_CPUB_CLK_DIV16] = &g12b_cpub_clk_div16.hw,
4952 [CLKID_CPUB_CLK_DIV2] = &g12b_cpub_clk_div2.hw,
4953 [CLKID_CPUB_CLK_DIV3] = &g12b_cpub_clk_div3.hw,
4954 [CLKID_CPUB_CLK_DIV4] = &g12b_cpub_clk_div4.hw,
4955 [CLKID_CPUB_CLK_DIV5] = &g12b_cpub_clk_div5.hw,
4956 [CLKID_CPUB_CLK_DIV6] = &g12b_cpub_clk_div6.hw,
4957 [CLKID_CPUB_CLK_DIV7] = &g12b_cpub_clk_div7.hw,
4958 [CLKID_CPUB_CLK_DIV8] = &g12b_cpub_clk_div8.hw,
4959 [CLKID_CPUB_CLK_APB_SEL] = &g12b_cpub_clk_apb_sel.hw,
4960 [CLKID_CPUB_CLK_APB] = &g12b_cpub_clk_apb.hw,
4961 [CLKID_CPUB_CLK_ATB_SEL] = &g12b_cpub_clk_atb_sel.hw,
4962 [CLKID_CPUB_CLK_ATB] = &g12b_cpub_clk_atb.hw,
4963 [CLKID_CPUB_CLK_AXI_SEL] = &g12b_cpub_clk_axi_sel.hw,
4964 [CLKID_CPUB_CLK_AXI] = &g12b_cpub_clk_axi.hw,
4965 [CLKID_CPUB_CLK_TRACE_SEL] = &g12b_cpub_clk_trace_sel.hw,
4966 [CLKID_CPUB_CLK_TRACE] = &g12b_cpub_clk_trace.hw,
4967 [CLKID_SPICC0_SCLK_SEL] = &g12a_spicc0_sclk_sel.hw,
4968 [CLKID_SPICC0_SCLK_DIV] = &g12a_spicc0_sclk_div.hw,
4969 [CLKID_SPICC0_SCLK] = &g12a_spicc0_sclk.hw,
4970 [CLKID_SPICC1_SCLK_SEL] = &g12a_spicc1_sclk_sel.hw,
4971 [CLKID_SPICC1_SCLK_DIV] = &g12a_spicc1_sclk_div.hw,
4972 [CLKID_SPICC1_SCLK] = &g12a_spicc1_sclk.hw,
4973 [CLKID_NNA_AXI_CLK_SEL] = &sm1_nna_axi_clk_sel.hw,
4974 [CLKID_NNA_AXI_CLK_DIV] = &sm1_nna_axi_clk_div.hw,
4975 [CLKID_NNA_AXI_CLK] = &sm1_nna_axi_clk.hw,
4976 [CLKID_NNA_CORE_CLK_SEL] = &sm1_nna_core_clk_sel.hw,
4977 [CLKID_NNA_CORE_CLK_DIV] = &sm1_nna_core_clk_div.hw,
4978 [CLKID_NNA_CORE_CLK] = &sm1_nna_core_clk.hw,
4979 [CLKID_MIPI_DSI_PXCLK_SEL] = &g12a_mipi_dsi_pxclk_sel.hw,
4980 [CLKID_MIPI_DSI_PXCLK_DIV] = &g12a_mipi_dsi_pxclk_div.hw,
4981 [CLKID_MIPI_DSI_PXCLK] = &g12a_mipi_dsi_pxclk.hw,
4982 [CLKID_MIPI_ISP_SEL] = &g12b_mipi_isp_sel.hw,
4983 [CLKID_MIPI_ISP_DIV] = &g12b_mipi_isp_div.hw,
4984 [CLKID_MIPI_ISP] = &g12b_mipi_isp.hw,
4985 [CLKID_MIPI_ISP_GATE] = &g12b_mipi_isp_gate.hw,
4986 [CLKID_MIPI_ISP_CSI_PHY0] = &g12b_csi_phy0.hw,
4987 [CLKID_MIPI_ISP_CSI_PHY1] = &g12b_csi_phy1.hw,
4988};
4989
4990static struct clk_hw *sm1_hw_clks[] = {
4991 [CLKID_SYS_PLL] = &g12a_sys_pll.hw,
4992 [CLKID_FIXED_PLL] = &g12a_fixed_pll.hw,
4993 [CLKID_FCLK_DIV2] = &g12a_fclk_div2.hw,
4994 [CLKID_FCLK_DIV3] = &g12a_fclk_div3.hw,
4995 [CLKID_FCLK_DIV4] = &g12a_fclk_div4.hw,
4996 [CLKID_FCLK_DIV5] = &g12a_fclk_div5.hw,
4997 [CLKID_FCLK_DIV7] = &g12a_fclk_div7.hw,
4998 [CLKID_FCLK_DIV2P5] = &g12a_fclk_div2p5.hw,
4999 [CLKID_GP0_PLL] = &g12a_gp0_pll.hw,
5000 [CLKID_MPEG_SEL] = &g12a_clk81_sel.hw,
5001 [CLKID_MPEG_DIV] = &g12a_clk81_div.hw,
5002 [CLKID_CLK81] = &g12a_clk81.hw,
5003 [CLKID_MPLL0] = &g12a_mpll0.hw,
5004 [CLKID_MPLL1] = &g12a_mpll1.hw,
5005 [CLKID_MPLL2] = &g12a_mpll2.hw,
5006 [CLKID_MPLL3] = &g12a_mpll3.hw,
5007 [CLKID_DDR] = &g12a_ddr.hw,
5008 [CLKID_DOS] = &g12a_dos.hw,
5009 [CLKID_AUDIO_LOCKER] = &g12a_audio_locker.hw,
5010 [CLKID_MIPI_DSI_HOST] = &g12a_mipi_dsi_host.hw,
5011 [CLKID_ETH_PHY] = &g12a_eth_phy.hw,
5012 [CLKID_ISA] = &g12a_isa.hw,
5013 [CLKID_PL301] = &g12a_pl301.hw,
5014 [CLKID_PERIPHS] = &g12a_periphs.hw,
5015 [CLKID_SPICC0] = &g12a_spicc_0.hw,
5016 [CLKID_I2C] = &g12a_i2c.hw,
5017 [CLKID_SANA] = &g12a_sana.hw,
5018 [CLKID_SD] = &g12a_sd.hw,
5019 [CLKID_RNG0] = &g12a_rng0.hw,
5020 [CLKID_UART0] = &g12a_uart0.hw,
5021 [CLKID_SPICC1] = &g12a_spicc_1.hw,
5022 [CLKID_HIU_IFACE] = &g12a_hiu_reg.hw,
5023 [CLKID_MIPI_DSI_PHY] = &g12a_mipi_dsi_phy.hw,
5024 [CLKID_ASSIST_MISC] = &g12a_assist_misc.hw,
5025 [CLKID_SD_EMMC_A] = &g12a_emmc_a.hw,
5026 [CLKID_SD_EMMC_B] = &g12a_emmc_b.hw,
5027 [CLKID_SD_EMMC_C] = &g12a_emmc_c.hw,
5028 [CLKID_AUDIO_CODEC] = &g12a_audio_codec.hw,
5029 [CLKID_AUDIO] = &g12a_audio.hw,
5030 [CLKID_ETH] = &g12a_eth_core.hw,
5031 [CLKID_DEMUX] = &g12a_demux.hw,
5032 [CLKID_AUDIO_IFIFO] = &g12a_audio_ififo.hw,
5033 [CLKID_ADC] = &g12a_adc.hw,
5034 [CLKID_UART1] = &g12a_uart1.hw,
5035 [CLKID_G2D] = &g12a_g2d.hw,
5036 [CLKID_RESET] = &g12a_reset.hw,
5037 [CLKID_PCIE_COMB] = &g12a_pcie_comb.hw,
5038 [CLKID_PARSER] = &g12a_parser.hw,
5039 [CLKID_USB] = &g12a_usb_general.hw,
5040 [CLKID_PCIE_PHY] = &g12a_pcie_phy.hw,
5041 [CLKID_AHB_ARB0] = &g12a_ahb_arb0.hw,
5042 [CLKID_AHB_DATA_BUS] = &g12a_ahb_data_bus.hw,
5043 [CLKID_AHB_CTRL_BUS] = &g12a_ahb_ctrl_bus.hw,
5044 [CLKID_HTX_HDCP22] = &g12a_htx_hdcp22.hw,
5045 [CLKID_HTX_PCLK] = &g12a_htx_pclk.hw,
5046 [CLKID_BT656] = &g12a_bt656.hw,
5047 [CLKID_USB1_DDR_BRIDGE] = &g12a_usb1_to_ddr.hw,
5048 [CLKID_MMC_PCLK] = &g12a_mmc_pclk.hw,
5049 [CLKID_UART2] = &g12a_uart2.hw,
5050 [CLKID_VPU_INTR] = &g12a_vpu_intr.hw,
5051 [CLKID_GIC] = &g12a_gic.hw,
5052 [CLKID_SD_EMMC_A_CLK0_SEL] = &g12a_sd_emmc_a_clk0_sel.hw,
5053 [CLKID_SD_EMMC_A_CLK0_DIV] = &g12a_sd_emmc_a_clk0_div.hw,
5054 [CLKID_SD_EMMC_A_CLK0] = &g12a_sd_emmc_a_clk0.hw,
5055 [CLKID_SD_EMMC_B_CLK0_SEL] = &g12a_sd_emmc_b_clk0_sel.hw,
5056 [CLKID_SD_EMMC_B_CLK0_DIV] = &g12a_sd_emmc_b_clk0_div.hw,
5057 [CLKID_SD_EMMC_B_CLK0] = &g12a_sd_emmc_b_clk0.hw,
5058 [CLKID_SD_EMMC_C_CLK0_SEL] = &g12a_sd_emmc_c_clk0_sel.hw,
5059 [CLKID_SD_EMMC_C_CLK0_DIV] = &g12a_sd_emmc_c_clk0_div.hw,
5060 [CLKID_SD_EMMC_C_CLK0] = &g12a_sd_emmc_c_clk0.hw,
5061 [CLKID_MPLL0_DIV] = &g12a_mpll0_div.hw,
5062 [CLKID_MPLL1_DIV] = &g12a_mpll1_div.hw,
5063 [CLKID_MPLL2_DIV] = &g12a_mpll2_div.hw,
5064 [CLKID_MPLL3_DIV] = &g12a_mpll3_div.hw,
5065 [CLKID_FCLK_DIV2_DIV] = &g12a_fclk_div2_div.hw,
5066 [CLKID_FCLK_DIV3_DIV] = &g12a_fclk_div3_div.hw,
5067 [CLKID_FCLK_DIV4_DIV] = &g12a_fclk_div4_div.hw,
5068 [CLKID_FCLK_DIV5_DIV] = &g12a_fclk_div5_div.hw,
5069 [CLKID_FCLK_DIV7_DIV] = &g12a_fclk_div7_div.hw,
5070 [CLKID_FCLK_DIV2P5_DIV] = &g12a_fclk_div2p5_div.hw,
5071 [CLKID_HIFI_PLL] = &g12a_hifi_pll.hw,
5072 [CLKID_VCLK2_VENCI0] = &g12a_vclk2_venci0.hw,
5073 [CLKID_VCLK2_VENCI1] = &g12a_vclk2_venci1.hw,
5074 [CLKID_VCLK2_VENCP0] = &g12a_vclk2_vencp0.hw,
5075 [CLKID_VCLK2_VENCP1] = &g12a_vclk2_vencp1.hw,
5076 [CLKID_VCLK2_VENCT0] = &g12a_vclk2_venct0.hw,
5077 [CLKID_VCLK2_VENCT1] = &g12a_vclk2_venct1.hw,
5078 [CLKID_VCLK2_OTHER] = &g12a_vclk2_other.hw,
5079 [CLKID_VCLK2_ENCI] = &g12a_vclk2_enci.hw,
5080 [CLKID_VCLK2_ENCP] = &g12a_vclk2_encp.hw,
5081 [CLKID_DAC_CLK] = &g12a_dac_clk.hw,
5082 [CLKID_AOCLK] = &g12a_aoclk_gate.hw,
5083 [CLKID_IEC958] = &g12a_iec958_gate.hw,
5084 [CLKID_ENC480P] = &g12a_enc480p.hw,
5085 [CLKID_RNG1] = &g12a_rng1.hw,
5086 [CLKID_VCLK2_ENCT] = &g12a_vclk2_enct.hw,
5087 [CLKID_VCLK2_ENCL] = &g12a_vclk2_encl.hw,
5088 [CLKID_VCLK2_VENCLMMC] = &g12a_vclk2_venclmmc.hw,
5089 [CLKID_VCLK2_VENCL] = &g12a_vclk2_vencl.hw,
5090 [CLKID_VCLK2_OTHER1] = &g12a_vclk2_other1.hw,
5091 [CLKID_FIXED_PLL_DCO] = &g12a_fixed_pll_dco.hw,
5092 [CLKID_SYS_PLL_DCO] = &g12a_sys_pll_dco.hw,
5093 [CLKID_GP0_PLL_DCO] = &g12a_gp0_pll_dco.hw,
5094 [CLKID_HIFI_PLL_DCO] = &g12a_hifi_pll_dco.hw,
5095 [CLKID_DMA] = &g12a_dma.hw,
5096 [CLKID_EFUSE] = &g12a_efuse.hw,
5097 [CLKID_ROM_BOOT] = &g12a_rom_boot.hw,
5098 [CLKID_RESET_SEC] = &g12a_reset_sec.hw,
5099 [CLKID_SEC_AHB_APB3] = &g12a_sec_ahb_apb3.hw,
5100 [CLKID_MPLL_PREDIV] = &g12a_mpll_prediv.hw,
5101 [CLKID_VPU_0_SEL] = &g12a_vpu_0_sel.hw,
5102 [CLKID_VPU_0_DIV] = &g12a_vpu_0_div.hw,
5103 [CLKID_VPU_0] = &g12a_vpu_0.hw,
5104 [CLKID_VPU_1_SEL] = &g12a_vpu_1_sel.hw,
5105 [CLKID_VPU_1_DIV] = &g12a_vpu_1_div.hw,
5106 [CLKID_VPU_1] = &g12a_vpu_1.hw,
5107 [CLKID_VPU] = &g12a_vpu.hw,
5108 [CLKID_VAPB_0_SEL] = &g12a_vapb_0_sel.hw,
5109 [CLKID_VAPB_0_DIV] = &g12a_vapb_0_div.hw,
5110 [CLKID_VAPB_0] = &g12a_vapb_0.hw,
5111 [CLKID_VAPB_1_SEL] = &g12a_vapb_1_sel.hw,
5112 [CLKID_VAPB_1_DIV] = &g12a_vapb_1_div.hw,
5113 [CLKID_VAPB_1] = &g12a_vapb_1.hw,
5114 [CLKID_VAPB_SEL] = &g12a_vapb_sel.hw,
5115 [CLKID_VAPB] = &g12a_vapb.hw,
5116 [CLKID_HDMI_PLL_DCO] = &g12a_hdmi_pll_dco.hw,
5117 [CLKID_HDMI_PLL_OD] = &g12a_hdmi_pll_od.hw,
5118 [CLKID_HDMI_PLL_OD2] = &g12a_hdmi_pll_od2.hw,
5119 [CLKID_HDMI_PLL] = &g12a_hdmi_pll.hw,
5120 [CLKID_VID_PLL] = &g12a_vid_pll_div.hw,
5121 [CLKID_VID_PLL_SEL] = &g12a_vid_pll_sel.hw,
5122 [CLKID_VID_PLL_DIV] = &g12a_vid_pll.hw,
5123 [CLKID_VCLK_SEL] = &g12a_vclk_sel.hw,
5124 [CLKID_VCLK2_SEL] = &g12a_vclk2_sel.hw,
5125 [CLKID_VCLK_INPUT] = &g12a_vclk_input.hw,
5126 [CLKID_VCLK2_INPUT] = &g12a_vclk2_input.hw,
5127 [CLKID_VCLK_DIV] = &g12a_vclk_div.hw,
5128 [CLKID_VCLK2_DIV] = &g12a_vclk2_div.hw,
5129 [CLKID_VCLK] = &g12a_vclk.hw,
5130 [CLKID_VCLK2] = &g12a_vclk2.hw,
5131 [CLKID_VCLK_DIV1] = &g12a_vclk_div1.hw,
5132 [CLKID_VCLK_DIV2_EN] = &g12a_vclk_div2_en.hw,
5133 [CLKID_VCLK_DIV4_EN] = &g12a_vclk_div4_en.hw,
5134 [CLKID_VCLK_DIV6_EN] = &g12a_vclk_div6_en.hw,
5135 [CLKID_VCLK_DIV12_EN] = &g12a_vclk_div12_en.hw,
5136 [CLKID_VCLK2_DIV1] = &g12a_vclk2_div1.hw,
5137 [CLKID_VCLK2_DIV2_EN] = &g12a_vclk2_div2_en.hw,
5138 [CLKID_VCLK2_DIV4_EN] = &g12a_vclk2_div4_en.hw,
5139 [CLKID_VCLK2_DIV6_EN] = &g12a_vclk2_div6_en.hw,
5140 [CLKID_VCLK2_DIV12_EN] = &g12a_vclk2_div12_en.hw,
5141 [CLKID_VCLK_DIV2] = &g12a_vclk_div2.hw,
5142 [CLKID_VCLK_DIV4] = &g12a_vclk_div4.hw,
5143 [CLKID_VCLK_DIV6] = &g12a_vclk_div6.hw,
5144 [CLKID_VCLK_DIV12] = &g12a_vclk_div12.hw,
5145 [CLKID_VCLK2_DIV2] = &g12a_vclk2_div2.hw,
5146 [CLKID_VCLK2_DIV4] = &g12a_vclk2_div4.hw,
5147 [CLKID_VCLK2_DIV6] = &g12a_vclk2_div6.hw,
5148 [CLKID_VCLK2_DIV12] = &g12a_vclk2_div12.hw,
5149 [CLKID_CTS_ENCI_SEL] = &g12a_cts_enci_sel.hw,
5150 [CLKID_CTS_ENCP_SEL] = &g12a_cts_encp_sel.hw,
5151 [CLKID_CTS_ENCL_SEL] = &g12a_cts_encl_sel.hw,
5152 [CLKID_CTS_VDAC_SEL] = &g12a_cts_vdac_sel.hw,
5153 [CLKID_HDMI_TX_SEL] = &g12a_hdmi_tx_sel.hw,
5154 [CLKID_CTS_ENCI] = &g12a_cts_enci.hw,
5155 [CLKID_CTS_ENCP] = &g12a_cts_encp.hw,
5156 [CLKID_CTS_ENCL] = &g12a_cts_encl.hw,
5157 [CLKID_CTS_VDAC] = &g12a_cts_vdac.hw,
5158 [CLKID_HDMI_TX] = &g12a_hdmi_tx.hw,
5159 [CLKID_HDMI_SEL] = &g12a_hdmi_sel.hw,
5160 [CLKID_HDMI_DIV] = &g12a_hdmi_div.hw,
5161 [CLKID_HDMI] = &g12a_hdmi.hw,
5162 [CLKID_MALI_0_SEL] = &g12a_mali_0_sel.hw,
5163 [CLKID_MALI_0_DIV] = &g12a_mali_0_div.hw,
5164 [CLKID_MALI_0] = &g12a_mali_0.hw,
5165 [CLKID_MALI_1_SEL] = &g12a_mali_1_sel.hw,
5166 [CLKID_MALI_1_DIV] = &g12a_mali_1_div.hw,
5167 [CLKID_MALI_1] = &g12a_mali_1.hw,
5168 [CLKID_MALI] = &g12a_mali.hw,
5169 [CLKID_MPLL_50M_DIV] = &g12a_mpll_50m_div.hw,
5170 [CLKID_MPLL_50M] = &g12a_mpll_50m.hw,
5171 [CLKID_SYS_PLL_DIV16_EN] = &g12a_sys_pll_div16_en.hw,
5172 [CLKID_SYS_PLL_DIV16] = &g12a_sys_pll_div16.hw,
5173 [CLKID_CPU_CLK_DYN0_SEL] = &g12a_cpu_clk_dyn0_sel.hw,
5174 [CLKID_CPU_CLK_DYN0_DIV] = &g12a_cpu_clk_dyn0_div.hw,
5175 [CLKID_CPU_CLK_DYN0] = &g12a_cpu_clk_dyn0.hw,
5176 [CLKID_CPU_CLK_DYN1_SEL] = &g12a_cpu_clk_dyn1_sel.hw,
5177 [CLKID_CPU_CLK_DYN1_DIV] = &g12a_cpu_clk_dyn1_div.hw,
5178 [CLKID_CPU_CLK_DYN1] = &g12a_cpu_clk_dyn1.hw,
5179 [CLKID_CPU_CLK_DYN] = &g12a_cpu_clk_dyn.hw,
5180 [CLKID_CPU_CLK] = &g12a_cpu_clk.hw,
5181 [CLKID_CPU_CLK_DIV16_EN] = &g12a_cpu_clk_div16_en.hw,
5182 [CLKID_CPU_CLK_DIV16] = &g12a_cpu_clk_div16.hw,
5183 [CLKID_CPU_CLK_APB_DIV] = &g12a_cpu_clk_apb_div.hw,
5184 [CLKID_CPU_CLK_APB] = &g12a_cpu_clk_apb.hw,
5185 [CLKID_CPU_CLK_ATB_DIV] = &g12a_cpu_clk_atb_div.hw,
5186 [CLKID_CPU_CLK_ATB] = &g12a_cpu_clk_atb.hw,
5187 [CLKID_CPU_CLK_AXI_DIV] = &g12a_cpu_clk_axi_div.hw,
5188 [CLKID_CPU_CLK_AXI] = &g12a_cpu_clk_axi.hw,
5189 [CLKID_CPU_CLK_TRACE_DIV] = &g12a_cpu_clk_trace_div.hw,
5190 [CLKID_CPU_CLK_TRACE] = &g12a_cpu_clk_trace.hw,
5191 [CLKID_PCIE_PLL_DCO] = &g12a_pcie_pll_dco.hw,
5192 [CLKID_PCIE_PLL_DCO_DIV2] = &g12a_pcie_pll_dco_div2.hw,
5193 [CLKID_PCIE_PLL_OD] = &g12a_pcie_pll_od.hw,
5194 [CLKID_PCIE_PLL] = &g12a_pcie_pll.hw,
5195 [CLKID_VDEC_1_SEL] = &g12a_vdec_1_sel.hw,
5196 [CLKID_VDEC_1_DIV] = &g12a_vdec_1_div.hw,
5197 [CLKID_VDEC_1] = &g12a_vdec_1.hw,
5198 [CLKID_VDEC_HEVC_SEL] = &g12a_vdec_hevc_sel.hw,
5199 [CLKID_VDEC_HEVC_DIV] = &g12a_vdec_hevc_div.hw,
5200 [CLKID_VDEC_HEVC] = &g12a_vdec_hevc.hw,
5201 [CLKID_VDEC_HEVCF_SEL] = &g12a_vdec_hevcf_sel.hw,
5202 [CLKID_VDEC_HEVCF_DIV] = &g12a_vdec_hevcf_div.hw,
5203 [CLKID_VDEC_HEVCF] = &g12a_vdec_hevcf.hw,
5204 [CLKID_TS_DIV] = &g12a_ts_div.hw,
5205 [CLKID_TS] = &g12a_ts.hw,
5206 [CLKID_GP1_PLL_DCO] = &sm1_gp1_pll_dco.hw,
5207 [CLKID_GP1_PLL] = &sm1_gp1_pll.hw,
5208 [CLKID_DSU_CLK_DYN0_SEL] = &sm1_dsu_clk_dyn0_sel.hw,
5209 [CLKID_DSU_CLK_DYN0_DIV] = &sm1_dsu_clk_dyn0_div.hw,
5210 [CLKID_DSU_CLK_DYN0] = &sm1_dsu_clk_dyn0.hw,
5211 [CLKID_DSU_CLK_DYN1_SEL] = &sm1_dsu_clk_dyn1_sel.hw,
5212 [CLKID_DSU_CLK_DYN1_DIV] = &sm1_dsu_clk_dyn1_div.hw,
5213 [CLKID_DSU_CLK_DYN1] = &sm1_dsu_clk_dyn1.hw,
5214 [CLKID_DSU_CLK_DYN] = &sm1_dsu_clk_dyn.hw,
5215 [CLKID_DSU_CLK_FINAL] = &sm1_dsu_final_clk.hw,
5216 [CLKID_DSU_CLK] = &sm1_dsu_clk.hw,
5217 [CLKID_CPU1_CLK] = &sm1_cpu1_clk.hw,
5218 [CLKID_CPU2_CLK] = &sm1_cpu2_clk.hw,
5219 [CLKID_CPU3_CLK] = &sm1_cpu3_clk.hw,
5220 [CLKID_SPICC0_SCLK_SEL] = &g12a_spicc0_sclk_sel.hw,
5221 [CLKID_SPICC0_SCLK_DIV] = &g12a_spicc0_sclk_div.hw,
5222 [CLKID_SPICC0_SCLK] = &g12a_spicc0_sclk.hw,
5223 [CLKID_SPICC1_SCLK_SEL] = &g12a_spicc1_sclk_sel.hw,
5224 [CLKID_SPICC1_SCLK_DIV] = &g12a_spicc1_sclk_div.hw,
5225 [CLKID_SPICC1_SCLK] = &g12a_spicc1_sclk.hw,
5226 [CLKID_NNA_AXI_CLK_SEL] = &sm1_nna_axi_clk_sel.hw,
5227 [CLKID_NNA_AXI_CLK_DIV] = &sm1_nna_axi_clk_div.hw,
5228 [CLKID_NNA_AXI_CLK] = &sm1_nna_axi_clk.hw,
5229 [CLKID_NNA_CORE_CLK_SEL] = &sm1_nna_core_clk_sel.hw,
5230 [CLKID_NNA_CORE_CLK_DIV] = &sm1_nna_core_clk_div.hw,
5231 [CLKID_NNA_CORE_CLK] = &sm1_nna_core_clk.hw,
5232 [CLKID_MIPI_DSI_PXCLK_SEL] = &g12a_mipi_dsi_pxclk_sel.hw,
5233 [CLKID_MIPI_DSI_PXCLK_DIV] = &g12a_mipi_dsi_pxclk_div.hw,
5234 [CLKID_MIPI_DSI_PXCLK] = &g12a_mipi_dsi_pxclk.hw,
5235};
5236
5237static const struct reg_sequence g12a_init_regs[] = {
5238 { .reg = HHI_MPLL_CNTL0, .def = 0x00000543 },
5239};
5240
5241#define DVFS_CON_ID "dvfs"
5242
5243static int g12a_dvfs_setup_common(struct device *dev, struct clk_hw **hws)
5244{
5245 struct clk *notifier_clk;
5246 struct clk_hw *xtal;
5247 int ret;
5248
5249 xtal = clk_hw_get_parent_by_index(hws[CLKID_CPU_CLK_DYN1_SEL], 0);
5250
5251 /* Setup clock notifier for cpu_clk_postmux0 */
5252 g12a_cpu_clk_dyn0_nb_data.xtal = xtal;
5253 notifier_clk = devm_clk_hw_get_clk(dev, &g12a_cpu_clk_dyn0.hw,
5254 DVFS_CON_ID);
5255 ret = devm_clk_notifier_register(dev, notifier_clk,
5256 &g12a_cpu_clk_dyn0_nb_data.nb);
5257 if (ret) {
5258 dev_err(dev, "failed to register the cpu_clk_dyn0 notifier\n");
5259 return ret;
5260 }
5261
5262 /* Setup clock notifier for cpu_clk_dyn mux */
5263 notifier_clk = devm_clk_hw_get_clk(dev, &g12a_cpu_clk_dyn.hw,
5264 DVFS_CON_ID);
5265 ret = devm_clk_notifier_register(dev, notifier_clk,
5266 &g12a_cpu_clk_mux_nb);
5267 if (ret) {
5268 dev_err(dev, "failed to register the cpu_clk_dyn notifier\n");
5269 return ret;
5270 }
5271
5272 return 0;
5273}
5274
5275static int g12b_dvfs_setup(struct platform_device *pdev)
5276{
5277 struct clk_hw **hws = g12b_hw_clks;
5278 struct device *dev = &pdev->dev;
5279 struct clk *notifier_clk;
5280 struct clk_hw *xtal;
5281 int ret;
5282
5283 ret = g12a_dvfs_setup_common(dev, hws);
5284 if (ret)
5285 return ret;
5286
5287 xtal = clk_hw_get_parent_by_index(hws[CLKID_CPU_CLK_DYN1_SEL], 0);
5288
5289 /* Setup clock notifier for cpu_clk mux */
5290 notifier_clk = devm_clk_hw_get_clk(dev, &g12b_cpu_clk.hw,
5291 DVFS_CON_ID);
5292 ret = devm_clk_notifier_register(dev, notifier_clk,
5293 &g12a_cpu_clk_mux_nb);
5294 if (ret) {
5295 dev_err(dev, "failed to register the cpu_clk notifier\n");
5296 return ret;
5297 }
5298
5299 /* Setup clock notifier for sys1_pll */
5300 notifier_clk = devm_clk_hw_get_clk(dev, &g12b_sys1_pll.hw,
5301 DVFS_CON_ID);
5302 ret = devm_clk_notifier_register(dev, notifier_clk,
5303 &g12b_cpu_clk_sys1_pll_nb_data.nb);
5304 if (ret) {
5305 dev_err(dev, "failed to register the sys1_pll notifier\n");
5306 return ret;
5307 }
5308
5309 /* Add notifiers for the second CPU cluster */
5310
5311 /* Setup clock notifier for cpub_clk_postmux0 */
5312 g12b_cpub_clk_dyn0_nb_data.xtal = xtal;
5313 notifier_clk = devm_clk_hw_get_clk(dev, &g12b_cpub_clk_dyn0.hw,
5314 DVFS_CON_ID);
5315 ret = devm_clk_notifier_register(dev, notifier_clk,
5316 &g12b_cpub_clk_dyn0_nb_data.nb);
5317 if (ret) {
5318 dev_err(dev, "failed to register the cpub_clk_dyn0 notifier\n");
5319 return ret;
5320 }
5321
5322 /* Setup clock notifier for cpub_clk_dyn mux */
5323 notifier_clk = devm_clk_hw_get_clk(dev, &g12b_cpub_clk_dyn.hw,
5324 DVFS_CON_ID);
5325 ret = devm_clk_notifier_register(dev, notifier_clk,
5326 &g12a_cpu_clk_mux_nb);
5327 if (ret) {
5328 dev_err(dev, "failed to register the cpub_clk_dyn notifier\n");
5329 return ret;
5330 }
5331
5332 /* Setup clock notifier for cpub_clk mux */
5333 notifier_clk = devm_clk_hw_get_clk(dev, &g12b_cpub_clk.hw, DVFS_CON_ID);
5334 ret = devm_clk_notifier_register(dev, notifier_clk,
5335 &g12a_cpu_clk_mux_nb);
5336 if (ret) {
5337 dev_err(dev, "failed to register the cpub_clk notifier\n");
5338 return ret;
5339 }
5340
5341 /* Setup clock notifier for sys_pll */
5342 notifier_clk = devm_clk_hw_get_clk(dev, &g12a_sys_pll.hw, DVFS_CON_ID);
5343 ret = devm_clk_notifier_register(dev, notifier_clk,
5344 &g12b_cpub_clk_sys_pll_nb_data.nb);
5345 if (ret) {
5346 dev_err(dev, "failed to register the sys_pll notifier\n");
5347 return ret;
5348 }
5349
5350 return 0;
5351}
5352
5353static int g12a_dvfs_setup(struct platform_device *pdev)
5354{
5355 struct clk_hw **hws = g12a_hw_clks;
5356 struct device *dev = &pdev->dev;
5357 struct clk *notifier_clk;
5358 int ret;
5359
5360 ret = g12a_dvfs_setup_common(dev, hws);
5361 if (ret)
5362 return ret;
5363
5364 /* Setup clock notifier for cpu_clk mux */
5365 notifier_clk = devm_clk_hw_get_clk(dev, &g12a_cpu_clk.hw, DVFS_CON_ID);
5366 ret = devm_clk_notifier_register(dev, notifier_clk,
5367 &g12a_cpu_clk_mux_nb);
5368 if (ret) {
5369 dev_err(dev, "failed to register the cpu_clk notifier\n");
5370 return ret;
5371 }
5372
5373 /* Setup clock notifier for sys_pll */
5374 notifier_clk = devm_clk_hw_get_clk(dev, &g12a_sys_pll.hw, DVFS_CON_ID);
5375 ret = devm_clk_notifier_register(dev, notifier_clk,
5376 &g12a_sys_pll_nb_data.nb);
5377 if (ret) {
5378 dev_err(dev, "failed to register the sys_pll notifier\n");
5379 return ret;
5380 }
5381
5382 return 0;
5383}
5384
5385struct g12a_clkc_data {
5386 const struct meson_clkc_data clkc_data;
5387 int (*dvfs_setup)(struct platform_device *pdev);
5388};
5389
5390static int g12a_clkc_probe(struct platform_device *pdev)
5391{
5392 const struct meson_clkc_data *clkc_data;
5393 const struct g12a_clkc_data *g12a_data;
5394 int ret;
5395
5396 clkc_data = of_device_get_match_data(&pdev->dev);
5397 if (!clkc_data)
5398 return -EINVAL;
5399
5400 ret = meson_clkc_syscon_probe(pdev);
5401 if (ret)
5402 return ret;
5403
5404 g12a_data = container_of(clkc_data, struct g12a_clkc_data,
5405 clkc_data);
5406
5407 if (g12a_data->dvfs_setup)
5408 return g12a_data->dvfs_setup(pdev);
5409
5410 return 0;
5411}
5412
5413static const struct g12a_clkc_data g12a_clkc_data = {
5414 .clkc_data = {
5415 .hw_clks = {
5416 .hws = g12a_hw_clks,
5417 .num = ARRAY_SIZE(g12a_hw_clks),
5418 },
5419 .init_regs = g12a_init_regs,
5420 .init_count = ARRAY_SIZE(g12a_init_regs),
5421 },
5422 .dvfs_setup = g12a_dvfs_setup,
5423};
5424
5425static const struct g12a_clkc_data g12b_clkc_data = {
5426 .clkc_data = {
5427 .hw_clks = {
5428 .hws = g12b_hw_clks,
5429 .num = ARRAY_SIZE(g12b_hw_clks),
5430 },
5431 },
5432 .dvfs_setup = g12b_dvfs_setup,
5433};
5434
5435static const struct g12a_clkc_data sm1_clkc_data = {
5436 .clkc_data = {
5437 .hw_clks = {
5438 .hws = sm1_hw_clks,
5439 .num = ARRAY_SIZE(sm1_hw_clks),
5440 },
5441 },
5442 .dvfs_setup = g12a_dvfs_setup,
5443};
5444
5445static const struct of_device_id g12a_clkc_match_table[] = {
5446 {
5447 .compatible = "amlogic,g12a-clkc",
5448 .data = &g12a_clkc_data.clkc_data
5449 },
5450 {
5451 .compatible = "amlogic,g12b-clkc",
5452 .data = &g12b_clkc_data.clkc_data
5453 },
5454 {
5455 .compatible = "amlogic,sm1-clkc",
5456 .data = &sm1_clkc_data.clkc_data
5457 },
5458 {}
5459};
5460MODULE_DEVICE_TABLE(of, g12a_clkc_match_table);
5461
5462static struct platform_driver g12a_clkc_driver = {
5463 .probe = g12a_clkc_probe,
5464 .driver = {
5465 .name = "g12a-clkc",
5466 .of_match_table = g12a_clkc_match_table,
5467 },
5468};
5469module_platform_driver(g12a_clkc_driver);
5470
5471MODULE_DESCRIPTION("Amlogic G12/SM1 Main Clock Controller driver");
5472MODULE_LICENSE("GPL");
5473MODULE_IMPORT_NS("CLK_MESON");