Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1// SPDX-License-Identifier: (GPL-2.0-only OR MIT)
2/*
3 * Amlogic S4 Peripherals Clock Controller Driver
4 *
5 * Copyright (c) 2022-2023 Amlogic, inc. All rights reserved
6 * Author: Yu Tu <yu.tu@amlogic.com>
7 */
8
9#include <linux/clk-provider.h>
10#include <linux/of_device.h>
11#include <linux/platform_device.h>
12
13#include "clk-regmap.h"
14#include "vid-pll-div.h"
15#include "clk-dualdiv.h"
16#include "meson-clkc-utils.h"
17#include <dt-bindings/clock/amlogic,s4-peripherals-clkc.h>
18
19#define CLKCTRL_RTC_BY_OSCIN_CTRL0 0x008
20#define CLKCTRL_RTC_BY_OSCIN_CTRL1 0x00c
21#define CLKCTRL_RTC_CTRL 0x010
22#define CLKCTRL_SYS_CLK_CTRL0 0x040
23#define CLKCTRL_SYS_CLK_EN0_REG0 0x044
24#define CLKCTRL_SYS_CLK_EN0_REG1 0x048
25#define CLKCTRL_SYS_CLK_EN0_REG2 0x04c
26#define CLKCTRL_SYS_CLK_EN0_REG3 0x050
27#define CLKCTRL_CECA_CTRL0 0x088
28#define CLKCTRL_CECA_CTRL1 0x08c
29#define CLKCTRL_CECB_CTRL0 0x090
30#define CLKCTRL_CECB_CTRL1 0x094
31#define CLKCTRL_SC_CLK_CTRL 0x098
32#define CLKCTRL_CLK12_24_CTRL 0x0a8
33#define CLKCTRL_VID_CLK_CTRL 0x0c0
34#define CLKCTRL_VID_CLK_CTRL2 0x0c4
35#define CLKCTRL_VID_CLK_DIV 0x0c8
36#define CLKCTRL_VIID_CLK_DIV 0x0cc
37#define CLKCTRL_VIID_CLK_CTRL 0x0d0
38#define CLKCTRL_HDMI_CLK_CTRL 0x0e0
39#define CLKCTRL_VID_PLL_CLK_DIV 0x0e4
40#define CLKCTRL_VPU_CLK_CTRL 0x0e8
41#define CLKCTRL_VPU_CLKB_CTRL 0x0ec
42#define CLKCTRL_VPU_CLKC_CTRL 0x0f0
43#define CLKCTRL_VID_LOCK_CLK_CTRL 0x0f4
44#define CLKCTRL_VDIN_MEAS_CLK_CTRL 0x0f8
45#define CLKCTRL_VAPBCLK_CTRL 0x0fc
46#define CLKCTRL_HDCP22_CTRL 0x100
47#define CLKCTRL_CDAC_CLK_CTRL 0x108
48#define CLKCTRL_VDEC_CLK_CTRL 0x140
49#define CLKCTRL_VDEC2_CLK_CTRL 0x144
50#define CLKCTRL_VDEC3_CLK_CTRL 0x148
51#define CLKCTRL_VDEC4_CLK_CTRL 0x14c
52#define CLKCTRL_TS_CLK_CTRL 0x158
53#define CLKCTRL_MALI_CLK_CTRL 0x15c
54#define CLKCTRL_NAND_CLK_CTRL 0x168
55#define CLKCTRL_SD_EMMC_CLK_CTRL 0x16c
56#define CLKCTRL_SPICC_CLK_CTRL 0x174
57#define CLKCTRL_GEN_CLK_CTRL 0x178
58#define CLKCTRL_SAR_CLK_CTRL 0x17c
59#define CLKCTRL_PWM_CLK_AB_CTRL 0x180
60#define CLKCTRL_PWM_CLK_CD_CTRL 0x184
61#define CLKCTRL_PWM_CLK_EF_CTRL 0x188
62#define CLKCTRL_PWM_CLK_GH_CTRL 0x18c
63#define CLKCTRL_PWM_CLK_IJ_CTRL 0x190
64#define CLKCTRL_DEMOD_CLK_CTRL 0x200
65
66#define S4_COMP_SEL(_name, _reg, _shift, _mask, _pdata) \
67 MESON_COMP_SEL(s4_, _name, _reg, _shift, _mask, _pdata, NULL, 0, 0)
68
69#define S4_COMP_DIV(_name, _reg, _shift, _width) \
70 MESON_COMP_DIV(s4_, _name, _reg, _shift, _width, 0, CLK_SET_RATE_PARENT)
71
72#define S4_COMP_GATE(_name, _reg, _bit) \
73 MESON_COMP_GATE(s4_, _name, _reg, _bit, CLK_SET_RATE_PARENT)
74
75static struct clk_regmap s4_rtc_32k_by_oscin_clkin = {
76 .data = &(struct clk_regmap_gate_data){
77 .offset = CLKCTRL_RTC_BY_OSCIN_CTRL0,
78 .bit_idx = 31,
79 },
80 .hw.init = &(struct clk_init_data) {
81 .name = "rtc_32k_by_oscin_clkin",
82 .ops = &clk_regmap_gate_ops,
83 .parent_data = (const struct clk_parent_data []) {
84 { .fw_name = "xtal", }
85 },
86 .num_parents = 1,
87 },
88};
89
90static const struct meson_clk_dualdiv_param s4_32k_div_table[] = {
91 {
92 .dual = 1,
93 .n1 = 733,
94 .m1 = 8,
95 .n2 = 732,
96 .m2 = 11,
97 },
98 {}
99};
100
101static struct clk_regmap s4_rtc_32k_by_oscin_div = {
102 .data = &(struct meson_clk_dualdiv_data){
103 .n1 = {
104 .reg_off = CLKCTRL_RTC_BY_OSCIN_CTRL0,
105 .shift = 0,
106 .width = 12,
107 },
108 .n2 = {
109 .reg_off = CLKCTRL_RTC_BY_OSCIN_CTRL0,
110 .shift = 12,
111 .width = 12,
112 },
113 .m1 = {
114 .reg_off = CLKCTRL_RTC_BY_OSCIN_CTRL1,
115 .shift = 0,
116 .width = 12,
117 },
118 .m2 = {
119 .reg_off = CLKCTRL_RTC_BY_OSCIN_CTRL1,
120 .shift = 12,
121 .width = 12,
122 },
123 .dual = {
124 .reg_off = CLKCTRL_RTC_BY_OSCIN_CTRL0,
125 .shift = 28,
126 .width = 1,
127 },
128 .table = s4_32k_div_table,
129 },
130 .hw.init = &(struct clk_init_data){
131 .name = "rtc_32k_by_oscin_div",
132 .ops = &meson_clk_dualdiv_ops,
133 .parent_hws = (const struct clk_hw *[]) {
134 &s4_rtc_32k_by_oscin_clkin.hw
135 },
136 .num_parents = 1,
137 },
138};
139
140static struct clk_regmap s4_rtc_32k_by_oscin_sel = {
141 .data = &(struct clk_regmap_mux_data) {
142 .offset = CLKCTRL_RTC_BY_OSCIN_CTRL1,
143 .mask = 0x1,
144 .shift = 24,
145 .flags = CLK_MUX_ROUND_CLOSEST,
146 },
147 .hw.init = &(struct clk_init_data){
148 .name = "rtc_32k_by_oscin_sel",
149 .ops = &clk_regmap_mux_ops,
150 .parent_hws = (const struct clk_hw *[]) {
151 &s4_rtc_32k_by_oscin_div.hw,
152 &s4_rtc_32k_by_oscin_clkin.hw,
153 },
154 .num_parents = 2,
155 .flags = CLK_SET_RATE_PARENT,
156 },
157};
158
159static struct clk_regmap s4_rtc_32k_by_oscin = {
160 .data = &(struct clk_regmap_gate_data){
161 .offset = CLKCTRL_RTC_BY_OSCIN_CTRL0,
162 .bit_idx = 30,
163 },
164 .hw.init = &(struct clk_init_data) {
165 .name = "rtc_32k_by_oscin",
166 .ops = &clk_regmap_gate_ops,
167 .parent_hws = (const struct clk_hw *[]) {
168 &s4_rtc_32k_by_oscin_sel.hw
169 },
170 .num_parents = 1,
171 .flags = CLK_SET_RATE_PARENT,
172 },
173};
174
175static struct clk_regmap s4_rtc_clk = {
176 .data = &(struct clk_regmap_mux_data) {
177 .offset = CLKCTRL_RTC_CTRL,
178 .mask = 0x3,
179 .shift = 0,
180 .flags = CLK_MUX_ROUND_CLOSEST,
181 },
182 .hw.init = &(struct clk_init_data){
183 .name = "rtc_clk_sel",
184 .ops = &clk_regmap_mux_ops,
185 .parent_hws = (const struct clk_hw *[]) {
186 &s4_rtc_32k_by_oscin.hw,
187 &s4_rtc_32k_by_oscin_div.hw,
188 },
189 .num_parents = 2,
190 .flags = CLK_SET_RATE_PARENT,
191 },
192};
193
194/* The index 5 is AXI_CLK, which is dedicated to AXI. So skip it. */
195static u32 s4_sysclk_parents_val_table[] = { 0, 1, 2, 3, 4, 6, 7 };
196static const struct clk_parent_data s4_sysclk_parents[] = {
197 { .fw_name = "xtal" },
198 { .fw_name = "fclk_div2" },
199 { .fw_name = "fclk_div3" },
200 { .fw_name = "fclk_div4" },
201 { .fw_name = "fclk_div5" },
202 { .fw_name = "fclk_div7" },
203 { .hw = &s4_rtc_clk.hw }
204};
205
206/*
207 * This clock is initialized by ROMcode.
208 * The chip was changed SYS CLK for security reasons. SYS CLK registers are not writable
209 * in the kernel phase. Write of SYS related register will cause the system to crash.
210 * Meanwhile, these clock won't ever change at runtime.
211 * For the above reasons, we can only use ro_ops for SYS related clocks.
212 */
213static struct clk_regmap s4_sysclk_b_sel = {
214 .data = &(struct clk_regmap_mux_data){
215 .offset = CLKCTRL_SYS_CLK_CTRL0,
216 .mask = 0x7,
217 .shift = 26,
218 .table = s4_sysclk_parents_val_table,
219 },
220 .hw.init = &(struct clk_init_data){
221 .name = "sysclk_b_sel",
222 .ops = &clk_regmap_mux_ro_ops,
223 .parent_data = s4_sysclk_parents,
224 .num_parents = ARRAY_SIZE(s4_sysclk_parents),
225 },
226};
227
228static struct clk_regmap s4_sysclk_b_div = {
229 .data = &(struct clk_regmap_div_data){
230 .offset = CLKCTRL_SYS_CLK_CTRL0,
231 .shift = 16,
232 .width = 10,
233 },
234 .hw.init = &(struct clk_init_data){
235 .name = "sysclk_b_div",
236 .ops = &clk_regmap_divider_ro_ops,
237 .parent_hws = (const struct clk_hw *[]) {
238 &s4_sysclk_b_sel.hw
239 },
240 .num_parents = 1,
241 },
242};
243
244static struct clk_regmap s4_sysclk_b = {
245 .data = &(struct clk_regmap_gate_data){
246 .offset = CLKCTRL_SYS_CLK_CTRL0,
247 .bit_idx = 29,
248 },
249 .hw.init = &(struct clk_init_data) {
250 .name = "sysclk_b",
251 .ops = &clk_regmap_gate_ro_ops,
252 .parent_hws = (const struct clk_hw *[]) {
253 &s4_sysclk_b_div.hw
254 },
255 .num_parents = 1,
256 },
257};
258
259static struct clk_regmap s4_sysclk_a_sel = {
260 .data = &(struct clk_regmap_mux_data){
261 .offset = CLKCTRL_SYS_CLK_CTRL0,
262 .mask = 0x7,
263 .shift = 10,
264 .table = s4_sysclk_parents_val_table,
265 },
266 .hw.init = &(struct clk_init_data){
267 .name = "sysclk_a_sel",
268 .ops = &clk_regmap_mux_ro_ops,
269 .parent_data = s4_sysclk_parents,
270 .num_parents = ARRAY_SIZE(s4_sysclk_parents),
271 },
272};
273
274static struct clk_regmap s4_sysclk_a_div = {
275 .data = &(struct clk_regmap_div_data){
276 .offset = CLKCTRL_SYS_CLK_CTRL0,
277 .shift = 0,
278 .width = 10,
279 },
280 .hw.init = &(struct clk_init_data){
281 .name = "sysclk_a_div",
282 .ops = &clk_regmap_divider_ro_ops,
283 .parent_hws = (const struct clk_hw *[]) {
284 &s4_sysclk_a_sel.hw
285 },
286 .num_parents = 1,
287 },
288};
289
290static struct clk_regmap s4_sysclk_a = {
291 .data = &(struct clk_regmap_gate_data){
292 .offset = CLKCTRL_SYS_CLK_CTRL0,
293 .bit_idx = 13,
294 },
295 .hw.init = &(struct clk_init_data) {
296 .name = "sysclk_a",
297 .ops = &clk_regmap_gate_ro_ops,
298 .parent_hws = (const struct clk_hw *[]) {
299 &s4_sysclk_a_div.hw
300 },
301 .num_parents = 1,
302 },
303};
304
305static struct clk_regmap s4_sys_clk = {
306 .data = &(struct clk_regmap_mux_data){
307 .offset = CLKCTRL_SYS_CLK_CTRL0,
308 .mask = 0x1,
309 .shift = 31,
310 },
311 .hw.init = &(struct clk_init_data){
312 .name = "sys_clk",
313 .ops = &clk_regmap_mux_ro_ops,
314 .parent_hws = (const struct clk_hw *[]) {
315 &s4_sysclk_a.hw,
316 &s4_sysclk_b.hw
317 },
318 .num_parents = 2,
319 },
320};
321
322static struct clk_regmap s4_ceca_32k_clkin = {
323 .data = &(struct clk_regmap_gate_data){
324 .offset = CLKCTRL_CECA_CTRL0,
325 .bit_idx = 31,
326 },
327 .hw.init = &(struct clk_init_data) {
328 .name = "ceca_32k_clkin",
329 .ops = &clk_regmap_gate_ops,
330 .parent_data = (const struct clk_parent_data []) {
331 { .fw_name = "xtal", }
332 },
333 .num_parents = 1,
334 },
335};
336
337static struct clk_regmap s4_ceca_32k_div = {
338 .data = &(struct meson_clk_dualdiv_data){
339 .n1 = {
340 .reg_off = CLKCTRL_CECA_CTRL0,
341 .shift = 0,
342 .width = 12,
343 },
344 .n2 = {
345 .reg_off = CLKCTRL_CECA_CTRL0,
346 .shift = 12,
347 .width = 12,
348 },
349 .m1 = {
350 .reg_off = CLKCTRL_CECA_CTRL1,
351 .shift = 0,
352 .width = 12,
353 },
354 .m2 = {
355 .reg_off = CLKCTRL_CECA_CTRL1,
356 .shift = 12,
357 .width = 12,
358 },
359 .dual = {
360 .reg_off = CLKCTRL_CECA_CTRL0,
361 .shift = 28,
362 .width = 1,
363 },
364 .table = s4_32k_div_table,
365 },
366 .hw.init = &(struct clk_init_data){
367 .name = "ceca_32k_div",
368 .ops = &meson_clk_dualdiv_ops,
369 .parent_hws = (const struct clk_hw *[]) {
370 &s4_ceca_32k_clkin.hw
371 },
372 .num_parents = 1,
373 },
374};
375
376static struct clk_regmap s4_ceca_32k_sel_pre = {
377 .data = &(struct clk_regmap_mux_data) {
378 .offset = CLKCTRL_CECA_CTRL1,
379 .mask = 0x1,
380 .shift = 24,
381 .flags = CLK_MUX_ROUND_CLOSEST,
382 },
383 .hw.init = &(struct clk_init_data){
384 .name = "ceca_32k_sel_pre",
385 .ops = &clk_regmap_mux_ops,
386 .parent_hws = (const struct clk_hw *[]) {
387 &s4_ceca_32k_div.hw,
388 &s4_ceca_32k_clkin.hw
389 },
390 .num_parents = 2,
391 .flags = CLK_SET_RATE_PARENT,
392 },
393};
394
395static struct clk_regmap s4_ceca_32k_sel = {
396 .data = &(struct clk_regmap_mux_data) {
397 .offset = CLKCTRL_CECA_CTRL1,
398 .mask = 0x1,
399 .shift = 31,
400 .flags = CLK_MUX_ROUND_CLOSEST,
401 },
402 .hw.init = &(struct clk_init_data){
403 .name = "ceca_32k_sel",
404 .ops = &clk_regmap_mux_ops,
405 .parent_hws = (const struct clk_hw *[]) {
406 &s4_ceca_32k_sel_pre.hw,
407 &s4_rtc_clk.hw
408 },
409 .num_parents = 2,
410 },
411};
412
413static struct clk_regmap s4_ceca_32k_clkout = {
414 .data = &(struct clk_regmap_gate_data){
415 .offset = CLKCTRL_CECA_CTRL0,
416 .bit_idx = 30,
417 },
418 .hw.init = &(struct clk_init_data){
419 .name = "ceca_32k_clkout",
420 .ops = &clk_regmap_gate_ops,
421 .parent_hws = (const struct clk_hw *[]) {
422 &s4_ceca_32k_sel.hw
423 },
424 .num_parents = 1,
425 .flags = CLK_SET_RATE_PARENT,
426 },
427};
428
429static struct clk_regmap s4_cecb_32k_clkin = {
430 .data = &(struct clk_regmap_gate_data){
431 .offset = CLKCTRL_CECB_CTRL0,
432 .bit_idx = 31,
433 },
434 .hw.init = &(struct clk_init_data) {
435 .name = "cecb_32k_clkin",
436 .ops = &clk_regmap_gate_ops,
437 .parent_data = (const struct clk_parent_data []) {
438 { .fw_name = "xtal", }
439 },
440 .num_parents = 1,
441 },
442};
443
444static struct clk_regmap s4_cecb_32k_div = {
445 .data = &(struct meson_clk_dualdiv_data){
446 .n1 = {
447 .reg_off = CLKCTRL_CECB_CTRL0,
448 .shift = 0,
449 .width = 12,
450 },
451 .n2 = {
452 .reg_off = CLKCTRL_CECB_CTRL0,
453 .shift = 12,
454 .width = 12,
455 },
456 .m1 = {
457 .reg_off = CLKCTRL_CECB_CTRL1,
458 .shift = 0,
459 .width = 12,
460 },
461 .m2 = {
462 .reg_off = CLKCTRL_CECB_CTRL1,
463 .shift = 12,
464 .width = 12,
465 },
466 .dual = {
467 .reg_off = CLKCTRL_CECB_CTRL0,
468 .shift = 28,
469 .width = 1,
470 },
471 .table = s4_32k_div_table,
472 },
473 .hw.init = &(struct clk_init_data){
474 .name = "cecb_32k_div",
475 .ops = &meson_clk_dualdiv_ops,
476 .parent_hws = (const struct clk_hw *[]) {
477 &s4_cecb_32k_clkin.hw
478 },
479 .num_parents = 1,
480 },
481};
482
483static struct clk_regmap s4_cecb_32k_sel_pre = {
484 .data = &(struct clk_regmap_mux_data) {
485 .offset = CLKCTRL_CECB_CTRL1,
486 .mask = 0x1,
487 .shift = 24,
488 .flags = CLK_MUX_ROUND_CLOSEST,
489 },
490 .hw.init = &(struct clk_init_data){
491 .name = "cecb_32k_sel_pre",
492 .ops = &clk_regmap_mux_ops,
493 .parent_hws = (const struct clk_hw *[]) {
494 &s4_cecb_32k_div.hw,
495 &s4_cecb_32k_clkin.hw
496 },
497 .num_parents = 2,
498 .flags = CLK_SET_RATE_PARENT,
499 },
500};
501
502static struct clk_regmap s4_cecb_32k_sel = {
503 .data = &(struct clk_regmap_mux_data) {
504 .offset = CLKCTRL_CECB_CTRL1,
505 .mask = 0x1,
506 .shift = 31,
507 .flags = CLK_MUX_ROUND_CLOSEST,
508 },
509 .hw.init = &(struct clk_init_data){
510 .name = "cecb_32k_sel",
511 .ops = &clk_regmap_mux_ops,
512 .parent_hws = (const struct clk_hw *[]) {
513 &s4_cecb_32k_sel_pre.hw,
514 &s4_rtc_clk.hw
515 },
516 .num_parents = 2,
517 },
518};
519
520static struct clk_regmap s4_cecb_32k_clkout = {
521 .data = &(struct clk_regmap_gate_data){
522 .offset = CLKCTRL_CECB_CTRL0,
523 .bit_idx = 30,
524 },
525 .hw.init = &(struct clk_init_data){
526 .name = "cecb_32k_clkout",
527 .ops = &clk_regmap_gate_ops,
528 .parent_hws = (const struct clk_hw *[]) {
529 &s4_cecb_32k_sel.hw
530 },
531 .num_parents = 1,
532 .flags = CLK_SET_RATE_PARENT,
533 },
534};
535
536static const struct clk_parent_data s4_sc_clk_parents[] = {
537 { .fw_name = "fclk_div4" },
538 { .fw_name = "fclk_div3" },
539 { .fw_name = "fclk_div5" },
540 { .fw_name = "xtal", }
541};
542
543static struct clk_regmap s4_sc_clk_sel = {
544 .data = &(struct clk_regmap_mux_data){
545 .offset = CLKCTRL_SC_CLK_CTRL,
546 .mask = 0x3,
547 .shift = 9,
548 },
549 .hw.init = &(struct clk_init_data) {
550 .name = "sc_clk_sel",
551 .ops = &clk_regmap_mux_ops,
552 .parent_data = s4_sc_clk_parents,
553 .num_parents = ARRAY_SIZE(s4_sc_clk_parents),
554 .flags = CLK_SET_RATE_PARENT,
555 },
556};
557
558static struct clk_regmap s4_sc_clk_div = {
559 .data = &(struct clk_regmap_div_data){
560 .offset = CLKCTRL_SC_CLK_CTRL,
561 .shift = 0,
562 .width = 8,
563 },
564 .hw.init = &(struct clk_init_data) {
565 .name = "sc_clk_div",
566 .ops = &clk_regmap_divider_ops,
567 .parent_hws = (const struct clk_hw *[]) {
568 &s4_sc_clk_sel.hw
569 },
570 .num_parents = 1,
571 .flags = CLK_SET_RATE_PARENT,
572 },
573};
574
575static struct clk_regmap s4_sc_clk = {
576 .data = &(struct clk_regmap_gate_data){
577 .offset = CLKCTRL_SC_CLK_CTRL,
578 .bit_idx = 8,
579 },
580 .hw.init = &(struct clk_init_data){
581 .name = "sc_clk",
582 .ops = &clk_regmap_gate_ops,
583 .parent_hws = (const struct clk_hw *[]) {
584 &s4_sc_clk_div.hw
585 },
586 .num_parents = 1,
587 .flags = CLK_SET_RATE_PARENT,
588 },
589};
590
591static struct clk_regmap s4_12_24M = {
592 .data = &(struct clk_regmap_gate_data){
593 .offset = CLKCTRL_CLK12_24_CTRL,
594 .bit_idx = 11,
595 },
596 .hw.init = &(struct clk_init_data) {
597 .name = "12_24M",
598 .ops = &clk_regmap_gate_ops,
599 .parent_data = (const struct clk_parent_data []) {
600 { .fw_name = "xtal", }
601 },
602 .num_parents = 1,
603 },
604};
605
606static struct clk_fixed_factor s4_12M_div = {
607 .mult = 1,
608 .div = 2,
609 .hw.init = &(struct clk_init_data){
610 .name = "12M_div",
611 .ops = &clk_fixed_factor_ops,
612 .parent_hws = (const struct clk_hw *[]) {
613 &s4_12_24M.hw
614 },
615 .num_parents = 1,
616 .flags = CLK_SET_RATE_PARENT,
617 },
618};
619
620static struct clk_regmap s4_12_24M_sel = {
621 .data = &(struct clk_regmap_mux_data){
622 .offset = CLKCTRL_CLK12_24_CTRL,
623 .mask = 0x1,
624 .shift = 10,
625 },
626 .hw.init = &(struct clk_init_data) {
627 .name = "12_24M_sel",
628 .ops = &clk_regmap_mux_ops,
629 .parent_hws = (const struct clk_hw *[]) {
630 &s4_12_24M.hw,
631 &s4_12M_div.hw,
632 },
633 .num_parents = 2,
634 .flags = CLK_SET_RATE_PARENT,
635 },
636};
637
638/* Video Clocks */
639static struct clk_regmap s4_vid_pll_div = {
640 .data = &(struct meson_vid_pll_div_data){
641 .val = {
642 .reg_off = CLKCTRL_VID_PLL_CLK_DIV,
643 .shift = 0,
644 .width = 15,
645 },
646 .sel = {
647 .reg_off = CLKCTRL_VID_PLL_CLK_DIV,
648 .shift = 16,
649 .width = 2,
650 },
651 },
652 .hw.init = &(struct clk_init_data) {
653 .name = "vid_pll_div",
654 /*
655 * TODO meson_vid_pll_div_ro_ops to meson_vid_pll_div_ops
656 */
657 .ops = &meson_vid_pll_div_ro_ops,
658 .parent_data = (const struct clk_parent_data []) {
659 { .fw_name = "hdmi_pll", }
660 },
661 .num_parents = 1,
662 .flags = CLK_SET_RATE_PARENT,
663 },
664};
665
666static struct clk_regmap s4_vid_pll_sel = {
667 .data = &(struct clk_regmap_mux_data){
668 .offset = CLKCTRL_VID_PLL_CLK_DIV,
669 .mask = 0x1,
670 .shift = 18,
671 },
672 .hw.init = &(struct clk_init_data){
673 .name = "vid_pll_sel",
674 .ops = &clk_regmap_mux_ops,
675 .parent_data = (const struct clk_parent_data []) {
676 { .hw = &s4_vid_pll_div.hw },
677 { .fw_name = "hdmi_pll", }
678 },
679 .num_parents = 2,
680 .flags = CLK_SET_RATE_PARENT,
681 },
682};
683
684static struct clk_regmap s4_vid_pll = {
685 .data = &(struct clk_regmap_gate_data){
686 .offset = CLKCTRL_VID_PLL_CLK_DIV,
687 .bit_idx = 19,
688 },
689 .hw.init = &(struct clk_init_data) {
690 .name = "vid_pll",
691 .ops = &clk_regmap_gate_ops,
692 .parent_hws = (const struct clk_hw *[]) {
693 &s4_vid_pll_sel.hw
694 },
695 .num_parents = 1,
696 .flags = CLK_SET_RATE_PARENT,
697 },
698};
699
700static const struct clk_parent_data s4_vclk_parents[] = {
701 { .hw = &s4_vid_pll.hw },
702 { .fw_name = "gp0_pll", },
703 { .fw_name = "hifi_pll", },
704 { .fw_name = "mpll1", },
705 { .fw_name = "fclk_div3", },
706 { .fw_name = "fclk_div4", },
707 { .fw_name = "fclk_div5", },
708 { .fw_name = "fclk_div7", },
709};
710
711static struct clk_regmap s4_vclk_sel = {
712 .data = &(struct clk_regmap_mux_data){
713 .offset = CLKCTRL_VID_CLK_CTRL,
714 .mask = 0x7,
715 .shift = 16,
716 },
717 .hw.init = &(struct clk_init_data){
718 .name = "vclk_sel",
719 .ops = &clk_regmap_mux_ops,
720 .parent_data = s4_vclk_parents,
721 .num_parents = ARRAY_SIZE(s4_vclk_parents),
722 .flags = 0,
723 },
724};
725
726static struct clk_regmap s4_vclk2_sel = {
727 .data = &(struct clk_regmap_mux_data){
728 .offset = CLKCTRL_VIID_CLK_CTRL,
729 .mask = 0x7,
730 .shift = 16,
731 },
732 .hw.init = &(struct clk_init_data){
733 .name = "vclk2_sel",
734 .ops = &clk_regmap_mux_ops,
735 .parent_data = s4_vclk_parents,
736 .num_parents = ARRAY_SIZE(s4_vclk_parents),
737 .flags = 0,
738 },
739};
740
741static struct clk_regmap s4_vclk_input = {
742 .data = &(struct clk_regmap_gate_data){
743 .offset = CLKCTRL_VID_CLK_DIV,
744 .bit_idx = 16,
745 },
746 .hw.init = &(struct clk_init_data) {
747 .name = "vclk_input",
748 .ops = &clk_regmap_gate_ops,
749 .parent_hws = (const struct clk_hw *[]) { &s4_vclk_sel.hw },
750 .num_parents = 1,
751 .flags = CLK_SET_RATE_PARENT,
752 },
753};
754
755static struct clk_regmap s4_vclk2_input = {
756 .data = &(struct clk_regmap_gate_data){
757 .offset = CLKCTRL_VIID_CLK_DIV,
758 .bit_idx = 16,
759 },
760 .hw.init = &(struct clk_init_data) {
761 .name = "vclk2_input",
762 .ops = &clk_regmap_gate_ops,
763 .parent_hws = (const struct clk_hw *[]) { &s4_vclk2_sel.hw },
764 .num_parents = 1,
765 .flags = CLK_SET_RATE_PARENT,
766 },
767};
768
769static struct clk_regmap s4_vclk_div = {
770 .data = &(struct clk_regmap_div_data){
771 .offset = CLKCTRL_VID_CLK_DIV,
772 .shift = 0,
773 .width = 8,
774 },
775 .hw.init = &(struct clk_init_data){
776 .name = "vclk_div",
777 .ops = &clk_regmap_divider_ops,
778 .parent_hws = (const struct clk_hw *[]) {
779 &s4_vclk_input.hw
780 },
781 .num_parents = 1,
782 .flags = CLK_SET_RATE_PARENT,
783 },
784};
785
786static struct clk_regmap s4_vclk2_div = {
787 .data = &(struct clk_regmap_div_data){
788 .offset = CLKCTRL_VIID_CLK_DIV,
789 .shift = 0,
790 .width = 8,
791 },
792 .hw.init = &(struct clk_init_data){
793 .name = "vclk2_div",
794 .ops = &clk_regmap_divider_ops,
795 .parent_hws = (const struct clk_hw *[]) {
796 &s4_vclk2_input.hw
797 },
798 .num_parents = 1,
799 .flags = CLK_SET_RATE_PARENT,
800 },
801};
802
803static struct clk_regmap s4_vclk = {
804 .data = &(struct clk_regmap_gate_data){
805 .offset = CLKCTRL_VID_CLK_CTRL,
806 .bit_idx = 19,
807 },
808 .hw.init = &(struct clk_init_data) {
809 .name = "vclk",
810 .ops = &clk_regmap_gate_ops,
811 .parent_hws = (const struct clk_hw *[]) { &s4_vclk_div.hw },
812 .num_parents = 1,
813 .flags = CLK_SET_RATE_PARENT,
814 },
815};
816
817static struct clk_regmap s4_vclk2 = {
818 .data = &(struct clk_regmap_gate_data){
819 .offset = CLKCTRL_VIID_CLK_CTRL,
820 .bit_idx = 19,
821 },
822 .hw.init = &(struct clk_init_data) {
823 .name = "vclk2",
824 .ops = &clk_regmap_gate_ops,
825 .parent_hws = (const struct clk_hw *[]) { &s4_vclk2_div.hw },
826 .num_parents = 1,
827 .flags = CLK_SET_RATE_PARENT,
828 },
829};
830
831static struct clk_regmap s4_vclk_div1 = {
832 .data = &(struct clk_regmap_gate_data){
833 .offset = CLKCTRL_VID_CLK_CTRL,
834 .bit_idx = 0,
835 },
836 .hw.init = &(struct clk_init_data) {
837 .name = "vclk_div1",
838 .ops = &clk_regmap_gate_ops,
839 .parent_hws = (const struct clk_hw *[]) { &s4_vclk.hw },
840 .num_parents = 1,
841 .flags = CLK_SET_RATE_PARENT,
842 },
843};
844
845static struct clk_regmap s4_vclk_div2_en = {
846 .data = &(struct clk_regmap_gate_data){
847 .offset = CLKCTRL_VID_CLK_CTRL,
848 .bit_idx = 1,
849 },
850 .hw.init = &(struct clk_init_data) {
851 .name = "vclk_div2_en",
852 .ops = &clk_regmap_gate_ops,
853 .parent_hws = (const struct clk_hw *[]) { &s4_vclk.hw },
854 .num_parents = 1,
855 .flags = CLK_SET_RATE_PARENT,
856 },
857};
858
859static struct clk_regmap s4_vclk_div4_en = {
860 .data = &(struct clk_regmap_gate_data){
861 .offset = CLKCTRL_VID_CLK_CTRL,
862 .bit_idx = 2,
863 },
864 .hw.init = &(struct clk_init_data) {
865 .name = "vclk_div4_en",
866 .ops = &clk_regmap_gate_ops,
867 .parent_hws = (const struct clk_hw *[]) { &s4_vclk.hw },
868 .num_parents = 1,
869 .flags = CLK_SET_RATE_PARENT,
870 },
871};
872
873static struct clk_regmap s4_vclk_div6_en = {
874 .data = &(struct clk_regmap_gate_data){
875 .offset = CLKCTRL_VID_CLK_CTRL,
876 .bit_idx = 3,
877 },
878 .hw.init = &(struct clk_init_data) {
879 .name = "vclk_div6_en",
880 .ops = &clk_regmap_gate_ops,
881 .parent_hws = (const struct clk_hw *[]) { &s4_vclk.hw },
882 .num_parents = 1,
883 .flags = CLK_SET_RATE_PARENT,
884 },
885};
886
887static struct clk_regmap s4_vclk_div12_en = {
888 .data = &(struct clk_regmap_gate_data){
889 .offset = CLKCTRL_VID_CLK_CTRL,
890 .bit_idx = 4,
891 },
892 .hw.init = &(struct clk_init_data) {
893 .name = "vclk_div12_en",
894 .ops = &clk_regmap_gate_ops,
895 .parent_hws = (const struct clk_hw *[]) { &s4_vclk.hw },
896 .num_parents = 1,
897 .flags = CLK_SET_RATE_PARENT,
898 },
899};
900
901static struct clk_regmap s4_vclk2_div1 = {
902 .data = &(struct clk_regmap_gate_data){
903 .offset = CLKCTRL_VIID_CLK_CTRL,
904 .bit_idx = 0,
905 },
906 .hw.init = &(struct clk_init_data) {
907 .name = "vclk2_div1",
908 .ops = &clk_regmap_gate_ops,
909 .parent_hws = (const struct clk_hw *[]) { &s4_vclk2.hw },
910 .num_parents = 1,
911 .flags = CLK_SET_RATE_PARENT,
912 },
913};
914
915static struct clk_regmap s4_vclk2_div2_en = {
916 .data = &(struct clk_regmap_gate_data){
917 .offset = CLKCTRL_VIID_CLK_CTRL,
918 .bit_idx = 1,
919 },
920 .hw.init = &(struct clk_init_data) {
921 .name = "vclk2_div2_en",
922 .ops = &clk_regmap_gate_ops,
923 .parent_hws = (const struct clk_hw *[]) { &s4_vclk2.hw },
924 .num_parents = 1,
925 .flags = CLK_SET_RATE_PARENT,
926 },
927};
928
929static struct clk_regmap s4_vclk2_div4_en = {
930 .data = &(struct clk_regmap_gate_data){
931 .offset = CLKCTRL_VIID_CLK_CTRL,
932 .bit_idx = 2,
933 },
934 .hw.init = &(struct clk_init_data) {
935 .name = "vclk2_div4_en",
936 .ops = &clk_regmap_gate_ops,
937 .parent_hws = (const struct clk_hw *[]) { &s4_vclk2.hw },
938 .num_parents = 1,
939 .flags = CLK_SET_RATE_PARENT,
940 },
941};
942
943static struct clk_regmap s4_vclk2_div6_en = {
944 .data = &(struct clk_regmap_gate_data){
945 .offset = CLKCTRL_VIID_CLK_CTRL,
946 .bit_idx = 3,
947 },
948 .hw.init = &(struct clk_init_data) {
949 .name = "vclk2_div6_en",
950 .ops = &clk_regmap_gate_ops,
951 .parent_hws = (const struct clk_hw *[]) { &s4_vclk2.hw },
952 .num_parents = 1,
953 .flags = CLK_SET_RATE_PARENT,
954 },
955};
956
957static struct clk_regmap s4_vclk2_div12_en = {
958 .data = &(struct clk_regmap_gate_data){
959 .offset = CLKCTRL_VIID_CLK_CTRL,
960 .bit_idx = 4,
961 },
962 .hw.init = &(struct clk_init_data) {
963 .name = "vclk2_div12_en",
964 .ops = &clk_regmap_gate_ops,
965 .parent_hws = (const struct clk_hw *[]) { &s4_vclk2.hw },
966 .num_parents = 1,
967 .flags = CLK_SET_RATE_PARENT,
968 },
969};
970
971static struct clk_fixed_factor s4_vclk_div2 = {
972 .mult = 1,
973 .div = 2,
974 .hw.init = &(struct clk_init_data){
975 .name = "vclk_div2",
976 .ops = &clk_fixed_factor_ops,
977 .parent_hws = (const struct clk_hw *[]) {
978 &s4_vclk_div2_en.hw
979 },
980 .num_parents = 1,
981 .flags = CLK_SET_RATE_PARENT,
982 },
983};
984
985static struct clk_fixed_factor s4_vclk_div4 = {
986 .mult = 1,
987 .div = 4,
988 .hw.init = &(struct clk_init_data){
989 .name = "vclk_div4",
990 .ops = &clk_fixed_factor_ops,
991 .parent_hws = (const struct clk_hw *[]) {
992 &s4_vclk_div4_en.hw
993 },
994 .num_parents = 1,
995 .flags = CLK_SET_RATE_PARENT,
996 },
997};
998
999static struct clk_fixed_factor s4_vclk_div6 = {
1000 .mult = 1,
1001 .div = 6,
1002 .hw.init = &(struct clk_init_data){
1003 .name = "vclk_div6",
1004 .ops = &clk_fixed_factor_ops,
1005 .parent_hws = (const struct clk_hw *[]) {
1006 &s4_vclk_div6_en.hw
1007 },
1008 .num_parents = 1,
1009 .flags = CLK_SET_RATE_PARENT,
1010 },
1011};
1012
1013static struct clk_fixed_factor s4_vclk_div12 = {
1014 .mult = 1,
1015 .div = 12,
1016 .hw.init = &(struct clk_init_data){
1017 .name = "vclk_div12",
1018 .ops = &clk_fixed_factor_ops,
1019 .parent_hws = (const struct clk_hw *[]) {
1020 &s4_vclk_div12_en.hw
1021 },
1022 .num_parents = 1,
1023 .flags = CLK_SET_RATE_PARENT,
1024 },
1025};
1026
1027static struct clk_fixed_factor s4_vclk2_div2 = {
1028 .mult = 1,
1029 .div = 2,
1030 .hw.init = &(struct clk_init_data){
1031 .name = "vclk2_div2",
1032 .ops = &clk_fixed_factor_ops,
1033 .parent_hws = (const struct clk_hw *[]) {
1034 &s4_vclk2_div2_en.hw
1035 },
1036 .num_parents = 1,
1037 .flags = CLK_SET_RATE_PARENT,
1038 },
1039};
1040
1041static struct clk_fixed_factor s4_vclk2_div4 = {
1042 .mult = 1,
1043 .div = 4,
1044 .hw.init = &(struct clk_init_data){
1045 .name = "vclk2_div4",
1046 .ops = &clk_fixed_factor_ops,
1047 .parent_hws = (const struct clk_hw *[]) {
1048 &s4_vclk2_div4_en.hw
1049 },
1050 .num_parents = 1,
1051 .flags = CLK_SET_RATE_PARENT,
1052 },
1053};
1054
1055static struct clk_fixed_factor s4_vclk2_div6 = {
1056 .mult = 1,
1057 .div = 6,
1058 .hw.init = &(struct clk_init_data){
1059 .name = "vclk2_div6",
1060 .ops = &clk_fixed_factor_ops,
1061 .parent_hws = (const struct clk_hw *[]) {
1062 &s4_vclk2_div6_en.hw
1063 },
1064 .num_parents = 1,
1065 .flags = CLK_SET_RATE_PARENT,
1066 },
1067};
1068
1069static struct clk_fixed_factor s4_vclk2_div12 = {
1070 .mult = 1,
1071 .div = 12,
1072 .hw.init = &(struct clk_init_data){
1073 .name = "vclk2_div12",
1074 .ops = &clk_fixed_factor_ops,
1075 .parent_hws = (const struct clk_hw *[]) {
1076 &s4_vclk2_div12_en.hw
1077 },
1078 .num_parents = 1,
1079 .flags = CLK_SET_RATE_PARENT,
1080 },
1081};
1082
1083/* The 5,6,7 indexes corresponds to no real clock, so there are not used. */
1084static u32 s4_cts_parents_val_table[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
1085static const struct clk_hw *s4_cts_parents[] = {
1086 &s4_vclk_div1.hw,
1087 &s4_vclk_div2.hw,
1088 &s4_vclk_div4.hw,
1089 &s4_vclk_div6.hw,
1090 &s4_vclk_div12.hw,
1091 &s4_vclk2_div1.hw,
1092 &s4_vclk2_div2.hw,
1093 &s4_vclk2_div4.hw,
1094 &s4_vclk2_div6.hw,
1095 &s4_vclk2_div12.hw
1096};
1097
1098static struct clk_regmap s4_cts_enci_sel = {
1099 .data = &(struct clk_regmap_mux_data){
1100 .offset = CLKCTRL_VID_CLK_DIV,
1101 .mask = 0xf,
1102 .shift = 28,
1103 .table = s4_cts_parents_val_table,
1104 },
1105 .hw.init = &(struct clk_init_data){
1106 .name = "cts_enci_sel",
1107 .ops = &clk_regmap_mux_ops,
1108 .parent_hws = s4_cts_parents,
1109 .num_parents = ARRAY_SIZE(s4_cts_parents),
1110 },
1111};
1112
1113static struct clk_regmap s4_cts_encp_sel = {
1114 .data = &(struct clk_regmap_mux_data){
1115 .offset = CLKCTRL_VID_CLK_DIV,
1116 .mask = 0xf,
1117 .shift = 20,
1118 .table = s4_cts_parents_val_table,
1119 },
1120 .hw.init = &(struct clk_init_data){
1121 .name = "cts_encp_sel",
1122 .ops = &clk_regmap_mux_ops,
1123 .parent_hws = s4_cts_parents,
1124 .num_parents = ARRAY_SIZE(s4_cts_parents),
1125 },
1126};
1127
1128static struct clk_regmap s4_cts_encl_sel = {
1129 .data = &(struct clk_regmap_mux_data){
1130 .offset = CLKCTRL_VIID_CLK_DIV,
1131 .mask = 0xf,
1132 .shift = 12,
1133 .table = s4_cts_parents_val_table,
1134 },
1135 .hw.init = &(struct clk_init_data){
1136 .name = "cts_encl_sel",
1137 .ops = &clk_regmap_mux_ops,
1138 .parent_hws = s4_cts_parents,
1139 .num_parents = ARRAY_SIZE(s4_cts_parents),
1140 },
1141};
1142
1143static struct clk_regmap s4_cts_vdac_sel = {
1144 .data = &(struct clk_regmap_mux_data){
1145 .offset = CLKCTRL_VIID_CLK_DIV,
1146 .mask = 0xf,
1147 .shift = 28,
1148 .table = s4_cts_parents_val_table,
1149 },
1150 .hw.init = &(struct clk_init_data){
1151 .name = "cts_vdac_sel",
1152 .ops = &clk_regmap_mux_ops,
1153 .parent_hws = s4_cts_parents,
1154 .num_parents = ARRAY_SIZE(s4_cts_parents),
1155 },
1156};
1157
1158/* The 5,6,7 indexes corresponds to no real clock, so there are not used. */
1159static u32 s4_hdmi_tx_parents_val_table[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
1160static const struct clk_hw *s4_hdmi_tx_parents[] = {
1161 &s4_vclk_div1.hw,
1162 &s4_vclk_div2.hw,
1163 &s4_vclk_div4.hw,
1164 &s4_vclk_div6.hw,
1165 &s4_vclk_div12.hw,
1166 &s4_vclk2_div1.hw,
1167 &s4_vclk2_div2.hw,
1168 &s4_vclk2_div4.hw,
1169 &s4_vclk2_div6.hw,
1170 &s4_vclk2_div12.hw
1171};
1172
1173static struct clk_regmap s4_hdmi_tx_sel = {
1174 .data = &(struct clk_regmap_mux_data){
1175 .offset = CLKCTRL_HDMI_CLK_CTRL,
1176 .mask = 0xf,
1177 .shift = 16,
1178 .table = s4_hdmi_tx_parents_val_table,
1179 },
1180 .hw.init = &(struct clk_init_data){
1181 .name = "hdmi_tx_sel",
1182 .ops = &clk_regmap_mux_ops,
1183 .parent_hws = s4_hdmi_tx_parents,
1184 .num_parents = ARRAY_SIZE(s4_hdmi_tx_parents),
1185 },
1186};
1187
1188static struct clk_regmap s4_cts_enci = {
1189 .data = &(struct clk_regmap_gate_data){
1190 .offset = CLKCTRL_VID_CLK_CTRL2,
1191 .bit_idx = 0,
1192 },
1193 .hw.init = &(struct clk_init_data) {
1194 .name = "cts_enci",
1195 .ops = &clk_regmap_gate_ops,
1196 .parent_hws = (const struct clk_hw *[]) {
1197 &s4_cts_enci_sel.hw
1198 },
1199 .num_parents = 1,
1200 .flags = CLK_SET_RATE_PARENT,
1201 },
1202};
1203
1204static struct clk_regmap s4_cts_encp = {
1205 .data = &(struct clk_regmap_gate_data){
1206 .offset = CLKCTRL_VID_CLK_CTRL2,
1207 .bit_idx = 2,
1208 },
1209 .hw.init = &(struct clk_init_data) {
1210 .name = "cts_encp",
1211 .ops = &clk_regmap_gate_ops,
1212 .parent_hws = (const struct clk_hw *[]) {
1213 &s4_cts_encp_sel.hw
1214 },
1215 .num_parents = 1,
1216 .flags = CLK_SET_RATE_PARENT,
1217 },
1218};
1219
1220static struct clk_regmap s4_cts_encl = {
1221 .data = &(struct clk_regmap_gate_data){
1222 .offset = CLKCTRL_VID_CLK_CTRL2,
1223 .bit_idx = 3,
1224 },
1225 .hw.init = &(struct clk_init_data) {
1226 .name = "cts_encl",
1227 .ops = &clk_regmap_gate_ops,
1228 .parent_hws = (const struct clk_hw *[]) {
1229 &s4_cts_encl_sel.hw
1230 },
1231 .num_parents = 1,
1232 .flags = CLK_SET_RATE_PARENT,
1233 },
1234};
1235
1236static struct clk_regmap s4_cts_vdac = {
1237 .data = &(struct clk_regmap_gate_data){
1238 .offset = CLKCTRL_VID_CLK_CTRL2,
1239 .bit_idx = 4,
1240 },
1241 .hw.init = &(struct clk_init_data) {
1242 .name = "cts_vdac",
1243 .ops = &clk_regmap_gate_ops,
1244 .parent_hws = (const struct clk_hw *[]) {
1245 &s4_cts_vdac_sel.hw
1246 },
1247 .num_parents = 1,
1248 .flags = CLK_SET_RATE_PARENT,
1249 },
1250};
1251
1252static struct clk_regmap s4_hdmi_tx = {
1253 .data = &(struct clk_regmap_gate_data){
1254 .offset = CLKCTRL_VID_CLK_CTRL2,
1255 .bit_idx = 5,
1256 },
1257 .hw.init = &(struct clk_init_data) {
1258 .name = "hdmi_tx",
1259 .ops = &clk_regmap_gate_ops,
1260 .parent_hws = (const struct clk_hw *[]) {
1261 &s4_hdmi_tx_sel.hw
1262 },
1263 .num_parents = 1,
1264 .flags = CLK_SET_RATE_PARENT,
1265 },
1266};
1267
1268/* HDMI Clocks */
1269static const struct clk_parent_data s4_hdmi_parents[] = {
1270 { .fw_name = "xtal", },
1271 { .fw_name = "fclk_div4", },
1272 { .fw_name = "fclk_div3", },
1273 { .fw_name = "fclk_div5", }
1274};
1275
1276static struct clk_regmap s4_hdmi_sel = {
1277 .data = &(struct clk_regmap_mux_data){
1278 .offset = CLKCTRL_HDMI_CLK_CTRL,
1279 .mask = 0x3,
1280 .shift = 9,
1281 .flags = CLK_MUX_ROUND_CLOSEST,
1282 },
1283 .hw.init = &(struct clk_init_data){
1284 .name = "hdmi_sel",
1285 .ops = &clk_regmap_mux_ops,
1286 .parent_data = s4_hdmi_parents,
1287 .num_parents = ARRAY_SIZE(s4_hdmi_parents),
1288 .flags = CLK_SET_RATE_PARENT,
1289 },
1290};
1291
1292static struct clk_regmap s4_hdmi_div = {
1293 .data = &(struct clk_regmap_div_data){
1294 .offset = CLKCTRL_HDMI_CLK_CTRL,
1295 .shift = 0,
1296 .width = 7,
1297 },
1298 .hw.init = &(struct clk_init_data){
1299 .name = "hdmi_div",
1300 .ops = &clk_regmap_divider_ops,
1301 .parent_hws = (const struct clk_hw *[]) { &s4_hdmi_sel.hw },
1302 .num_parents = 1,
1303 .flags = CLK_SET_RATE_PARENT,
1304 },
1305};
1306
1307static struct clk_regmap s4_hdmi = {
1308 .data = &(struct clk_regmap_gate_data){
1309 .offset = CLKCTRL_HDMI_CLK_CTRL,
1310 .bit_idx = 8,
1311 },
1312 .hw.init = &(struct clk_init_data) {
1313 .name = "hdmi",
1314 .ops = &clk_regmap_gate_ops,
1315 .parent_hws = (const struct clk_hw *[]) { &s4_hdmi_div.hw },
1316 .num_parents = 1,
1317 .flags = CLK_SET_RATE_PARENT,
1318 },
1319};
1320
1321static struct clk_regmap s4_ts_clk_div = {
1322 .data = &(struct clk_regmap_div_data){
1323 .offset = CLKCTRL_TS_CLK_CTRL,
1324 .shift = 0,
1325 .width = 8,
1326 },
1327 .hw.init = &(struct clk_init_data){
1328 .name = "ts_clk_div",
1329 .ops = &clk_regmap_divider_ops,
1330 .parent_data = &(const struct clk_parent_data) {
1331 .fw_name = "xtal",
1332 },
1333 .num_parents = 1,
1334 .flags = CLK_SET_RATE_PARENT,
1335 },
1336};
1337
1338static struct clk_regmap s4_ts_clk = {
1339 .data = &(struct clk_regmap_gate_data){
1340 .offset = CLKCTRL_TS_CLK_CTRL,
1341 .bit_idx = 8,
1342 },
1343 .hw.init = &(struct clk_init_data){
1344 .name = "ts_clk",
1345 .ops = &clk_regmap_gate_ops,
1346 .parent_hws = (const struct clk_hw *[]) {
1347 &s4_ts_clk_div.hw
1348 },
1349 .num_parents = 1,
1350 .flags = CLK_SET_RATE_PARENT,
1351 },
1352};
1353
1354/*
1355 * The MALI IP is clocked by two identical clocks (mali_0 and mali_1)
1356 * muxed by a glitch-free switch. The CCF can manage this glitch-free
1357 * mux because it does top-to-bottom updates the each clock tree and
1358 * switches to the "inactive" one when CLK_SET_RATE_GATE is set.
1359 */
1360static const struct clk_parent_data s4_mali_parents[] = {
1361 { .fw_name = "xtal", },
1362 { .fw_name = "gp0_pll", },
1363 { .fw_name = "hifi_pll", },
1364 { .fw_name = "fclk_div2p5", },
1365 { .fw_name = "fclk_div3", },
1366 { .fw_name = "fclk_div4", },
1367 { .fw_name = "fclk_div5", },
1368 { .fw_name = "fclk_div7", }
1369};
1370
1371static struct clk_regmap s4_mali_0_sel = {
1372 .data = &(struct clk_regmap_mux_data){
1373 .offset = CLKCTRL_MALI_CLK_CTRL,
1374 .mask = 0x7,
1375 .shift = 9,
1376 },
1377 .hw.init = &(struct clk_init_data){
1378 .name = "mali_0_sel",
1379 .ops = &clk_regmap_mux_ops,
1380 .parent_data = s4_mali_parents,
1381 .num_parents = ARRAY_SIZE(s4_mali_parents),
1382 /*
1383 * Don't request the parent to change the rate because
1384 * all GPU frequencies can be derived from the fclk_*
1385 * clocks and one special GP0_PLL setting. This is
1386 * important because we need the HIFI PLL clock for audio.
1387 */
1388 .flags = 0,
1389 },
1390};
1391
1392static struct clk_regmap s4_mali_0_div = {
1393 .data = &(struct clk_regmap_div_data){
1394 .offset = CLKCTRL_MALI_CLK_CTRL,
1395 .shift = 0,
1396 .width = 7,
1397 },
1398 .hw.init = &(struct clk_init_data){
1399 .name = "mali_0_div",
1400 .ops = &clk_regmap_divider_ops,
1401 .parent_hws = (const struct clk_hw *[]) {
1402 &s4_mali_0_sel.hw
1403 },
1404 .num_parents = 1,
1405 .flags = CLK_SET_RATE_PARENT,
1406 },
1407};
1408
1409static struct clk_regmap s4_mali_0 = {
1410 .data = &(struct clk_regmap_gate_data){
1411 .offset = CLKCTRL_MALI_CLK_CTRL,
1412 .bit_idx = 8,
1413 },
1414 .hw.init = &(struct clk_init_data){
1415 .name = "mali_0",
1416 .ops = &clk_regmap_gate_ops,
1417 .parent_hws = (const struct clk_hw *[]) {
1418 &s4_mali_0_div.hw
1419 },
1420 .num_parents = 1,
1421 .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
1422 },
1423};
1424
1425static struct clk_regmap s4_mali_1_sel = {
1426 .data = &(struct clk_regmap_mux_data){
1427 .offset = CLKCTRL_MALI_CLK_CTRL,
1428 .mask = 0x7,
1429 .shift = 25,
1430 },
1431 .hw.init = &(struct clk_init_data){
1432 .name = "mali_1_sel",
1433 .ops = &clk_regmap_mux_ops,
1434 .parent_data = s4_mali_parents,
1435 .num_parents = ARRAY_SIZE(s4_mali_parents),
1436 .flags = 0,
1437 },
1438};
1439
1440static struct clk_regmap s4_mali_1_div = {
1441 .data = &(struct clk_regmap_div_data){
1442 .offset = CLKCTRL_MALI_CLK_CTRL,
1443 .shift = 16,
1444 .width = 7,
1445 },
1446 .hw.init = &(struct clk_init_data){
1447 .name = "mali_1_div",
1448 .ops = &clk_regmap_divider_ops,
1449 .parent_hws = (const struct clk_hw *[]) {
1450 &s4_mali_1_sel.hw
1451 },
1452 .num_parents = 1,
1453 .flags = CLK_SET_RATE_PARENT,
1454 },
1455};
1456
1457static struct clk_regmap s4_mali_1 = {
1458 .data = &(struct clk_regmap_gate_data){
1459 .offset = CLKCTRL_MALI_CLK_CTRL,
1460 .bit_idx = 24,
1461 },
1462 .hw.init = &(struct clk_init_data){
1463 .name = "mali_1",
1464 .ops = &clk_regmap_gate_ops,
1465 .parent_hws = (const struct clk_hw *[]) {
1466 &s4_mali_1_div.hw
1467 },
1468 .num_parents = 1,
1469 .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
1470 },
1471};
1472
1473static struct clk_regmap s4_mali_sel = {
1474 .data = &(struct clk_regmap_mux_data){
1475 .offset = CLKCTRL_MALI_CLK_CTRL,
1476 .mask = 1,
1477 .shift = 31,
1478 },
1479 .hw.init = &(struct clk_init_data){
1480 .name = "mali_sel",
1481 .ops = &clk_regmap_mux_ops,
1482 .parent_hws = (const struct clk_hw *[]) {
1483 &s4_mali_0.hw,
1484 &s4_mali_1.hw,
1485 },
1486 .num_parents = 2,
1487 .flags = CLK_SET_RATE_PARENT,
1488 },
1489};
1490
1491/* VDEC clocks */
1492static const struct clk_parent_data s4_dec_parents[] = {
1493 { .fw_name = "fclk_div2p5", },
1494 { .fw_name = "fclk_div3", },
1495 { .fw_name = "fclk_div4", },
1496 { .fw_name = "fclk_div5", },
1497 { .fw_name = "fclk_div7", },
1498 { .fw_name = "hifi_pll", },
1499 { .fw_name = "gp0_pll", },
1500 { .fw_name = "xtal", }
1501};
1502
1503static struct clk_regmap s4_vdec_p0_sel = {
1504 .data = &(struct clk_regmap_mux_data){
1505 .offset = CLKCTRL_VDEC_CLK_CTRL,
1506 .mask = 0x7,
1507 .shift = 9,
1508 .flags = CLK_MUX_ROUND_CLOSEST,
1509 },
1510 .hw.init = &(struct clk_init_data) {
1511 .name = "vdec_p0_sel",
1512 .ops = &clk_regmap_mux_ops,
1513 .parent_data = s4_dec_parents,
1514 .num_parents = ARRAY_SIZE(s4_dec_parents),
1515 .flags = 0,
1516 },
1517};
1518
1519static struct clk_regmap s4_vdec_p0_div = {
1520 .data = &(struct clk_regmap_div_data){
1521 .offset = CLKCTRL_VDEC_CLK_CTRL,
1522 .shift = 0,
1523 .width = 7,
1524 .flags = CLK_DIVIDER_ROUND_CLOSEST,
1525 },
1526 .hw.init = &(struct clk_init_data) {
1527 .name = "vdec_p0_div",
1528 .ops = &clk_regmap_divider_ops,
1529 .parent_hws = (const struct clk_hw *[]) {
1530 &s4_vdec_p0_sel.hw
1531 },
1532 .num_parents = 1,
1533 .flags = CLK_SET_RATE_PARENT,
1534 },
1535};
1536
1537static struct clk_regmap s4_vdec_p0 = {
1538 .data = &(struct clk_regmap_gate_data){
1539 .offset = CLKCTRL_VDEC_CLK_CTRL,
1540 .bit_idx = 8,
1541 },
1542 .hw.init = &(struct clk_init_data){
1543 .name = "vdec_p0",
1544 .ops = &clk_regmap_gate_ops,
1545 .parent_hws = (const struct clk_hw *[]) {
1546 &s4_vdec_p0_div.hw
1547 },
1548 .num_parents = 1,
1549 .flags = CLK_SET_RATE_PARENT,
1550 },
1551};
1552
1553static struct clk_regmap s4_vdec_p1_sel = {
1554 .data = &(struct clk_regmap_mux_data){
1555 .offset = CLKCTRL_VDEC3_CLK_CTRL,
1556 .mask = 0x7,
1557 .shift = 9,
1558 .flags = CLK_MUX_ROUND_CLOSEST,
1559 },
1560 .hw.init = &(struct clk_init_data) {
1561 .name = "vdec_p1_sel",
1562 .ops = &clk_regmap_mux_ops,
1563 .parent_data = s4_dec_parents,
1564 .num_parents = ARRAY_SIZE(s4_dec_parents),
1565 .flags = 0,
1566 },
1567};
1568
1569static struct clk_regmap s4_vdec_p1_div = {
1570 .data = &(struct clk_regmap_div_data){
1571 .offset = CLKCTRL_VDEC3_CLK_CTRL,
1572 .shift = 0,
1573 .width = 7,
1574 .flags = CLK_DIVIDER_ROUND_CLOSEST,
1575 },
1576 .hw.init = &(struct clk_init_data) {
1577 .name = "vdec_p1_div",
1578 .ops = &clk_regmap_divider_ops,
1579 .parent_hws = (const struct clk_hw *[]) {
1580 &s4_vdec_p1_sel.hw
1581 },
1582 .num_parents = 1,
1583 .flags = CLK_SET_RATE_PARENT,
1584 },
1585};
1586
1587static struct clk_regmap s4_vdec_p1 = {
1588 .data = &(struct clk_regmap_gate_data){
1589 .offset = CLKCTRL_VDEC3_CLK_CTRL,
1590 .bit_idx = 8,
1591 },
1592 .hw.init = &(struct clk_init_data){
1593 .name = "vdec_p1",
1594 .ops = &clk_regmap_gate_ops,
1595 .parent_hws = (const struct clk_hw *[]) {
1596 &s4_vdec_p1_div.hw
1597 },
1598 .num_parents = 1,
1599 .flags = CLK_SET_RATE_PARENT,
1600 },
1601};
1602
1603static struct clk_regmap s4_vdec_sel = {
1604 .data = &(struct clk_regmap_mux_data){
1605 .offset = CLKCTRL_VDEC3_CLK_CTRL,
1606 .mask = 0x1,
1607 .shift = 15,
1608 },
1609 .hw.init = &(struct clk_init_data) {
1610 .name = "vdec_sel",
1611 .ops = &clk_regmap_mux_ops,
1612 .parent_hws = (const struct clk_hw *[]) {
1613 &s4_vdec_p0.hw,
1614 &s4_vdec_p1.hw,
1615 },
1616 .num_parents = 2,
1617 .flags = CLK_SET_RATE_PARENT,
1618 },
1619};
1620
1621static struct clk_regmap s4_hevcf_p0_sel = {
1622 .data = &(struct clk_regmap_mux_data){
1623 .offset = CLKCTRL_VDEC2_CLK_CTRL,
1624 .mask = 0x7,
1625 .shift = 9,
1626 .flags = CLK_MUX_ROUND_CLOSEST,
1627 },
1628 .hw.init = &(struct clk_init_data) {
1629 .name = "hevcf_p0_sel",
1630 .ops = &clk_regmap_mux_ops,
1631 .parent_data = s4_dec_parents,
1632 .num_parents = ARRAY_SIZE(s4_dec_parents),
1633 .flags = 0,
1634 },
1635};
1636
1637static struct clk_regmap s4_hevcf_p0_div = {
1638 .data = &(struct clk_regmap_div_data){
1639 .offset = CLKCTRL_VDEC2_CLK_CTRL,
1640 .shift = 0,
1641 .width = 7,
1642 .flags = CLK_DIVIDER_ROUND_CLOSEST,
1643 },
1644 .hw.init = &(struct clk_init_data) {
1645 .name = "hevcf_p0_div",
1646 .ops = &clk_regmap_divider_ops,
1647 .parent_hws = (const struct clk_hw *[]) {
1648 &s4_hevcf_p0_sel.hw
1649 },
1650 .num_parents = 1,
1651 .flags = CLK_SET_RATE_PARENT,
1652 },
1653};
1654
1655static struct clk_regmap s4_hevcf_p0 = {
1656 .data = &(struct clk_regmap_gate_data){
1657 .offset = CLKCTRL_VDEC2_CLK_CTRL,
1658 .bit_idx = 8,
1659 },
1660 .hw.init = &(struct clk_init_data){
1661 .name = "hevcf_p0",
1662 .ops = &clk_regmap_gate_ops,
1663 .parent_hws = (const struct clk_hw *[]) {
1664 &s4_hevcf_p0_div.hw
1665 },
1666 .num_parents = 1,
1667 .flags = CLK_SET_RATE_PARENT,
1668 },
1669};
1670
1671static struct clk_regmap s4_hevcf_p1_sel = {
1672 .data = &(struct clk_regmap_mux_data){
1673 .offset = CLKCTRL_VDEC4_CLK_CTRL,
1674 .mask = 0x7,
1675 .shift = 9,
1676 .flags = CLK_MUX_ROUND_CLOSEST,
1677 },
1678 .hw.init = &(struct clk_init_data) {
1679 .name = "hevcf_p1_sel",
1680 .ops = &clk_regmap_mux_ops,
1681 .parent_data = s4_dec_parents,
1682 .num_parents = ARRAY_SIZE(s4_dec_parents),
1683 .flags = 0,
1684 },
1685};
1686
1687static struct clk_regmap s4_hevcf_p1_div = {
1688 .data = &(struct clk_regmap_div_data){
1689 .offset = CLKCTRL_VDEC4_CLK_CTRL,
1690 .shift = 0,
1691 .width = 7,
1692 .flags = CLK_DIVIDER_ROUND_CLOSEST,
1693 },
1694 .hw.init = &(struct clk_init_data) {
1695 .name = "hevcf_p1_div",
1696 .ops = &clk_regmap_divider_ops,
1697 .parent_hws = (const struct clk_hw *[]) {
1698 &s4_hevcf_p1_sel.hw
1699 },
1700 .num_parents = 1,
1701 .flags = CLK_SET_RATE_PARENT,
1702 },
1703};
1704
1705static struct clk_regmap s4_hevcf_p1 = {
1706 .data = &(struct clk_regmap_gate_data){
1707 .offset = CLKCTRL_VDEC4_CLK_CTRL,
1708 .bit_idx = 8,
1709 },
1710 .hw.init = &(struct clk_init_data){
1711 .name = "hevcf_p1",
1712 .ops = &clk_regmap_gate_ops,
1713 .parent_hws = (const struct clk_hw *[]) {
1714 &s4_hevcf_p1_div.hw
1715 },
1716 .num_parents = 1,
1717 .flags = CLK_SET_RATE_PARENT,
1718 },
1719};
1720
1721static struct clk_regmap s4_hevcf_sel = {
1722 .data = &(struct clk_regmap_mux_data){
1723 .offset = CLKCTRL_VDEC4_CLK_CTRL,
1724 .mask = 0x1,
1725 .shift = 15,
1726 },
1727 .hw.init = &(struct clk_init_data) {
1728 .name = "hevcf_sel",
1729 .ops = &clk_regmap_mux_ops,
1730 .parent_hws = (const struct clk_hw *[]) {
1731 &s4_hevcf_p0.hw,
1732 &s4_hevcf_p1.hw,
1733 },
1734 .num_parents = 2,
1735 .flags = CLK_SET_RATE_PARENT,
1736 },
1737};
1738
1739/* VPU Clock */
1740static const struct clk_parent_data s4_vpu_parents[] = {
1741 { .fw_name = "fclk_div3", },
1742 { .fw_name = "fclk_div4", },
1743 { .fw_name = "fclk_div5", },
1744 { .fw_name = "fclk_div7", },
1745 { .fw_name = "mpll1", },
1746 { .hw = &s4_vid_pll.hw },
1747 { .fw_name = "hifi_pll", },
1748 { .fw_name = "gp0_pll", },
1749};
1750
1751static struct clk_regmap s4_vpu_0_sel = {
1752 .data = &(struct clk_regmap_mux_data){
1753 .offset = CLKCTRL_VPU_CLK_CTRL,
1754 .mask = 0x7,
1755 .shift = 9,
1756 },
1757 .hw.init = &(struct clk_init_data){
1758 .name = "vpu_0_sel",
1759 .ops = &clk_regmap_mux_ops,
1760 .parent_data = s4_vpu_parents,
1761 .num_parents = ARRAY_SIZE(s4_vpu_parents),
1762 .flags = 0,
1763 },
1764};
1765
1766static struct clk_regmap s4_vpu_0_div = {
1767 .data = &(struct clk_regmap_div_data){
1768 .offset = CLKCTRL_VPU_CLK_CTRL,
1769 .shift = 0,
1770 .width = 7,
1771 },
1772 .hw.init = &(struct clk_init_data){
1773 .name = "vpu_0_div",
1774 .ops = &clk_regmap_divider_ops,
1775 .parent_hws = (const struct clk_hw *[]) { &s4_vpu_0_sel.hw },
1776 .num_parents = 1,
1777 .flags = CLK_SET_RATE_PARENT,
1778 },
1779};
1780
1781static struct clk_regmap s4_vpu_0 = {
1782 .data = &(struct clk_regmap_gate_data){
1783 .offset = CLKCTRL_VPU_CLK_CTRL,
1784 .bit_idx = 8,
1785 },
1786 .hw.init = &(struct clk_init_data) {
1787 .name = "vpu_0",
1788 .ops = &clk_regmap_gate_ops,
1789 .parent_hws = (const struct clk_hw *[]) { &s4_vpu_0_div.hw },
1790 .num_parents = 1,
1791 .flags = CLK_SET_RATE_PARENT,
1792 },
1793};
1794
1795static struct clk_regmap s4_vpu_1_sel = {
1796 .data = &(struct clk_regmap_mux_data){
1797 .offset = CLKCTRL_VPU_CLK_CTRL,
1798 .mask = 0x7,
1799 .shift = 25,
1800 },
1801 .hw.init = &(struct clk_init_data){
1802 .name = "vpu_1_sel",
1803 .ops = &clk_regmap_mux_ops,
1804 .parent_data = s4_vpu_parents,
1805 .num_parents = ARRAY_SIZE(s4_vpu_parents),
1806 .flags = 0,
1807 },
1808};
1809
1810static struct clk_regmap s4_vpu_1_div = {
1811 .data = &(struct clk_regmap_div_data){
1812 .offset = CLKCTRL_VPU_CLK_CTRL,
1813 .shift = 16,
1814 .width = 7,
1815 },
1816 .hw.init = &(struct clk_init_data){
1817 .name = "vpu_1_div",
1818 .ops = &clk_regmap_divider_ops,
1819 .parent_hws = (const struct clk_hw *[]) { &s4_vpu_1_sel.hw },
1820 .num_parents = 1,
1821 .flags = CLK_SET_RATE_PARENT,
1822 },
1823};
1824
1825static struct clk_regmap s4_vpu_1 = {
1826 .data = &(struct clk_regmap_gate_data){
1827 .offset = CLKCTRL_VPU_CLK_CTRL,
1828 .bit_idx = 24,
1829 },
1830 .hw.init = &(struct clk_init_data) {
1831 .name = "vpu_1",
1832 .ops = &clk_regmap_gate_ops,
1833 .parent_hws = (const struct clk_hw *[]) { &s4_vpu_1_div.hw },
1834 .num_parents = 1,
1835 .flags = CLK_SET_RATE_PARENT,
1836 },
1837};
1838
1839static struct clk_regmap s4_vpu = {
1840 .data = &(struct clk_regmap_mux_data){
1841 .offset = CLKCTRL_VPU_CLK_CTRL,
1842 .mask = 1,
1843 .shift = 31,
1844 },
1845 .hw.init = &(struct clk_init_data){
1846 .name = "vpu",
1847 .ops = &clk_regmap_mux_ops,
1848 .parent_hws = (const struct clk_hw *[]) {
1849 &s4_vpu_0.hw,
1850 &s4_vpu_1.hw,
1851 },
1852 .num_parents = 2,
1853 .flags = CLK_SET_RATE_PARENT,
1854 },
1855};
1856
1857static const struct clk_parent_data vpu_clkb_tmp_parents[] = {
1858 { .hw = &s4_vpu.hw },
1859 { .fw_name = "fclk_div4", },
1860 { .fw_name = "fclk_div5", },
1861 { .fw_name = "fclk_div7", }
1862};
1863
1864static struct clk_regmap s4_vpu_clkb_tmp_sel = {
1865 .data = &(struct clk_regmap_mux_data){
1866 .offset = CLKCTRL_VPU_CLKB_CTRL,
1867 .mask = 0x3,
1868 .shift = 20,
1869 },
1870 .hw.init = &(struct clk_init_data) {
1871 .name = "vpu_clkb_tmp_sel",
1872 .ops = &clk_regmap_mux_ops,
1873 .parent_data = vpu_clkb_tmp_parents,
1874 .num_parents = ARRAY_SIZE(vpu_clkb_tmp_parents),
1875 .flags = CLK_SET_RATE_PARENT,
1876 },
1877};
1878
1879static struct clk_regmap s4_vpu_clkb_tmp_div = {
1880 .data = &(struct clk_regmap_div_data){
1881 .offset = CLKCTRL_VPU_CLKB_CTRL,
1882 .shift = 16,
1883 .width = 4,
1884 },
1885 .hw.init = &(struct clk_init_data) {
1886 .name = "vpu_clkb_tmp_div",
1887 .ops = &clk_regmap_divider_ops,
1888 .parent_hws = (const struct clk_hw *[]) {
1889 &s4_vpu_clkb_tmp_sel.hw
1890 },
1891 .num_parents = 1,
1892 .flags = CLK_SET_RATE_PARENT,
1893 },
1894};
1895
1896static struct clk_regmap s4_vpu_clkb_tmp = {
1897 .data = &(struct clk_regmap_gate_data){
1898 .offset = CLKCTRL_VPU_CLKB_CTRL,
1899 .bit_idx = 24,
1900 },
1901 .hw.init = &(struct clk_init_data){
1902 .name = "vpu_clkb_tmp",
1903 .ops = &clk_regmap_gate_ops,
1904 .parent_hws = (const struct clk_hw *[]) {
1905 &s4_vpu_clkb_tmp_div.hw
1906 },
1907 .num_parents = 1,
1908 .flags = CLK_SET_RATE_PARENT,
1909 },
1910};
1911
1912static struct clk_regmap s4_vpu_clkb_div = {
1913 .data = &(struct clk_regmap_div_data){
1914 .offset = CLKCTRL_VPU_CLKB_CTRL,
1915 .shift = 0,
1916 .width = 8,
1917 },
1918 .hw.init = &(struct clk_init_data) {
1919 .name = "vpu_clkb_div",
1920 .ops = &clk_regmap_divider_ops,
1921 .parent_hws = (const struct clk_hw *[]) {
1922 &s4_vpu_clkb_tmp.hw
1923 },
1924 .num_parents = 1,
1925 .flags = CLK_SET_RATE_PARENT,
1926 },
1927};
1928
1929static struct clk_regmap s4_vpu_clkb = {
1930 .data = &(struct clk_regmap_gate_data){
1931 .offset = CLKCTRL_VPU_CLKB_CTRL,
1932 .bit_idx = 8,
1933 },
1934 .hw.init = &(struct clk_init_data){
1935 .name = "vpu_clkb",
1936 .ops = &clk_regmap_gate_ops,
1937 .parent_hws = (const struct clk_hw *[]) {
1938 &s4_vpu_clkb_div.hw
1939 },
1940 .num_parents = 1,
1941 .flags = CLK_SET_RATE_PARENT,
1942 },
1943};
1944
1945static const struct clk_parent_data s4_vpu_clkc_parents[] = {
1946 { .fw_name = "fclk_div4", },
1947 { .fw_name = "fclk_div3", },
1948 { .fw_name = "fclk_div5", },
1949 { .fw_name = "fclk_div7", },
1950 { .fw_name = "mpll1", },
1951 { .hw = &s4_vid_pll.hw },
1952 { .fw_name = "mpll2", },
1953 { .fw_name = "gp0_pll", },
1954};
1955
1956static struct clk_regmap s4_vpu_clkc_p0_sel = {
1957 .data = &(struct clk_regmap_mux_data){
1958 .offset = CLKCTRL_VPU_CLKC_CTRL,
1959 .mask = 0x7,
1960 .shift = 9,
1961 },
1962 .hw.init = &(struct clk_init_data) {
1963 .name = "vpu_clkc_p0_sel",
1964 .ops = &clk_regmap_mux_ops,
1965 .parent_data = s4_vpu_clkc_parents,
1966 .num_parents = ARRAY_SIZE(s4_vpu_clkc_parents),
1967 .flags = 0,
1968 },
1969};
1970
1971static struct clk_regmap s4_vpu_clkc_p0_div = {
1972 .data = &(struct clk_regmap_div_data){
1973 .offset = CLKCTRL_VPU_CLKC_CTRL,
1974 .shift = 0,
1975 .width = 7,
1976 },
1977 .hw.init = &(struct clk_init_data) {
1978 .name = "vpu_clkc_p0_div",
1979 .ops = &clk_regmap_divider_ops,
1980 .parent_hws = (const struct clk_hw *[]) {
1981 &s4_vpu_clkc_p0_sel.hw
1982 },
1983 .num_parents = 1,
1984 .flags = CLK_SET_RATE_PARENT,
1985 },
1986};
1987
1988static struct clk_regmap s4_vpu_clkc_p0 = {
1989 .data = &(struct clk_regmap_gate_data){
1990 .offset = CLKCTRL_VPU_CLKC_CTRL,
1991 .bit_idx = 8,
1992 },
1993 .hw.init = &(struct clk_init_data){
1994 .name = "vpu_clkc_p0",
1995 .ops = &clk_regmap_gate_ops,
1996 .parent_hws = (const struct clk_hw *[]) {
1997 &s4_vpu_clkc_p0_div.hw
1998 },
1999 .num_parents = 1,
2000 .flags = CLK_SET_RATE_PARENT,
2001 },
2002};
2003
2004static struct clk_regmap s4_vpu_clkc_p1_sel = {
2005 .data = &(struct clk_regmap_mux_data){
2006 .offset = CLKCTRL_VPU_CLKC_CTRL,
2007 .mask = 0x7,
2008 .shift = 25,
2009 },
2010 .hw.init = &(struct clk_init_data) {
2011 .name = "vpu_clkc_p1_sel",
2012 .ops = &clk_regmap_mux_ops,
2013 .parent_data = s4_vpu_clkc_parents,
2014 .num_parents = ARRAY_SIZE(s4_vpu_clkc_parents),
2015 .flags = 0,
2016 },
2017};
2018
2019static struct clk_regmap s4_vpu_clkc_p1_div = {
2020 .data = &(struct clk_regmap_div_data){
2021 .offset = CLKCTRL_VPU_CLKC_CTRL,
2022 .shift = 16,
2023 .width = 7,
2024 },
2025 .hw.init = &(struct clk_init_data) {
2026 .name = "vpu_clkc_p1_div",
2027 .ops = &clk_regmap_divider_ops,
2028 .parent_hws = (const struct clk_hw *[]) {
2029 &s4_vpu_clkc_p1_sel.hw
2030 },
2031 .num_parents = 1,
2032 .flags = CLK_SET_RATE_PARENT,
2033 },
2034};
2035
2036static struct clk_regmap s4_vpu_clkc_p1 = {
2037 .data = &(struct clk_regmap_gate_data){
2038 .offset = CLKCTRL_VPU_CLKC_CTRL,
2039 .bit_idx = 24,
2040 },
2041 .hw.init = &(struct clk_init_data){
2042 .name = "vpu_clkc_p1",
2043 .ops = &clk_regmap_gate_ops,
2044 .parent_hws = (const struct clk_hw *[]) {
2045 &s4_vpu_clkc_p1_div.hw
2046 },
2047 .num_parents = 1,
2048 .flags = CLK_SET_RATE_PARENT,
2049 },
2050};
2051
2052static struct clk_regmap s4_vpu_clkc_sel = {
2053 .data = &(struct clk_regmap_mux_data){
2054 .offset = CLKCTRL_VPU_CLKC_CTRL,
2055 .mask = 0x1,
2056 .shift = 31,
2057 },
2058 .hw.init = &(struct clk_init_data) {
2059 .name = "vpu_clkc_sel",
2060 .ops = &clk_regmap_mux_ops,
2061 .parent_hws = (const struct clk_hw *[]) {
2062 &s4_vpu_clkc_p0.hw,
2063 &s4_vpu_clkc_p1.hw,
2064 },
2065 .num_parents = 2,
2066 .flags = CLK_SET_RATE_PARENT,
2067 },
2068};
2069
2070/* VAPB Clock */
2071static const struct clk_parent_data s4_vapb_parents[] = {
2072 { .fw_name = "fclk_div4", },
2073 { .fw_name = "fclk_div3", },
2074 { .fw_name = "fclk_div5", },
2075 { .fw_name = "fclk_div7", },
2076 { .fw_name = "mpll1", },
2077 { .hw = &s4_vid_pll.hw },
2078 { .fw_name = "mpll2", },
2079 { .fw_name = "fclk_div2p5", },
2080};
2081
2082static struct clk_regmap s4_vapb_0_sel = {
2083 .data = &(struct clk_regmap_mux_data){
2084 .offset = CLKCTRL_VAPBCLK_CTRL,
2085 .mask = 0x7,
2086 .shift = 9,
2087 },
2088 .hw.init = &(struct clk_init_data){
2089 .name = "vapb_0_sel",
2090 .ops = &clk_regmap_mux_ops,
2091 .parent_data = s4_vapb_parents,
2092 .num_parents = ARRAY_SIZE(s4_vapb_parents),
2093 .flags = 0,
2094 },
2095};
2096
2097static struct clk_regmap s4_vapb_0_div = {
2098 .data = &(struct clk_regmap_div_data){
2099 .offset = CLKCTRL_VAPBCLK_CTRL,
2100 .shift = 0,
2101 .width = 7,
2102 },
2103 .hw.init = &(struct clk_init_data){
2104 .name = "vapb_0_div",
2105 .ops = &clk_regmap_divider_ops,
2106 .parent_hws = (const struct clk_hw *[]) {
2107 &s4_vapb_0_sel.hw
2108 },
2109 .num_parents = 1,
2110 .flags = CLK_SET_RATE_PARENT,
2111 },
2112};
2113
2114static struct clk_regmap s4_vapb_0 = {
2115 .data = &(struct clk_regmap_gate_data){
2116 .offset = CLKCTRL_VAPBCLK_CTRL,
2117 .bit_idx = 8,
2118 },
2119 .hw.init = &(struct clk_init_data) {
2120 .name = "vapb_0",
2121 .ops = &clk_regmap_gate_ops,
2122 .parent_hws = (const struct clk_hw *[]) {
2123 &s4_vapb_0_div.hw
2124 },
2125 .num_parents = 1,
2126 .flags = CLK_SET_RATE_PARENT,
2127 },
2128};
2129
2130static struct clk_regmap s4_vapb_1_sel = {
2131 .data = &(struct clk_regmap_mux_data){
2132 .offset = CLKCTRL_VAPBCLK_CTRL,
2133 .mask = 0x7,
2134 .shift = 25,
2135 },
2136 .hw.init = &(struct clk_init_data){
2137 .name = "vapb_1_sel",
2138 .ops = &clk_regmap_mux_ops,
2139 .parent_data = s4_vapb_parents,
2140 .num_parents = ARRAY_SIZE(s4_vapb_parents),
2141 .flags = 0,
2142 },
2143};
2144
2145static struct clk_regmap s4_vapb_1_div = {
2146 .data = &(struct clk_regmap_div_data){
2147 .offset = CLKCTRL_VAPBCLK_CTRL,
2148 .shift = 16,
2149 .width = 7,
2150 },
2151 .hw.init = &(struct clk_init_data){
2152 .name = "vapb_1_div",
2153 .ops = &clk_regmap_divider_ops,
2154 .parent_hws = (const struct clk_hw *[]) {
2155 &s4_vapb_1_sel.hw
2156 },
2157 .num_parents = 1,
2158 .flags = CLK_SET_RATE_PARENT,
2159 },
2160};
2161
2162static struct clk_regmap s4_vapb_1 = {
2163 .data = &(struct clk_regmap_gate_data){
2164 .offset = CLKCTRL_VAPBCLK_CTRL,
2165 .bit_idx = 24,
2166 },
2167 .hw.init = &(struct clk_init_data) {
2168 .name = "vapb_1",
2169 .ops = &clk_regmap_gate_ops,
2170 .parent_hws = (const struct clk_hw *[]) {
2171 &s4_vapb_1_div.hw
2172 },
2173 .num_parents = 1,
2174 .flags = CLK_SET_RATE_PARENT,
2175 },
2176};
2177
2178static struct clk_regmap s4_vapb = {
2179 .data = &(struct clk_regmap_mux_data){
2180 .offset = CLKCTRL_VAPBCLK_CTRL,
2181 .mask = 1,
2182 .shift = 31,
2183 },
2184 .hw.init = &(struct clk_init_data){
2185 .name = "vapb_sel",
2186 .ops = &clk_regmap_mux_ops,
2187 .parent_hws = (const struct clk_hw *[]) {
2188 &s4_vapb_0.hw,
2189 &s4_vapb_1.hw
2190 },
2191 .num_parents = 2,
2192 .flags = CLK_SET_RATE_PARENT,
2193 },
2194};
2195
2196static struct clk_regmap s4_ge2d = {
2197 .data = &(struct clk_regmap_gate_data){
2198 .offset = CLKCTRL_VAPBCLK_CTRL,
2199 .bit_idx = 30,
2200 },
2201 .hw.init = &(struct clk_init_data) {
2202 .name = "ge2d",
2203 .ops = &clk_regmap_gate_ops,
2204 .parent_hws = (const struct clk_hw *[]) { &s4_vapb.hw },
2205 .num_parents = 1,
2206 .flags = CLK_SET_RATE_PARENT,
2207 },
2208};
2209
2210static const struct clk_parent_data s4_hdcp22_esmclk_parents[] = {
2211 { .fw_name = "fclk_div7", },
2212 { .fw_name = "fclk_div4", },
2213 { .fw_name = "fclk_div3", },
2214 { .fw_name = "fclk_div5", },
2215};
2216
2217static struct clk_regmap s4_hdcp22_esmclk_sel = {
2218 .data = &(struct clk_regmap_mux_data){
2219 .offset = CLKCTRL_HDCP22_CTRL,
2220 .mask = 0x3,
2221 .shift = 9,
2222 },
2223 .hw.init = &(struct clk_init_data) {
2224 .name = "hdcp22_esmclk_sel",
2225 .ops = &clk_regmap_mux_ops,
2226 .parent_data = s4_hdcp22_esmclk_parents,
2227 .num_parents = ARRAY_SIZE(s4_hdcp22_esmclk_parents),
2228 .flags = CLK_SET_RATE_PARENT,
2229 },
2230};
2231
2232static struct clk_regmap s4_hdcp22_esmclk_div = {
2233 .data = &(struct clk_regmap_div_data){
2234 .offset = CLKCTRL_HDCP22_CTRL,
2235 .shift = 0,
2236 .width = 7,
2237 },
2238 .hw.init = &(struct clk_init_data) {
2239 .name = "hdcp22_esmclk_div",
2240 .ops = &clk_regmap_divider_ops,
2241 .parent_hws = (const struct clk_hw *[]) {
2242 &s4_hdcp22_esmclk_sel.hw
2243 },
2244 .num_parents = 1,
2245 .flags = CLK_SET_RATE_PARENT,
2246 },
2247};
2248
2249static struct clk_regmap s4_hdcp22_esmclk = {
2250 .data = &(struct clk_regmap_gate_data){
2251 .offset = CLKCTRL_HDCP22_CTRL,
2252 .bit_idx = 8,
2253 },
2254 .hw.init = &(struct clk_init_data){
2255 .name = "hdcp22_esmclk",
2256 .ops = &clk_regmap_gate_ops,
2257 .parent_hws = (const struct clk_hw *[]) {
2258 &s4_hdcp22_esmclk_div.hw
2259 },
2260 .num_parents = 1,
2261 .flags = CLK_SET_RATE_PARENT,
2262 },
2263};
2264
2265static const struct clk_parent_data s4_hdcp22_skpclk_parents[] = {
2266 { .fw_name = "xtal", },
2267 { .fw_name = "fclk_div4", },
2268 { .fw_name = "fclk_div3", },
2269 { .fw_name = "fclk_div5", },
2270};
2271
2272static struct clk_regmap s4_hdcp22_skpclk_sel = {
2273 .data = &(struct clk_regmap_mux_data){
2274 .offset = CLKCTRL_HDCP22_CTRL,
2275 .mask = 0x3,
2276 .shift = 25,
2277 },
2278 .hw.init = &(struct clk_init_data) {
2279 .name = "hdcp22_skpclk_sel",
2280 .ops = &clk_regmap_mux_ops,
2281 .parent_data = s4_hdcp22_skpclk_parents,
2282 .num_parents = ARRAY_SIZE(s4_hdcp22_skpclk_parents),
2283 .flags = CLK_SET_RATE_PARENT,
2284 },
2285};
2286
2287static struct clk_regmap s4_hdcp22_skpclk_div = {
2288 .data = &(struct clk_regmap_div_data){
2289 .offset = CLKCTRL_HDCP22_CTRL,
2290 .shift = 16,
2291 .width = 7,
2292 },
2293 .hw.init = &(struct clk_init_data) {
2294 .name = "hdcp22_skpclk_div",
2295 .ops = &clk_regmap_divider_ops,
2296 .parent_hws = (const struct clk_hw *[]) {
2297 &s4_hdcp22_skpclk_sel.hw
2298 },
2299 .num_parents = 1,
2300 .flags = CLK_SET_RATE_PARENT,
2301 },
2302};
2303
2304static struct clk_regmap s4_hdcp22_skpclk = {
2305 .data = &(struct clk_regmap_gate_data){
2306 .offset = CLKCTRL_HDCP22_CTRL,
2307 .bit_idx = 24,
2308 },
2309 .hw.init = &(struct clk_init_data){
2310 .name = "hdcp22_skpclk",
2311 .ops = &clk_regmap_gate_ops,
2312 .parent_hws = (const struct clk_hw *[]) {
2313 &s4_hdcp22_skpclk_div.hw
2314 },
2315 .num_parents = 1,
2316 .flags = CLK_SET_RATE_PARENT,
2317 },
2318};
2319
2320static const struct clk_parent_data s4_vdin_parents[] = {
2321 { .fw_name = "xtal", },
2322 { .fw_name = "fclk_div4", },
2323 { .fw_name = "fclk_div3", },
2324 { .fw_name = "fclk_div5", },
2325 { .hw = &s4_vid_pll.hw }
2326};
2327
2328static struct clk_regmap s4_vdin_meas_sel = {
2329 .data = &(struct clk_regmap_mux_data){
2330 .offset = CLKCTRL_VDIN_MEAS_CLK_CTRL,
2331 .mask = 0x7,
2332 .shift = 9,
2333 },
2334 .hw.init = &(struct clk_init_data) {
2335 .name = "vdin_meas_sel",
2336 .ops = &clk_regmap_mux_ops,
2337 .parent_data = s4_vdin_parents,
2338 .num_parents = ARRAY_SIZE(s4_vdin_parents),
2339 .flags = CLK_SET_RATE_PARENT,
2340 },
2341};
2342
2343static struct clk_regmap s4_vdin_meas_div = {
2344 .data = &(struct clk_regmap_div_data){
2345 .offset = CLKCTRL_VDIN_MEAS_CLK_CTRL,
2346 .shift = 0,
2347 .width = 7,
2348 },
2349 .hw.init = &(struct clk_init_data) {
2350 .name = "vdin_meas_div",
2351 .ops = &clk_regmap_divider_ops,
2352 .parent_hws = (const struct clk_hw *[]) {
2353 &s4_vdin_meas_sel.hw
2354 },
2355 .num_parents = 1,
2356 .flags = CLK_SET_RATE_PARENT,
2357 },
2358};
2359
2360static struct clk_regmap s4_vdin_meas = {
2361 .data = &(struct clk_regmap_gate_data){
2362 .offset = CLKCTRL_VDIN_MEAS_CLK_CTRL,
2363 .bit_idx = 8,
2364 },
2365 .hw.init = &(struct clk_init_data){
2366 .name = "vdin_meas",
2367 .ops = &clk_regmap_gate_ops,
2368 .parent_hws = (const struct clk_hw *[]) {
2369 &s4_vdin_meas_div.hw
2370 },
2371 .num_parents = 1,
2372 .flags = CLK_SET_RATE_PARENT,
2373 },
2374};
2375
2376/* EMMC/NAND clock */
2377static const struct clk_parent_data s4_sd_emmc_clk0_parents[] = {
2378 { .fw_name = "xtal", },
2379 { .fw_name = "fclk_div2", },
2380 { .fw_name = "fclk_div3", },
2381 { .fw_name = "hifi_pll", },
2382 { .fw_name = "fclk_div2p5", },
2383 { .fw_name = "mpll2", },
2384 { .fw_name = "mpll3", },
2385 { .fw_name = "gp0_pll", },
2386};
2387
2388static struct clk_regmap s4_sd_emmc_c_clk0_sel = {
2389 .data = &(struct clk_regmap_mux_data){
2390 .offset = CLKCTRL_NAND_CLK_CTRL,
2391 .mask = 0x7,
2392 .shift = 9,
2393 },
2394 .hw.init = &(struct clk_init_data) {
2395 .name = "sd_emmc_c_clk0_sel",
2396 .ops = &clk_regmap_mux_ops,
2397 .parent_data = s4_sd_emmc_clk0_parents,
2398 .num_parents = ARRAY_SIZE(s4_sd_emmc_clk0_parents),
2399 .flags = 0,
2400 },
2401};
2402
2403static struct clk_regmap s4_sd_emmc_c_clk0_div = {
2404 .data = &(struct clk_regmap_div_data){
2405 .offset = CLKCTRL_NAND_CLK_CTRL,
2406 .shift = 0,
2407 .width = 7,
2408 },
2409 .hw.init = &(struct clk_init_data) {
2410 .name = "sd_emmc_c_clk0_div",
2411 .ops = &clk_regmap_divider_ops,
2412 .parent_hws = (const struct clk_hw *[]) {
2413 &s4_sd_emmc_c_clk0_sel.hw
2414 },
2415 .num_parents = 1,
2416 .flags = CLK_SET_RATE_PARENT,
2417 },
2418};
2419
2420static struct clk_regmap s4_sd_emmc_c_clk0 = {
2421 .data = &(struct clk_regmap_gate_data){
2422 .offset = CLKCTRL_NAND_CLK_CTRL,
2423 .bit_idx = 7,
2424 },
2425 .hw.init = &(struct clk_init_data){
2426 .name = "sd_emmc_c_clk0",
2427 .ops = &clk_regmap_gate_ops,
2428 .parent_hws = (const struct clk_hw *[]) {
2429 &s4_sd_emmc_c_clk0_div.hw
2430 },
2431 .num_parents = 1,
2432 .flags = CLK_SET_RATE_PARENT,
2433 },
2434};
2435
2436static struct clk_regmap s4_sd_emmc_a_clk0_sel = {
2437 .data = &(struct clk_regmap_mux_data){
2438 .offset = CLKCTRL_SD_EMMC_CLK_CTRL,
2439 .mask = 0x7,
2440 .shift = 9,
2441 },
2442 .hw.init = &(struct clk_init_data) {
2443 .name = "sd_emmc_a_clk0_sel",
2444 .ops = &clk_regmap_mux_ops,
2445 .parent_data = s4_sd_emmc_clk0_parents,
2446 .num_parents = ARRAY_SIZE(s4_sd_emmc_clk0_parents),
2447 .flags = 0,
2448 },
2449};
2450
2451static struct clk_regmap s4_sd_emmc_a_clk0_div = {
2452 .data = &(struct clk_regmap_div_data){
2453 .offset = CLKCTRL_SD_EMMC_CLK_CTRL,
2454 .shift = 0,
2455 .width = 7,
2456 },
2457 .hw.init = &(struct clk_init_data) {
2458 .name = "sd_emmc_a_clk0_div",
2459 .ops = &clk_regmap_divider_ops,
2460 .parent_hws = (const struct clk_hw *[]) {
2461 &s4_sd_emmc_a_clk0_sel.hw
2462 },
2463 .num_parents = 1,
2464 .flags = CLK_SET_RATE_PARENT,
2465 },
2466};
2467
2468static struct clk_regmap s4_sd_emmc_a_clk0 = {
2469 .data = &(struct clk_regmap_gate_data){
2470 .offset = CLKCTRL_SD_EMMC_CLK_CTRL,
2471 .bit_idx = 7,
2472 },
2473 .hw.init = &(struct clk_init_data){
2474 .name = "sd_emmc_a_clk0",
2475 .ops = &clk_regmap_gate_ops,
2476 .parent_hws = (const struct clk_hw *[]) {
2477 &s4_sd_emmc_a_clk0_div.hw
2478 },
2479 .num_parents = 1,
2480 .flags = CLK_SET_RATE_PARENT,
2481 },
2482};
2483
2484static struct clk_regmap s4_sd_emmc_b_clk0_sel = {
2485 .data = &(struct clk_regmap_mux_data){
2486 .offset = CLKCTRL_SD_EMMC_CLK_CTRL,
2487 .mask = 0x7,
2488 .shift = 25,
2489 },
2490 .hw.init = &(struct clk_init_data) {
2491 .name = "sd_emmc_b_clk0_sel",
2492 .ops = &clk_regmap_mux_ops,
2493 .parent_data = s4_sd_emmc_clk0_parents,
2494 .num_parents = ARRAY_SIZE(s4_sd_emmc_clk0_parents),
2495 .flags = 0,
2496 },
2497};
2498
2499static struct clk_regmap s4_sd_emmc_b_clk0_div = {
2500 .data = &(struct clk_regmap_div_data){
2501 .offset = CLKCTRL_SD_EMMC_CLK_CTRL,
2502 .shift = 16,
2503 .width = 7,
2504 },
2505 .hw.init = &(struct clk_init_data) {
2506 .name = "sd_emmc_b_clk0_div",
2507 .ops = &clk_regmap_divider_ops,
2508 .parent_hws = (const struct clk_hw *[]) {
2509 &s4_sd_emmc_b_clk0_sel.hw
2510 },
2511 .num_parents = 1,
2512 .flags = CLK_SET_RATE_PARENT,
2513 },
2514};
2515
2516static struct clk_regmap s4_sd_emmc_b_clk0 = {
2517 .data = &(struct clk_regmap_gate_data){
2518 .offset = CLKCTRL_SD_EMMC_CLK_CTRL,
2519 .bit_idx = 23,
2520 },
2521 .hw.init = &(struct clk_init_data){
2522 .name = "sd_emmc_b_clk0",
2523 .ops = &clk_regmap_gate_ops,
2524 .parent_hws = (const struct clk_hw *[]) {
2525 &s4_sd_emmc_b_clk0_div.hw
2526 },
2527 .num_parents = 1,
2528 .flags = CLK_SET_RATE_PARENT,
2529 },
2530};
2531
2532/* SPICC Clock */
2533static const struct clk_parent_data s4_spicc_parents[] = {
2534 { .fw_name = "xtal", },
2535 { .hw = &s4_sys_clk.hw },
2536 { .fw_name = "fclk_div4", },
2537 { .fw_name = "fclk_div3", },
2538 { .fw_name = "fclk_div2", },
2539 { .fw_name = "fclk_div5", },
2540 { .fw_name = "fclk_div7", },
2541};
2542
2543static struct clk_regmap s4_spicc0_sel = {
2544 .data = &(struct clk_regmap_mux_data){
2545 .offset = CLKCTRL_SPICC_CLK_CTRL,
2546 .mask = 0x7,
2547 .shift = 7,
2548 },
2549 .hw.init = &(struct clk_init_data) {
2550 .name = "spicc0_sel",
2551 .ops = &clk_regmap_mux_ops,
2552 .parent_data = s4_spicc_parents,
2553 .num_parents = ARRAY_SIZE(s4_spicc_parents),
2554 .flags = CLK_SET_RATE_PARENT,
2555 },
2556};
2557
2558static struct clk_regmap s4_spicc0_div = {
2559 .data = &(struct clk_regmap_div_data){
2560 .offset = CLKCTRL_SPICC_CLK_CTRL,
2561 .shift = 0,
2562 .width = 6,
2563 },
2564 .hw.init = &(struct clk_init_data) {
2565 .name = "spicc0_div",
2566 .ops = &clk_regmap_divider_ops,
2567 .parent_hws = (const struct clk_hw *[]) {
2568 &s4_spicc0_sel.hw
2569 },
2570 .num_parents = 1,
2571 .flags = CLK_SET_RATE_PARENT,
2572 },
2573};
2574
2575static struct clk_regmap s4_spicc0_en = {
2576 .data = &(struct clk_regmap_gate_data){
2577 .offset = CLKCTRL_SPICC_CLK_CTRL,
2578 .bit_idx = 6,
2579 },
2580 .hw.init = &(struct clk_init_data){
2581 .name = "spicc0_en",
2582 .ops = &clk_regmap_gate_ops,
2583 .parent_hws = (const struct clk_hw *[]) {
2584 &s4_spicc0_div.hw
2585 },
2586 .num_parents = 1,
2587 .flags = CLK_SET_RATE_PARENT,
2588 },
2589};
2590
2591/* PWM Clock */
2592static const struct clk_parent_data s4_pwm_parents[] = {
2593 { .fw_name = "xtal", },
2594 { .hw = &s4_vid_pll.hw },
2595 { .fw_name = "fclk_div4", },
2596 { .fw_name = "fclk_div3", },
2597};
2598
2599static S4_COMP_SEL(pwm_a, CLKCTRL_PWM_CLK_AB_CTRL, 9, 0x3, s4_pwm_parents);
2600static S4_COMP_DIV(pwm_a, CLKCTRL_PWM_CLK_AB_CTRL, 0, 8);
2601static S4_COMP_GATE(pwm_a, CLKCTRL_PWM_CLK_AB_CTRL, 8);
2602
2603static S4_COMP_SEL(pwm_b, CLKCTRL_PWM_CLK_AB_CTRL, 25, 0x3, s4_pwm_parents);
2604static S4_COMP_DIV(pwm_b, CLKCTRL_PWM_CLK_AB_CTRL, 16, 8);
2605static S4_COMP_GATE(pwm_b, CLKCTRL_PWM_CLK_AB_CTRL, 24);
2606
2607static S4_COMP_SEL(pwm_c, CLKCTRL_PWM_CLK_CD_CTRL, 9, 0x3, s4_pwm_parents);
2608static S4_COMP_DIV(pwm_c, CLKCTRL_PWM_CLK_CD_CTRL, 0, 8);
2609static S4_COMP_GATE(pwm_c, CLKCTRL_PWM_CLK_CD_CTRL, 8);
2610
2611static S4_COMP_SEL(pwm_d, CLKCTRL_PWM_CLK_CD_CTRL, 25, 0x3, s4_pwm_parents);
2612static S4_COMP_DIV(pwm_d, CLKCTRL_PWM_CLK_CD_CTRL, 16, 8);
2613static S4_COMP_GATE(pwm_d, CLKCTRL_PWM_CLK_CD_CTRL, 24);
2614
2615static S4_COMP_SEL(pwm_e, CLKCTRL_PWM_CLK_EF_CTRL, 9, 0x3, s4_pwm_parents);
2616static S4_COMP_DIV(pwm_e, CLKCTRL_PWM_CLK_EF_CTRL, 0, 8);
2617static S4_COMP_GATE(pwm_e, CLKCTRL_PWM_CLK_EF_CTRL, 8);
2618
2619static S4_COMP_SEL(pwm_f, CLKCTRL_PWM_CLK_EF_CTRL, 25, 0x3, s4_pwm_parents);
2620static S4_COMP_DIV(pwm_f, CLKCTRL_PWM_CLK_EF_CTRL, 16, 8);
2621static S4_COMP_GATE(pwm_f, CLKCTRL_PWM_CLK_EF_CTRL, 24);
2622
2623static S4_COMP_SEL(pwm_g, CLKCTRL_PWM_CLK_GH_CTRL, 9, 0x3, s4_pwm_parents);
2624static S4_COMP_DIV(pwm_g, CLKCTRL_PWM_CLK_GH_CTRL, 0, 8);
2625static S4_COMP_GATE(pwm_g, CLKCTRL_PWM_CLK_GH_CTRL, 8);
2626
2627static S4_COMP_SEL(pwm_h, CLKCTRL_PWM_CLK_GH_CTRL, 25, 0x3, s4_pwm_parents);
2628static S4_COMP_DIV(pwm_h, CLKCTRL_PWM_CLK_GH_CTRL, 16, 8);
2629static S4_COMP_GATE(pwm_h, CLKCTRL_PWM_CLK_GH_CTRL, 24);
2630
2631static S4_COMP_SEL(pwm_i, CLKCTRL_PWM_CLK_IJ_CTRL, 9, 0x3, s4_pwm_parents);
2632static S4_COMP_DIV(pwm_i, CLKCTRL_PWM_CLK_IJ_CTRL, 0, 8);
2633static S4_COMP_GATE(pwm_i, CLKCTRL_PWM_CLK_IJ_CTRL, 8);
2634
2635static S4_COMP_SEL(pwm_j, CLKCTRL_PWM_CLK_IJ_CTRL, 25, 0x3, s4_pwm_parents);
2636static S4_COMP_DIV(pwm_j, CLKCTRL_PWM_CLK_IJ_CTRL, 16, 8);
2637static S4_COMP_GATE(pwm_j, CLKCTRL_PWM_CLK_IJ_CTRL, 24);
2638
2639static struct clk_regmap s4_saradc_sel = {
2640 .data = &(struct clk_regmap_mux_data) {
2641 .offset = CLKCTRL_SAR_CLK_CTRL,
2642 .mask = 0x3,
2643 .shift = 9,
2644 },
2645 .hw.init = &(struct clk_init_data){
2646 .name = "saradc_sel",
2647 .ops = &clk_regmap_mux_ops,
2648 .parent_data = (const struct clk_parent_data []) {
2649 { .fw_name = "xtal", },
2650 { .hw = &s4_sys_clk.hw },
2651 },
2652 .num_parents = 2,
2653 .flags = CLK_SET_RATE_PARENT,
2654 },
2655};
2656
2657static struct clk_regmap s4_saradc_div = {
2658 .data = &(struct clk_regmap_div_data) {
2659 .offset = CLKCTRL_SAR_CLK_CTRL,
2660 .shift = 0,
2661 .width = 8,
2662 },
2663 .hw.init = &(struct clk_init_data){
2664 .name = "saradc_div",
2665 .ops = &clk_regmap_divider_ops,
2666 .parent_hws = (const struct clk_hw *[]) {
2667 &s4_saradc_sel.hw
2668 },
2669 .num_parents = 1,
2670 .flags = CLK_SET_RATE_PARENT,
2671 },
2672};
2673
2674static struct clk_regmap s4_saradc = {
2675 .data = &(struct clk_regmap_gate_data) {
2676 .offset = CLKCTRL_SAR_CLK_CTRL,
2677 .bit_idx = 8,
2678 },
2679 .hw.init = &(struct clk_init_data){
2680 .name = "saradc",
2681 .ops = &clk_regmap_gate_ops,
2682 .parent_hws = (const struct clk_hw *[]) {
2683 &s4_saradc_div.hw
2684 },
2685 .num_parents = 1,
2686 .flags = CLK_SET_RATE_PARENT,
2687 },
2688};
2689
2690/*
2691 * gen clk is designed for debug/monitor some internal clock quality. Some of the
2692 * corresponding clock sources are not described in the clock tree and internal clock
2693 * for debug, so they are skipped.
2694 */
2695static u32 s4_gen_clk_parents_val_table[] = { 0, 4, 5, 7, 19, 21, 22, 23, 24, 25, 26, 27, 28 };
2696static const struct clk_parent_data s4_gen_clk_parents[] = {
2697 { .fw_name = "xtal", },
2698 { .hw = &s4_vid_pll.hw },
2699 { .fw_name = "gp0_pll", },
2700 { .fw_name = "hifi_pll", },
2701 { .fw_name = "fclk_div2", },
2702 { .fw_name = "fclk_div3", },
2703 { .fw_name = "fclk_div4", },
2704 { .fw_name = "fclk_div5", },
2705 { .fw_name = "fclk_div7", },
2706 { .fw_name = "mpll0", },
2707 { .fw_name = "mpll1", },
2708 { .fw_name = "mpll2", },
2709 { .fw_name = "mpll3", },
2710};
2711
2712static struct clk_regmap s4_gen_clk_sel = {
2713 .data = &(struct clk_regmap_mux_data){
2714 .offset = CLKCTRL_GEN_CLK_CTRL,
2715 .mask = 0x1f,
2716 .shift = 12,
2717 .table = s4_gen_clk_parents_val_table,
2718 },
2719 .hw.init = &(struct clk_init_data){
2720 .name = "gen_clk_sel",
2721 .ops = &clk_regmap_mux_ops,
2722 .parent_data = s4_gen_clk_parents,
2723 .num_parents = ARRAY_SIZE(s4_gen_clk_parents),
2724 /*
2725 * Because the GEN clock can be connected to an external pad
2726 * and may be set up directly from the device tree. Don't
2727 * really want to automatically reparent.
2728 */
2729 .flags = CLK_SET_RATE_NO_REPARENT,
2730 },
2731};
2732
2733static struct clk_regmap s4_gen_clk_div = {
2734 .data = &(struct clk_regmap_div_data){
2735 .offset = CLKCTRL_GEN_CLK_CTRL,
2736 .shift = 0,
2737 .width = 11,
2738 },
2739 .hw.init = &(struct clk_init_data){
2740 .name = "gen_clk_div",
2741 .ops = &clk_regmap_divider_ops,
2742 .parent_hws = (const struct clk_hw *[]) {
2743 &s4_gen_clk_sel.hw
2744 },
2745 .num_parents = 1,
2746 .flags = CLK_SET_RATE_PARENT,
2747 },
2748};
2749
2750static struct clk_regmap s4_gen_clk = {
2751 .data = &(struct clk_regmap_gate_data){
2752 .offset = CLKCTRL_GEN_CLK_CTRL,
2753 .bit_idx = 11,
2754 },
2755 .hw.init = &(struct clk_init_data) {
2756 .name = "gen_clk",
2757 .ops = &clk_regmap_gate_ops,
2758 .parent_hws = (const struct clk_hw *[]) {
2759 &s4_gen_clk_div.hw
2760 },
2761 .num_parents = 1,
2762 .flags = CLK_SET_RATE_PARENT,
2763 },
2764};
2765
2766/* CVBS DAC */
2767static struct clk_regmap s4_cdac_sel = {
2768 .data = &(struct clk_regmap_mux_data) {
2769 .offset = CLKCTRL_CDAC_CLK_CTRL,
2770 .mask = 0x3,
2771 .shift = 16,
2772 },
2773 .hw.init = &(struct clk_init_data){
2774 .name = "cdac_sel",
2775 .ops = &clk_regmap_mux_ops,
2776 .parent_data = (const struct clk_parent_data []) {
2777 { .fw_name = "xtal", },
2778 { .fw_name = "fclk_div5" },
2779 },
2780 .num_parents = 2,
2781 },
2782};
2783
2784static struct clk_regmap s4_cdac_div = {
2785 .data = &(struct clk_regmap_div_data) {
2786 .offset = CLKCTRL_CDAC_CLK_CTRL,
2787 .shift = 0,
2788 .width = 16,
2789 },
2790 .hw.init = &(struct clk_init_data){
2791 .name = "cdac_div",
2792 .ops = &clk_regmap_divider_ops,
2793 .parent_hws = (const struct clk_hw *[]) {
2794 &s4_cdac_sel.hw
2795 },
2796 .num_parents = 1,
2797 .flags = CLK_SET_RATE_PARENT,
2798 },
2799};
2800
2801static struct clk_regmap s4_cdac = {
2802 .data = &(struct clk_regmap_gate_data) {
2803 .offset = CLKCTRL_CDAC_CLK_CTRL,
2804 .bit_idx = 20,
2805 },
2806 .hw.init = &(struct clk_init_data){
2807 .name = "cdac",
2808 .ops = &clk_regmap_gate_ops,
2809 .parent_hws = (const struct clk_hw *[]) {
2810 &s4_cdac_div.hw
2811 },
2812 .num_parents = 1,
2813 .flags = CLK_SET_RATE_PARENT,
2814 },
2815};
2816
2817static struct clk_regmap s4_demod_core_sel = {
2818 .data = &(struct clk_regmap_mux_data) {
2819 .offset = CLKCTRL_DEMOD_CLK_CTRL,
2820 .mask = 0x3,
2821 .shift = 9,
2822 },
2823 .hw.init = &(struct clk_init_data){
2824 .name = "demod_core_sel",
2825 .ops = &clk_regmap_mux_ops,
2826 .parent_data = (const struct clk_parent_data []) {
2827 { .fw_name = "xtal" },
2828 { .fw_name = "fclk_div7" },
2829 { .fw_name = "fclk_div4" }
2830 },
2831 .num_parents = 3,
2832 },
2833};
2834
2835static struct clk_regmap s4_demod_core_div = {
2836 .data = &(struct clk_regmap_div_data) {
2837 .offset = CLKCTRL_DEMOD_CLK_CTRL,
2838 .shift = 0,
2839 .width = 7,
2840 },
2841 .hw.init = &(struct clk_init_data){
2842 .name = "demod_core_div",
2843 .ops = &clk_regmap_divider_ops,
2844 .parent_hws = (const struct clk_hw *[]) {
2845 &s4_demod_core_sel.hw
2846 },
2847 .num_parents = 1,
2848 .flags = CLK_SET_RATE_PARENT,
2849 },
2850};
2851
2852static struct clk_regmap s4_demod_core = {
2853 .data = &(struct clk_regmap_gate_data) {
2854 .offset = CLKCTRL_DEMOD_CLK_CTRL,
2855 .bit_idx = 8
2856 },
2857 .hw.init = &(struct clk_init_data){
2858 .name = "demod_core",
2859 .ops = &clk_regmap_gate_ops,
2860 .parent_hws = (const struct clk_hw *[]) {
2861 &s4_demod_core_div.hw
2862 },
2863 .num_parents = 1,
2864 .flags = CLK_SET_RATE_PARENT,
2865 },
2866};
2867
2868/* CVBS ADC */
2869static struct clk_regmap s4_adc_extclk_in_sel = {
2870 .data = &(struct clk_regmap_mux_data) {
2871 .offset = CLKCTRL_DEMOD_CLK_CTRL,
2872 .mask = 0x7,
2873 .shift = 25,
2874 },
2875 .hw.init = &(struct clk_init_data){
2876 .name = "adc_extclk_in_sel",
2877 .ops = &clk_regmap_mux_ops,
2878 .parent_data = (const struct clk_parent_data []) {
2879 { .fw_name = "xtal" },
2880 { .fw_name = "fclk_div4" },
2881 { .fw_name = "fclk_div3" },
2882 { .fw_name = "fclk_div5" },
2883 { .fw_name = "fclk_div7" },
2884 { .fw_name = "mpll2" },
2885 { .fw_name = "gp0_pll" },
2886 { .fw_name = "hifi_pll" }
2887 },
2888 .num_parents = 8,
2889 },
2890};
2891
2892static struct clk_regmap s4_adc_extclk_in_div = {
2893 .data = &(struct clk_regmap_div_data) {
2894 .offset = CLKCTRL_DEMOD_CLK_CTRL,
2895 .shift = 16,
2896 .width = 7,
2897 },
2898 .hw.init = &(struct clk_init_data){
2899 .name = "adc_extclk_in_div",
2900 .ops = &clk_regmap_divider_ops,
2901 .parent_hws = (const struct clk_hw *[]) {
2902 &s4_adc_extclk_in_sel.hw
2903 },
2904 .num_parents = 1,
2905 .flags = CLK_SET_RATE_PARENT,
2906 },
2907};
2908
2909static struct clk_regmap s4_adc_extclk_in = {
2910 .data = &(struct clk_regmap_gate_data) {
2911 .offset = CLKCTRL_DEMOD_CLK_CTRL,
2912 .bit_idx = 24
2913 },
2914 .hw.init = &(struct clk_init_data){
2915 .name = "adc_extclk_in",
2916 .ops = &clk_regmap_gate_ops,
2917 .parent_hws = (const struct clk_hw *[]) {
2918 &s4_adc_extclk_in_div.hw
2919 },
2920 .num_parents = 1,
2921 .flags = CLK_SET_RATE_PARENT,
2922 },
2923};
2924
2925static const struct clk_parent_data s4_pclk_parents = { .hw = &s4_sys_clk.hw };
2926
2927#define S4_PCLK(_name, _reg, _bit, _flags) \
2928 MESON_PCLK(_name, _reg, _bit, &s4_pclk_parents, _flags)
2929
2930/*
2931 * NOTE: The gates below are marked with CLK_IGNORE_UNUSED for historic reasons
2932 * Users are encouraged to test without it and submit changes to:
2933 * - remove the flag if not necessary
2934 * - replace the flag with something more adequate, such as CLK_IS_CRITICAL,
2935 * if appropriate.
2936 * - add a comment explaining why the use of CLK_IGNORE_UNUSED is desirable
2937 * for a particular clock.
2938 */
2939static S4_PCLK(s4_ddr, CLKCTRL_SYS_CLK_EN0_REG0, 0, CLK_IGNORE_UNUSED);
2940static S4_PCLK(s4_dos, CLKCTRL_SYS_CLK_EN0_REG0, 1, CLK_IGNORE_UNUSED);
2941static S4_PCLK(s4_ethphy, CLKCTRL_SYS_CLK_EN0_REG0, 4, CLK_IGNORE_UNUSED);
2942static S4_PCLK(s4_mali, CLKCTRL_SYS_CLK_EN0_REG0, 6, CLK_IGNORE_UNUSED);
2943static S4_PCLK(s4_aocpu, CLKCTRL_SYS_CLK_EN0_REG0, 13, CLK_IGNORE_UNUSED);
2944static S4_PCLK(s4_aucpu, CLKCTRL_SYS_CLK_EN0_REG0, 14, CLK_IGNORE_UNUSED);
2945static S4_PCLK(s4_cec, CLKCTRL_SYS_CLK_EN0_REG0, 16, CLK_IGNORE_UNUSED);
2946static S4_PCLK(s4_sdemmca, CLKCTRL_SYS_CLK_EN0_REG0, 24, CLK_IGNORE_UNUSED);
2947static S4_PCLK(s4_sdemmcb, CLKCTRL_SYS_CLK_EN0_REG0, 25, CLK_IGNORE_UNUSED);
2948static S4_PCLK(s4_nand, CLKCTRL_SYS_CLK_EN0_REG0, 26, CLK_IGNORE_UNUSED);
2949static S4_PCLK(s4_smartcard, CLKCTRL_SYS_CLK_EN0_REG0, 27, CLK_IGNORE_UNUSED);
2950static S4_PCLK(s4_acodec, CLKCTRL_SYS_CLK_EN0_REG0, 28, CLK_IGNORE_UNUSED);
2951static S4_PCLK(s4_spifc, CLKCTRL_SYS_CLK_EN0_REG0, 29, CLK_IGNORE_UNUSED);
2952static S4_PCLK(s4_msr_clk, CLKCTRL_SYS_CLK_EN0_REG0, 30, CLK_IGNORE_UNUSED);
2953static S4_PCLK(s4_ir_ctrl, CLKCTRL_SYS_CLK_EN0_REG0, 31, CLK_IGNORE_UNUSED);
2954
2955static S4_PCLK(s4_audio, CLKCTRL_SYS_CLK_EN0_REG1, 0, CLK_IGNORE_UNUSED);
2956static S4_PCLK(s4_eth, CLKCTRL_SYS_CLK_EN0_REG1, 3, CLK_IGNORE_UNUSED);
2957static S4_PCLK(s4_uart_a, CLKCTRL_SYS_CLK_EN0_REG1, 5, CLK_IGNORE_UNUSED);
2958static S4_PCLK(s4_uart_b, CLKCTRL_SYS_CLK_EN0_REG1, 6, CLK_IGNORE_UNUSED);
2959static S4_PCLK(s4_uart_c, CLKCTRL_SYS_CLK_EN0_REG1, 7, CLK_IGNORE_UNUSED);
2960static S4_PCLK(s4_uart_d, CLKCTRL_SYS_CLK_EN0_REG1, 8, CLK_IGNORE_UNUSED);
2961static S4_PCLK(s4_uart_e, CLKCTRL_SYS_CLK_EN0_REG1, 9, CLK_IGNORE_UNUSED);
2962static S4_PCLK(s4_aififo, CLKCTRL_SYS_CLK_EN0_REG1, 11, CLK_IGNORE_UNUSED);
2963static S4_PCLK(s4_ts_ddr, CLKCTRL_SYS_CLK_EN0_REG1, 15, CLK_IGNORE_UNUSED);
2964static S4_PCLK(s4_ts_pll, CLKCTRL_SYS_CLK_EN0_REG1, 16, CLK_IGNORE_UNUSED);
2965static S4_PCLK(s4_g2d, CLKCTRL_SYS_CLK_EN0_REG1, 20, CLK_IGNORE_UNUSED);
2966static S4_PCLK(s4_spicc0, CLKCTRL_SYS_CLK_EN0_REG1, 21, CLK_IGNORE_UNUSED);
2967static S4_PCLK(s4_usb, CLKCTRL_SYS_CLK_EN0_REG1, 26, CLK_IGNORE_UNUSED);
2968static S4_PCLK(s4_i2c_m_a, CLKCTRL_SYS_CLK_EN0_REG1, 30, CLK_IGNORE_UNUSED);
2969static S4_PCLK(s4_i2c_m_b, CLKCTRL_SYS_CLK_EN0_REG1, 31, CLK_IGNORE_UNUSED);
2970
2971static S4_PCLK(s4_i2c_m_c, CLKCTRL_SYS_CLK_EN0_REG2, 0, CLK_IGNORE_UNUSED);
2972static S4_PCLK(s4_i2c_m_d, CLKCTRL_SYS_CLK_EN0_REG2, 1, CLK_IGNORE_UNUSED);
2973static S4_PCLK(s4_i2c_m_e, CLKCTRL_SYS_CLK_EN0_REG2, 2, CLK_IGNORE_UNUSED);
2974static S4_PCLK(s4_hdmitx_apb, CLKCTRL_SYS_CLK_EN0_REG2, 4, CLK_IGNORE_UNUSED);
2975static S4_PCLK(s4_i2c_s_a, CLKCTRL_SYS_CLK_EN0_REG2, 5, CLK_IGNORE_UNUSED);
2976static S4_PCLK(s4_usb1_to_ddr, CLKCTRL_SYS_CLK_EN0_REG2, 8, CLK_IGNORE_UNUSED);
2977static S4_PCLK(s4_hdcp22, CLKCTRL_SYS_CLK_EN0_REG2, 10, CLK_IGNORE_UNUSED);
2978static S4_PCLK(s4_mmc_apb, CLKCTRL_SYS_CLK_EN0_REG2, 11, CLK_IGNORE_UNUSED);
2979static S4_PCLK(s4_rsa, CLKCTRL_SYS_CLK_EN0_REG2, 18, CLK_IGNORE_UNUSED);
2980static S4_PCLK(s4_cpu_debug, CLKCTRL_SYS_CLK_EN0_REG2, 19, CLK_IGNORE_UNUSED);
2981static S4_PCLK(s4_vpu_intr, CLKCTRL_SYS_CLK_EN0_REG2, 25, CLK_IGNORE_UNUSED);
2982static S4_PCLK(s4_demod, CLKCTRL_SYS_CLK_EN0_REG2, 27, CLK_IGNORE_UNUSED);
2983static S4_PCLK(s4_sar_adc, CLKCTRL_SYS_CLK_EN0_REG2, 28, CLK_IGNORE_UNUSED);
2984static S4_PCLK(s4_gic, CLKCTRL_SYS_CLK_EN0_REG2, 30, CLK_IGNORE_UNUSED);
2985
2986static S4_PCLK(s4_pwm_ab, CLKCTRL_SYS_CLK_EN0_REG3, 7, CLK_IGNORE_UNUSED);
2987static S4_PCLK(s4_pwm_cd, CLKCTRL_SYS_CLK_EN0_REG3, 8, CLK_IGNORE_UNUSED);
2988static S4_PCLK(s4_pwm_ef, CLKCTRL_SYS_CLK_EN0_REG3, 9, CLK_IGNORE_UNUSED);
2989static S4_PCLK(s4_pwm_gh, CLKCTRL_SYS_CLK_EN0_REG3, 10, CLK_IGNORE_UNUSED);
2990static S4_PCLK(s4_pwm_ij, CLKCTRL_SYS_CLK_EN0_REG3, 11, CLK_IGNORE_UNUSED);
2991
2992/* Array of all clocks provided by this provider */
2993static struct clk_hw *s4_peripherals_hw_clks[] = {
2994 [CLKID_RTC_32K_CLKIN] = &s4_rtc_32k_by_oscin_clkin.hw,
2995 [CLKID_RTC_32K_DIV] = &s4_rtc_32k_by_oscin_div.hw,
2996 [CLKID_RTC_32K_SEL] = &s4_rtc_32k_by_oscin_sel.hw,
2997 [CLKID_RTC_32K_XATL] = &s4_rtc_32k_by_oscin.hw,
2998 [CLKID_RTC] = &s4_rtc_clk.hw,
2999 [CLKID_SYS_CLK_B_SEL] = &s4_sysclk_b_sel.hw,
3000 [CLKID_SYS_CLK_B_DIV] = &s4_sysclk_b_div.hw,
3001 [CLKID_SYS_CLK_B] = &s4_sysclk_b.hw,
3002 [CLKID_SYS_CLK_A_SEL] = &s4_sysclk_a_sel.hw,
3003 [CLKID_SYS_CLK_A_DIV] = &s4_sysclk_a_div.hw,
3004 [CLKID_SYS_CLK_A] = &s4_sysclk_a.hw,
3005 [CLKID_SYS] = &s4_sys_clk.hw,
3006 [CLKID_CECA_32K_CLKIN] = &s4_ceca_32k_clkin.hw,
3007 [CLKID_CECA_32K_DIV] = &s4_ceca_32k_div.hw,
3008 [CLKID_CECA_32K_SEL_PRE] = &s4_ceca_32k_sel_pre.hw,
3009 [CLKID_CECA_32K_SEL] = &s4_ceca_32k_sel.hw,
3010 [CLKID_CECA_32K_CLKOUT] = &s4_ceca_32k_clkout.hw,
3011 [CLKID_CECB_32K_CLKIN] = &s4_cecb_32k_clkin.hw,
3012 [CLKID_CECB_32K_DIV] = &s4_cecb_32k_div.hw,
3013 [CLKID_CECB_32K_SEL_PRE] = &s4_cecb_32k_sel_pre.hw,
3014 [CLKID_CECB_32K_SEL] = &s4_cecb_32k_sel.hw,
3015 [CLKID_CECB_32K_CLKOUT] = &s4_cecb_32k_clkout.hw,
3016 [CLKID_SC_CLK_SEL] = &s4_sc_clk_sel.hw,
3017 [CLKID_SC_CLK_DIV] = &s4_sc_clk_div.hw,
3018 [CLKID_SC] = &s4_sc_clk.hw,
3019 [CLKID_12_24M] = &s4_12_24M.hw,
3020 [CLKID_12M_CLK_DIV] = &s4_12M_div.hw,
3021 [CLKID_12_24M_CLK_SEL] = &s4_12_24M_sel.hw,
3022 [CLKID_VID_PLL_DIV] = &s4_vid_pll_div.hw,
3023 [CLKID_VID_PLL_SEL] = &s4_vid_pll_sel.hw,
3024 [CLKID_VID_PLL] = &s4_vid_pll.hw,
3025 [CLKID_VCLK_SEL] = &s4_vclk_sel.hw,
3026 [CLKID_VCLK2_SEL] = &s4_vclk2_sel.hw,
3027 [CLKID_VCLK_INPUT] = &s4_vclk_input.hw,
3028 [CLKID_VCLK2_INPUT] = &s4_vclk2_input.hw,
3029 [CLKID_VCLK_DIV] = &s4_vclk_div.hw,
3030 [CLKID_VCLK2_DIV] = &s4_vclk2_div.hw,
3031 [CLKID_VCLK] = &s4_vclk.hw,
3032 [CLKID_VCLK2] = &s4_vclk2.hw,
3033 [CLKID_VCLK_DIV1] = &s4_vclk_div1.hw,
3034 [CLKID_VCLK_DIV2_EN] = &s4_vclk_div2_en.hw,
3035 [CLKID_VCLK_DIV4_EN] = &s4_vclk_div4_en.hw,
3036 [CLKID_VCLK_DIV6_EN] = &s4_vclk_div6_en.hw,
3037 [CLKID_VCLK_DIV12_EN] = &s4_vclk_div12_en.hw,
3038 [CLKID_VCLK2_DIV1] = &s4_vclk2_div1.hw,
3039 [CLKID_VCLK2_DIV2_EN] = &s4_vclk2_div2_en.hw,
3040 [CLKID_VCLK2_DIV4_EN] = &s4_vclk2_div4_en.hw,
3041 [CLKID_VCLK2_DIV6_EN] = &s4_vclk2_div6_en.hw,
3042 [CLKID_VCLK2_DIV12_EN] = &s4_vclk2_div12_en.hw,
3043 [CLKID_VCLK_DIV2] = &s4_vclk_div2.hw,
3044 [CLKID_VCLK_DIV4] = &s4_vclk_div4.hw,
3045 [CLKID_VCLK_DIV6] = &s4_vclk_div6.hw,
3046 [CLKID_VCLK_DIV12] = &s4_vclk_div12.hw,
3047 [CLKID_VCLK2_DIV2] = &s4_vclk2_div2.hw,
3048 [CLKID_VCLK2_DIV4] = &s4_vclk2_div4.hw,
3049 [CLKID_VCLK2_DIV6] = &s4_vclk2_div6.hw,
3050 [CLKID_VCLK2_DIV12] = &s4_vclk2_div12.hw,
3051 [CLKID_CTS_ENCI_SEL] = &s4_cts_enci_sel.hw,
3052 [CLKID_CTS_ENCP_SEL] = &s4_cts_encp_sel.hw,
3053 [CLKID_CTS_VDAC_SEL] = &s4_cts_vdac_sel.hw,
3054 [CLKID_HDMI_TX_SEL] = &s4_hdmi_tx_sel.hw,
3055 [CLKID_CTS_ENCI] = &s4_cts_enci.hw,
3056 [CLKID_CTS_ENCP] = &s4_cts_encp.hw,
3057 [CLKID_CTS_VDAC] = &s4_cts_vdac.hw,
3058 [CLKID_HDMI_TX] = &s4_hdmi_tx.hw,
3059 [CLKID_HDMI_SEL] = &s4_hdmi_sel.hw,
3060 [CLKID_HDMI_DIV] = &s4_hdmi_div.hw,
3061 [CLKID_HDMI] = &s4_hdmi.hw,
3062 [CLKID_TS_CLK_DIV] = &s4_ts_clk_div.hw,
3063 [CLKID_TS] = &s4_ts_clk.hw,
3064 [CLKID_MALI_0_SEL] = &s4_mali_0_sel.hw,
3065 [CLKID_MALI_0_DIV] = &s4_mali_0_div.hw,
3066 [CLKID_MALI_0] = &s4_mali_0.hw,
3067 [CLKID_MALI_1_SEL] = &s4_mali_1_sel.hw,
3068 [CLKID_MALI_1_DIV] = &s4_mali_1_div.hw,
3069 [CLKID_MALI_1] = &s4_mali_1.hw,
3070 [CLKID_MALI_SEL] = &s4_mali_sel.hw,
3071 [CLKID_VDEC_P0_SEL] = &s4_vdec_p0_sel.hw,
3072 [CLKID_VDEC_P0_DIV] = &s4_vdec_p0_div.hw,
3073 [CLKID_VDEC_P0] = &s4_vdec_p0.hw,
3074 [CLKID_VDEC_P1_SEL] = &s4_vdec_p1_sel.hw,
3075 [CLKID_VDEC_P1_DIV] = &s4_vdec_p1_div.hw,
3076 [CLKID_VDEC_P1] = &s4_vdec_p1.hw,
3077 [CLKID_VDEC_SEL] = &s4_vdec_sel.hw,
3078 [CLKID_HEVCF_P0_SEL] = &s4_hevcf_p0_sel.hw,
3079 [CLKID_HEVCF_P0_DIV] = &s4_hevcf_p0_div.hw,
3080 [CLKID_HEVCF_P0] = &s4_hevcf_p0.hw,
3081 [CLKID_HEVCF_P1_SEL] = &s4_hevcf_p1_sel.hw,
3082 [CLKID_HEVCF_P1_DIV] = &s4_hevcf_p1_div.hw,
3083 [CLKID_HEVCF_P1] = &s4_hevcf_p1.hw,
3084 [CLKID_HEVCF_SEL] = &s4_hevcf_sel.hw,
3085 [CLKID_VPU_0_SEL] = &s4_vpu_0_sel.hw,
3086 [CLKID_VPU_0_DIV] = &s4_vpu_0_div.hw,
3087 [CLKID_VPU_0] = &s4_vpu_0.hw,
3088 [CLKID_VPU_1_SEL] = &s4_vpu_1_sel.hw,
3089 [CLKID_VPU_1_DIV] = &s4_vpu_1_div.hw,
3090 [CLKID_VPU_1] = &s4_vpu_1.hw,
3091 [CLKID_VPU] = &s4_vpu.hw,
3092 [CLKID_VPU_CLKB_TMP_SEL] = &s4_vpu_clkb_tmp_sel.hw,
3093 [CLKID_VPU_CLKB_TMP_DIV] = &s4_vpu_clkb_tmp_div.hw,
3094 [CLKID_VPU_CLKB_TMP] = &s4_vpu_clkb_tmp.hw,
3095 [CLKID_VPU_CLKB_DIV] = &s4_vpu_clkb_div.hw,
3096 [CLKID_VPU_CLKB] = &s4_vpu_clkb.hw,
3097 [CLKID_VPU_CLKC_P0_SEL] = &s4_vpu_clkc_p0_sel.hw,
3098 [CLKID_VPU_CLKC_P0_DIV] = &s4_vpu_clkc_p0_div.hw,
3099 [CLKID_VPU_CLKC_P0] = &s4_vpu_clkc_p0.hw,
3100 [CLKID_VPU_CLKC_P1_SEL] = &s4_vpu_clkc_p1_sel.hw,
3101 [CLKID_VPU_CLKC_P1_DIV] = &s4_vpu_clkc_p1_div.hw,
3102 [CLKID_VPU_CLKC_P1] = &s4_vpu_clkc_p1.hw,
3103 [CLKID_VPU_CLKC_SEL] = &s4_vpu_clkc_sel.hw,
3104 [CLKID_VAPB_0_SEL] = &s4_vapb_0_sel.hw,
3105 [CLKID_VAPB_0_DIV] = &s4_vapb_0_div.hw,
3106 [CLKID_VAPB_0] = &s4_vapb_0.hw,
3107 [CLKID_VAPB_1_SEL] = &s4_vapb_1_sel.hw,
3108 [CLKID_VAPB_1_DIV] = &s4_vapb_1_div.hw,
3109 [CLKID_VAPB_1] = &s4_vapb_1.hw,
3110 [CLKID_VAPB] = &s4_vapb.hw,
3111 [CLKID_GE2D] = &s4_ge2d.hw,
3112 [CLKID_VDIN_MEAS_SEL] = &s4_vdin_meas_sel.hw,
3113 [CLKID_VDIN_MEAS_DIV] = &s4_vdin_meas_div.hw,
3114 [CLKID_VDIN_MEAS] = &s4_vdin_meas.hw,
3115 [CLKID_SD_EMMC_C_CLK_SEL] = &s4_sd_emmc_c_clk0_sel.hw,
3116 [CLKID_SD_EMMC_C_CLK_DIV] = &s4_sd_emmc_c_clk0_div.hw,
3117 [CLKID_SD_EMMC_C] = &s4_sd_emmc_c_clk0.hw,
3118 [CLKID_SD_EMMC_A_CLK_SEL] = &s4_sd_emmc_a_clk0_sel.hw,
3119 [CLKID_SD_EMMC_A_CLK_DIV] = &s4_sd_emmc_a_clk0_div.hw,
3120 [CLKID_SD_EMMC_A] = &s4_sd_emmc_a_clk0.hw,
3121 [CLKID_SD_EMMC_B_CLK_SEL] = &s4_sd_emmc_b_clk0_sel.hw,
3122 [CLKID_SD_EMMC_B_CLK_DIV] = &s4_sd_emmc_b_clk0_div.hw,
3123 [CLKID_SD_EMMC_B] = &s4_sd_emmc_b_clk0.hw,
3124 [CLKID_SPICC0_SEL] = &s4_spicc0_sel.hw,
3125 [CLKID_SPICC0_DIV] = &s4_spicc0_div.hw,
3126 [CLKID_SPICC0_EN] = &s4_spicc0_en.hw,
3127 [CLKID_PWM_A_SEL] = &s4_pwm_a_sel.hw,
3128 [CLKID_PWM_A_DIV] = &s4_pwm_a_div.hw,
3129 [CLKID_PWM_A] = &s4_pwm_a.hw,
3130 [CLKID_PWM_B_SEL] = &s4_pwm_b_sel.hw,
3131 [CLKID_PWM_B_DIV] = &s4_pwm_b_div.hw,
3132 [CLKID_PWM_B] = &s4_pwm_b.hw,
3133 [CLKID_PWM_C_SEL] = &s4_pwm_c_sel.hw,
3134 [CLKID_PWM_C_DIV] = &s4_pwm_c_div.hw,
3135 [CLKID_PWM_C] = &s4_pwm_c.hw,
3136 [CLKID_PWM_D_SEL] = &s4_pwm_d_sel.hw,
3137 [CLKID_PWM_D_DIV] = &s4_pwm_d_div.hw,
3138 [CLKID_PWM_D] = &s4_pwm_d.hw,
3139 [CLKID_PWM_E_SEL] = &s4_pwm_e_sel.hw,
3140 [CLKID_PWM_E_DIV] = &s4_pwm_e_div.hw,
3141 [CLKID_PWM_E] = &s4_pwm_e.hw,
3142 [CLKID_PWM_F_SEL] = &s4_pwm_f_sel.hw,
3143 [CLKID_PWM_F_DIV] = &s4_pwm_f_div.hw,
3144 [CLKID_PWM_F] = &s4_pwm_f.hw,
3145 [CLKID_PWM_G_SEL] = &s4_pwm_g_sel.hw,
3146 [CLKID_PWM_G_DIV] = &s4_pwm_g_div.hw,
3147 [CLKID_PWM_G] = &s4_pwm_g.hw,
3148 [CLKID_PWM_H_SEL] = &s4_pwm_h_sel.hw,
3149 [CLKID_PWM_H_DIV] = &s4_pwm_h_div.hw,
3150 [CLKID_PWM_H] = &s4_pwm_h.hw,
3151 [CLKID_PWM_I_SEL] = &s4_pwm_i_sel.hw,
3152 [CLKID_PWM_I_DIV] = &s4_pwm_i_div.hw,
3153 [CLKID_PWM_I] = &s4_pwm_i.hw,
3154 [CLKID_PWM_J_SEL] = &s4_pwm_j_sel.hw,
3155 [CLKID_PWM_J_DIV] = &s4_pwm_j_div.hw,
3156 [CLKID_PWM_J] = &s4_pwm_j.hw,
3157 [CLKID_SARADC_SEL] = &s4_saradc_sel.hw,
3158 [CLKID_SARADC_DIV] = &s4_saradc_div.hw,
3159 [CLKID_SARADC] = &s4_saradc.hw,
3160 [CLKID_GEN_SEL] = &s4_gen_clk_sel.hw,
3161 [CLKID_GEN_DIV] = &s4_gen_clk_div.hw,
3162 [CLKID_GEN] = &s4_gen_clk.hw,
3163 [CLKID_DDR] = &s4_ddr.hw,
3164 [CLKID_DOS] = &s4_dos.hw,
3165 [CLKID_ETHPHY] = &s4_ethphy.hw,
3166 [CLKID_MALI] = &s4_mali.hw,
3167 [CLKID_AOCPU] = &s4_aocpu.hw,
3168 [CLKID_AUCPU] = &s4_aucpu.hw,
3169 [CLKID_CEC] = &s4_cec.hw,
3170 [CLKID_SDEMMC_A] = &s4_sdemmca.hw,
3171 [CLKID_SDEMMC_B] = &s4_sdemmcb.hw,
3172 [CLKID_NAND] = &s4_nand.hw,
3173 [CLKID_SMARTCARD] = &s4_smartcard.hw,
3174 [CLKID_ACODEC] = &s4_acodec.hw,
3175 [CLKID_SPIFC] = &s4_spifc.hw,
3176 [CLKID_MSR] = &s4_msr_clk.hw,
3177 [CLKID_IR_CTRL] = &s4_ir_ctrl.hw,
3178 [CLKID_AUDIO] = &s4_audio.hw,
3179 [CLKID_ETH] = &s4_eth.hw,
3180 [CLKID_UART_A] = &s4_uart_a.hw,
3181 [CLKID_UART_B] = &s4_uart_b.hw,
3182 [CLKID_UART_C] = &s4_uart_c.hw,
3183 [CLKID_UART_D] = &s4_uart_d.hw,
3184 [CLKID_UART_E] = &s4_uart_e.hw,
3185 [CLKID_AIFIFO] = &s4_aififo.hw,
3186 [CLKID_TS_DDR] = &s4_ts_ddr.hw,
3187 [CLKID_TS_PLL] = &s4_ts_pll.hw,
3188 [CLKID_G2D] = &s4_g2d.hw,
3189 [CLKID_SPICC0] = &s4_spicc0.hw,
3190 [CLKID_USB] = &s4_usb.hw,
3191 [CLKID_I2C_M_A] = &s4_i2c_m_a.hw,
3192 [CLKID_I2C_M_B] = &s4_i2c_m_b.hw,
3193 [CLKID_I2C_M_C] = &s4_i2c_m_c.hw,
3194 [CLKID_I2C_M_D] = &s4_i2c_m_d.hw,
3195 [CLKID_I2C_M_E] = &s4_i2c_m_e.hw,
3196 [CLKID_HDMITX_APB] = &s4_hdmitx_apb.hw,
3197 [CLKID_I2C_S_A] = &s4_i2c_s_a.hw,
3198 [CLKID_USB1_TO_DDR] = &s4_usb1_to_ddr.hw,
3199 [CLKID_HDCP22] = &s4_hdcp22.hw,
3200 [CLKID_MMC_APB] = &s4_mmc_apb.hw,
3201 [CLKID_RSA] = &s4_rsa.hw,
3202 [CLKID_CPU_DEBUG] = &s4_cpu_debug.hw,
3203 [CLKID_VPU_INTR] = &s4_vpu_intr.hw,
3204 [CLKID_DEMOD] = &s4_demod.hw,
3205 [CLKID_SAR_ADC] = &s4_sar_adc.hw,
3206 [CLKID_GIC] = &s4_gic.hw,
3207 [CLKID_PWM_AB] = &s4_pwm_ab.hw,
3208 [CLKID_PWM_CD] = &s4_pwm_cd.hw,
3209 [CLKID_PWM_EF] = &s4_pwm_ef.hw,
3210 [CLKID_PWM_GH] = &s4_pwm_gh.hw,
3211 [CLKID_PWM_IJ] = &s4_pwm_ij.hw,
3212 [CLKID_HDCP22_ESMCLK_SEL] = &s4_hdcp22_esmclk_sel.hw,
3213 [CLKID_HDCP22_ESMCLK_DIV] = &s4_hdcp22_esmclk_div.hw,
3214 [CLKID_HDCP22_ESMCLK] = &s4_hdcp22_esmclk.hw,
3215 [CLKID_HDCP22_SKPCLK_SEL] = &s4_hdcp22_skpclk_sel.hw,
3216 [CLKID_HDCP22_SKPCLK_DIV] = &s4_hdcp22_skpclk_div.hw,
3217 [CLKID_HDCP22_SKPCLK] = &s4_hdcp22_skpclk.hw,
3218 [CLKID_CTS_ENCL_SEL] = &s4_cts_encl_sel.hw,
3219 [CLKID_CTS_ENCL] = &s4_cts_encl.hw,
3220 [CLKID_CDAC_SEL] = &s4_cdac_sel.hw,
3221 [CLKID_CDAC_DIV] = &s4_cdac_div.hw,
3222 [CLKID_CDAC] = &s4_cdac.hw,
3223 [CLKID_DEMOD_CORE_SEL] = &s4_demod_core_sel.hw,
3224 [CLKID_DEMOD_CORE_DIV] = &s4_demod_core_div.hw,
3225 [CLKID_DEMOD_CORE] = &s4_demod_core.hw,
3226 [CLKID_ADC_EXTCLK_IN_SEL] = &s4_adc_extclk_in_sel.hw,
3227 [CLKID_ADC_EXTCLK_IN_DIV] = &s4_adc_extclk_in_div.hw,
3228 [CLKID_ADC_EXTCLK_IN] = &s4_adc_extclk_in.hw,
3229};
3230
3231static const struct meson_clkc_data s4_peripherals_clkc_data = {
3232 .hw_clks = {
3233 .hws = s4_peripherals_hw_clks,
3234 .num = ARRAY_SIZE(s4_peripherals_hw_clks),
3235 },
3236};
3237
3238static const struct of_device_id s4_peripherals_clkc_match_table[] = {
3239 {
3240 .compatible = "amlogic,s4-peripherals-clkc",
3241 .data = &s4_peripherals_clkc_data,
3242 },
3243 {}
3244};
3245MODULE_DEVICE_TABLE(of, s4_peripherals_clkc_match_table);
3246
3247static struct platform_driver s4_peripherals_clkc_driver = {
3248 .probe = meson_clkc_mmio_probe,
3249 .driver = {
3250 .name = "s4-peripherals-clkc",
3251 .of_match_table = s4_peripherals_clkc_match_table,
3252 },
3253};
3254module_platform_driver(s4_peripherals_clkc_driver);
3255
3256MODULE_DESCRIPTION("Amlogic S4 Peripherals Clock Controller driver");
3257MODULE_AUTHOR("Yu Tu <yu.tu@amlogic.com>");
3258MODULE_LICENSE("GPL");
3259MODULE_IMPORT_NS("CLK_MESON");