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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Marvell Armada CP110 System Controller
4 *
5 * Copyright (C) 2016 Marvell
6 *
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
8 *
9 */
10
11/*
12 * CP110 has 6 core clocks:
13 *
14 * - PLL0 (1 Ghz)
15 * - PPv2 core (1/3 PLL0)
16 * - x2 Core (1/2 PLL0)
17 * - Core (1/2 x2 Core)
18 * - SDIO (2/5 PLL0)
19 *
20 * - NAND clock, which is either:
21 * - Equal to SDIO clock
22 * - 2/5 PLL0
23 *
24 * CP110 has 32 gateable clocks, for the various peripherals in the IP.
25 */
26
27#define pr_fmt(fmt) "cp110-system-controller: " fmt
28
29#include "armada_ap_cp_helper.h"
30#include <linux/clk-provider.h>
31#include <linux/mfd/syscon.h>
32#include <linux/init.h>
33#include <linux/of.h>
34#include <linux/platform_device.h>
35#include <linux/regmap.h>
36#include <linux/slab.h>
37
38#define CP110_PM_CLOCK_GATING_REG 0x220
39#define CP110_NAND_FLASH_CLK_CTRL_REG 0x700
40#define NF_CLOCK_SEL_400_MASK BIT(0)
41
42enum {
43 CP110_CLK_TYPE_CORE,
44 CP110_CLK_TYPE_GATABLE,
45};
46
47#define CP110_MAX_CORE_CLOCKS 6
48#define CP110_MAX_GATABLE_CLOCKS 32
49
50#define CP110_CLK_NUM \
51 (CP110_MAX_CORE_CLOCKS + CP110_MAX_GATABLE_CLOCKS)
52
53#define CP110_CORE_PLL0 0
54#define CP110_CORE_PPV2 1
55#define CP110_CORE_X2CORE 2
56#define CP110_CORE_CORE 3
57#define CP110_CORE_NAND 4
58#define CP110_CORE_SDIO 5
59
60/* A number of gateable clocks need special handling */
61#define CP110_GATE_AUDIO 0
62#define CP110_GATE_COMM_UNIT 1
63#define CP110_GATE_NAND 2
64#define CP110_GATE_PPV2 3
65#define CP110_GATE_SDIO 4
66#define CP110_GATE_MG 5
67#define CP110_GATE_MG_CORE 6
68#define CP110_GATE_XOR1 7
69#define CP110_GATE_XOR0 8
70#define CP110_GATE_GOP_DP 9
71#define CP110_GATE_PCIE_X1_0 11
72#define CP110_GATE_PCIE_X1_1 12
73#define CP110_GATE_PCIE_X4 13
74#define CP110_GATE_PCIE_XOR 14
75#define CP110_GATE_SATA 15
76#define CP110_GATE_SATA_USB 16
77#define CP110_GATE_MAIN 17
78#define CP110_GATE_SDMMC_GOP 18
79#define CP110_GATE_SLOW_IO 21
80#define CP110_GATE_USB3H0 22
81#define CP110_GATE_USB3H1 23
82#define CP110_GATE_USB3DEV 24
83#define CP110_GATE_EIP150 25
84#define CP110_GATE_EIP197 26
85
86static const char * const gate_base_names[] = {
87 [CP110_GATE_AUDIO] = "audio",
88 [CP110_GATE_COMM_UNIT] = "communit",
89 [CP110_GATE_NAND] = "nand",
90 [CP110_GATE_PPV2] = "ppv2",
91 [CP110_GATE_SDIO] = "sdio",
92 [CP110_GATE_MG] = "mg-domain",
93 [CP110_GATE_MG_CORE] = "mg-core",
94 [CP110_GATE_XOR1] = "xor1",
95 [CP110_GATE_XOR0] = "xor0",
96 [CP110_GATE_GOP_DP] = "gop-dp",
97 [CP110_GATE_PCIE_X1_0] = "pcie_x10",
98 [CP110_GATE_PCIE_X1_1] = "pcie_x11",
99 [CP110_GATE_PCIE_X4] = "pcie_x4",
100 [CP110_GATE_PCIE_XOR] = "pcie-xor",
101 [CP110_GATE_SATA] = "sata",
102 [CP110_GATE_SATA_USB] = "sata-usb",
103 [CP110_GATE_MAIN] = "main",
104 [CP110_GATE_SDMMC_GOP] = "sd-mmc-gop",
105 [CP110_GATE_SLOW_IO] = "slow-io",
106 [CP110_GATE_USB3H0] = "usb3h0",
107 [CP110_GATE_USB3H1] = "usb3h1",
108 [CP110_GATE_USB3DEV] = "usb3dev",
109 [CP110_GATE_EIP150] = "eip150",
110 [CP110_GATE_EIP197] = "eip197"
111};
112
113static unsigned long gate_flags(const u8 bit_idx)
114{
115 switch (bit_idx) {
116 case CP110_GATE_PCIE_X1_0:
117 case CP110_GATE_PCIE_X1_1:
118 case CP110_GATE_PCIE_X4:
119 /*
120 * If a port had an active link at boot time, stopping
121 * the clock creates a failed state from which controller
122 * driver can not recover.
123 * Prevent stopping this clock till after a driver has taken
124 * ownership.
125 */
126 return CLK_IGNORE_UNUSED;
127 default:
128 return 0;
129 }
130};
131
132struct cp110_gate_clk {
133 struct clk_hw hw;
134 struct regmap *regmap;
135 u8 bit_idx;
136};
137
138#define to_cp110_gate_clk(hw) container_of(hw, struct cp110_gate_clk, hw)
139
140static int cp110_gate_enable(struct clk_hw *hw)
141{
142 struct cp110_gate_clk *gate = to_cp110_gate_clk(hw);
143
144 regmap_update_bits(gate->regmap, CP110_PM_CLOCK_GATING_REG,
145 BIT(gate->bit_idx), BIT(gate->bit_idx));
146
147 return 0;
148}
149
150static void cp110_gate_disable(struct clk_hw *hw)
151{
152 struct cp110_gate_clk *gate = to_cp110_gate_clk(hw);
153
154 regmap_update_bits(gate->regmap, CP110_PM_CLOCK_GATING_REG,
155 BIT(gate->bit_idx), 0);
156}
157
158static int cp110_gate_is_enabled(struct clk_hw *hw)
159{
160 struct cp110_gate_clk *gate = to_cp110_gate_clk(hw);
161 u32 val;
162
163 regmap_read(gate->regmap, CP110_PM_CLOCK_GATING_REG, &val);
164
165 return val & BIT(gate->bit_idx);
166}
167
168static const struct clk_ops cp110_gate_ops = {
169 .enable = cp110_gate_enable,
170 .disable = cp110_gate_disable,
171 .is_enabled = cp110_gate_is_enabled,
172};
173
174static struct clk_hw *cp110_register_gate(const char *name,
175 const char *parent_name,
176 struct regmap *regmap, u8 bit_idx)
177{
178 struct cp110_gate_clk *gate;
179 struct clk_hw *hw;
180 struct clk_init_data init;
181 int ret;
182
183 gate = kzalloc_obj(*gate);
184 if (!gate)
185 return ERR_PTR(-ENOMEM);
186
187 memset(&init, 0, sizeof(init));
188
189 init.name = name;
190 init.ops = &cp110_gate_ops;
191 init.parent_names = &parent_name;
192 init.num_parents = 1;
193 init.flags = gate_flags(bit_idx);
194
195 gate->regmap = regmap;
196 gate->bit_idx = bit_idx;
197 gate->hw.init = &init;
198
199 hw = &gate->hw;
200 ret = clk_hw_register(NULL, hw);
201 if (ret) {
202 kfree(gate);
203 hw = ERR_PTR(ret);
204 }
205
206 return hw;
207}
208
209static void cp110_unregister_gate(struct clk_hw *hw)
210{
211 clk_hw_unregister(hw);
212 kfree(to_cp110_gate_clk(hw));
213}
214
215static struct clk_hw *cp110_of_clk_get(struct of_phandle_args *clkspec,
216 void *data)
217{
218 struct clk_hw_onecell_data *clk_data = data;
219 unsigned int type = clkspec->args[0];
220 unsigned int idx = clkspec->args[1];
221
222 if (type == CP110_CLK_TYPE_CORE) {
223 if (idx >= CP110_MAX_CORE_CLOCKS)
224 return ERR_PTR(-EINVAL);
225 return clk_data->hws[idx];
226 } else if (type == CP110_CLK_TYPE_GATABLE) {
227 if (idx >= CP110_MAX_GATABLE_CLOCKS)
228 return ERR_PTR(-EINVAL);
229 return clk_data->hws[CP110_MAX_CORE_CLOCKS + idx];
230 }
231
232 return ERR_PTR(-EINVAL);
233}
234
235static int cp110_syscon_common_probe(struct platform_device *pdev,
236 struct device_node *syscon_node)
237{
238 struct regmap *regmap;
239 struct device *dev = &pdev->dev;
240 struct device_node *np = dev->of_node;
241 const char *ppv2_name, *pll0_name, *core_name, *x2core_name, *nand_name,
242 *sdio_name;
243 struct clk_hw_onecell_data *cp110_clk_data;
244 struct clk_hw *hw, **cp110_clks;
245 u32 nand_clk_ctrl;
246 int i, ret;
247 char *gate_name[ARRAY_SIZE(gate_base_names)];
248
249 regmap = syscon_node_to_regmap(syscon_node);
250 if (IS_ERR(regmap))
251 return PTR_ERR(regmap);
252
253 ret = regmap_read(regmap, CP110_NAND_FLASH_CLK_CTRL_REG,
254 &nand_clk_ctrl);
255 if (ret)
256 return ret;
257
258 cp110_clk_data = devm_kzalloc(dev, struct_size(cp110_clk_data, hws,
259 CP110_CLK_NUM),
260 GFP_KERNEL);
261 if (!cp110_clk_data)
262 return -ENOMEM;
263 cp110_clk_data->num = CP110_CLK_NUM;
264
265 cp110_clks = cp110_clk_data->hws;
266
267 /* Register the PLL0 which is the root of the hw tree */
268 pll0_name = ap_cp_unique_name(dev, syscon_node, "pll0");
269 hw = clk_hw_register_fixed_rate(NULL, pll0_name, NULL, 0,
270 1000 * 1000 * 1000);
271 if (IS_ERR(hw)) {
272 ret = PTR_ERR(hw);
273 goto fail_pll0;
274 }
275
276 cp110_clks[CP110_CORE_PLL0] = hw;
277
278 /* PPv2 is PLL0/3 */
279 ppv2_name = ap_cp_unique_name(dev, syscon_node, "ppv2-core");
280 hw = clk_hw_register_fixed_factor(NULL, ppv2_name, pll0_name, 0, 1, 3);
281 if (IS_ERR(hw)) {
282 ret = PTR_ERR(hw);
283 goto fail_ppv2;
284 }
285
286 cp110_clks[CP110_CORE_PPV2] = hw;
287
288 /* X2CORE clock is PLL0/2 */
289 x2core_name = ap_cp_unique_name(dev, syscon_node, "x2core");
290 hw = clk_hw_register_fixed_factor(NULL, x2core_name, pll0_name,
291 0, 1, 2);
292 if (IS_ERR(hw)) {
293 ret = PTR_ERR(hw);
294 goto fail_eip;
295 }
296
297 cp110_clks[CP110_CORE_X2CORE] = hw;
298
299 /* Core clock is X2CORE/2 */
300 core_name = ap_cp_unique_name(dev, syscon_node, "core");
301 hw = clk_hw_register_fixed_factor(NULL, core_name, x2core_name,
302 0, 1, 2);
303 if (IS_ERR(hw)) {
304 ret = PTR_ERR(hw);
305 goto fail_core;
306 }
307
308 cp110_clks[CP110_CORE_CORE] = hw;
309 /* NAND can be either PLL0/2.5 or core clock */
310 nand_name = ap_cp_unique_name(dev, syscon_node, "nand-core");
311 if (nand_clk_ctrl & NF_CLOCK_SEL_400_MASK)
312 hw = clk_hw_register_fixed_factor(NULL, nand_name,
313 pll0_name, 0, 2, 5);
314 else
315 hw = clk_hw_register_fixed_factor(NULL, nand_name,
316 core_name, 0, 1, 1);
317 if (IS_ERR(hw)) {
318 ret = PTR_ERR(hw);
319 goto fail_nand;
320 }
321
322 cp110_clks[CP110_CORE_NAND] = hw;
323
324 /* SDIO clock is PLL0/2.5 */
325 sdio_name = ap_cp_unique_name(dev, syscon_node, "sdio-core");
326 hw = clk_hw_register_fixed_factor(NULL, sdio_name,
327 pll0_name, 0, 2, 5);
328 if (IS_ERR(hw)) {
329 ret = PTR_ERR(hw);
330 goto fail_sdio;
331 }
332
333 cp110_clks[CP110_CORE_SDIO] = hw;
334
335 /* create the unique name for all the gate clocks */
336 for (i = 0; i < ARRAY_SIZE(gate_base_names); i++)
337 gate_name[i] = ap_cp_unique_name(dev, syscon_node,
338 gate_base_names[i]);
339
340 for (i = 0; i < ARRAY_SIZE(gate_base_names); i++) {
341 const char *parent;
342
343 if (gate_name[i] == NULL)
344 continue;
345
346 switch (i) {
347 case CP110_GATE_NAND:
348 parent = nand_name;
349 break;
350 case CP110_GATE_MG:
351 case CP110_GATE_GOP_DP:
352 case CP110_GATE_PPV2:
353 parent = ppv2_name;
354 break;
355 case CP110_GATE_SDIO:
356 parent = sdio_name;
357 break;
358 case CP110_GATE_MAIN:
359 case CP110_GATE_PCIE_XOR:
360 case CP110_GATE_PCIE_X4:
361 case CP110_GATE_EIP150:
362 case CP110_GATE_EIP197:
363 parent = x2core_name;
364 break;
365 default:
366 parent = core_name;
367 break;
368 }
369 hw = cp110_register_gate(gate_name[i], parent, regmap, i);
370
371 if (IS_ERR(hw)) {
372 ret = PTR_ERR(hw);
373 goto fail_gate;
374 }
375
376 cp110_clks[CP110_MAX_CORE_CLOCKS + i] = hw;
377 }
378
379 ret = of_clk_add_hw_provider(np, cp110_of_clk_get, cp110_clk_data);
380 if (ret)
381 goto fail_clk_add;
382
383 platform_set_drvdata(pdev, cp110_clks);
384
385 return 0;
386
387fail_clk_add:
388fail_gate:
389 for (i = 0; i < CP110_MAX_GATABLE_CLOCKS; i++) {
390 hw = cp110_clks[CP110_MAX_CORE_CLOCKS + i];
391
392 if (hw)
393 cp110_unregister_gate(hw);
394 }
395
396 clk_hw_unregister_fixed_factor(cp110_clks[CP110_CORE_SDIO]);
397fail_sdio:
398 clk_hw_unregister_fixed_factor(cp110_clks[CP110_CORE_NAND]);
399fail_nand:
400 clk_hw_unregister_fixed_factor(cp110_clks[CP110_CORE_CORE]);
401fail_core:
402 clk_hw_unregister_fixed_factor(cp110_clks[CP110_CORE_X2CORE]);
403fail_eip:
404 clk_hw_unregister_fixed_factor(cp110_clks[CP110_CORE_PPV2]);
405fail_ppv2:
406 clk_hw_unregister_fixed_rate(cp110_clks[CP110_CORE_PLL0]);
407fail_pll0:
408 return ret;
409}
410
411static int cp110_syscon_legacy_clk_probe(struct platform_device *pdev)
412{
413 dev_warn(&pdev->dev, FW_WARN "Using legacy device tree binding\n");
414 dev_warn(&pdev->dev, FW_WARN "Update your device tree:\n");
415 dev_warn(&pdev->dev, FW_WARN
416 "This binding won't be supported in future kernels\n");
417
418 return cp110_syscon_common_probe(pdev, pdev->dev.of_node);
419}
420
421static int cp110_clk_probe(struct platform_device *pdev)
422{
423 return cp110_syscon_common_probe(pdev, pdev->dev.of_node->parent);
424}
425
426static const struct of_device_id cp110_syscon_legacy_of_match[] = {
427 { .compatible = "marvell,cp110-system-controller0", },
428 { }
429};
430
431static struct platform_driver cp110_syscon_legacy_driver = {
432 .probe = cp110_syscon_legacy_clk_probe,
433 .driver = {
434 .name = "marvell-cp110-system-controller0",
435 .of_match_table = cp110_syscon_legacy_of_match,
436 .suppress_bind_attrs = true,
437 },
438};
439builtin_platform_driver(cp110_syscon_legacy_driver);
440
441static const struct of_device_id cp110_clock_of_match[] = {
442 { .compatible = "marvell,cp110-clock", },
443 { }
444};
445
446static struct platform_driver cp110_clock_driver = {
447 .probe = cp110_clk_probe,
448 .driver = {
449 .name = "marvell-cp110-clock",
450 .of_match_table = cp110_clock_of_match,
451 .suppress_bind_attrs = true,
452 },
453};
454builtin_platform_driver(cp110_clock_driver);