Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
4 */
5
6#include <linux/clk-provider.h>
7#include <linux/mod_devicetable.h>
8#include <linux/module.h>
9#include <linux/platform_device.h>
10#include <linux/regmap.h>
11
12#include <dt-bindings/clock/qcom,x1e80100-gcc.h>
13
14#include "clk-alpha-pll.h"
15#include "clk-branch.h"
16#include "clk-rcg.h"
17#include "clk-regmap.h"
18#include "clk-regmap-divider.h"
19#include "clk-regmap-mux.h"
20#include "clk-regmap-phy-mux.h"
21#include "gdsc.h"
22#include "reset.h"
23
24enum {
25 DT_BI_TCXO,
26 DT_SLEEP_CLK,
27 DT_PCIE_3_PIPE,
28 DT_PCIE_4_PIPE,
29 DT_PCIE_5_PIPE,
30 DT_PCIE_6A_PIPE,
31 DT_PCIE_6B_PIPE,
32 DT_USB3_PHY_0_WRAPPER_GCC_USB30_PIPE,
33 DT_USB3_PHY_1_WRAPPER_GCC_USB30_PIPE,
34 DT_USB3_PHY_2_WRAPPER_GCC_USB30_PIPE,
35 DT_GCC_USB4_0_PHY_DP0_GMUX_CLK_SRC,
36 DT_GCC_USB4_0_PHY_DP1_GMUX_CLK_SRC,
37 DT_GCC_USB4_0_PHY_PCIE_PIPEGMUX_CLK_SRC,
38 DT_GCC_USB4_0_PHY_PIPEGMUX_CLK_SRC,
39 DT_GCC_USB4_0_PHY_SYS_PIPEGMUX_CLK_SRC,
40 DT_GCC_USB4_1_PHY_DP0_GMUX_CLK_SRC,
41 DT_GCC_USB4_1_PHY_DP1_GMUX_CLK_SRC,
42 DT_GCC_USB4_1_PHY_PCIE_PIPEGMUX_CLK_SRC,
43 DT_GCC_USB4_1_PHY_PIPEGMUX_CLK_SRC,
44 DT_GCC_USB4_1_PHY_SYS_PIPEGMUX_CLK_SRC,
45 DT_GCC_USB4_2_PHY_DP0_GMUX_CLK_SRC,
46 DT_GCC_USB4_2_PHY_DP1_GMUX_CLK_SRC,
47 DT_GCC_USB4_2_PHY_PCIE_PIPEGMUX_CLK_SRC,
48 DT_GCC_USB4_2_PHY_PIPEGMUX_CLK_SRC,
49 DT_GCC_USB4_2_PHY_SYS_PIPEGMUX_CLK_SRC,
50 DT_QUSB4PHY_0_GCC_USB4_RX0_CLK,
51 DT_QUSB4PHY_0_GCC_USB4_RX1_CLK,
52 DT_QUSB4PHY_1_GCC_USB4_RX0_CLK,
53 DT_QUSB4PHY_1_GCC_USB4_RX1_CLK,
54 DT_QUSB4PHY_2_GCC_USB4_RX0_CLK,
55 DT_QUSB4PHY_2_GCC_USB4_RX1_CLK,
56 DT_USB4_0_PHY_GCC_USB4_PCIE_PIPE_CLK,
57 DT_USB4_0_PHY_GCC_USB4RTR_MAX_PIPE_CLK,
58 DT_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK,
59 DT_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK,
60 DT_USB4_2_PHY_GCC_USB4_PCIE_PIPE_CLK,
61 DT_USB4_2_PHY_GCC_USB4RTR_MAX_PIPE_CLK,
62 DT_UFS_PHY_RX_SYMBOL_0_CLK,
63 DT_UFS_PHY_RX_SYMBOL_1_CLK,
64 DT_UFS_PHY_TX_SYMBOL_0_CLK,
65};
66
67enum {
68 P_BI_TCXO,
69 P_GCC_GPLL0_OUT_EVEN,
70 P_GCC_GPLL0_OUT_MAIN,
71 P_GCC_GPLL4_OUT_MAIN,
72 P_GCC_GPLL7_OUT_MAIN,
73 P_GCC_GPLL8_OUT_MAIN,
74 P_GCC_GPLL9_OUT_MAIN,
75 P_GCC_USB3_PRIM_PHY_PIPE_CLK_SRC,
76 P_GCC_USB3_SEC_PHY_PIPE_CLK_SRC,
77 P_GCC_USB3_TERT_PHY_PIPE_CLK_SRC,
78 P_GCC_USB4_0_PHY_DP0_GMUX_CLK_SRC,
79 P_GCC_USB4_0_PHY_DP1_GMUX_CLK_SRC,
80 P_GCC_USB4_0_PHY_PCIE_PIPEGMUX_CLK_SRC,
81 P_GCC_USB4_0_PHY_PIPEGMUX_CLK_SRC,
82 P_GCC_USB4_0_PHY_SYS_PIPEGMUX_CLK_SRC,
83 P_GCC_USB4_1_PHY_DP0_GMUX_CLK_SRC,
84 P_GCC_USB4_1_PHY_DP1_GMUX_CLK_SRC,
85 P_GCC_USB4_1_PHY_PCIE_PIPEGMUX_CLK_SRC,
86 P_GCC_USB4_1_PHY_PIPEGMUX_CLK_SRC,
87 P_GCC_USB4_1_PHY_SYS_PIPEGMUX_CLK_SRC,
88 P_GCC_USB4_2_PHY_DP0_GMUX_CLK_SRC,
89 P_GCC_USB4_2_PHY_DP1_GMUX_CLK_SRC,
90 P_GCC_USB4_2_PHY_PCIE_PIPEGMUX_CLK_SRC,
91 P_GCC_USB4_2_PHY_PIPEGMUX_CLK_SRC,
92 P_GCC_USB4_2_PHY_SYS_PIPEGMUX_CLK_SRC,
93 P_QUSB4PHY_0_GCC_USB4_RX0_CLK,
94 P_QUSB4PHY_0_GCC_USB4_RX1_CLK,
95 P_QUSB4PHY_1_GCC_USB4_RX0_CLK,
96 P_QUSB4PHY_1_GCC_USB4_RX1_CLK,
97 P_QUSB4PHY_2_GCC_USB4_RX0_CLK,
98 P_QUSB4PHY_2_GCC_USB4_RX1_CLK,
99 P_SLEEP_CLK,
100 P_USB3_PHY_0_WRAPPER_GCC_USB30_PIPE_CLK,
101 P_USB3_PHY_1_WRAPPER_GCC_USB30_PIPE_CLK,
102 P_USB3_PHY_2_WRAPPER_GCC_USB30_PIPE_CLK,
103 P_USB4_0_PHY_GCC_USB4_PCIE_PIPE_CLK,
104 P_USB4_0_PHY_GCC_USB4RTR_MAX_PIPE_CLK,
105 P_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK,
106 P_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK,
107 P_USB4_2_PHY_GCC_USB4_PCIE_PIPE_CLK,
108 P_USB4_2_PHY_GCC_USB4RTR_MAX_PIPE_CLK,
109 P_UFS_PHY_RX_SYMBOL_0_CLK,
110 P_UFS_PHY_RX_SYMBOL_1_CLK,
111 P_UFS_PHY_TX_SYMBOL_0_CLK,
112};
113
114static struct clk_alpha_pll gcc_gpll0 = {
115 .offset = 0x0,
116 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
117 .clkr = {
118 .enable_reg = 0x52030,
119 .enable_mask = BIT(0),
120 .hw.init = &(const struct clk_init_data) {
121 .name = "gcc_gpll0",
122 .parent_data = &(const struct clk_parent_data) {
123 .index = DT_BI_TCXO,
124 },
125 .num_parents = 1,
126 .ops = &clk_alpha_pll_fixed_lucid_ole_ops,
127 },
128 },
129};
130
131static const struct clk_div_table post_div_table_gcc_gpll0_out_even[] = {
132 { 0x1, 2 },
133 { }
134};
135
136static struct clk_alpha_pll_postdiv gcc_gpll0_out_even = {
137 .offset = 0x0,
138 .post_div_shift = 10,
139 .post_div_table = post_div_table_gcc_gpll0_out_even,
140 .num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even),
141 .width = 4,
142 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
143 .clkr.hw.init = &(const struct clk_init_data) {
144 .name = "gcc_gpll0_out_even",
145 .parent_hws = (const struct clk_hw*[]) {
146 &gcc_gpll0.clkr.hw,
147 },
148 .num_parents = 1,
149 .ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
150 },
151};
152
153static struct clk_alpha_pll gcc_gpll4 = {
154 .offset = 0x4000,
155 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
156 .clkr = {
157 .enable_reg = 0x52030,
158 .enable_mask = BIT(4),
159 .hw.init = &(const struct clk_init_data) {
160 .name = "gcc_gpll4",
161 .parent_data = &(const struct clk_parent_data) {
162 .index = DT_BI_TCXO,
163 },
164 .num_parents = 1,
165 .ops = &clk_alpha_pll_fixed_lucid_ole_ops,
166 },
167 },
168};
169
170static struct clk_alpha_pll gcc_gpll7 = {
171 .offset = 0x7000,
172 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
173 .clkr = {
174 .enable_reg = 0x52030,
175 .enable_mask = BIT(7),
176 .hw.init = &(const struct clk_init_data) {
177 .name = "gcc_gpll7",
178 .parent_data = &(const struct clk_parent_data) {
179 .index = DT_BI_TCXO,
180 },
181 .num_parents = 1,
182 .ops = &clk_alpha_pll_fixed_lucid_ole_ops,
183 },
184 },
185};
186
187static struct clk_alpha_pll gcc_gpll8 = {
188 .offset = 0x8000,
189 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
190 .clkr = {
191 .enable_reg = 0x52030,
192 .enable_mask = BIT(8),
193 .hw.init = &(const struct clk_init_data) {
194 .name = "gcc_gpll8",
195 .parent_data = &(const struct clk_parent_data) {
196 .index = DT_BI_TCXO,
197 },
198 .num_parents = 1,
199 .ops = &clk_alpha_pll_fixed_lucid_ole_ops,
200 },
201 },
202};
203
204static struct clk_alpha_pll gcc_gpll9 = {
205 .offset = 0x9000,
206 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
207 .clkr = {
208 .enable_reg = 0x52030,
209 .enable_mask = BIT(9),
210 .hw.init = &(const struct clk_init_data) {
211 .name = "gcc_gpll9",
212 .parent_data = &(const struct clk_parent_data) {
213 .index = DT_BI_TCXO,
214 },
215 .num_parents = 1,
216 .ops = &clk_alpha_pll_fixed_lucid_ole_ops,
217 },
218 },
219};
220
221static const struct parent_map gcc_parent_map_0[] = {
222 { P_BI_TCXO, 0 },
223 { P_GCC_GPLL0_OUT_MAIN, 1 },
224 { P_GCC_GPLL0_OUT_EVEN, 6 },
225};
226
227static const struct clk_parent_data gcc_parent_data_0[] = {
228 { .index = DT_BI_TCXO },
229 { .hw = &gcc_gpll0.clkr.hw },
230 { .hw = &gcc_gpll0_out_even.clkr.hw },
231};
232
233static const struct parent_map gcc_parent_map_1[] = {
234 { P_BI_TCXO, 0 },
235 { P_SLEEP_CLK, 5 },
236};
237
238static const struct clk_parent_data gcc_parent_data_1[] = {
239 { .index = DT_BI_TCXO },
240 { .index = DT_SLEEP_CLK },
241};
242
243static const struct parent_map gcc_parent_map_2[] = {
244 { P_BI_TCXO, 0 },
245 { P_GCC_GPLL0_OUT_MAIN, 1 },
246 { P_SLEEP_CLK, 5 },
247 { P_GCC_GPLL0_OUT_EVEN, 6 },
248};
249
250static const struct clk_parent_data gcc_parent_data_2[] = {
251 { .index = DT_BI_TCXO },
252 { .hw = &gcc_gpll0.clkr.hw },
253 { .index = DT_SLEEP_CLK },
254 { .hw = &gcc_gpll0_out_even.clkr.hw },
255};
256
257static const struct parent_map gcc_parent_map_3[] = {
258 { P_BI_TCXO, 0 },
259};
260
261static const struct clk_parent_data gcc_parent_data_3[] = {
262 { .index = DT_BI_TCXO },
263};
264
265static const struct parent_map gcc_parent_map_4[] = {
266 { P_BI_TCXO, 0 },
267 { P_GCC_GPLL0_OUT_MAIN, 1 },
268 { P_GCC_GPLL8_OUT_MAIN, 2 },
269 { P_GCC_GPLL0_OUT_EVEN, 6 },
270};
271
272static const struct clk_parent_data gcc_parent_data_4[] = {
273 { .index = DT_BI_TCXO },
274 { .hw = &gcc_gpll0.clkr.hw },
275 { .hw = &gcc_gpll8.clkr.hw },
276 { .hw = &gcc_gpll0_out_even.clkr.hw },
277};
278
279static const struct parent_map gcc_parent_map_5[] = {
280 { P_BI_TCXO, 0 },
281 { P_GCC_GPLL0_OUT_MAIN, 1 },
282 { P_GCC_GPLL7_OUT_MAIN, 2 },
283 { P_SLEEP_CLK, 5 },
284};
285
286static const struct clk_parent_data gcc_parent_data_5[] = {
287 { .index = DT_BI_TCXO },
288 { .hw = &gcc_gpll0.clkr.hw },
289 { .hw = &gcc_gpll7.clkr.hw },
290 { .index = DT_SLEEP_CLK },
291};
292
293static const struct parent_map gcc_parent_map_6[] = {
294 { P_BI_TCXO, 0 },
295 { P_GCC_GPLL0_OUT_MAIN, 1 },
296 { P_GCC_GPLL7_OUT_MAIN, 2 },
297};
298
299static const struct clk_parent_data gcc_parent_data_6[] = {
300 { .index = DT_BI_TCXO },
301 { .hw = &gcc_gpll0.clkr.hw },
302 { .hw = &gcc_gpll7.clkr.hw },
303};
304
305static const struct parent_map gcc_parent_map_7[] = {
306 { P_BI_TCXO, 0 },
307 { P_GCC_GPLL0_OUT_MAIN, 1 },
308 { P_GCC_GPLL4_OUT_MAIN, 5 },
309 { P_GCC_GPLL0_OUT_EVEN, 6 },
310};
311
312static const struct clk_parent_data gcc_parent_data_7[] = {
313 { .index = DT_BI_TCXO },
314 { .hw = &gcc_gpll0.clkr.hw },
315 { .hw = &gcc_gpll4.clkr.hw },
316 { .hw = &gcc_gpll0_out_even.clkr.hw },
317};
318
319static const struct parent_map gcc_parent_map_8[] = {
320 { P_BI_TCXO, 0 },
321 { P_GCC_GPLL0_OUT_MAIN, 1 },
322 { P_GCC_GPLL7_OUT_MAIN, 2 },
323 { P_GCC_GPLL0_OUT_EVEN, 6 },
324};
325
326static const struct clk_parent_data gcc_parent_data_8[] = {
327 { .index = DT_BI_TCXO },
328 { .hw = &gcc_gpll0.clkr.hw },
329 { .hw = &gcc_gpll7.clkr.hw },
330 { .hw = &gcc_gpll0_out_even.clkr.hw },
331};
332
333static const struct parent_map gcc_parent_map_9[] = {
334 { P_BI_TCXO, 0 },
335 { P_GCC_GPLL0_OUT_MAIN, 1 },
336 { P_GCC_GPLL9_OUT_MAIN, 2 },
337 { P_GCC_GPLL4_OUT_MAIN, 5 },
338 { P_GCC_GPLL0_OUT_EVEN, 6 },
339};
340
341static const struct clk_parent_data gcc_parent_data_10[] = {
342 { .index = DT_USB3_PHY_0_WRAPPER_GCC_USB30_PIPE },
343 { .index = DT_BI_TCXO },
344};
345
346static const struct parent_map gcc_parent_map_10[] = {
347 { P_USB3_PHY_0_WRAPPER_GCC_USB30_PIPE_CLK, 0 },
348 { P_BI_TCXO, 2 },
349};
350
351static const struct clk_parent_data gcc_parent_data_11[] = {
352 { .index = DT_USB3_PHY_1_WRAPPER_GCC_USB30_PIPE },
353 { .index = DT_BI_TCXO },
354};
355
356static const struct parent_map gcc_parent_map_11[] = {
357 { P_USB3_PHY_1_WRAPPER_GCC_USB30_PIPE_CLK, 0 },
358 { P_BI_TCXO, 2 },
359};
360
361static const struct clk_parent_data gcc_parent_data_12[] = {
362 { .index = DT_USB3_PHY_2_WRAPPER_GCC_USB30_PIPE },
363 { .index = DT_BI_TCXO },
364};
365
366static const struct parent_map gcc_parent_map_12[] = {
367 { P_USB3_PHY_2_WRAPPER_GCC_USB30_PIPE_CLK, 0 },
368 { P_BI_TCXO, 2 },
369};
370
371static const struct clk_parent_data gcc_parent_data_9[] = {
372 { .index = DT_BI_TCXO },
373 { .hw = &gcc_gpll0.clkr.hw },
374 { .hw = &gcc_gpll9.clkr.hw },
375 { .hw = &gcc_gpll4.clkr.hw },
376 { .hw = &gcc_gpll0_out_even.clkr.hw },
377};
378
379static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
380 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
381 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
382 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
383 { }
384};
385
386static const struct clk_parent_data gcc_parent_data_13[] = {
387 { .index = DT_GCC_USB4_0_PHY_DP0_GMUX_CLK_SRC },
388 { .index = DT_USB4_0_PHY_GCC_USB4RTR_MAX_PIPE_CLK },
389};
390
391static const struct clk_parent_data gcc_parent_data_14[] = {
392 { .index = DT_GCC_USB4_0_PHY_DP1_GMUX_CLK_SRC },
393 { .index = DT_USB4_0_PHY_GCC_USB4RTR_MAX_PIPE_CLK },
394};
395
396static const struct clk_parent_data gcc_parent_data_15[] = {
397 { .index = DT_USB4_0_PHY_GCC_USB4_PCIE_PIPE_CLK },
398 { .index = DT_BI_TCXO },
399};
400
401static const struct clk_parent_data gcc_parent_data_16[] = {
402 { .index = DT_GCC_USB4_0_PHY_PCIE_PIPEGMUX_CLK_SRC },
403 { .index = DT_USB4_0_PHY_GCC_USB4_PCIE_PIPE_CLK },
404};
405
406static const struct clk_parent_data gcc_parent_data_17[] = {
407 { .index = DT_QUSB4PHY_0_GCC_USB4_RX0_CLK },
408 { .index = DT_BI_TCXO },
409};
410
411static const struct clk_parent_data gcc_parent_data_18[] = {
412 { .index = DT_QUSB4PHY_0_GCC_USB4_RX1_CLK },
413 { .index = DT_BI_TCXO },
414};
415
416static const struct clk_parent_data gcc_parent_data_19[] = {
417 { .index = DT_GCC_USB4_0_PHY_SYS_PIPEGMUX_CLK_SRC },
418 { .index = DT_USB4_0_PHY_GCC_USB4_PCIE_PIPE_CLK },
419};
420
421static const struct clk_parent_data gcc_parent_data_20[] = {
422 { .index = DT_GCC_USB4_1_PHY_DP0_GMUX_CLK_SRC },
423 { .index = DT_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK },
424};
425
426static const struct clk_parent_data gcc_parent_data_21[] = {
427 { .index = DT_GCC_USB4_1_PHY_DP1_GMUX_CLK_SRC },
428 { .index = DT_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK },
429};
430
431static const struct clk_parent_data gcc_parent_data_22[] = {
432 { .index = DT_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK },
433 { .index = DT_BI_TCXO },
434};
435
436static const struct clk_parent_data gcc_parent_data_23[] = {
437 { .index = DT_GCC_USB4_1_PHY_PCIE_PIPEGMUX_CLK_SRC },
438 { .index = DT_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK },
439};
440
441static const struct clk_parent_data gcc_parent_data_24[] = {
442 { .index = DT_QUSB4PHY_1_GCC_USB4_RX0_CLK },
443 { .index = DT_BI_TCXO },
444};
445
446static const struct clk_parent_data gcc_parent_data_25[] = {
447 { .index = DT_QUSB4PHY_1_GCC_USB4_RX1_CLK },
448 { .index = DT_BI_TCXO },
449};
450
451static const struct clk_parent_data gcc_parent_data_26[] = {
452 { .index = DT_GCC_USB4_1_PHY_SYS_PIPEGMUX_CLK_SRC },
453 { .index = DT_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK },
454};
455
456static const struct clk_parent_data gcc_parent_data_27[] = {
457 { .index = DT_GCC_USB4_2_PHY_DP0_GMUX_CLK_SRC },
458 { .index = DT_USB4_2_PHY_GCC_USB4RTR_MAX_PIPE_CLK },
459};
460
461static const struct clk_parent_data gcc_parent_data_28[] = {
462 { .index = DT_GCC_USB4_2_PHY_DP1_GMUX_CLK_SRC },
463 { .index = DT_USB4_2_PHY_GCC_USB4RTR_MAX_PIPE_CLK },
464};
465
466static const struct clk_parent_data gcc_parent_data_29[] = {
467 { .index = DT_USB4_2_PHY_GCC_USB4_PCIE_PIPE_CLK },
468 { .index = DT_BI_TCXO },
469};
470
471static const struct clk_parent_data gcc_parent_data_30[] = {
472 { .index = DT_GCC_USB4_2_PHY_PCIE_PIPEGMUX_CLK_SRC },
473 { .index = DT_USB4_2_PHY_GCC_USB4_PCIE_PIPE_CLK },
474};
475
476static const struct clk_parent_data gcc_parent_data_31[] = {
477 { .index = DT_QUSB4PHY_2_GCC_USB4_RX0_CLK },
478 { .index = DT_BI_TCXO },
479};
480
481static const struct clk_parent_data gcc_parent_data_32[] = {
482 { .index = DT_QUSB4PHY_2_GCC_USB4_RX1_CLK },
483 { .index = DT_BI_TCXO },
484};
485
486static const struct clk_parent_data gcc_parent_data_33[] = {
487 { .index = DT_GCC_USB4_2_PHY_SYS_PIPEGMUX_CLK_SRC },
488 { .index = DT_USB4_2_PHY_GCC_USB4_PCIE_PIPE_CLK },
489};
490
491static struct clk_regmap_phy_mux gcc_ufs_phy_rx_symbol_0_clk_src = {
492 .reg = 0x77064,
493 .clkr = {
494 .hw.init = &(const struct clk_init_data) {
495 .name = "gcc_ufs_phy_rx_symbol_0_clk_src",
496 .parent_data = &(const struct clk_parent_data) {
497 .index = DT_UFS_PHY_RX_SYMBOL_0_CLK,
498 },
499 .num_parents = 1,
500 .ops = &clk_regmap_phy_mux_ops,
501 },
502 },
503};
504
505static struct clk_regmap_phy_mux gcc_ufs_phy_rx_symbol_1_clk_src = {
506 .reg = 0x770e0,
507 .clkr = {
508 .hw.init = &(const struct clk_init_data) {
509 .name = "gcc_ufs_phy_rx_symbol_1_clk_src",
510 .parent_data = &(const struct clk_parent_data) {
511 .index = DT_UFS_PHY_RX_SYMBOL_1_CLK,
512 },
513 .num_parents = 1,
514 .ops = &clk_regmap_phy_mux_ops,
515 },
516 },
517};
518
519static struct clk_regmap_phy_mux gcc_ufs_phy_tx_symbol_0_clk_src = {
520 .reg = 0x77054,
521 .clkr = {
522 .hw.init = &(const struct clk_init_data) {
523 .name = "gcc_ufs_phy_tx_symbol_0_clk_src",
524 .parent_data = &(const struct clk_parent_data) {
525 .index = DT_UFS_PHY_TX_SYMBOL_0_CLK,
526 },
527 .num_parents = 1,
528 .ops = &clk_regmap_phy_mux_ops,
529 },
530 },
531};
532
533static struct clk_regmap_phy_mux gcc_usb4_0_phy_dp0_clk_src = {
534 .reg = 0x9f06c,
535 .clkr = {
536 .hw.init = &(const struct clk_init_data) {
537 .name = "gcc_usb4_0_phy_dp0_clk_src",
538 .parent_data = gcc_parent_data_13,
539 .ops = &clk_regmap_phy_mux_ops,
540 },
541 },
542};
543
544static struct clk_regmap_phy_mux gcc_usb4_0_phy_dp1_clk_src = {
545 .reg = 0x9f114,
546 .clkr = {
547 .hw.init = &(const struct clk_init_data) {
548 .name = "gcc_usb4_0_phy_dp1_clk_src",
549 .parent_data = gcc_parent_data_14,
550 .ops = &clk_regmap_phy_mux_ops,
551 },
552 },
553};
554
555static struct clk_regmap_phy_mux gcc_usb4_0_phy_p2rr2p_pipe_clk_src = {
556 .reg = 0x9f0d4,
557 .clkr = {
558 .hw.init = &(const struct clk_init_data) {
559 .name = "gcc_usb4_0_phy_p2rr2p_pipe_clk_src",
560 .parent_data = gcc_parent_data_15,
561 .ops = &clk_regmap_phy_mux_ops,
562 },
563 },
564};
565
566static struct clk_regmap_phy_mux gcc_usb4_0_phy_pcie_pipe_mux_clk_src = {
567 .reg = 0x9f104,
568 .clkr = {
569 .hw.init = &(const struct clk_init_data) {
570 .name = "gcc_usb4_0_phy_pcie_pipe_mux_clk_src",
571 .parent_data = gcc_parent_data_16,
572 .ops = &clk_regmap_phy_mux_ops,
573 },
574 },
575};
576
577static struct clk_regmap_phy_mux gcc_usb4_0_phy_rx0_clk_src = {
578 .reg = 0x9f0ac,
579 .clkr = {
580 .hw.init = &(const struct clk_init_data) {
581 .name = "gcc_usb4_0_phy_rx0_clk_src",
582 .parent_data = gcc_parent_data_17,
583 .ops = &clk_regmap_phy_mux_ops,
584 },
585 },
586};
587
588static struct clk_regmap_phy_mux gcc_usb4_0_phy_rx1_clk_src = {
589 .reg = 0x9f0bc,
590 .clkr = {
591 .hw.init = &(const struct clk_init_data) {
592 .name = "gcc_usb4_0_phy_rx1_clk_src",
593 .parent_data = gcc_parent_data_18,
594 .ops = &clk_regmap_phy_mux_ops,
595 },
596 },
597};
598
599static struct clk_regmap_phy_mux gcc_usb4_0_phy_sys_clk_src = {
600 .reg = 0x9f0e4,
601 .clkr = {
602 .hw.init = &(const struct clk_init_data) {
603 .name = "gcc_usb4_0_phy_sys_clk_src",
604 .parent_data = gcc_parent_data_19,
605 .ops = &clk_regmap_phy_mux_ops,
606 },
607 },
608};
609
610static struct clk_regmap_phy_mux gcc_usb4_1_phy_dp0_clk_src = {
611 .reg = 0x2b06c,
612 .clkr = {
613 .hw.init = &(const struct clk_init_data) {
614 .name = "gcc_usb4_1_phy_dp0_clk_src",
615 .parent_data = gcc_parent_data_20,
616 .ops = &clk_regmap_phy_mux_ops,
617 },
618 },
619};
620
621static struct clk_regmap_phy_mux gcc_usb4_1_phy_dp1_clk_src = {
622 .reg = 0x2b114,
623 .clkr = {
624 .hw.init = &(const struct clk_init_data) {
625 .name = "gcc_usb4_1_phy_dp1_clk_src",
626 .parent_data = gcc_parent_data_21,
627 .ops = &clk_regmap_phy_mux_ops,
628 },
629 },
630};
631
632static struct clk_regmap_phy_mux gcc_usb4_1_phy_p2rr2p_pipe_clk_src = {
633 .reg = 0x2b0d4,
634 .clkr = {
635 .hw.init = &(const struct clk_init_data) {
636 .name = "gcc_usb4_1_phy_p2rr2p_pipe_clk_src",
637 .parent_data = gcc_parent_data_22,
638 .ops = &clk_regmap_phy_mux_ops,
639 },
640 },
641};
642
643static struct clk_regmap_phy_mux gcc_usb4_1_phy_pcie_pipe_mux_clk_src = {
644 .reg = 0x2b104,
645 .clkr = {
646 .hw.init = &(const struct clk_init_data) {
647 .name = "gcc_usb4_1_phy_pcie_pipe_mux_clk_src",
648 .parent_data = gcc_parent_data_23,
649 .ops = &clk_regmap_phy_mux_ops,
650 },
651 },
652};
653
654static struct clk_regmap_phy_mux gcc_usb4_1_phy_rx0_clk_src = {
655 .reg = 0x2b0ac,
656 .clkr = {
657 .hw.init = &(const struct clk_init_data) {
658 .name = "gcc_usb4_1_phy_rx0_clk_src",
659 .parent_data = gcc_parent_data_24,
660 .ops = &clk_regmap_phy_mux_ops,
661 },
662 },
663};
664
665static struct clk_regmap_phy_mux gcc_usb4_1_phy_rx1_clk_src = {
666 .reg = 0x2b0bc,
667 .clkr = {
668 .hw.init = &(const struct clk_init_data) {
669 .name = "gcc_usb4_1_phy_rx1_clk_src",
670 .parent_data = gcc_parent_data_25,
671 .ops = &clk_regmap_phy_mux_ops,
672 },
673 },
674};
675
676static struct clk_regmap_phy_mux gcc_usb4_1_phy_sys_clk_src = {
677 .reg = 0x2b0e4,
678 .clkr = {
679 .hw.init = &(const struct clk_init_data) {
680 .name = "gcc_usb4_1_phy_sys_clk_src",
681 .parent_data = gcc_parent_data_26,
682 .ops = &clk_regmap_phy_mux_ops,
683 },
684 },
685};
686
687static struct clk_regmap_phy_mux gcc_usb4_2_phy_dp0_clk_src = {
688 .reg = 0x1106c,
689 .clkr = {
690 .hw.init = &(const struct clk_init_data) {
691 .name = "gcc_usb4_2_phy_dp0_clk_src",
692 .parent_data = gcc_parent_data_27,
693 .ops = &clk_regmap_phy_mux_ops,
694 },
695 },
696};
697
698static struct clk_regmap_phy_mux gcc_usb4_2_phy_dp1_clk_src = {
699 .reg = 0x11114,
700 .clkr = {
701 .hw.init = &(const struct clk_init_data) {
702 .name = "gcc_usb4_2_phy_dp1_clk_src",
703 .parent_data = gcc_parent_data_28,
704 .ops = &clk_regmap_phy_mux_ops,
705 },
706 },
707};
708
709static struct clk_regmap_phy_mux gcc_usb4_2_phy_p2rr2p_pipe_clk_src = {
710 .reg = 0x110d4,
711 .clkr = {
712 .hw.init = &(const struct clk_init_data) {
713 .name = "gcc_usb4_2_phy_p2rr2p_pipe_clk_src",
714 .parent_data = gcc_parent_data_29,
715 .ops = &clk_regmap_phy_mux_ops,
716 },
717 },
718};
719
720static struct clk_regmap_phy_mux gcc_usb4_2_phy_pcie_pipe_mux_clk_src = {
721 .reg = 0x11104,
722 .clkr = {
723 .hw.init = &(const struct clk_init_data) {
724 .name = "gcc_usb4_2_phy_pcie_pipe_mux_clk_src",
725 .parent_data = gcc_parent_data_30,
726 .ops = &clk_regmap_phy_mux_ops,
727 },
728 },
729};
730
731static struct clk_regmap_phy_mux gcc_usb4_2_phy_rx0_clk_src = {
732 .reg = 0x110ac,
733 .clkr = {
734 .hw.init = &(const struct clk_init_data) {
735 .name = "gcc_usb4_2_phy_rx0_clk_src",
736 .parent_data = gcc_parent_data_31,
737 .ops = &clk_regmap_phy_mux_ops,
738 },
739 },
740};
741
742static struct clk_regmap_phy_mux gcc_usb4_2_phy_rx1_clk_src = {
743 .reg = 0x110bc,
744 .clkr = {
745 .hw.init = &(const struct clk_init_data) {
746 .name = "gcc_usb4_2_phy_rx1_clk_src",
747 .parent_data = gcc_parent_data_32,
748 .ops = &clk_regmap_phy_mux_ops,
749 },
750 },
751};
752
753static struct clk_regmap_phy_mux gcc_usb4_2_phy_sys_clk_src = {
754 .reg = 0x110e4,
755 .clkr = {
756 .hw.init = &(const struct clk_init_data) {
757 .name = "gcc_usb4_2_phy_sys_clk_src",
758 .parent_data = gcc_parent_data_33,
759 .ops = &clk_regmap_phy_mux_ops,
760 },
761 },
762};
763
764static struct clk_rcg2 gcc_gp1_clk_src = {
765 .cmd_rcgr = 0x64004,
766 .mnd_width = 16,
767 .hid_width = 5,
768 .parent_map = gcc_parent_map_2,
769 .freq_tbl = ftbl_gcc_gp1_clk_src,
770 .clkr.hw.init = &(const struct clk_init_data) {
771 .name = "gcc_gp1_clk_src",
772 .parent_data = gcc_parent_data_2,
773 .num_parents = ARRAY_SIZE(gcc_parent_data_2),
774 .flags = CLK_SET_RATE_PARENT,
775 .ops = &clk_rcg2_shared_ops,
776 },
777};
778
779static struct clk_rcg2 gcc_gp2_clk_src = {
780 .cmd_rcgr = 0x65004,
781 .mnd_width = 16,
782 .hid_width = 5,
783 .parent_map = gcc_parent_map_2,
784 .freq_tbl = ftbl_gcc_gp1_clk_src,
785 .clkr.hw.init = &(const struct clk_init_data) {
786 .name = "gcc_gp2_clk_src",
787 .parent_data = gcc_parent_data_2,
788 .num_parents = ARRAY_SIZE(gcc_parent_data_2),
789 .flags = CLK_SET_RATE_PARENT,
790 .ops = &clk_rcg2_shared_ops,
791 },
792};
793
794static struct clk_rcg2 gcc_gp3_clk_src = {
795 .cmd_rcgr = 0x66004,
796 .mnd_width = 16,
797 .hid_width = 5,
798 .parent_map = gcc_parent_map_2,
799 .freq_tbl = ftbl_gcc_gp1_clk_src,
800 .clkr.hw.init = &(const struct clk_init_data) {
801 .name = "gcc_gp3_clk_src",
802 .parent_data = gcc_parent_data_2,
803 .num_parents = ARRAY_SIZE(gcc_parent_data_2),
804 .flags = CLK_SET_RATE_PARENT,
805 .ops = &clk_rcg2_shared_ops,
806 },
807};
808
809static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = {
810 F(19200000, P_BI_TCXO, 1, 0, 0),
811 { }
812};
813
814static struct clk_rcg2 gcc_pcie_0_aux_clk_src = {
815 .cmd_rcgr = 0xa0180,
816 .mnd_width = 16,
817 .hid_width = 5,
818 .parent_map = gcc_parent_map_1,
819 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
820 .clkr.hw.init = &(const struct clk_init_data) {
821 .name = "gcc_pcie_0_aux_clk_src",
822 .parent_data = gcc_parent_data_1,
823 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
824 .flags = CLK_SET_RATE_PARENT,
825 .ops = &clk_rcg2_shared_ops,
826 },
827};
828
829static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = {
830 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
831 { }
832};
833
834static struct clk_rcg2 gcc_pcie_0_phy_rchng_clk_src = {
835 .cmd_rcgr = 0xa0054,
836 .mnd_width = 0,
837 .hid_width = 5,
838 .parent_map = gcc_parent_map_0,
839 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
840 .clkr.hw.init = &(const struct clk_init_data) {
841 .name = "gcc_pcie_0_phy_rchng_clk_src",
842 .parent_data = gcc_parent_data_0,
843 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
844 .flags = CLK_SET_RATE_PARENT,
845 .ops = &clk_rcg2_shared_ops,
846 },
847};
848
849static struct clk_rcg2 gcc_pcie_1_aux_clk_src = {
850 .cmd_rcgr = 0x2c180,
851 .mnd_width = 16,
852 .hid_width = 5,
853 .parent_map = gcc_parent_map_1,
854 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
855 .clkr.hw.init = &(const struct clk_init_data) {
856 .name = "gcc_pcie_1_aux_clk_src",
857 .parent_data = gcc_parent_data_1,
858 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
859 .flags = CLK_SET_RATE_PARENT,
860 .ops = &clk_rcg2_shared_ops,
861 },
862};
863
864static struct clk_rcg2 gcc_pcie_1_phy_rchng_clk_src = {
865 .cmd_rcgr = 0x2c054,
866 .mnd_width = 0,
867 .hid_width = 5,
868 .parent_map = gcc_parent_map_0,
869 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
870 .clkr.hw.init = &(const struct clk_init_data) {
871 .name = "gcc_pcie_1_phy_rchng_clk_src",
872 .parent_data = gcc_parent_data_0,
873 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
874 .flags = CLK_SET_RATE_PARENT,
875 .ops = &clk_rcg2_shared_ops,
876 },
877};
878
879static struct clk_rcg2 gcc_pcie_2_aux_clk_src = {
880 .cmd_rcgr = 0x13180,
881 .mnd_width = 16,
882 .hid_width = 5,
883 .parent_map = gcc_parent_map_1,
884 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
885 .clkr.hw.init = &(const struct clk_init_data) {
886 .name = "gcc_pcie_2_aux_clk_src",
887 .parent_data = gcc_parent_data_1,
888 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
889 .flags = CLK_SET_RATE_PARENT,
890 .ops = &clk_rcg2_shared_ops,
891 },
892};
893
894static struct clk_rcg2 gcc_pcie_2_phy_rchng_clk_src = {
895 .cmd_rcgr = 0x13054,
896 .mnd_width = 0,
897 .hid_width = 5,
898 .parent_map = gcc_parent_map_0,
899 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
900 .clkr.hw.init = &(const struct clk_init_data) {
901 .name = "gcc_pcie_2_phy_rchng_clk_src",
902 .parent_data = gcc_parent_data_0,
903 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
904 .flags = CLK_SET_RATE_PARENT,
905 .ops = &clk_rcg2_shared_ops,
906 },
907};
908
909static struct clk_rcg2 gcc_pcie_3_aux_clk_src = {
910 .cmd_rcgr = 0x5808c,
911 .mnd_width = 16,
912 .hid_width = 5,
913 .parent_map = gcc_parent_map_1,
914 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
915 .clkr.hw.init = &(const struct clk_init_data) {
916 .name = "gcc_pcie_3_aux_clk_src",
917 .parent_data = gcc_parent_data_1,
918 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
919 .flags = CLK_SET_RATE_PARENT,
920 .ops = &clk_rcg2_shared_ops,
921 },
922};
923
924static struct clk_rcg2 gcc_pcie_3_phy_rchng_clk_src = {
925 .cmd_rcgr = 0x58070,
926 .mnd_width = 0,
927 .hid_width = 5,
928 .parent_map = gcc_parent_map_0,
929 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
930 .clkr.hw.init = &(const struct clk_init_data) {
931 .name = "gcc_pcie_3_phy_rchng_clk_src",
932 .parent_data = gcc_parent_data_0,
933 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
934 .flags = CLK_SET_RATE_PARENT,
935 .ops = &clk_rcg2_shared_ops,
936 },
937};
938
939static struct clk_rcg2 gcc_pcie_4_aux_clk_src = {
940 .cmd_rcgr = 0x6b080,
941 .mnd_width = 16,
942 .hid_width = 5,
943 .parent_map = gcc_parent_map_1,
944 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
945 .clkr.hw.init = &(const struct clk_init_data) {
946 .name = "gcc_pcie_4_aux_clk_src",
947 .parent_data = gcc_parent_data_1,
948 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
949 .flags = CLK_SET_RATE_PARENT,
950 .ops = &clk_rcg2_shared_ops,
951 },
952};
953
954static struct clk_rcg2 gcc_pcie_4_phy_rchng_clk_src = {
955 .cmd_rcgr = 0x6b064,
956 .mnd_width = 0,
957 .hid_width = 5,
958 .parent_map = gcc_parent_map_0,
959 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
960 .clkr.hw.init = &(const struct clk_init_data) {
961 .name = "gcc_pcie_4_phy_rchng_clk_src",
962 .parent_data = gcc_parent_data_0,
963 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
964 .flags = CLK_SET_RATE_PARENT,
965 .ops = &clk_rcg2_shared_ops,
966 },
967};
968
969static struct clk_rcg2 gcc_pcie_5_aux_clk_src = {
970 .cmd_rcgr = 0x2f080,
971 .mnd_width = 16,
972 .hid_width = 5,
973 .parent_map = gcc_parent_map_1,
974 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
975 .clkr.hw.init = &(const struct clk_init_data) {
976 .name = "gcc_pcie_5_aux_clk_src",
977 .parent_data = gcc_parent_data_1,
978 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
979 .flags = CLK_SET_RATE_PARENT,
980 .ops = &clk_rcg2_shared_ops,
981 },
982};
983
984static struct clk_rcg2 gcc_pcie_5_phy_rchng_clk_src = {
985 .cmd_rcgr = 0x2f064,
986 .mnd_width = 0,
987 .hid_width = 5,
988 .parent_map = gcc_parent_map_0,
989 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
990 .clkr.hw.init = &(const struct clk_init_data) {
991 .name = "gcc_pcie_5_phy_rchng_clk_src",
992 .parent_data = gcc_parent_data_0,
993 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
994 .flags = CLK_SET_RATE_PARENT,
995 .ops = &clk_rcg2_shared_ops,
996 },
997};
998
999static struct clk_rcg2 gcc_pcie_6a_aux_clk_src = {
1000 .cmd_rcgr = 0x3108c,
1001 .mnd_width = 16,
1002 .hid_width = 5,
1003 .parent_map = gcc_parent_map_1,
1004 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
1005 .clkr.hw.init = &(const struct clk_init_data) {
1006 .name = "gcc_pcie_6a_aux_clk_src",
1007 .parent_data = gcc_parent_data_1,
1008 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
1009 .flags = CLK_SET_RATE_PARENT,
1010 .ops = &clk_rcg2_shared_ops,
1011 },
1012};
1013
1014static struct clk_rcg2 gcc_pcie_6a_phy_rchng_clk_src = {
1015 .cmd_rcgr = 0x31070,
1016 .mnd_width = 0,
1017 .hid_width = 5,
1018 .parent_map = gcc_parent_map_0,
1019 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
1020 .clkr.hw.init = &(const struct clk_init_data) {
1021 .name = "gcc_pcie_6a_phy_rchng_clk_src",
1022 .parent_data = gcc_parent_data_0,
1023 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1024 .flags = CLK_SET_RATE_PARENT,
1025 .ops = &clk_rcg2_shared_ops,
1026 },
1027};
1028
1029static struct clk_rcg2 gcc_pcie_6b_aux_clk_src = {
1030 .cmd_rcgr = 0x8d08c,
1031 .mnd_width = 16,
1032 .hid_width = 5,
1033 .parent_map = gcc_parent_map_1,
1034 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
1035 .clkr.hw.init = &(const struct clk_init_data) {
1036 .name = "gcc_pcie_6b_aux_clk_src",
1037 .parent_data = gcc_parent_data_1,
1038 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
1039 .flags = CLK_SET_RATE_PARENT,
1040 .ops = &clk_rcg2_shared_ops,
1041 },
1042};
1043
1044static struct clk_rcg2 gcc_pcie_6b_phy_rchng_clk_src = {
1045 .cmd_rcgr = 0x8d070,
1046 .mnd_width = 0,
1047 .hid_width = 5,
1048 .parent_map = gcc_parent_map_0,
1049 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
1050 .clkr.hw.init = &(const struct clk_init_data) {
1051 .name = "gcc_pcie_6b_phy_rchng_clk_src",
1052 .parent_data = gcc_parent_data_0,
1053 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1054 .flags = CLK_SET_RATE_PARENT,
1055 .ops = &clk_rcg2_shared_ops,
1056 },
1057};
1058
1059static struct clk_rcg2 gcc_pcie_rscc_xo_clk_src = {
1060 .cmd_rcgr = 0xa400c,
1061 .mnd_width = 0,
1062 .hid_width = 5,
1063 .parent_map = gcc_parent_map_3,
1064 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
1065 .clkr.hw.init = &(const struct clk_init_data) {
1066 .name = "gcc_pcie_rscc_xo_clk_src",
1067 .parent_data = gcc_parent_data_3,
1068 .num_parents = ARRAY_SIZE(gcc_parent_data_3),
1069 .flags = CLK_SET_RATE_PARENT,
1070 .ops = &clk_rcg2_shared_ops,
1071 },
1072};
1073
1074static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
1075 F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0),
1076 { }
1077};
1078
1079static struct clk_rcg2 gcc_pdm2_clk_src = {
1080 .cmd_rcgr = 0x33010,
1081 .mnd_width = 0,
1082 .hid_width = 5,
1083 .parent_map = gcc_parent_map_0,
1084 .freq_tbl = ftbl_gcc_pdm2_clk_src,
1085 .clkr.hw.init = &(const struct clk_init_data) {
1086 .name = "gcc_pdm2_clk_src",
1087 .parent_data = gcc_parent_data_0,
1088 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1089 .flags = CLK_SET_RATE_PARENT,
1090 .ops = &clk_rcg2_shared_ops,
1091 },
1092};
1093
1094static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
1095 F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
1096 F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
1097 F(19200000, P_BI_TCXO, 1, 0, 0),
1098 F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
1099 F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
1100 F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
1101 F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
1102 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1103 F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
1104 F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
1105 F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0),
1106 { }
1107};
1108
1109static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
1110 .name = "gcc_qupv3_wrap0_s0_clk_src",
1111 .parent_data = gcc_parent_data_0,
1112 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1113 .flags = CLK_SET_RATE_PARENT,
1114 .ops = &clk_rcg2_ops,
1115};
1116
1117static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
1118 .cmd_rcgr = 0x42010,
1119 .mnd_width = 16,
1120 .hid_width = 5,
1121 .parent_map = gcc_parent_map_0,
1122 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
1123 .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init,
1124};
1125
1126static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
1127 .name = "gcc_qupv3_wrap0_s1_clk_src",
1128 .parent_data = gcc_parent_data_0,
1129 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1130 .flags = CLK_SET_RATE_PARENT,
1131 .ops = &clk_rcg2_ops,
1132};
1133
1134static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
1135 .cmd_rcgr = 0x42148,
1136 .mnd_width = 16,
1137 .hid_width = 5,
1138 .parent_map = gcc_parent_map_0,
1139 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
1140 .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init,
1141};
1142
1143static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s2_clk_src[] = {
1144 F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
1145 F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
1146 F(19200000, P_BI_TCXO, 1, 0, 0),
1147 F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
1148 F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
1149 F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
1150 F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
1151 F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
1152 F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
1153 F(150000000, P_GCC_GPLL0_OUT_EVEN, 2, 0, 0),
1154 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
1155 { }
1156};
1157
1158static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
1159 .name = "gcc_qupv3_wrap0_s2_clk_src",
1160 .parent_data = gcc_parent_data_0,
1161 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1162 .flags = CLK_SET_RATE_PARENT,
1163 .ops = &clk_rcg2_ops,
1164};
1165
1166static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
1167 .cmd_rcgr = 0x42288,
1168 .mnd_width = 16,
1169 .hid_width = 5,
1170 .parent_map = gcc_parent_map_0,
1171 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
1172 .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init,
1173};
1174
1175static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
1176 .name = "gcc_qupv3_wrap0_s3_clk_src",
1177 .parent_data = gcc_parent_data_0,
1178 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1179 .flags = CLK_SET_RATE_PARENT,
1180 .ops = &clk_rcg2_ops,
1181};
1182
1183static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
1184 .cmd_rcgr = 0x423c8,
1185 .mnd_width = 16,
1186 .hid_width = 5,
1187 .parent_map = gcc_parent_map_0,
1188 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
1189 .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init,
1190};
1191
1192static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s4_clk_src[] = {
1193 F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
1194 F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
1195 F(19200000, P_BI_TCXO, 1, 0, 0),
1196 F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
1197 F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
1198 F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
1199 F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
1200 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1201 F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
1202 F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
1203 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
1204 { }
1205};
1206
1207static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
1208 .name = "gcc_qupv3_wrap0_s4_clk_src",
1209 .parent_data = gcc_parent_data_0,
1210 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1211 .flags = CLK_SET_RATE_PARENT,
1212 .ops = &clk_rcg2_ops,
1213};
1214
1215static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
1216 .cmd_rcgr = 0x42500,
1217 .mnd_width = 16,
1218 .hid_width = 5,
1219 .parent_map = gcc_parent_map_0,
1220 .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src,
1221 .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init,
1222};
1223
1224static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
1225 .name = "gcc_qupv3_wrap0_s5_clk_src",
1226 .parent_data = gcc_parent_data_0,
1227 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1228 .flags = CLK_SET_RATE_PARENT,
1229 .ops = &clk_rcg2_ops,
1230};
1231
1232static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
1233 .cmd_rcgr = 0x42638,
1234 .mnd_width = 16,
1235 .hid_width = 5,
1236 .parent_map = gcc_parent_map_0,
1237 .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src,
1238 .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init,
1239};
1240
1241static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = {
1242 .name = "gcc_qupv3_wrap0_s6_clk_src",
1243 .parent_data = gcc_parent_data_0,
1244 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1245 .flags = CLK_SET_RATE_PARENT,
1246 .ops = &clk_rcg2_ops,
1247};
1248
1249static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
1250 .cmd_rcgr = 0x42770,
1251 .mnd_width = 16,
1252 .hid_width = 5,
1253 .parent_map = gcc_parent_map_0,
1254 .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src,
1255 .clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_src_init,
1256};
1257
1258static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = {
1259 .name = "gcc_qupv3_wrap0_s7_clk_src",
1260 .parent_data = gcc_parent_data_0,
1261 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1262 .flags = CLK_SET_RATE_PARENT,
1263 .ops = &clk_rcg2_ops,
1264};
1265
1266static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {
1267 .cmd_rcgr = 0x428a8,
1268 .mnd_width = 16,
1269 .hid_width = 5,
1270 .parent_map = gcc_parent_map_0,
1271 .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src,
1272 .clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_src_init,
1273};
1274
1275static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
1276 .name = "gcc_qupv3_wrap1_s0_clk_src",
1277 .parent_data = gcc_parent_data_0,
1278 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1279 .flags = CLK_SET_RATE_PARENT,
1280 .ops = &clk_rcg2_ops,
1281};
1282
1283static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
1284 .cmd_rcgr = 0x18010,
1285 .mnd_width = 16,
1286 .hid_width = 5,
1287 .parent_map = gcc_parent_map_0,
1288 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
1289 .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init,
1290};
1291
1292static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
1293 .name = "gcc_qupv3_wrap1_s1_clk_src",
1294 .parent_data = gcc_parent_data_0,
1295 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1296 .flags = CLK_SET_RATE_PARENT,
1297 .ops = &clk_rcg2_ops,
1298};
1299
1300static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
1301 .cmd_rcgr = 0x18148,
1302 .mnd_width = 16,
1303 .hid_width = 5,
1304 .parent_map = gcc_parent_map_0,
1305 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
1306 .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init,
1307};
1308
1309static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {
1310 .name = "gcc_qupv3_wrap1_s2_clk_src",
1311 .parent_data = gcc_parent_data_0,
1312 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1313 .flags = CLK_SET_RATE_PARENT,
1314 .ops = &clk_rcg2_ops,
1315};
1316
1317static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
1318 .cmd_rcgr = 0x18288,
1319 .mnd_width = 16,
1320 .hid_width = 5,
1321 .parent_map = gcc_parent_map_0,
1322 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
1323 .clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init,
1324};
1325
1326static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
1327 .name = "gcc_qupv3_wrap1_s3_clk_src",
1328 .parent_data = gcc_parent_data_0,
1329 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1330 .flags = CLK_SET_RATE_PARENT,
1331 .ops = &clk_rcg2_ops,
1332};
1333
1334static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
1335 .cmd_rcgr = 0x183c8,
1336 .mnd_width = 16,
1337 .hid_width = 5,
1338 .parent_map = gcc_parent_map_0,
1339 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
1340 .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init,
1341};
1342
1343static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
1344 .name = "gcc_qupv3_wrap1_s4_clk_src",
1345 .parent_data = gcc_parent_data_0,
1346 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1347 .flags = CLK_SET_RATE_PARENT,
1348 .ops = &clk_rcg2_ops,
1349};
1350
1351static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
1352 .cmd_rcgr = 0x18500,
1353 .mnd_width = 16,
1354 .hid_width = 5,
1355 .parent_map = gcc_parent_map_0,
1356 .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src,
1357 .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init,
1358};
1359
1360static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
1361 .name = "gcc_qupv3_wrap1_s5_clk_src",
1362 .parent_data = gcc_parent_data_0,
1363 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1364 .flags = CLK_SET_RATE_PARENT,
1365 .ops = &clk_rcg2_ops,
1366};
1367
1368static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
1369 .cmd_rcgr = 0x18638,
1370 .mnd_width = 16,
1371 .hid_width = 5,
1372 .parent_map = gcc_parent_map_0,
1373 .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src,
1374 .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init,
1375};
1376
1377static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = {
1378 .name = "gcc_qupv3_wrap1_s6_clk_src",
1379 .parent_data = gcc_parent_data_0,
1380 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1381 .flags = CLK_SET_RATE_PARENT,
1382 .ops = &clk_rcg2_ops,
1383};
1384
1385static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = {
1386 .cmd_rcgr = 0x18770,
1387 .mnd_width = 16,
1388 .hid_width = 5,
1389 .parent_map = gcc_parent_map_0,
1390 .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src,
1391 .clkr.hw.init = &gcc_qupv3_wrap1_s6_clk_src_init,
1392};
1393
1394static struct clk_init_data gcc_qupv3_wrap1_s7_clk_src_init = {
1395 .name = "gcc_qupv3_wrap1_s7_clk_src",
1396 .parent_data = gcc_parent_data_0,
1397 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1398 .flags = CLK_SET_RATE_PARENT,
1399 .ops = &clk_rcg2_ops,
1400};
1401
1402static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = {
1403 .cmd_rcgr = 0x188a8,
1404 .mnd_width = 16,
1405 .hid_width = 5,
1406 .parent_map = gcc_parent_map_0,
1407 .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src,
1408 .clkr.hw.init = &gcc_qupv3_wrap1_s7_clk_src_init,
1409};
1410
1411static struct clk_init_data gcc_qupv3_wrap2_s0_clk_src_init = {
1412 .name = "gcc_qupv3_wrap2_s0_clk_src",
1413 .parent_data = gcc_parent_data_0,
1414 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1415 .flags = CLK_SET_RATE_PARENT,
1416 .ops = &clk_rcg2_ops,
1417};
1418
1419static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = {
1420 .cmd_rcgr = 0x1e010,
1421 .mnd_width = 16,
1422 .hid_width = 5,
1423 .parent_map = gcc_parent_map_0,
1424 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
1425 .clkr.hw.init = &gcc_qupv3_wrap2_s0_clk_src_init,
1426};
1427
1428static struct clk_init_data gcc_qupv3_wrap2_s1_clk_src_init = {
1429 .name = "gcc_qupv3_wrap2_s1_clk_src",
1430 .parent_data = gcc_parent_data_0,
1431 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1432 .flags = CLK_SET_RATE_PARENT,
1433 .ops = &clk_rcg2_ops,
1434};
1435
1436static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = {
1437 .cmd_rcgr = 0x1e148,
1438 .mnd_width = 16,
1439 .hid_width = 5,
1440 .parent_map = gcc_parent_map_0,
1441 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
1442 .clkr.hw.init = &gcc_qupv3_wrap2_s1_clk_src_init,
1443};
1444
1445static struct clk_init_data gcc_qupv3_wrap2_s2_clk_src_init = {
1446 .name = "gcc_qupv3_wrap2_s2_clk_src",
1447 .parent_data = gcc_parent_data_0,
1448 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1449 .flags = CLK_SET_RATE_PARENT,
1450 .ops = &clk_rcg2_ops,
1451};
1452
1453static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = {
1454 .cmd_rcgr = 0x1e288,
1455 .mnd_width = 16,
1456 .hid_width = 5,
1457 .parent_map = gcc_parent_map_0,
1458 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
1459 .clkr.hw.init = &gcc_qupv3_wrap2_s2_clk_src_init,
1460};
1461
1462static struct clk_init_data gcc_qupv3_wrap2_s3_clk_src_init = {
1463 .name = "gcc_qupv3_wrap2_s3_clk_src",
1464 .parent_data = gcc_parent_data_0,
1465 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1466 .flags = CLK_SET_RATE_PARENT,
1467 .ops = &clk_rcg2_ops,
1468};
1469
1470static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = {
1471 .cmd_rcgr = 0x1e3c8,
1472 .mnd_width = 16,
1473 .hid_width = 5,
1474 .parent_map = gcc_parent_map_0,
1475 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
1476 .clkr.hw.init = &gcc_qupv3_wrap2_s3_clk_src_init,
1477};
1478
1479static struct clk_init_data gcc_qupv3_wrap2_s4_clk_src_init = {
1480 .name = "gcc_qupv3_wrap2_s4_clk_src",
1481 .parent_data = gcc_parent_data_0,
1482 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1483 .flags = CLK_SET_RATE_PARENT,
1484 .ops = &clk_rcg2_ops,
1485};
1486
1487static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = {
1488 .cmd_rcgr = 0x1e500,
1489 .mnd_width = 16,
1490 .hid_width = 5,
1491 .parent_map = gcc_parent_map_0,
1492 .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src,
1493 .clkr.hw.init = &gcc_qupv3_wrap2_s4_clk_src_init,
1494};
1495
1496static struct clk_init_data gcc_qupv3_wrap2_s5_clk_src_init = {
1497 .name = "gcc_qupv3_wrap2_s5_clk_src",
1498 .parent_data = gcc_parent_data_0,
1499 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1500 .flags = CLK_SET_RATE_PARENT,
1501 .ops = &clk_rcg2_ops,
1502};
1503
1504static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = {
1505 .cmd_rcgr = 0x1e638,
1506 .mnd_width = 16,
1507 .hid_width = 5,
1508 .parent_map = gcc_parent_map_0,
1509 .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src,
1510 .clkr.hw.init = &gcc_qupv3_wrap2_s5_clk_src_init,
1511};
1512
1513static struct clk_init_data gcc_qupv3_wrap2_s6_clk_src_init = {
1514 .name = "gcc_qupv3_wrap2_s6_clk_src",
1515 .parent_data = gcc_parent_data_8,
1516 .num_parents = ARRAY_SIZE(gcc_parent_data_8),
1517 .flags = CLK_SET_RATE_PARENT,
1518 .ops = &clk_rcg2_ops,
1519};
1520
1521static struct clk_rcg2 gcc_qupv3_wrap2_s6_clk_src = {
1522 .cmd_rcgr = 0x1e770,
1523 .mnd_width = 16,
1524 .hid_width = 5,
1525 .parent_map = gcc_parent_map_8,
1526 .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src,
1527 .clkr.hw.init = &gcc_qupv3_wrap2_s6_clk_src_init,
1528};
1529
1530static struct clk_init_data gcc_qupv3_wrap2_s7_clk_src_init = {
1531 .name = "gcc_qupv3_wrap2_s7_clk_src",
1532 .parent_data = gcc_parent_data_0,
1533 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1534 .flags = CLK_SET_RATE_PARENT,
1535 .ops = &clk_rcg2_ops,
1536};
1537
1538static struct clk_rcg2 gcc_qupv3_wrap2_s7_clk_src = {
1539 .cmd_rcgr = 0x1e8a8,
1540 .mnd_width = 16,
1541 .hid_width = 5,
1542 .parent_map = gcc_parent_map_0,
1543 .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src,
1544 .clkr.hw.init = &gcc_qupv3_wrap2_s7_clk_src_init,
1545};
1546
1547static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
1548 F(400000, P_BI_TCXO, 12, 1, 4),
1549 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
1550 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
1551 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
1552 F(202000000, P_GCC_GPLL9_OUT_MAIN, 4, 0, 0),
1553 { }
1554};
1555
1556static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
1557 .cmd_rcgr = 0x14018,
1558 .mnd_width = 8,
1559 .hid_width = 5,
1560 .parent_map = gcc_parent_map_9,
1561 .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
1562 .clkr.hw.init = &(const struct clk_init_data) {
1563 .name = "gcc_sdcc2_apps_clk_src",
1564 .parent_data = gcc_parent_data_9,
1565 .num_parents = ARRAY_SIZE(gcc_parent_data_9),
1566 .flags = CLK_SET_RATE_PARENT,
1567 .ops = &clk_rcg2_shared_floor_ops,
1568 },
1569};
1570
1571static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = {
1572 F(400000, P_BI_TCXO, 12, 1, 4),
1573 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
1574 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1575 { }
1576};
1577
1578static struct clk_rcg2 gcc_sdcc4_apps_clk_src = {
1579 .cmd_rcgr = 0x16018,
1580 .mnd_width = 8,
1581 .hid_width = 5,
1582 .parent_map = gcc_parent_map_0,
1583 .freq_tbl = ftbl_gcc_sdcc4_apps_clk_src,
1584 .clkr.hw.init = &(const struct clk_init_data) {
1585 .name = "gcc_sdcc4_apps_clk_src",
1586 .parent_data = gcc_parent_data_0,
1587 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1588 .flags = CLK_SET_RATE_PARENT,
1589 .ops = &clk_rcg2_shared_floor_ops,
1590 },
1591};
1592
1593static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {
1594 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
1595 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1596 F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
1597 F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
1598 { }
1599};
1600
1601static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
1602 .cmd_rcgr = 0x77030,
1603 .mnd_width = 8,
1604 .hid_width = 5,
1605 .parent_map = gcc_parent_map_0,
1606 .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src,
1607 .clkr.hw.init = &(const struct clk_init_data) {
1608 .name = "gcc_ufs_phy_axi_clk_src",
1609 .parent_data = gcc_parent_data_0,
1610 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1611 .flags = CLK_SET_RATE_PARENT,
1612 .ops = &clk_rcg2_shared_ops,
1613 },
1614};
1615
1616static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = {
1617 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
1618 F(201500000, P_GCC_GPLL4_OUT_MAIN, 4, 0, 0),
1619 F(403000000, P_GCC_GPLL4_OUT_MAIN, 2, 0, 0),
1620 { }
1621};
1622
1623static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {
1624 .cmd_rcgr = 0x77080,
1625 .mnd_width = 0,
1626 .hid_width = 5,
1627 .parent_map = gcc_parent_map_7,
1628 .freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src,
1629 .clkr.hw.init = &(const struct clk_init_data) {
1630 .name = "gcc_ufs_phy_ice_core_clk_src",
1631 .parent_data = gcc_parent_data_7,
1632 .num_parents = ARRAY_SIZE(gcc_parent_data_7),
1633 .flags = CLK_SET_RATE_PARENT,
1634 .ops = &clk_rcg2_shared_ops,
1635 },
1636};
1637
1638static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
1639 .cmd_rcgr = 0x770b4,
1640 .mnd_width = 0,
1641 .hid_width = 5,
1642 .parent_map = gcc_parent_map_3,
1643 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
1644 .clkr.hw.init = &(const struct clk_init_data) {
1645 .name = "gcc_ufs_phy_phy_aux_clk_src",
1646 .parent_data = gcc_parent_data_3,
1647 .num_parents = ARRAY_SIZE(gcc_parent_data_3),
1648 .flags = CLK_SET_RATE_PARENT,
1649 .ops = &clk_rcg2_shared_ops,
1650 },
1651};
1652
1653static const struct freq_tbl ftbl_gcc_ufs_phy_unipro_core_clk_src[] = {
1654 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1655 F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
1656 F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
1657 { }
1658};
1659
1660static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
1661 .cmd_rcgr = 0x77098,
1662 .mnd_width = 0,
1663 .hid_width = 5,
1664 .parent_map = gcc_parent_map_0,
1665 .freq_tbl = ftbl_gcc_ufs_phy_unipro_core_clk_src,
1666 .clkr.hw.init = &(const struct clk_init_data) {
1667 .name = "gcc_ufs_phy_unipro_core_clk_src",
1668 .parent_data = gcc_parent_data_0,
1669 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1670 .flags = CLK_SET_RATE_PARENT,
1671 .ops = &clk_rcg2_shared_ops,
1672 },
1673};
1674
1675static const struct freq_tbl ftbl_gcc_usb20_master_clk_src[] = {
1676 F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0),
1677 F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0),
1678 { }
1679};
1680
1681static struct clk_rcg2 gcc_usb20_master_clk_src = {
1682 .cmd_rcgr = 0x2902c,
1683 .mnd_width = 8,
1684 .hid_width = 5,
1685 .parent_map = gcc_parent_map_0,
1686 .freq_tbl = ftbl_gcc_usb20_master_clk_src,
1687 .clkr.hw.init = &(const struct clk_init_data) {
1688 .name = "gcc_usb20_master_clk_src",
1689 .parent_data = gcc_parent_data_0,
1690 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1691 .flags = CLK_SET_RATE_PARENT,
1692 .ops = &clk_rcg2_shared_ops,
1693 },
1694};
1695
1696static struct clk_rcg2 gcc_usb20_mock_utmi_clk_src = {
1697 .cmd_rcgr = 0x29158,
1698 .mnd_width = 0,
1699 .hid_width = 5,
1700 .parent_map = gcc_parent_map_0,
1701 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
1702 .clkr.hw.init = &(const struct clk_init_data) {
1703 .name = "gcc_usb20_mock_utmi_clk_src",
1704 .parent_data = gcc_parent_data_0,
1705 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1706 .flags = CLK_SET_RATE_PARENT,
1707 .ops = &clk_rcg2_shared_ops,
1708 },
1709};
1710
1711static const struct freq_tbl ftbl_gcc_usb30_mp_master_clk_src[] = {
1712 F(66666667, P_GCC_GPLL0_OUT_EVEN, 4.5, 0, 0),
1713 F(133333333, P_GCC_GPLL0_OUT_MAIN, 4.5, 0, 0),
1714 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
1715 F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0),
1716 { }
1717};
1718
1719static struct clk_rcg2 gcc_usb30_mp_master_clk_src = {
1720 .cmd_rcgr = 0x1702c,
1721 .mnd_width = 8,
1722 .hid_width = 5,
1723 .parent_map = gcc_parent_map_0,
1724 .freq_tbl = ftbl_gcc_usb30_mp_master_clk_src,
1725 .clkr.hw.init = &(const struct clk_init_data) {
1726 .name = "gcc_usb30_mp_master_clk_src",
1727 .parent_data = gcc_parent_data_0,
1728 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1729 .flags = CLK_SET_RATE_PARENT,
1730 .ops = &clk_rcg2_shared_ops,
1731 },
1732};
1733
1734static struct clk_rcg2 gcc_usb30_mp_mock_utmi_clk_src = {
1735 .cmd_rcgr = 0x17158,
1736 .mnd_width = 0,
1737 .hid_width = 5,
1738 .parent_map = gcc_parent_map_0,
1739 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
1740 .clkr.hw.init = &(const struct clk_init_data) {
1741 .name = "gcc_usb30_mp_mock_utmi_clk_src",
1742 .parent_data = gcc_parent_data_0,
1743 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1744 .flags = CLK_SET_RATE_PARENT,
1745 .ops = &clk_rcg2_shared_ops,
1746 },
1747};
1748
1749static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
1750 .cmd_rcgr = 0x3902c,
1751 .mnd_width = 8,
1752 .hid_width = 5,
1753 .parent_map = gcc_parent_map_0,
1754 .freq_tbl = ftbl_gcc_usb30_mp_master_clk_src,
1755 .clkr.hw.init = &(const struct clk_init_data) {
1756 .name = "gcc_usb30_prim_master_clk_src",
1757 .parent_data = gcc_parent_data_0,
1758 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1759 .flags = CLK_SET_RATE_PARENT,
1760 .ops = &clk_rcg2_shared_ops,
1761 },
1762};
1763
1764static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
1765 .cmd_rcgr = 0x39044,
1766 .mnd_width = 0,
1767 .hid_width = 5,
1768 .parent_map = gcc_parent_map_0,
1769 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
1770 .clkr.hw.init = &(const struct clk_init_data) {
1771 .name = "gcc_usb30_prim_mock_utmi_clk_src",
1772 .parent_data = gcc_parent_data_0,
1773 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1774 .flags = CLK_SET_RATE_PARENT,
1775 .ops = &clk_rcg2_shared_ops,
1776 },
1777};
1778
1779static struct clk_rcg2 gcc_usb30_sec_master_clk_src = {
1780 .cmd_rcgr = 0xa102c,
1781 .mnd_width = 8,
1782 .hid_width = 5,
1783 .parent_map = gcc_parent_map_0,
1784 .freq_tbl = ftbl_gcc_usb30_mp_master_clk_src,
1785 .clkr.hw.init = &(const struct clk_init_data) {
1786 .name = "gcc_usb30_sec_master_clk_src",
1787 .parent_data = gcc_parent_data_0,
1788 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1789 .flags = CLK_SET_RATE_PARENT,
1790 .ops = &clk_rcg2_shared_ops,
1791 },
1792};
1793
1794static struct clk_rcg2 gcc_usb30_sec_mock_utmi_clk_src = {
1795 .cmd_rcgr = 0xa1044,
1796 .mnd_width = 0,
1797 .hid_width = 5,
1798 .parent_map = gcc_parent_map_0,
1799 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
1800 .clkr.hw.init = &(const struct clk_init_data) {
1801 .name = "gcc_usb30_sec_mock_utmi_clk_src",
1802 .parent_data = gcc_parent_data_0,
1803 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1804 .flags = CLK_SET_RATE_PARENT,
1805 .ops = &clk_rcg2_shared_ops,
1806 },
1807};
1808
1809static struct clk_rcg2 gcc_usb30_tert_master_clk_src = {
1810 .cmd_rcgr = 0xa202c,
1811 .mnd_width = 8,
1812 .hid_width = 5,
1813 .parent_map = gcc_parent_map_0,
1814 .freq_tbl = ftbl_gcc_usb30_mp_master_clk_src,
1815 .clkr.hw.init = &(const struct clk_init_data) {
1816 .name = "gcc_usb30_tert_master_clk_src",
1817 .parent_data = gcc_parent_data_0,
1818 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1819 .flags = CLK_SET_RATE_PARENT,
1820 .ops = &clk_rcg2_shared_ops,
1821 },
1822};
1823
1824static struct clk_rcg2 gcc_usb30_tert_mock_utmi_clk_src = {
1825 .cmd_rcgr = 0xa2044,
1826 .mnd_width = 0,
1827 .hid_width = 5,
1828 .parent_map = gcc_parent_map_0,
1829 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
1830 .clkr.hw.init = &(const struct clk_init_data) {
1831 .name = "gcc_usb30_tert_mock_utmi_clk_src",
1832 .parent_data = gcc_parent_data_0,
1833 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1834 .flags = CLK_SET_RATE_PARENT,
1835 .ops = &clk_rcg2_shared_ops,
1836 },
1837};
1838
1839static struct clk_rcg2 gcc_usb3_mp_phy_aux_clk_src = {
1840 .cmd_rcgr = 0x172a0,
1841 .mnd_width = 0,
1842 .hid_width = 5,
1843 .parent_map = gcc_parent_map_1,
1844 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
1845 .clkr.hw.init = &(const struct clk_init_data) {
1846 .name = "gcc_usb3_mp_phy_aux_clk_src",
1847 .parent_data = gcc_parent_data_1,
1848 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
1849 .flags = CLK_SET_RATE_PARENT,
1850 .ops = &clk_rcg2_shared_ops,
1851 },
1852};
1853
1854static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
1855 .cmd_rcgr = 0x39074,
1856 .mnd_width = 0,
1857 .hid_width = 5,
1858 .parent_map = gcc_parent_map_1,
1859 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
1860 .clkr.hw.init = &(const struct clk_init_data) {
1861 .name = "gcc_usb3_prim_phy_aux_clk_src",
1862 .parent_data = gcc_parent_data_1,
1863 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
1864 .flags = CLK_SET_RATE_PARENT,
1865 .ops = &clk_rcg2_shared_ops,
1866 },
1867};
1868
1869static struct clk_rcg2 gcc_usb3_sec_phy_aux_clk_src = {
1870 .cmd_rcgr = 0xa1074,
1871 .mnd_width = 0,
1872 .hid_width = 5,
1873 .parent_map = gcc_parent_map_1,
1874 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
1875 .clkr.hw.init = &(const struct clk_init_data) {
1876 .name = "gcc_usb3_sec_phy_aux_clk_src",
1877 .parent_data = gcc_parent_data_1,
1878 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
1879 .flags = CLK_SET_RATE_PARENT,
1880 .ops = &clk_rcg2_shared_ops,
1881 },
1882};
1883
1884static struct clk_rcg2 gcc_usb3_tert_phy_aux_clk_src = {
1885 .cmd_rcgr = 0xa2074,
1886 .mnd_width = 0,
1887 .hid_width = 5,
1888 .parent_map = gcc_parent_map_1,
1889 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
1890 .clkr.hw.init = &(const struct clk_init_data) {
1891 .name = "gcc_usb3_tert_phy_aux_clk_src",
1892 .parent_data = gcc_parent_data_1,
1893 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
1894 .flags = CLK_SET_RATE_PARENT,
1895 .ops = &clk_rcg2_shared_ops,
1896 },
1897};
1898
1899static const struct freq_tbl ftbl_gcc_usb4_0_master_clk_src[] = {
1900 F(175000000, P_GCC_GPLL8_OUT_MAIN, 4, 0, 0),
1901 F(350000000, P_GCC_GPLL8_OUT_MAIN, 2, 0, 0),
1902 { }
1903};
1904
1905static struct clk_rcg2 gcc_usb4_0_master_clk_src = {
1906 .cmd_rcgr = 0x9f024,
1907 .mnd_width = 8,
1908 .hid_width = 5,
1909 .parent_map = gcc_parent_map_4,
1910 .freq_tbl = ftbl_gcc_usb4_0_master_clk_src,
1911 .clkr.hw.init = &(const struct clk_init_data) {
1912 .name = "gcc_usb4_0_master_clk_src",
1913 .parent_data = gcc_parent_data_4,
1914 .num_parents = ARRAY_SIZE(gcc_parent_data_4),
1915 .flags = CLK_SET_RATE_PARENT,
1916 .ops = &clk_rcg2_shared_ops,
1917 },
1918};
1919
1920static const struct freq_tbl ftbl_gcc_usb4_0_phy_pcie_pipe_clk_src[] = {
1921 F(19200000, P_BI_TCXO, 1, 0, 0),
1922 F(125000000, P_GCC_GPLL7_OUT_MAIN, 8, 0, 0),
1923 F(250000000, P_GCC_GPLL7_OUT_MAIN, 4, 0, 0),
1924 { }
1925};
1926
1927static struct clk_rcg2 gcc_usb4_0_phy_pcie_pipe_clk_src = {
1928 .cmd_rcgr = 0x9f0e8,
1929 .mnd_width = 0,
1930 .hid_width = 5,
1931 .parent_map = gcc_parent_map_5,
1932 .freq_tbl = ftbl_gcc_usb4_0_phy_pcie_pipe_clk_src,
1933 .clkr.hw.init = &(const struct clk_init_data) {
1934 .name = "gcc_usb4_0_phy_pcie_pipe_clk_src",
1935 .parent_data = gcc_parent_data_5,
1936 .num_parents = ARRAY_SIZE(gcc_parent_data_5),
1937 .flags = CLK_SET_RATE_PARENT,
1938 .ops = &clk_rcg2_shared_ops,
1939 },
1940};
1941
1942static struct clk_rcg2 gcc_usb4_0_sb_if_clk_src = {
1943 .cmd_rcgr = 0x9f08c,
1944 .mnd_width = 0,
1945 .hid_width = 5,
1946 .parent_map = gcc_parent_map_3,
1947 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
1948 .clkr.hw.init = &(const struct clk_init_data) {
1949 .name = "gcc_usb4_0_sb_if_clk_src",
1950 .parent_data = gcc_parent_data_3,
1951 .num_parents = ARRAY_SIZE(gcc_parent_data_3),
1952 .flags = CLK_SET_RATE_PARENT,
1953 .ops = &clk_rcg2_shared_ops,
1954 },
1955};
1956
1957static const struct freq_tbl ftbl_gcc_usb4_0_tmu_clk_src[] = {
1958 F(19200000, P_BI_TCXO, 1, 0, 0),
1959 F(250000000, P_GCC_GPLL7_OUT_MAIN, 4, 0, 0),
1960 { }
1961};
1962
1963static struct clk_rcg2 gcc_usb4_0_tmu_clk_src = {
1964 .cmd_rcgr = 0x9f070,
1965 .mnd_width = 0,
1966 .hid_width = 5,
1967 .parent_map = gcc_parent_map_6,
1968 .freq_tbl = ftbl_gcc_usb4_0_tmu_clk_src,
1969 .clkr.hw.init = &(const struct clk_init_data) {
1970 .name = "gcc_usb4_0_tmu_clk_src",
1971 .parent_data = gcc_parent_data_6,
1972 .num_parents = ARRAY_SIZE(gcc_parent_data_6),
1973 .flags = CLK_SET_RATE_PARENT,
1974 .ops = &clk_rcg2_shared_ops,
1975 },
1976};
1977
1978static struct clk_rcg2 gcc_usb4_1_master_clk_src = {
1979 .cmd_rcgr = 0x2b024,
1980 .mnd_width = 8,
1981 .hid_width = 5,
1982 .parent_map = gcc_parent_map_4,
1983 .freq_tbl = ftbl_gcc_usb4_0_master_clk_src,
1984 .clkr.hw.init = &(const struct clk_init_data) {
1985 .name = "gcc_usb4_1_master_clk_src",
1986 .parent_data = gcc_parent_data_4,
1987 .num_parents = ARRAY_SIZE(gcc_parent_data_4),
1988 .flags = CLK_SET_RATE_PARENT,
1989 .ops = &clk_rcg2_shared_ops,
1990 },
1991};
1992
1993static struct clk_rcg2 gcc_usb4_1_phy_pcie_pipe_clk_src = {
1994 .cmd_rcgr = 0x2b0e8,
1995 .mnd_width = 0,
1996 .hid_width = 5,
1997 .parent_map = gcc_parent_map_5,
1998 .freq_tbl = ftbl_gcc_usb4_0_phy_pcie_pipe_clk_src,
1999 .clkr.hw.init = &(const struct clk_init_data) {
2000 .name = "gcc_usb4_1_phy_pcie_pipe_clk_src",
2001 .parent_data = gcc_parent_data_5,
2002 .num_parents = ARRAY_SIZE(gcc_parent_data_5),
2003 .flags = CLK_SET_RATE_PARENT,
2004 .ops = &clk_rcg2_shared_ops,
2005 },
2006};
2007
2008static struct clk_rcg2 gcc_usb4_1_sb_if_clk_src = {
2009 .cmd_rcgr = 0x2b08c,
2010 .mnd_width = 0,
2011 .hid_width = 5,
2012 .parent_map = gcc_parent_map_3,
2013 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
2014 .clkr.hw.init = &(const struct clk_init_data) {
2015 .name = "gcc_usb4_1_sb_if_clk_src",
2016 .parent_data = gcc_parent_data_3,
2017 .num_parents = ARRAY_SIZE(gcc_parent_data_3),
2018 .flags = CLK_SET_RATE_PARENT,
2019 .ops = &clk_rcg2_shared_ops,
2020 },
2021};
2022
2023static struct clk_rcg2 gcc_usb4_1_tmu_clk_src = {
2024 .cmd_rcgr = 0x2b070,
2025 .mnd_width = 0,
2026 .hid_width = 5,
2027 .parent_map = gcc_parent_map_6,
2028 .freq_tbl = ftbl_gcc_usb4_0_tmu_clk_src,
2029 .clkr.hw.init = &(const struct clk_init_data) {
2030 .name = "gcc_usb4_1_tmu_clk_src",
2031 .parent_data = gcc_parent_data_6,
2032 .num_parents = ARRAY_SIZE(gcc_parent_data_6),
2033 .flags = CLK_SET_RATE_PARENT,
2034 .ops = &clk_rcg2_shared_ops,
2035 },
2036};
2037
2038static struct clk_rcg2 gcc_usb4_2_master_clk_src = {
2039 .cmd_rcgr = 0x11024,
2040 .mnd_width = 8,
2041 .hid_width = 5,
2042 .parent_map = gcc_parent_map_4,
2043 .freq_tbl = ftbl_gcc_usb4_0_master_clk_src,
2044 .clkr.hw.init = &(const struct clk_init_data) {
2045 .name = "gcc_usb4_2_master_clk_src",
2046 .parent_data = gcc_parent_data_4,
2047 .num_parents = ARRAY_SIZE(gcc_parent_data_4),
2048 .flags = CLK_SET_RATE_PARENT,
2049 .ops = &clk_rcg2_shared_ops,
2050 },
2051};
2052
2053static struct clk_rcg2 gcc_usb4_2_phy_pcie_pipe_clk_src = {
2054 .cmd_rcgr = 0x110e8,
2055 .mnd_width = 0,
2056 .hid_width = 5,
2057 .parent_map = gcc_parent_map_5,
2058 .freq_tbl = ftbl_gcc_usb4_0_phy_pcie_pipe_clk_src,
2059 .clkr.hw.init = &(const struct clk_init_data) {
2060 .name = "gcc_usb4_2_phy_pcie_pipe_clk_src",
2061 .parent_data = gcc_parent_data_5,
2062 .num_parents = ARRAY_SIZE(gcc_parent_data_5),
2063 .flags = CLK_SET_RATE_PARENT,
2064 .ops = &clk_rcg2_shared_ops,
2065 },
2066};
2067
2068static struct clk_rcg2 gcc_usb4_2_sb_if_clk_src = {
2069 .cmd_rcgr = 0x1108c,
2070 .mnd_width = 0,
2071 .hid_width = 5,
2072 .parent_map = gcc_parent_map_3,
2073 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
2074 .clkr.hw.init = &(const struct clk_init_data) {
2075 .name = "gcc_usb4_2_sb_if_clk_src",
2076 .parent_data = gcc_parent_data_3,
2077 .num_parents = ARRAY_SIZE(gcc_parent_data_3),
2078 .flags = CLK_SET_RATE_PARENT,
2079 .ops = &clk_rcg2_shared_ops,
2080 },
2081};
2082
2083static struct clk_rcg2 gcc_usb4_2_tmu_clk_src = {
2084 .cmd_rcgr = 0x11070,
2085 .mnd_width = 0,
2086 .hid_width = 5,
2087 .parent_map = gcc_parent_map_6,
2088 .freq_tbl = ftbl_gcc_usb4_0_tmu_clk_src,
2089 .clkr.hw.init = &(const struct clk_init_data) {
2090 .name = "gcc_usb4_2_tmu_clk_src",
2091 .parent_data = gcc_parent_data_6,
2092 .num_parents = ARRAY_SIZE(gcc_parent_data_6),
2093 .flags = CLK_SET_RATE_PARENT,
2094 .ops = &clk_rcg2_shared_ops,
2095 },
2096};
2097
2098static struct clk_regmap_phy_mux gcc_pcie_3_pipe_clk_src = {
2099 .reg = 0x58088,
2100 .clkr = {
2101 .hw.init = &(struct clk_init_data){
2102 .name = "gcc_pcie_3_pipe_clk_src",
2103 .parent_data = &(const struct clk_parent_data){
2104 .index = DT_PCIE_3_PIPE,
2105 },
2106 .num_parents = 1,
2107 .ops = &clk_regmap_phy_mux_ops,
2108 },
2109 },
2110};
2111
2112static struct clk_regmap_div gcc_pcie_3_pipe_div_clk_src = {
2113 .reg = 0x5806c,
2114 .shift = 0,
2115 .width = 4,
2116 .clkr.hw.init = &(const struct clk_init_data) {
2117 .name = "gcc_pcie_3_pipe_div_clk_src",
2118 .parent_hws = (const struct clk_hw*[]) {
2119 &gcc_pcie_3_pipe_clk_src.clkr.hw,
2120 },
2121 .num_parents = 1,
2122 .ops = &clk_regmap_div_ro_ops,
2123 },
2124};
2125
2126static struct clk_regmap_phy_mux gcc_pcie_4_pipe_clk_src = {
2127 .reg = 0x6b07c,
2128 .clkr = {
2129 .hw.init = &(struct clk_init_data){
2130 .name = "gcc_pcie_4_pipe_clk_src",
2131 .parent_data = &(const struct clk_parent_data){
2132 .index = DT_PCIE_4_PIPE,
2133 },
2134 .num_parents = 1,
2135 .ops = &clk_regmap_phy_mux_ops,
2136 },
2137 },
2138};
2139
2140static struct clk_regmap_div gcc_pcie_4_pipe_div_clk_src = {
2141 .reg = 0x6b060,
2142 .shift = 0,
2143 .width = 4,
2144 .clkr.hw.init = &(const struct clk_init_data) {
2145 .name = "gcc_pcie_4_pipe_div_clk_src",
2146 .parent_hws = (const struct clk_hw*[]) {
2147 &gcc_pcie_4_pipe_clk_src.clkr.hw,
2148 },
2149 .num_parents = 1,
2150 .ops = &clk_regmap_div_ro_ops,
2151 },
2152};
2153
2154static struct clk_regmap_phy_mux gcc_pcie_5_pipe_clk_src = {
2155 .reg = 0x2f07c,
2156 .clkr = {
2157 .hw.init = &(struct clk_init_data){
2158 .name = "gcc_pcie_5_pipe_clk_src",
2159 .parent_data = &(const struct clk_parent_data){
2160 .index = DT_PCIE_5_PIPE,
2161 },
2162 .num_parents = 1,
2163 .ops = &clk_regmap_phy_mux_ops,
2164 },
2165 },
2166};
2167
2168static struct clk_regmap_div gcc_pcie_5_pipe_div_clk_src = {
2169 .reg = 0x2f060,
2170 .shift = 0,
2171 .width = 4,
2172 .clkr.hw.init = &(const struct clk_init_data) {
2173 .name = "gcc_pcie_5_pipe_div_clk_src",
2174 .parent_hws = (const struct clk_hw*[]) {
2175 &gcc_pcie_5_pipe_clk_src.clkr.hw,
2176 },
2177 .num_parents = 1,
2178 .ops = &clk_regmap_div_ro_ops,
2179 },
2180};
2181
2182static struct clk_regmap_phy_mux gcc_pcie_6a_pipe_clk_src = {
2183 .reg = 0x31088,
2184 .clkr = {
2185 .hw.init = &(struct clk_init_data){
2186 .name = "gcc_pcie_6a_pipe_clk_src",
2187 .parent_data = &(const struct clk_parent_data){
2188 .index = DT_PCIE_6A_PIPE,
2189 },
2190 .num_parents = 1,
2191 .ops = &clk_regmap_phy_mux_ops,
2192 },
2193 },
2194};
2195
2196static struct clk_regmap_div gcc_pcie_6a_pipe_div_clk_src = {
2197 .reg = 0x3106c,
2198 .shift = 0,
2199 .width = 4,
2200 .clkr.hw.init = &(const struct clk_init_data) {
2201 .name = "gcc_pcie_6a_pipe_div_clk_src",
2202 .parent_hws = (const struct clk_hw*[]) {
2203 &gcc_pcie_6a_pipe_clk_src.clkr.hw,
2204 },
2205 .num_parents = 1,
2206 .ops = &clk_regmap_div_ro_ops,
2207 },
2208};
2209
2210static struct clk_regmap_phy_mux gcc_pcie_6b_pipe_clk_src = {
2211 .reg = 0x8d088,
2212 .clkr = {
2213 .hw.init = &(struct clk_init_data){
2214 .name = "gcc_pcie_6b_pipe_clk_src",
2215 .parent_data = &(const struct clk_parent_data){
2216 .index = DT_PCIE_6B_PIPE,
2217 },
2218 .num_parents = 1,
2219 .ops = &clk_regmap_phy_mux_ops,
2220 },
2221 },
2222};
2223
2224static struct clk_regmap_div gcc_pcie_6b_pipe_div_clk_src = {
2225 .reg = 0x8d06c,
2226 .shift = 0,
2227 .width = 4,
2228 .clkr.hw.init = &(const struct clk_init_data) {
2229 .name = "gcc_pcie_6b_pipe_div_clk_src",
2230 .parent_hws = (const struct clk_hw*[]) {
2231 &gcc_pcie_6b_pipe_clk_src.clkr.hw,
2232 },
2233 .num_parents = 1,
2234 .ops = &clk_regmap_div_ro_ops,
2235 },
2236};
2237
2238static struct clk_regmap_div gcc_qupv3_wrap0_s2_div_clk_src = {
2239 .reg = 0x42284,
2240 .shift = 0,
2241 .width = 4,
2242 .clkr.hw.init = &(const struct clk_init_data) {
2243 .name = "gcc_qupv3_wrap0_s2_div_clk_src",
2244 .parent_hws = (const struct clk_hw*[]) {
2245 &gcc_qupv3_wrap0_s2_clk_src.clkr.hw,
2246 },
2247 .num_parents = 1,
2248 .flags = CLK_SET_RATE_PARENT,
2249 .ops = &clk_regmap_div_ro_ops,
2250 },
2251};
2252
2253static struct clk_regmap_div gcc_qupv3_wrap0_s3_div_clk_src = {
2254 .reg = 0x423c4,
2255 .shift = 0,
2256 .width = 4,
2257 .clkr.hw.init = &(const struct clk_init_data) {
2258 .name = "gcc_qupv3_wrap0_s3_div_clk_src",
2259 .parent_hws = (const struct clk_hw*[]) {
2260 &gcc_qupv3_wrap0_s3_clk_src.clkr.hw,
2261 },
2262 .num_parents = 1,
2263 .flags = CLK_SET_RATE_PARENT,
2264 .ops = &clk_regmap_div_ro_ops,
2265 },
2266};
2267
2268static struct clk_regmap_div gcc_qupv3_wrap1_s2_div_clk_src = {
2269 .reg = 0x18284,
2270 .shift = 0,
2271 .width = 4,
2272 .clkr.hw.init = &(const struct clk_init_data) {
2273 .name = "gcc_qupv3_wrap1_s2_div_clk_src",
2274 .parent_hws = (const struct clk_hw*[]) {
2275 &gcc_qupv3_wrap1_s2_clk_src.clkr.hw,
2276 },
2277 .num_parents = 1,
2278 .flags = CLK_SET_RATE_PARENT,
2279 .ops = &clk_regmap_div_ro_ops,
2280 },
2281};
2282
2283static struct clk_regmap_div gcc_qupv3_wrap1_s3_div_clk_src = {
2284 .reg = 0x183c4,
2285 .shift = 0,
2286 .width = 4,
2287 .clkr.hw.init = &(const struct clk_init_data) {
2288 .name = "gcc_qupv3_wrap1_s3_div_clk_src",
2289 .parent_hws = (const struct clk_hw*[]) {
2290 &gcc_qupv3_wrap1_s3_clk_src.clkr.hw,
2291 },
2292 .num_parents = 1,
2293 .flags = CLK_SET_RATE_PARENT,
2294 .ops = &clk_regmap_div_ro_ops,
2295 },
2296};
2297
2298static struct clk_regmap_div gcc_qupv3_wrap2_s2_div_clk_src = {
2299 .reg = 0x1e284,
2300 .shift = 0,
2301 .width = 4,
2302 .clkr.hw.init = &(const struct clk_init_data) {
2303 .name = "gcc_qupv3_wrap2_s2_div_clk_src",
2304 .parent_hws = (const struct clk_hw*[]) {
2305 &gcc_qupv3_wrap2_s2_clk_src.clkr.hw,
2306 },
2307 .num_parents = 1,
2308 .flags = CLK_SET_RATE_PARENT,
2309 .ops = &clk_regmap_div_ro_ops,
2310 },
2311};
2312
2313static struct clk_regmap_div gcc_qupv3_wrap2_s3_div_clk_src = {
2314 .reg = 0x1e3c4,
2315 .shift = 0,
2316 .width = 4,
2317 .clkr.hw.init = &(const struct clk_init_data) {
2318 .name = "gcc_qupv3_wrap2_s3_div_clk_src",
2319 .parent_hws = (const struct clk_hw*[]) {
2320 &gcc_qupv3_wrap2_s3_clk_src.clkr.hw,
2321 },
2322 .num_parents = 1,
2323 .flags = CLK_SET_RATE_PARENT,
2324 .ops = &clk_regmap_div_ro_ops,
2325 },
2326};
2327
2328static struct clk_regmap_div gcc_usb20_mock_utmi_postdiv_clk_src = {
2329 .reg = 0x29284,
2330 .shift = 0,
2331 .width = 4,
2332 .clkr.hw.init = &(const struct clk_init_data) {
2333 .name = "gcc_usb20_mock_utmi_postdiv_clk_src",
2334 .parent_hws = (const struct clk_hw*[]) {
2335 &gcc_usb20_mock_utmi_clk_src.clkr.hw,
2336 },
2337 .num_parents = 1,
2338 .flags = CLK_SET_RATE_PARENT,
2339 .ops = &clk_regmap_div_ro_ops,
2340 },
2341};
2342
2343static struct clk_regmap_div gcc_usb30_mp_mock_utmi_postdiv_clk_src = {
2344 .reg = 0x17284,
2345 .shift = 0,
2346 .width = 4,
2347 .clkr.hw.init = &(const struct clk_init_data) {
2348 .name = "gcc_usb30_mp_mock_utmi_postdiv_clk_src",
2349 .parent_hws = (const struct clk_hw*[]) {
2350 &gcc_usb30_mp_mock_utmi_clk_src.clkr.hw,
2351 },
2352 .num_parents = 1,
2353 .flags = CLK_SET_RATE_PARENT,
2354 .ops = &clk_regmap_div_ro_ops,
2355 },
2356};
2357
2358static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = {
2359 .reg = 0x3905c,
2360 .shift = 0,
2361 .width = 4,
2362 .clkr.hw.init = &(const struct clk_init_data) {
2363 .name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src",
2364 .parent_hws = (const struct clk_hw*[]) {
2365 &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw,
2366 },
2367 .num_parents = 1,
2368 .flags = CLK_SET_RATE_PARENT,
2369 .ops = &clk_regmap_div_ro_ops,
2370 },
2371};
2372
2373static struct clk_regmap_div gcc_usb30_sec_mock_utmi_postdiv_clk_src = {
2374 .reg = 0xa105c,
2375 .shift = 0,
2376 .width = 4,
2377 .clkr.hw.init = &(const struct clk_init_data) {
2378 .name = "gcc_usb30_sec_mock_utmi_postdiv_clk_src",
2379 .parent_hws = (const struct clk_hw*[]) {
2380 &gcc_usb30_sec_mock_utmi_clk_src.clkr.hw,
2381 },
2382 .num_parents = 1,
2383 .flags = CLK_SET_RATE_PARENT,
2384 .ops = &clk_regmap_div_ro_ops,
2385 },
2386};
2387
2388static struct clk_regmap_div gcc_usb30_tert_mock_utmi_postdiv_clk_src = {
2389 .reg = 0xa205c,
2390 .shift = 0,
2391 .width = 4,
2392 .clkr.hw.init = &(const struct clk_init_data) {
2393 .name = "gcc_usb30_tert_mock_utmi_postdiv_clk_src",
2394 .parent_hws = (const struct clk_hw*[]) {
2395 &gcc_usb30_tert_mock_utmi_clk_src.clkr.hw,
2396 },
2397 .num_parents = 1,
2398 .flags = CLK_SET_RATE_PARENT,
2399 .ops = &clk_regmap_div_ro_ops,
2400 },
2401};
2402
2403static struct clk_branch gcc_aggre_noc_usb_north_axi_clk = {
2404 .halt_reg = 0x2d17c,
2405 .halt_check = BRANCH_HALT_VOTED,
2406 .hwcg_reg = 0x2d17c,
2407 .hwcg_bit = 1,
2408 .clkr = {
2409 .enable_reg = 0x2d17c,
2410 .enable_mask = BIT(0),
2411 .hw.init = &(const struct clk_init_data) {
2412 .name = "gcc_aggre_noc_usb_north_axi_clk",
2413 .ops = &clk_branch2_ops,
2414 },
2415 },
2416};
2417
2418static struct clk_branch gcc_aggre_noc_usb_south_axi_clk = {
2419 .halt_reg = 0x2d174,
2420 .halt_check = BRANCH_HALT_VOTED,
2421 .hwcg_reg = 0x2d174,
2422 .hwcg_bit = 1,
2423 .clkr = {
2424 .enable_reg = 0x2d174,
2425 .enable_mask = BIT(0),
2426 .hw.init = &(const struct clk_init_data) {
2427 .name = "gcc_aggre_noc_usb_south_axi_clk",
2428 .ops = &clk_branch2_ops,
2429 },
2430 },
2431};
2432
2433static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {
2434 .halt_reg = 0x770e4,
2435 .halt_check = BRANCH_HALT_VOTED,
2436 .hwcg_reg = 0x770e4,
2437 .hwcg_bit = 1,
2438 .clkr = {
2439 .enable_reg = 0x770e4,
2440 .enable_mask = BIT(0),
2441 .hw.init = &(const struct clk_init_data) {
2442 .name = "gcc_aggre_ufs_phy_axi_clk",
2443 .parent_hws = (const struct clk_hw*[]) {
2444 &gcc_ufs_phy_axi_clk_src.clkr.hw,
2445 },
2446 .num_parents = 1,
2447 .flags = CLK_SET_RATE_PARENT,
2448 .ops = &clk_branch2_ops,
2449 },
2450 },
2451};
2452
2453static struct clk_branch gcc_aggre_usb2_prim_axi_clk = {
2454 .halt_reg = 0x2928c,
2455 .halt_check = BRANCH_HALT_VOTED,
2456 .hwcg_reg = 0x2928c,
2457 .hwcg_bit = 1,
2458 .clkr = {
2459 .enable_reg = 0x2928c,
2460 .enable_mask = BIT(0),
2461 .hw.init = &(const struct clk_init_data) {
2462 .name = "gcc_aggre_usb2_prim_axi_clk",
2463 .parent_hws = (const struct clk_hw*[]) {
2464 &gcc_usb20_master_clk_src.clkr.hw,
2465 },
2466 .num_parents = 1,
2467 .flags = CLK_SET_RATE_PARENT,
2468 .ops = &clk_branch2_ops,
2469 },
2470 },
2471};
2472
2473static struct clk_branch gcc_aggre_usb3_mp_axi_clk = {
2474 .halt_reg = 0x173d0,
2475 .halt_check = BRANCH_HALT_VOTED,
2476 .hwcg_reg = 0x173d0,
2477 .hwcg_bit = 1,
2478 .clkr = {
2479 .enable_reg = 0x173d0,
2480 .enable_mask = BIT(0),
2481 .hw.init = &(const struct clk_init_data) {
2482 .name = "gcc_aggre_usb3_mp_axi_clk",
2483 .parent_hws = (const struct clk_hw*[]) {
2484 &gcc_usb30_mp_master_clk_src.clkr.hw,
2485 },
2486 .num_parents = 1,
2487 .flags = CLK_SET_RATE_PARENT,
2488 .ops = &clk_branch2_ops,
2489 },
2490 },
2491};
2492
2493static struct clk_branch gcc_aggre_usb3_prim_axi_clk = {
2494 .halt_reg = 0x39090,
2495 .halt_check = BRANCH_HALT_VOTED,
2496 .hwcg_reg = 0x39090,
2497 .hwcg_bit = 1,
2498 .clkr = {
2499 .enable_reg = 0x39090,
2500 .enable_mask = BIT(0),
2501 .hw.init = &(const struct clk_init_data) {
2502 .name = "gcc_aggre_usb3_prim_axi_clk",
2503 .parent_hws = (const struct clk_hw*[]) {
2504 &gcc_usb30_prim_master_clk_src.clkr.hw,
2505 },
2506 .num_parents = 1,
2507 .flags = CLK_SET_RATE_PARENT,
2508 .ops = &clk_branch2_ops,
2509 },
2510 },
2511};
2512
2513static struct clk_branch gcc_aggre_usb3_sec_axi_clk = {
2514 .halt_reg = 0xa1090,
2515 .halt_check = BRANCH_HALT_VOTED,
2516 .hwcg_reg = 0xa1090,
2517 .hwcg_bit = 1,
2518 .clkr = {
2519 .enable_reg = 0xa1090,
2520 .enable_mask = BIT(0),
2521 .hw.init = &(const struct clk_init_data) {
2522 .name = "gcc_aggre_usb3_sec_axi_clk",
2523 .parent_hws = (const struct clk_hw*[]) {
2524 &gcc_usb30_sec_master_clk_src.clkr.hw,
2525 },
2526 .num_parents = 1,
2527 .flags = CLK_SET_RATE_PARENT,
2528 .ops = &clk_branch2_ops,
2529 },
2530 },
2531};
2532
2533static struct clk_branch gcc_aggre_usb3_tert_axi_clk = {
2534 .halt_reg = 0xa2090,
2535 .halt_check = BRANCH_HALT_VOTED,
2536 .hwcg_reg = 0xa2090,
2537 .hwcg_bit = 1,
2538 .clkr = {
2539 .enable_reg = 0xa2090,
2540 .enable_mask = BIT(0),
2541 .hw.init = &(const struct clk_init_data) {
2542 .name = "gcc_aggre_usb3_tert_axi_clk",
2543 .parent_hws = (const struct clk_hw*[]) {
2544 &gcc_usb30_tert_master_clk_src.clkr.hw,
2545 },
2546 .num_parents = 1,
2547 .flags = CLK_SET_RATE_PARENT,
2548 .ops = &clk_branch2_ops,
2549 },
2550 },
2551};
2552
2553static struct clk_branch gcc_aggre_usb4_0_axi_clk = {
2554 .halt_reg = 0x9f118,
2555 .halt_check = BRANCH_HALT_VOTED,
2556 .hwcg_reg = 0x9f118,
2557 .hwcg_bit = 1,
2558 .clkr = {
2559 .enable_reg = 0x9f118,
2560 .enable_mask = BIT(0),
2561 .hw.init = &(const struct clk_init_data) {
2562 .name = "gcc_aggre_usb4_0_axi_clk",
2563 .parent_hws = (const struct clk_hw*[]) {
2564 &gcc_usb4_0_master_clk_src.clkr.hw,
2565 },
2566 .num_parents = 1,
2567 .flags = CLK_SET_RATE_PARENT,
2568 .ops = &clk_branch2_ops,
2569 },
2570 },
2571};
2572
2573static struct clk_branch gcc_aggre_usb4_1_axi_clk = {
2574 .halt_reg = 0x2b118,
2575 .halt_check = BRANCH_HALT_VOTED,
2576 .hwcg_reg = 0x2b118,
2577 .hwcg_bit = 1,
2578 .clkr = {
2579 .enable_reg = 0x2b118,
2580 .enable_mask = BIT(0),
2581 .hw.init = &(const struct clk_init_data) {
2582 .name = "gcc_aggre_usb4_1_axi_clk",
2583 .parent_hws = (const struct clk_hw*[]) {
2584 &gcc_usb4_1_master_clk_src.clkr.hw,
2585 },
2586 .num_parents = 1,
2587 .flags = CLK_SET_RATE_PARENT,
2588 .ops = &clk_branch2_ops,
2589 },
2590 },
2591};
2592
2593static struct clk_branch gcc_aggre_usb4_2_axi_clk = {
2594 .halt_reg = 0x11118,
2595 .halt_check = BRANCH_HALT_VOTED,
2596 .hwcg_reg = 0x11118,
2597 .hwcg_bit = 1,
2598 .clkr = {
2599 .enable_reg = 0x11118,
2600 .enable_mask = BIT(0),
2601 .hw.init = &(const struct clk_init_data) {
2602 .name = "gcc_aggre_usb4_2_axi_clk",
2603 .parent_hws = (const struct clk_hw*[]) {
2604 &gcc_usb4_2_master_clk_src.clkr.hw,
2605 },
2606 .num_parents = 1,
2607 .flags = CLK_SET_RATE_PARENT,
2608 .ops = &clk_branch2_ops,
2609 },
2610 },
2611};
2612
2613static struct clk_branch gcc_aggre_usb_noc_axi_clk = {
2614 .halt_reg = 0x2d034,
2615 .halt_check = BRANCH_HALT_VOTED,
2616 .hwcg_reg = 0x2d034,
2617 .hwcg_bit = 1,
2618 .clkr = {
2619 .enable_reg = 0x2d034,
2620 .enable_mask = BIT(0),
2621 .hw.init = &(const struct clk_init_data) {
2622 .name = "gcc_aggre_usb_noc_axi_clk",
2623 .ops = &clk_branch2_ops,
2624 },
2625 },
2626};
2627
2628static struct clk_branch gcc_av1e_ahb_clk = {
2629 .halt_reg = 0x4a004,
2630 .halt_check = BRANCH_HALT_VOTED,
2631 .hwcg_reg = 0x4a004,
2632 .hwcg_bit = 1,
2633 .clkr = {
2634 .enable_reg = 0x4a004,
2635 .enable_mask = BIT(0),
2636 .hw.init = &(const struct clk_init_data) {
2637 .name = "gcc_av1e_ahb_clk",
2638 .ops = &clk_branch2_ops,
2639 },
2640 },
2641};
2642
2643static struct clk_branch gcc_av1e_axi_clk = {
2644 .halt_reg = 0x4a008,
2645 .halt_check = BRANCH_HALT_SKIP,
2646 .hwcg_reg = 0x4a008,
2647 .hwcg_bit = 1,
2648 .clkr = {
2649 .enable_reg = 0x4a008,
2650 .enable_mask = BIT(0),
2651 .hw.init = &(const struct clk_init_data) {
2652 .name = "gcc_av1e_axi_clk",
2653 .ops = &clk_branch2_ops,
2654 },
2655 },
2656};
2657
2658static struct clk_branch gcc_av1e_xo_clk = {
2659 .halt_reg = 0x4a014,
2660 .halt_check = BRANCH_HALT,
2661 .clkr = {
2662 .enable_reg = 0x4a014,
2663 .enable_mask = BIT(0),
2664 .hw.init = &(const struct clk_init_data) {
2665 .name = "gcc_av1e_xo_clk",
2666 .ops = &clk_branch2_ops,
2667 },
2668 },
2669};
2670
2671static struct clk_branch gcc_boot_rom_ahb_clk = {
2672 .halt_reg = 0x38004,
2673 .halt_check = BRANCH_HALT_VOTED,
2674 .hwcg_reg = 0x38004,
2675 .hwcg_bit = 1,
2676 .clkr = {
2677 .enable_reg = 0x52000,
2678 .enable_mask = BIT(10),
2679 .hw.init = &(const struct clk_init_data) {
2680 .name = "gcc_boot_rom_ahb_clk",
2681 .ops = &clk_branch2_ops,
2682 },
2683 },
2684};
2685
2686static struct clk_branch gcc_camera_hf_axi_clk = {
2687 .halt_reg = 0x26010,
2688 .halt_check = BRANCH_HALT_SKIP,
2689 .hwcg_reg = 0x26010,
2690 .hwcg_bit = 1,
2691 .clkr = {
2692 .enable_reg = 0x26010,
2693 .enable_mask = BIT(0),
2694 .hw.init = &(const struct clk_init_data) {
2695 .name = "gcc_camera_hf_axi_clk",
2696 .ops = &clk_branch2_ops,
2697 },
2698 },
2699};
2700
2701static struct clk_branch gcc_camera_sf_axi_clk = {
2702 .halt_reg = 0x2601c,
2703 .halt_check = BRANCH_HALT_SKIP,
2704 .hwcg_reg = 0x2601c,
2705 .hwcg_bit = 1,
2706 .clkr = {
2707 .enable_reg = 0x2601c,
2708 .enable_mask = BIT(0),
2709 .hw.init = &(const struct clk_init_data) {
2710 .name = "gcc_camera_sf_axi_clk",
2711 .ops = &clk_branch2_ops,
2712 },
2713 },
2714};
2715
2716static struct clk_branch gcc_cfg_noc_pcie_anoc_ahb_clk = {
2717 .halt_reg = 0x10028,
2718 .halt_check = BRANCH_HALT_VOTED,
2719 .hwcg_reg = 0x10028,
2720 .hwcg_bit = 1,
2721 .clkr = {
2722 .enable_reg = 0x52028,
2723 .enable_mask = BIT(20),
2724 .hw.init = &(const struct clk_init_data) {
2725 .name = "gcc_cfg_noc_pcie_anoc_ahb_clk",
2726 .ops = &clk_branch2_ops,
2727 },
2728 },
2729};
2730
2731static struct clk_branch gcc_cfg_noc_pcie_anoc_north_ahb_clk = {
2732 .halt_reg = 0x1002c,
2733 .halt_check = BRANCH_HALT_VOTED,
2734 .hwcg_reg = 0x1002c,
2735 .hwcg_bit = 1,
2736 .clkr = {
2737 .enable_reg = 0x52028,
2738 .enable_mask = BIT(22),
2739 .hw.init = &(const struct clk_init_data) {
2740 .name = "gcc_cfg_noc_pcie_anoc_north_ahb_clk",
2741 .ops = &clk_branch2_ops,
2742 },
2743 },
2744};
2745
2746static struct clk_branch gcc_cfg_noc_pcie_anoc_south_ahb_clk = {
2747 .halt_reg = 0x10030,
2748 .halt_check = BRANCH_HALT_VOTED,
2749 .hwcg_reg = 0x10030,
2750 .hwcg_bit = 1,
2751 .clkr = {
2752 .enable_reg = 0x52000,
2753 .enable_mask = BIT(20),
2754 .hw.init = &(const struct clk_init_data) {
2755 .name = "gcc_cfg_noc_pcie_anoc_south_ahb_clk",
2756 .ops = &clk_branch2_ops,
2757 },
2758 },
2759};
2760
2761static struct clk_branch gcc_cfg_noc_usb2_prim_axi_clk = {
2762 .halt_reg = 0x29288,
2763 .halt_check = BRANCH_HALT_VOTED,
2764 .hwcg_reg = 0x29288,
2765 .hwcg_bit = 1,
2766 .clkr = {
2767 .enable_reg = 0x29288,
2768 .enable_mask = BIT(0),
2769 .hw.init = &(const struct clk_init_data) {
2770 .name = "gcc_cfg_noc_usb2_prim_axi_clk",
2771 .parent_hws = (const struct clk_hw*[]) {
2772 &gcc_usb20_master_clk_src.clkr.hw,
2773 },
2774 .num_parents = 1,
2775 .flags = CLK_SET_RATE_PARENT,
2776 .ops = &clk_branch2_ops,
2777 },
2778 },
2779};
2780
2781static struct clk_branch gcc_cfg_noc_usb3_mp_axi_clk = {
2782 .halt_reg = 0x173cc,
2783 .halt_check = BRANCH_HALT_VOTED,
2784 .hwcg_reg = 0x173cc,
2785 .hwcg_bit = 1,
2786 .clkr = {
2787 .enable_reg = 0x173cc,
2788 .enable_mask = BIT(0),
2789 .hw.init = &(const struct clk_init_data) {
2790 .name = "gcc_cfg_noc_usb3_mp_axi_clk",
2791 .parent_hws = (const struct clk_hw*[]) {
2792 &gcc_usb30_mp_master_clk_src.clkr.hw,
2793 },
2794 .num_parents = 1,
2795 .flags = CLK_SET_RATE_PARENT,
2796 .ops = &clk_branch2_ops,
2797 },
2798 },
2799};
2800
2801static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
2802 .halt_reg = 0x3908c,
2803 .halt_check = BRANCH_HALT_VOTED,
2804 .hwcg_reg = 0x3908c,
2805 .hwcg_bit = 1,
2806 .clkr = {
2807 .enable_reg = 0x3908c,
2808 .enable_mask = BIT(0),
2809 .hw.init = &(const struct clk_init_data) {
2810 .name = "gcc_cfg_noc_usb3_prim_axi_clk",
2811 .parent_hws = (const struct clk_hw*[]) {
2812 &gcc_usb30_prim_master_clk_src.clkr.hw,
2813 },
2814 .num_parents = 1,
2815 .flags = CLK_SET_RATE_PARENT,
2816 .ops = &clk_branch2_ops,
2817 },
2818 },
2819};
2820
2821static struct clk_branch gcc_cfg_noc_usb3_sec_axi_clk = {
2822 .halt_reg = 0xa108c,
2823 .halt_check = BRANCH_HALT_VOTED,
2824 .hwcg_reg = 0xa108c,
2825 .hwcg_bit = 1,
2826 .clkr = {
2827 .enable_reg = 0xa108c,
2828 .enable_mask = BIT(0),
2829 .hw.init = &(const struct clk_init_data) {
2830 .name = "gcc_cfg_noc_usb3_sec_axi_clk",
2831 .parent_hws = (const struct clk_hw*[]) {
2832 &gcc_usb30_sec_master_clk_src.clkr.hw,
2833 },
2834 .num_parents = 1,
2835 .flags = CLK_SET_RATE_PARENT,
2836 .ops = &clk_branch2_ops,
2837 },
2838 },
2839};
2840
2841static struct clk_branch gcc_cfg_noc_usb3_tert_axi_clk = {
2842 .halt_reg = 0xa208c,
2843 .halt_check = BRANCH_HALT_VOTED,
2844 .hwcg_reg = 0xa208c,
2845 .hwcg_bit = 1,
2846 .clkr = {
2847 .enable_reg = 0xa208c,
2848 .enable_mask = BIT(0),
2849 .hw.init = &(const struct clk_init_data) {
2850 .name = "gcc_cfg_noc_usb3_tert_axi_clk",
2851 .parent_hws = (const struct clk_hw*[]) {
2852 &gcc_usb30_tert_master_clk_src.clkr.hw,
2853 },
2854 .num_parents = 1,
2855 .flags = CLK_SET_RATE_PARENT,
2856 .ops = &clk_branch2_ops,
2857 },
2858 },
2859};
2860
2861static struct clk_branch gcc_cfg_noc_usb_anoc_ahb_clk = {
2862 .halt_reg = 0x2d024,
2863 .halt_check = BRANCH_HALT_VOTED,
2864 .hwcg_reg = 0x2d024,
2865 .hwcg_bit = 1,
2866 .clkr = {
2867 .enable_reg = 0x52028,
2868 .enable_mask = BIT(21),
2869 .hw.init = &(const struct clk_init_data) {
2870 .name = "gcc_cfg_noc_usb_anoc_ahb_clk",
2871 .ops = &clk_branch2_ops,
2872 },
2873 },
2874};
2875
2876static struct clk_branch gcc_cfg_noc_usb_anoc_north_ahb_clk = {
2877 .halt_reg = 0x2d028,
2878 .halt_check = BRANCH_HALT_VOTED,
2879 .hwcg_reg = 0x2d028,
2880 .hwcg_bit = 1,
2881 .clkr = {
2882 .enable_reg = 0x52028,
2883 .enable_mask = BIT(23),
2884 .hw.init = &(const struct clk_init_data) {
2885 .name = "gcc_cfg_noc_usb_anoc_north_ahb_clk",
2886 .ops = &clk_branch2_ops,
2887 },
2888 },
2889};
2890
2891static struct clk_branch gcc_cfg_noc_usb_anoc_south_ahb_clk = {
2892 .halt_reg = 0x2d02c,
2893 .halt_check = BRANCH_HALT_VOTED,
2894 .hwcg_reg = 0x2d02c,
2895 .hwcg_bit = 1,
2896 .clkr = {
2897 .enable_reg = 0x52018,
2898 .enable_mask = BIT(7),
2899 .hw.init = &(const struct clk_init_data) {
2900 .name = "gcc_cfg_noc_usb_anoc_south_ahb_clk",
2901 .ops = &clk_branch2_ops,
2902 },
2903 },
2904};
2905
2906static struct clk_branch gcc_cnoc_pcie1_tunnel_clk = {
2907 .halt_reg = 0x2c2b4,
2908 .halt_check = BRANCH_HALT_VOTED,
2909 .clkr = {
2910 .enable_reg = 0x52010,
2911 .enable_mask = BIT(30),
2912 .hw.init = &(const struct clk_init_data) {
2913 .name = "gcc_cnoc_pcie1_tunnel_clk",
2914 .ops = &clk_branch2_ops,
2915 },
2916 },
2917};
2918
2919static struct clk_branch gcc_cnoc_pcie2_tunnel_clk = {
2920 .halt_reg = 0x132b4,
2921 .halt_check = BRANCH_HALT_VOTED,
2922 .clkr = {
2923 .enable_reg = 0x52010,
2924 .enable_mask = BIT(31),
2925 .hw.init = &(const struct clk_init_data) {
2926 .name = "gcc_cnoc_pcie2_tunnel_clk",
2927 .ops = &clk_branch2_ops,
2928 },
2929 },
2930};
2931
2932static struct clk_branch gcc_cnoc_pcie_north_sf_axi_clk = {
2933 .halt_reg = 0x10014,
2934 .halt_check = BRANCH_HALT_VOTED,
2935 .hwcg_reg = 0x10014,
2936 .hwcg_bit = 1,
2937 .clkr = {
2938 .enable_reg = 0x52008,
2939 .enable_mask = BIT(6),
2940 .hw.init = &(const struct clk_init_data) {
2941 .name = "gcc_cnoc_pcie_north_sf_axi_clk",
2942 .ops = &clk_branch2_ops,
2943 },
2944 },
2945};
2946
2947static struct clk_branch gcc_cnoc_pcie_south_sf_axi_clk = {
2948 .halt_reg = 0x10018,
2949 .halt_check = BRANCH_HALT_VOTED,
2950 .hwcg_reg = 0x10018,
2951 .hwcg_bit = 1,
2952 .clkr = {
2953 .enable_reg = 0x52028,
2954 .enable_mask = BIT(12),
2955 .hw.init = &(const struct clk_init_data) {
2956 .name = "gcc_cnoc_pcie_south_sf_axi_clk",
2957 .ops = &clk_branch2_ops,
2958 },
2959 },
2960};
2961
2962static struct clk_branch gcc_cnoc_pcie_tunnel_clk = {
2963 .halt_reg = 0xa02b4,
2964 .halt_check = BRANCH_HALT_VOTED,
2965 .hwcg_reg = 0xa02b4,
2966 .hwcg_bit = 1,
2967 .clkr = {
2968 .enable_reg = 0x52010,
2969 .enable_mask = BIT(29),
2970 .hw.init = &(const struct clk_init_data) {
2971 .name = "gcc_cnoc_pcie_tunnel_clk",
2972 .ops = &clk_branch2_ops,
2973 },
2974 },
2975};
2976
2977static struct clk_branch gcc_ddrss_gpu_axi_clk = {
2978 .halt_reg = 0x7115c,
2979 .halt_check = BRANCH_HALT_SKIP,
2980 .hwcg_reg = 0x7115c,
2981 .hwcg_bit = 1,
2982 .clkr = {
2983 .enable_reg = 0x7115c,
2984 .enable_mask = BIT(0),
2985 .hw.init = &(const struct clk_init_data) {
2986 .name = "gcc_ddrss_gpu_axi_clk",
2987 .ops = &clk_branch2_ops,
2988 },
2989 },
2990};
2991
2992static struct clk_branch gcc_disp_hf_axi_clk = {
2993 .halt_reg = 0x2700c,
2994 .halt_check = BRANCH_HALT_SKIP,
2995 .hwcg_reg = 0x2700c,
2996 .hwcg_bit = 1,
2997 .clkr = {
2998 .enable_reg = 0x2700c,
2999 .enable_mask = BIT(0),
3000 .hw.init = &(const struct clk_init_data) {
3001 .name = "gcc_disp_hf_axi_clk",
3002 .ops = &clk_branch2_ops,
3003 },
3004 },
3005};
3006
3007static struct clk_branch gcc_gp1_clk = {
3008 .halt_reg = 0x64000,
3009 .halt_check = BRANCH_HALT,
3010 .clkr = {
3011 .enable_reg = 0x64000,
3012 .enable_mask = BIT(0),
3013 .hw.init = &(const struct clk_init_data) {
3014 .name = "gcc_gp1_clk",
3015 .parent_hws = (const struct clk_hw*[]) {
3016 &gcc_gp1_clk_src.clkr.hw,
3017 },
3018 .num_parents = 1,
3019 .flags = CLK_SET_RATE_PARENT,
3020 .ops = &clk_branch2_ops,
3021 },
3022 },
3023};
3024
3025static struct clk_branch gcc_gp2_clk = {
3026 .halt_reg = 0x65000,
3027 .halt_check = BRANCH_HALT,
3028 .clkr = {
3029 .enable_reg = 0x65000,
3030 .enable_mask = BIT(0),
3031 .hw.init = &(const struct clk_init_data) {
3032 .name = "gcc_gp2_clk",
3033 .parent_hws = (const struct clk_hw*[]) {
3034 &gcc_gp2_clk_src.clkr.hw,
3035 },
3036 .num_parents = 1,
3037 .flags = CLK_SET_RATE_PARENT,
3038 .ops = &clk_branch2_ops,
3039 },
3040 },
3041};
3042
3043static struct clk_branch gcc_gp3_clk = {
3044 .halt_reg = 0x66000,
3045 .halt_check = BRANCH_HALT,
3046 .clkr = {
3047 .enable_reg = 0x66000,
3048 .enable_mask = BIT(0),
3049 .hw.init = &(const struct clk_init_data) {
3050 .name = "gcc_gp3_clk",
3051 .parent_hws = (const struct clk_hw*[]) {
3052 &gcc_gp3_clk_src.clkr.hw,
3053 },
3054 .num_parents = 1,
3055 .flags = CLK_SET_RATE_PARENT,
3056 .ops = &clk_branch2_ops,
3057 },
3058 },
3059};
3060
3061static struct clk_branch gcc_gpu_gpll0_cph_clk_src = {
3062 .halt_check = BRANCH_HALT_DELAY,
3063 .clkr = {
3064 .enable_reg = 0x52000,
3065 .enable_mask = BIT(15),
3066 .hw.init = &(const struct clk_init_data) {
3067 .name = "gcc_gpu_gpll0_cph_clk_src",
3068 .parent_hws = (const struct clk_hw*[]) {
3069 &gcc_gpll0.clkr.hw,
3070 },
3071 .num_parents = 1,
3072 .flags = CLK_SET_RATE_PARENT,
3073 .ops = &clk_branch2_ops,
3074 },
3075 },
3076};
3077
3078static struct clk_branch gcc_gpu_gpll0_div_cph_clk_src = {
3079 .halt_check = BRANCH_HALT_DELAY,
3080 .clkr = {
3081 .enable_reg = 0x52000,
3082 .enable_mask = BIT(16),
3083 .hw.init = &(const struct clk_init_data) {
3084 .name = "gcc_gpu_gpll0_div_cph_clk_src",
3085 .parent_hws = (const struct clk_hw*[]) {
3086 &gcc_gpll0_out_even.clkr.hw,
3087 },
3088 .num_parents = 1,
3089 .flags = CLK_SET_RATE_PARENT,
3090 .ops = &clk_branch2_ops,
3091 },
3092 },
3093};
3094
3095static struct clk_branch gcc_gpu_memnoc_gfx_clk = {
3096 .halt_reg = 0x71010,
3097 .halt_check = BRANCH_HALT_VOTED,
3098 .hwcg_reg = 0x71010,
3099 .hwcg_bit = 1,
3100 .clkr = {
3101 .enable_reg = 0x71010,
3102 .enable_mask = BIT(0),
3103 .hw.init = &(const struct clk_init_data) {
3104 .name = "gcc_gpu_memnoc_gfx_clk",
3105 .ops = &clk_branch2_ops,
3106 },
3107 },
3108};
3109
3110static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
3111 .halt_reg = 0x71018,
3112 .halt_check = BRANCH_HALT,
3113 .clkr = {
3114 .enable_reg = 0x71018,
3115 .enable_mask = BIT(0),
3116 .hw.init = &(const struct clk_init_data) {
3117 .name = "gcc_gpu_snoc_dvm_gfx_clk",
3118 .ops = &clk_branch2_ops,
3119 },
3120 },
3121};
3122
3123static struct clk_branch gcc_pcie0_phy_rchng_clk = {
3124 .halt_reg = 0xa0050,
3125 .halt_check = BRANCH_HALT_VOTED,
3126 .clkr = {
3127 .enable_reg = 0x52010,
3128 .enable_mask = BIT(26),
3129 .hw.init = &(const struct clk_init_data) {
3130 .name = "gcc_pcie0_phy_rchng_clk",
3131 .parent_hws = (const struct clk_hw*[]) {
3132 &gcc_pcie_0_phy_rchng_clk_src.clkr.hw,
3133 },
3134 .num_parents = 1,
3135 .flags = CLK_SET_RATE_PARENT,
3136 .ops = &clk_branch2_ops,
3137 },
3138 },
3139};
3140
3141static struct clk_branch gcc_pcie1_phy_rchng_clk = {
3142 .halt_reg = 0x2c050,
3143 .halt_check = BRANCH_HALT_VOTED,
3144 .clkr = {
3145 .enable_reg = 0x52020,
3146 .enable_mask = BIT(31),
3147 .hw.init = &(const struct clk_init_data) {
3148 .name = "gcc_pcie1_phy_rchng_clk",
3149 .parent_hws = (const struct clk_hw*[]) {
3150 &gcc_pcie_1_phy_rchng_clk_src.clkr.hw,
3151 },
3152 .num_parents = 1,
3153 .flags = CLK_SET_RATE_PARENT,
3154 .ops = &clk_branch2_ops,
3155 },
3156 },
3157};
3158
3159static struct clk_branch gcc_pcie2_phy_rchng_clk = {
3160 .halt_reg = 0x13050,
3161 .halt_check = BRANCH_HALT_VOTED,
3162 .clkr = {
3163 .enable_reg = 0x52020,
3164 .enable_mask = BIT(24),
3165 .hw.init = &(const struct clk_init_data) {
3166 .name = "gcc_pcie2_phy_rchng_clk",
3167 .parent_hws = (const struct clk_hw*[]) {
3168 &gcc_pcie_2_phy_rchng_clk_src.clkr.hw,
3169 },
3170 .num_parents = 1,
3171 .flags = CLK_SET_RATE_PARENT,
3172 .ops = &clk_branch2_ops,
3173 },
3174 },
3175};
3176
3177static struct clk_branch gcc_pcie_0_aux_clk = {
3178 .halt_reg = 0xa0038,
3179 .halt_check = BRANCH_HALT_VOTED,
3180 .clkr = {
3181 .enable_reg = 0x52010,
3182 .enable_mask = BIT(24),
3183 .hw.init = &(const struct clk_init_data) {
3184 .name = "gcc_pcie_0_aux_clk",
3185 .parent_hws = (const struct clk_hw*[]) {
3186 &gcc_pcie_0_aux_clk_src.clkr.hw,
3187 },
3188 .num_parents = 1,
3189 .flags = CLK_SET_RATE_PARENT,
3190 .ops = &clk_branch2_ops,
3191 },
3192 },
3193};
3194
3195static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
3196 .halt_reg = 0xa0034,
3197 .halt_check = BRANCH_HALT_VOTED,
3198 .hwcg_reg = 0xa0034,
3199 .hwcg_bit = 1,
3200 .clkr = {
3201 .enable_reg = 0x52010,
3202 .enable_mask = BIT(23),
3203 .hw.init = &(const struct clk_init_data) {
3204 .name = "gcc_pcie_0_cfg_ahb_clk",
3205 .ops = &clk_branch2_ops,
3206 },
3207 },
3208};
3209
3210static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
3211 .halt_reg = 0xa0028,
3212 .halt_check = BRANCH_HALT_SKIP,
3213 .hwcg_reg = 0xa0028,
3214 .hwcg_bit = 1,
3215 .clkr = {
3216 .enable_reg = 0x52010,
3217 .enable_mask = BIT(22),
3218 .hw.init = &(const struct clk_init_data) {
3219 .name = "gcc_pcie_0_mstr_axi_clk",
3220 .ops = &clk_branch2_ops,
3221 },
3222 },
3223};
3224
3225static struct clk_branch gcc_pcie_0_pipe_clk = {
3226 .halt_reg = 0xa0044,
3227 .halt_check = BRANCH_HALT_SKIP,
3228 .clkr = {
3229 .enable_reg = 0x52010,
3230 .enable_mask = BIT(25),
3231 .hw.init = &(const struct clk_init_data) {
3232 .name = "gcc_pcie_0_pipe_clk",
3233 .parent_hws = (const struct clk_hw*[]) {
3234 &gcc_usb4_0_phy_pcie_pipe_mux_clk_src.clkr.hw,
3235 },
3236 .num_parents = 1,
3237 .flags = CLK_SET_RATE_PARENT,
3238 .ops = &clk_branch2_ops,
3239 },
3240 },
3241};
3242
3243static struct clk_branch gcc_pcie_0_slv_axi_clk = {
3244 .halt_reg = 0xa001c,
3245 .halt_check = BRANCH_HALT_VOTED,
3246 .hwcg_reg = 0xa001c,
3247 .hwcg_bit = 1,
3248 .clkr = {
3249 .enable_reg = 0x52010,
3250 .enable_mask = BIT(21),
3251 .hw.init = &(const struct clk_init_data) {
3252 .name = "gcc_pcie_0_slv_axi_clk",
3253 .ops = &clk_branch2_ops,
3254 },
3255 },
3256};
3257
3258static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = {
3259 .halt_reg = 0xa0018,
3260 .halt_check = BRANCH_HALT_VOTED,
3261 .clkr = {
3262 .enable_reg = 0x52010,
3263 .enable_mask = BIT(20),
3264 .hw.init = &(const struct clk_init_data) {
3265 .name = "gcc_pcie_0_slv_q2a_axi_clk",
3266 .ops = &clk_branch2_ops,
3267 },
3268 },
3269};
3270
3271static struct clk_branch gcc_pcie_1_aux_clk = {
3272 .halt_reg = 0x2c038,
3273 .halt_check = BRANCH_HALT_VOTED,
3274 .clkr = {
3275 .enable_reg = 0x52020,
3276 .enable_mask = BIT(29),
3277 .hw.init = &(const struct clk_init_data) {
3278 .name = "gcc_pcie_1_aux_clk",
3279 .parent_hws = (const struct clk_hw*[]) {
3280 &gcc_pcie_1_aux_clk_src.clkr.hw,
3281 },
3282 .num_parents = 1,
3283 .flags = CLK_SET_RATE_PARENT,
3284 .ops = &clk_branch2_ops,
3285 },
3286 },
3287};
3288
3289static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
3290 .halt_reg = 0x2c034,
3291 .halt_check = BRANCH_HALT_VOTED,
3292 .hwcg_reg = 0x2c034,
3293 .hwcg_bit = 1,
3294 .clkr = {
3295 .enable_reg = 0x52020,
3296 .enable_mask = BIT(28),
3297 .hw.init = &(const struct clk_init_data) {
3298 .name = "gcc_pcie_1_cfg_ahb_clk",
3299 .ops = &clk_branch2_ops,
3300 },
3301 },
3302};
3303
3304static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
3305 .halt_reg = 0x2c028,
3306 .halt_check = BRANCH_HALT_SKIP,
3307 .hwcg_reg = 0x2c028,
3308 .hwcg_bit = 1,
3309 .clkr = {
3310 .enable_reg = 0x52020,
3311 .enable_mask = BIT(27),
3312 .hw.init = &(const struct clk_init_data) {
3313 .name = "gcc_pcie_1_mstr_axi_clk",
3314 .ops = &clk_branch2_ops,
3315 },
3316 },
3317};
3318
3319static struct clk_branch gcc_pcie_1_pipe_clk = {
3320 .halt_reg = 0x2c044,
3321 .halt_check = BRANCH_HALT_SKIP,
3322 .clkr = {
3323 .enable_reg = 0x52020,
3324 .enable_mask = BIT(30),
3325 .hw.init = &(const struct clk_init_data) {
3326 .name = "gcc_pcie_1_pipe_clk",
3327 .parent_hws = (const struct clk_hw*[]) {
3328 &gcc_usb4_1_phy_pcie_pipe_mux_clk_src.clkr.hw,
3329 },
3330 .num_parents = 1,
3331 .flags = CLK_SET_RATE_PARENT,
3332 .ops = &clk_branch2_ops,
3333 },
3334 },
3335};
3336
3337static struct clk_branch gcc_pcie_1_slv_axi_clk = {
3338 .halt_reg = 0x2c01c,
3339 .halt_check = BRANCH_HALT_VOTED,
3340 .hwcg_reg = 0x2c01c,
3341 .hwcg_bit = 1,
3342 .clkr = {
3343 .enable_reg = 0x52020,
3344 .enable_mask = BIT(26),
3345 .hw.init = &(const struct clk_init_data) {
3346 .name = "gcc_pcie_1_slv_axi_clk",
3347 .ops = &clk_branch2_ops,
3348 },
3349 },
3350};
3351
3352static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = {
3353 .halt_reg = 0x2c018,
3354 .halt_check = BRANCH_HALT_VOTED,
3355 .clkr = {
3356 .enable_reg = 0x52020,
3357 .enable_mask = BIT(25),
3358 .hw.init = &(const struct clk_init_data) {
3359 .name = "gcc_pcie_1_slv_q2a_axi_clk",
3360 .ops = &clk_branch2_ops,
3361 },
3362 },
3363};
3364
3365static struct clk_branch gcc_pcie_2_aux_clk = {
3366 .halt_reg = 0x13038,
3367 .halt_check = BRANCH_HALT_VOTED,
3368 .clkr = {
3369 .enable_reg = 0x52020,
3370 .enable_mask = BIT(22),
3371 .hw.init = &(const struct clk_init_data) {
3372 .name = "gcc_pcie_2_aux_clk",
3373 .parent_hws = (const struct clk_hw*[]) {
3374 &gcc_pcie_2_aux_clk_src.clkr.hw,
3375 },
3376 .num_parents = 1,
3377 .flags = CLK_SET_RATE_PARENT,
3378 .ops = &clk_branch2_ops,
3379 },
3380 },
3381};
3382
3383static struct clk_branch gcc_pcie_2_cfg_ahb_clk = {
3384 .halt_reg = 0x13034,
3385 .halt_check = BRANCH_HALT_VOTED,
3386 .hwcg_reg = 0x13034,
3387 .hwcg_bit = 1,
3388 .clkr = {
3389 .enable_reg = 0x52020,
3390 .enable_mask = BIT(21),
3391 .hw.init = &(const struct clk_init_data) {
3392 .name = "gcc_pcie_2_cfg_ahb_clk",
3393 .ops = &clk_branch2_ops,
3394 },
3395 },
3396};
3397
3398static struct clk_branch gcc_pcie_2_mstr_axi_clk = {
3399 .halt_reg = 0x13028,
3400 .halt_check = BRANCH_HALT_SKIP,
3401 .hwcg_reg = 0x13028,
3402 .hwcg_bit = 1,
3403 .clkr = {
3404 .enable_reg = 0x52020,
3405 .enable_mask = BIT(20),
3406 .hw.init = &(const struct clk_init_data) {
3407 .name = "gcc_pcie_2_mstr_axi_clk",
3408 .ops = &clk_branch2_ops,
3409 },
3410 },
3411};
3412
3413static struct clk_branch gcc_pcie_2_pipe_clk = {
3414 .halt_reg = 0x13044,
3415 .halt_check = BRANCH_HALT_SKIP,
3416 .clkr = {
3417 .enable_reg = 0x52020,
3418 .enable_mask = BIT(23),
3419 .hw.init = &(const struct clk_init_data) {
3420 .name = "gcc_pcie_2_pipe_clk",
3421 .parent_hws = (const struct clk_hw*[]) {
3422 &gcc_usb4_2_phy_pcie_pipe_mux_clk_src.clkr.hw,
3423 },
3424 .num_parents = 1,
3425 .flags = CLK_SET_RATE_PARENT,
3426 .ops = &clk_branch2_ops,
3427 },
3428 },
3429};
3430
3431static struct clk_branch gcc_pcie_2_slv_axi_clk = {
3432 .halt_reg = 0x1301c,
3433 .halt_check = BRANCH_HALT_VOTED,
3434 .hwcg_reg = 0x1301c,
3435 .hwcg_bit = 1,
3436 .clkr = {
3437 .enable_reg = 0x52020,
3438 .enable_mask = BIT(19),
3439 .hw.init = &(const struct clk_init_data) {
3440 .name = "gcc_pcie_2_slv_axi_clk",
3441 .ops = &clk_branch2_ops,
3442 },
3443 },
3444};
3445
3446static struct clk_branch gcc_pcie_2_slv_q2a_axi_clk = {
3447 .halt_reg = 0x13018,
3448 .halt_check = BRANCH_HALT_VOTED,
3449 .clkr = {
3450 .enable_reg = 0x52020,
3451 .enable_mask = BIT(18),
3452 .hw.init = &(const struct clk_init_data) {
3453 .name = "gcc_pcie_2_slv_q2a_axi_clk",
3454 .ops = &clk_branch2_ops,
3455 },
3456 },
3457};
3458
3459static struct clk_branch gcc_pcie_3_aux_clk = {
3460 .halt_reg = 0x58038,
3461 .halt_check = BRANCH_HALT_VOTED,
3462 .clkr = {
3463 .enable_reg = 0x52020,
3464 .enable_mask = BIT(1),
3465 .hw.init = &(const struct clk_init_data) {
3466 .name = "gcc_pcie_3_aux_clk",
3467 .parent_hws = (const struct clk_hw*[]) {
3468 &gcc_pcie_3_aux_clk_src.clkr.hw,
3469 },
3470 .num_parents = 1,
3471 .flags = CLK_SET_RATE_PARENT,
3472 .ops = &clk_branch2_ops,
3473 },
3474 },
3475};
3476
3477static struct clk_branch gcc_pcie_3_cfg_ahb_clk = {
3478 .halt_reg = 0x58034,
3479 .halt_check = BRANCH_HALT_VOTED,
3480 .hwcg_reg = 0x58034,
3481 .hwcg_bit = 1,
3482 .clkr = {
3483 .enable_reg = 0x52020,
3484 .enable_mask = BIT(0),
3485 .hw.init = &(const struct clk_init_data) {
3486 .name = "gcc_pcie_3_cfg_ahb_clk",
3487 .ops = &clk_branch2_ops,
3488 },
3489 },
3490};
3491
3492static struct clk_branch gcc_pcie_3_mstr_axi_clk = {
3493 .halt_reg = 0x58028,
3494 .halt_check = BRANCH_HALT_SKIP,
3495 .hwcg_reg = 0x58028,
3496 .hwcg_bit = 1,
3497 .clkr = {
3498 .enable_reg = 0x52018,
3499 .enable_mask = BIT(31),
3500 .hw.init = &(const struct clk_init_data) {
3501 .name = "gcc_pcie_3_mstr_axi_clk",
3502 .ops = &clk_branch2_ops,
3503 },
3504 },
3505};
3506
3507static struct clk_branch gcc_pcie_3_phy_aux_clk = {
3508 .halt_reg = 0x58044,
3509 .halt_check = BRANCH_HALT_VOTED,
3510 .clkr = {
3511 .enable_reg = 0x52020,
3512 .enable_mask = BIT(2),
3513 .hw.init = &(const struct clk_init_data) {
3514 .name = "gcc_pcie_3_phy_aux_clk",
3515 .ops = &clk_branch2_ops,
3516 },
3517 },
3518};
3519
3520static struct clk_branch gcc_pcie_3_phy_rchng_clk = {
3521 .halt_reg = 0x5805c,
3522 .halt_check = BRANCH_HALT_VOTED,
3523 .clkr = {
3524 .enable_reg = 0x52020,
3525 .enable_mask = BIT(4),
3526 .hw.init = &(const struct clk_init_data) {
3527 .name = "gcc_pcie_3_phy_rchng_clk",
3528 .parent_hws = (const struct clk_hw*[]) {
3529 &gcc_pcie_3_phy_rchng_clk_src.clkr.hw,
3530 },
3531 .num_parents = 1,
3532 .flags = CLK_SET_RATE_PARENT,
3533 .ops = &clk_branch2_ops,
3534 },
3535 },
3536};
3537
3538static struct clk_branch gcc_pcie_3_pipe_clk = {
3539 .halt_reg = 0x58050,
3540 .halt_check = BRANCH_HALT_SKIP,
3541 .clkr = {
3542 .enable_reg = 0x52020,
3543 .enable_mask = BIT(3),
3544 .hw.init = &(const struct clk_init_data) {
3545 .name = "gcc_pcie_3_pipe_clk",
3546 .ops = &clk_branch2_ops,
3547 },
3548 },
3549};
3550
3551static struct clk_branch gcc_pcie_3_pipediv2_clk = {
3552 .halt_reg = 0x58060,
3553 .halt_check = BRANCH_HALT_SKIP,
3554 .clkr = {
3555 .enable_reg = 0x52020,
3556 .enable_mask = BIT(5),
3557 .hw.init = &(const struct clk_init_data) {
3558 .name = "gcc_pcie_3_pipediv2_clk",
3559 .parent_hws = (const struct clk_hw*[]) {
3560 &gcc_pcie_3_pipe_div_clk_src.clkr.hw,
3561 },
3562 .num_parents = 1,
3563 .flags = CLK_SET_RATE_PARENT,
3564 .ops = &clk_branch2_ops,
3565 },
3566 },
3567};
3568
3569static struct clk_branch gcc_pcie_3_slv_axi_clk = {
3570 .halt_reg = 0x5801c,
3571 .halt_check = BRANCH_HALT_VOTED,
3572 .hwcg_reg = 0x5801c,
3573 .hwcg_bit = 1,
3574 .clkr = {
3575 .enable_reg = 0x52018,
3576 .enable_mask = BIT(30),
3577 .hw.init = &(const struct clk_init_data) {
3578 .name = "gcc_pcie_3_slv_axi_clk",
3579 .ops = &clk_branch2_ops,
3580 },
3581 },
3582};
3583
3584static struct clk_branch gcc_pcie_3_slv_q2a_axi_clk = {
3585 .halt_reg = 0x58018,
3586 .halt_check = BRANCH_HALT_VOTED,
3587 .clkr = {
3588 .enable_reg = 0x52018,
3589 .enable_mask = BIT(29),
3590 .hw.init = &(const struct clk_init_data) {
3591 .name = "gcc_pcie_3_slv_q2a_axi_clk",
3592 .ops = &clk_branch2_ops,
3593 },
3594 },
3595};
3596
3597static struct clk_branch gcc_pcie_4_aux_clk = {
3598 .halt_reg = 0x6b038,
3599 .halt_check = BRANCH_HALT_VOTED,
3600 .clkr = {
3601 .enable_reg = 0x52008,
3602 .enable_mask = BIT(3),
3603 .hw.init = &(const struct clk_init_data) {
3604 .name = "gcc_pcie_4_aux_clk",
3605 .parent_hws = (const struct clk_hw*[]) {
3606 &gcc_pcie_4_aux_clk_src.clkr.hw,
3607 },
3608 .num_parents = 1,
3609 .flags = CLK_SET_RATE_PARENT,
3610 .ops = &clk_branch2_ops,
3611 },
3612 },
3613};
3614
3615static struct clk_branch gcc_pcie_4_cfg_ahb_clk = {
3616 .halt_reg = 0x6b034,
3617 .halt_check = BRANCH_HALT_VOTED,
3618 .hwcg_reg = 0x6b034,
3619 .hwcg_bit = 1,
3620 .clkr = {
3621 .enable_reg = 0x52008,
3622 .enable_mask = BIT(2),
3623 .hw.init = &(const struct clk_init_data) {
3624 .name = "gcc_pcie_4_cfg_ahb_clk",
3625 .ops = &clk_branch2_ops,
3626 },
3627 },
3628};
3629
3630static struct clk_branch gcc_pcie_4_mstr_axi_clk = {
3631 .halt_reg = 0x6b028,
3632 .halt_check = BRANCH_HALT_SKIP,
3633 .hwcg_reg = 0x6b028,
3634 .hwcg_bit = 1,
3635 .clkr = {
3636 .enable_reg = 0x52008,
3637 .enable_mask = BIT(1),
3638 .hw.init = &(const struct clk_init_data) {
3639 .name = "gcc_pcie_4_mstr_axi_clk",
3640 .ops = &clk_branch2_ops,
3641 },
3642 },
3643};
3644
3645static struct clk_branch gcc_pcie_4_phy_rchng_clk = {
3646 .halt_reg = 0x6b050,
3647 .halt_check = BRANCH_HALT_VOTED,
3648 .clkr = {
3649 .enable_reg = 0x52000,
3650 .enable_mask = BIT(22),
3651 .hw.init = &(const struct clk_init_data) {
3652 .name = "gcc_pcie_4_phy_rchng_clk",
3653 .parent_hws = (const struct clk_hw*[]) {
3654 &gcc_pcie_4_phy_rchng_clk_src.clkr.hw,
3655 },
3656 .num_parents = 1,
3657 .flags = CLK_SET_RATE_PARENT,
3658 .ops = &clk_branch2_ops,
3659 },
3660 },
3661};
3662
3663static struct clk_branch gcc_pcie_4_pipe_clk = {
3664 .halt_reg = 0x6b044,
3665 .halt_check = BRANCH_HALT_SKIP,
3666 .clkr = {
3667 .enable_reg = 0x52008,
3668 .enable_mask = BIT(4),
3669 .hw.init = &(const struct clk_init_data) {
3670 .name = "gcc_pcie_4_pipe_clk",
3671 .ops = &clk_branch2_ops,
3672 },
3673 },
3674};
3675
3676static struct clk_branch gcc_pcie_4_pipediv2_clk = {
3677 .halt_reg = 0x6b054,
3678 .halt_check = BRANCH_HALT_SKIP,
3679 .clkr = {
3680 .enable_reg = 0x52010,
3681 .enable_mask = BIT(27),
3682 .hw.init = &(const struct clk_init_data) {
3683 .name = "gcc_pcie_4_pipediv2_clk",
3684 .parent_hws = (const struct clk_hw*[]) {
3685 &gcc_pcie_4_pipe_div_clk_src.clkr.hw,
3686 },
3687 .num_parents = 1,
3688 .flags = CLK_SET_RATE_PARENT,
3689 .ops = &clk_branch2_ops,
3690 },
3691 },
3692};
3693
3694static struct clk_branch gcc_pcie_4_slv_axi_clk = {
3695 .halt_reg = 0x6b01c,
3696 .halt_check = BRANCH_HALT_VOTED,
3697 .hwcg_reg = 0x6b01c,
3698 .hwcg_bit = 1,
3699 .clkr = {
3700 .enable_reg = 0x52008,
3701 .enable_mask = BIT(0),
3702 .hw.init = &(const struct clk_init_data) {
3703 .name = "gcc_pcie_4_slv_axi_clk",
3704 .ops = &clk_branch2_ops,
3705 },
3706 },
3707};
3708
3709static struct clk_branch gcc_pcie_4_slv_q2a_axi_clk = {
3710 .halt_reg = 0x6b018,
3711 .halt_check = BRANCH_HALT_VOTED,
3712 .clkr = {
3713 .enable_reg = 0x52008,
3714 .enable_mask = BIT(5),
3715 .hw.init = &(const struct clk_init_data) {
3716 .name = "gcc_pcie_4_slv_q2a_axi_clk",
3717 .ops = &clk_branch2_ops,
3718 },
3719 },
3720};
3721
3722static struct clk_branch gcc_pcie_5_aux_clk = {
3723 .halt_reg = 0x2f038,
3724 .halt_check = BRANCH_HALT_VOTED,
3725 .clkr = {
3726 .enable_reg = 0x52018,
3727 .enable_mask = BIT(16),
3728 .hw.init = &(const struct clk_init_data) {
3729 .name = "gcc_pcie_5_aux_clk",
3730 .parent_hws = (const struct clk_hw*[]) {
3731 &gcc_pcie_5_aux_clk_src.clkr.hw,
3732 },
3733 .num_parents = 1,
3734 .flags = CLK_SET_RATE_PARENT,
3735 .ops = &clk_branch2_ops,
3736 },
3737 },
3738};
3739
3740static struct clk_branch gcc_pcie_5_cfg_ahb_clk = {
3741 .halt_reg = 0x2f034,
3742 .halt_check = BRANCH_HALT_VOTED,
3743 .hwcg_reg = 0x2f034,
3744 .hwcg_bit = 1,
3745 .clkr = {
3746 .enable_reg = 0x52018,
3747 .enable_mask = BIT(15),
3748 .hw.init = &(const struct clk_init_data) {
3749 .name = "gcc_pcie_5_cfg_ahb_clk",
3750 .ops = &clk_branch2_ops,
3751 },
3752 },
3753};
3754
3755static struct clk_branch gcc_pcie_5_mstr_axi_clk = {
3756 .halt_reg = 0x2f028,
3757 .halt_check = BRANCH_HALT_SKIP,
3758 .hwcg_reg = 0x2f028,
3759 .hwcg_bit = 1,
3760 .clkr = {
3761 .enable_reg = 0x52018,
3762 .enable_mask = BIT(14),
3763 .hw.init = &(const struct clk_init_data) {
3764 .name = "gcc_pcie_5_mstr_axi_clk",
3765 .ops = &clk_branch2_ops,
3766 },
3767 },
3768};
3769
3770static struct clk_branch gcc_pcie_5_phy_rchng_clk = {
3771 .halt_reg = 0x2f050,
3772 .halt_check = BRANCH_HALT_VOTED,
3773 .clkr = {
3774 .enable_reg = 0x52018,
3775 .enable_mask = BIT(18),
3776 .hw.init = &(const struct clk_init_data) {
3777 .name = "gcc_pcie_5_phy_rchng_clk",
3778 .parent_hws = (const struct clk_hw*[]) {
3779 &gcc_pcie_5_phy_rchng_clk_src.clkr.hw,
3780 },
3781 .num_parents = 1,
3782 .flags = CLK_SET_RATE_PARENT,
3783 .ops = &clk_branch2_ops,
3784 },
3785 },
3786};
3787
3788static struct clk_branch gcc_pcie_5_pipe_clk = {
3789 .halt_reg = 0x2f044,
3790 .halt_check = BRANCH_HALT_SKIP,
3791 .clkr = {
3792 .enable_reg = 0x52018,
3793 .enable_mask = BIT(17),
3794 .hw.init = &(const struct clk_init_data) {
3795 .name = "gcc_pcie_5_pipe_clk",
3796 .ops = &clk_branch2_ops,
3797 },
3798 },
3799};
3800
3801static struct clk_branch gcc_pcie_5_pipediv2_clk = {
3802 .halt_reg = 0x2f054,
3803 .halt_check = BRANCH_HALT_SKIP,
3804 .clkr = {
3805 .enable_reg = 0x52018,
3806 .enable_mask = BIT(19),
3807 .hw.init = &(const struct clk_init_data) {
3808 .name = "gcc_pcie_5_pipediv2_clk",
3809 .parent_hws = (const struct clk_hw*[]) {
3810 &gcc_pcie_5_pipe_div_clk_src.clkr.hw,
3811 },
3812 .num_parents = 1,
3813 .flags = CLK_SET_RATE_PARENT,
3814 .ops = &clk_branch2_ops,
3815 },
3816 },
3817};
3818
3819static struct clk_branch gcc_pcie_5_slv_axi_clk = {
3820 .halt_reg = 0x2f01c,
3821 .halt_check = BRANCH_HALT_VOTED,
3822 .hwcg_reg = 0x2f01c,
3823 .hwcg_bit = 1,
3824 .clkr = {
3825 .enable_reg = 0x52018,
3826 .enable_mask = BIT(13),
3827 .hw.init = &(const struct clk_init_data) {
3828 .name = "gcc_pcie_5_slv_axi_clk",
3829 .ops = &clk_branch2_ops,
3830 },
3831 },
3832};
3833
3834static struct clk_branch gcc_pcie_5_slv_q2a_axi_clk = {
3835 .halt_reg = 0x2f018,
3836 .halt_check = BRANCH_HALT_VOTED,
3837 .clkr = {
3838 .enable_reg = 0x52018,
3839 .enable_mask = BIT(12),
3840 .hw.init = &(const struct clk_init_data) {
3841 .name = "gcc_pcie_5_slv_q2a_axi_clk",
3842 .ops = &clk_branch2_ops,
3843 },
3844 },
3845};
3846
3847static struct clk_branch gcc_pcie_6a_aux_clk = {
3848 .halt_reg = 0x31038,
3849 .halt_check = BRANCH_HALT_VOTED,
3850 .clkr = {
3851 .enable_reg = 0x52018,
3852 .enable_mask = BIT(24),
3853 .hw.init = &(const struct clk_init_data) {
3854 .name = "gcc_pcie_6a_aux_clk",
3855 .parent_hws = (const struct clk_hw*[]) {
3856 &gcc_pcie_6a_aux_clk_src.clkr.hw,
3857 },
3858 .num_parents = 1,
3859 .flags = CLK_SET_RATE_PARENT,
3860 .ops = &clk_branch2_ops,
3861 },
3862 },
3863};
3864
3865static struct clk_branch gcc_pcie_6a_cfg_ahb_clk = {
3866 .halt_reg = 0x31034,
3867 .halt_check = BRANCH_HALT_VOTED,
3868 .hwcg_reg = 0x31034,
3869 .hwcg_bit = 1,
3870 .clkr = {
3871 .enable_reg = 0x52018,
3872 .enable_mask = BIT(23),
3873 .hw.init = &(const struct clk_init_data) {
3874 .name = "gcc_pcie_6a_cfg_ahb_clk",
3875 .ops = &clk_branch2_ops,
3876 },
3877 },
3878};
3879
3880static struct clk_branch gcc_pcie_6a_mstr_axi_clk = {
3881 .halt_reg = 0x31028,
3882 .halt_check = BRANCH_HALT_SKIP,
3883 .hwcg_reg = 0x31028,
3884 .hwcg_bit = 1,
3885 .clkr = {
3886 .enable_reg = 0x52018,
3887 .enable_mask = BIT(22),
3888 .hw.init = &(const struct clk_init_data) {
3889 .name = "gcc_pcie_6a_mstr_axi_clk",
3890 .ops = &clk_branch2_ops,
3891 },
3892 },
3893};
3894
3895static struct clk_branch gcc_pcie_6a_phy_aux_clk = {
3896 .halt_reg = 0x31044,
3897 .halt_check = BRANCH_HALT_VOTED,
3898 .clkr = {
3899 .enable_reg = 0x52018,
3900 .enable_mask = BIT(25),
3901 .hw.init = &(const struct clk_init_data) {
3902 .name = "gcc_pcie_6a_phy_aux_clk",
3903 .ops = &clk_branch2_ops,
3904 },
3905 },
3906};
3907
3908static struct clk_branch gcc_pcie_6a_phy_rchng_clk = {
3909 .halt_reg = 0x3105c,
3910 .halt_check = BRANCH_HALT_VOTED,
3911 .clkr = {
3912 .enable_reg = 0x52018,
3913 .enable_mask = BIT(27),
3914 .hw.init = &(const struct clk_init_data) {
3915 .name = "gcc_pcie_6a_phy_rchng_clk",
3916 .parent_hws = (const struct clk_hw*[]) {
3917 &gcc_pcie_6a_phy_rchng_clk_src.clkr.hw,
3918 },
3919 .num_parents = 1,
3920 .flags = CLK_SET_RATE_PARENT,
3921 .ops = &clk_branch2_ops,
3922 },
3923 },
3924};
3925
3926static struct clk_branch gcc_pcie_6a_pipe_clk = {
3927 .halt_reg = 0x31050,
3928 .halt_check = BRANCH_HALT_SKIP,
3929 .clkr = {
3930 .enable_reg = 0x52018,
3931 .enable_mask = BIT(26),
3932 .hw.init = &(const struct clk_init_data) {
3933 .name = "gcc_pcie_6a_pipe_clk",
3934 .ops = &clk_branch2_ops,
3935 },
3936 },
3937};
3938
3939static struct clk_branch gcc_pcie_6a_pipediv2_clk = {
3940 .halt_reg = 0x31060,
3941 .halt_check = BRANCH_HALT_SKIP,
3942 .clkr = {
3943 .enable_reg = 0x52018,
3944 .enable_mask = BIT(28),
3945 .hw.init = &(const struct clk_init_data) {
3946 .name = "gcc_pcie_6a_pipediv2_clk",
3947 .parent_hws = (const struct clk_hw*[]) {
3948 &gcc_pcie_6a_pipe_div_clk_src.clkr.hw,
3949 },
3950 .num_parents = 1,
3951 .flags = CLK_SET_RATE_PARENT,
3952 .ops = &clk_branch2_ops,
3953 },
3954 },
3955};
3956
3957static struct clk_branch gcc_pcie_6a_slv_axi_clk = {
3958 .halt_reg = 0x3101c,
3959 .halt_check = BRANCH_HALT_VOTED,
3960 .hwcg_reg = 0x3101c,
3961 .hwcg_bit = 1,
3962 .clkr = {
3963 .enable_reg = 0x52018,
3964 .enable_mask = BIT(21),
3965 .hw.init = &(const struct clk_init_data) {
3966 .name = "gcc_pcie_6a_slv_axi_clk",
3967 .ops = &clk_branch2_ops,
3968 },
3969 },
3970};
3971
3972static struct clk_branch gcc_pcie_6a_slv_q2a_axi_clk = {
3973 .halt_reg = 0x31018,
3974 .halt_check = BRANCH_HALT_VOTED,
3975 .clkr = {
3976 .enable_reg = 0x52018,
3977 .enable_mask = BIT(20),
3978 .hw.init = &(const struct clk_init_data) {
3979 .name = "gcc_pcie_6a_slv_q2a_axi_clk",
3980 .ops = &clk_branch2_ops,
3981 },
3982 },
3983};
3984
3985static struct clk_branch gcc_pcie_6b_aux_clk = {
3986 .halt_reg = 0x8d038,
3987 .halt_check = BRANCH_HALT_VOTED,
3988 .clkr = {
3989 .enable_reg = 0x52000,
3990 .enable_mask = BIT(29),
3991 .hw.init = &(const struct clk_init_data) {
3992 .name = "gcc_pcie_6b_aux_clk",
3993 .parent_hws = (const struct clk_hw*[]) {
3994 &gcc_pcie_6b_aux_clk_src.clkr.hw,
3995 },
3996 .num_parents = 1,
3997 .flags = CLK_SET_RATE_PARENT,
3998 .ops = &clk_branch2_ops,
3999 },
4000 },
4001};
4002
4003static struct clk_branch gcc_pcie_6b_cfg_ahb_clk = {
4004 .halt_reg = 0x8d034,
4005 .halt_check = BRANCH_HALT_VOTED,
4006 .hwcg_reg = 0x8d034,
4007 .hwcg_bit = 1,
4008 .clkr = {
4009 .enable_reg = 0x52000,
4010 .enable_mask = BIT(28),
4011 .hw.init = &(const struct clk_init_data) {
4012 .name = "gcc_pcie_6b_cfg_ahb_clk",
4013 .ops = &clk_branch2_ops,
4014 },
4015 },
4016};
4017
4018static struct clk_branch gcc_pcie_6b_mstr_axi_clk = {
4019 .halt_reg = 0x8d028,
4020 .halt_check = BRANCH_HALT_SKIP,
4021 .hwcg_reg = 0x8d028,
4022 .hwcg_bit = 1,
4023 .clkr = {
4024 .enable_reg = 0x52000,
4025 .enable_mask = BIT(27),
4026 .hw.init = &(const struct clk_init_data) {
4027 .name = "gcc_pcie_6b_mstr_axi_clk",
4028 .ops = &clk_branch2_ops,
4029 },
4030 },
4031};
4032
4033static struct clk_branch gcc_pcie_6b_phy_aux_clk = {
4034 .halt_reg = 0x8d044,
4035 .halt_check = BRANCH_HALT_VOTED,
4036 .clkr = {
4037 .enable_reg = 0x52000,
4038 .enable_mask = BIT(24),
4039 .hw.init = &(const struct clk_init_data) {
4040 .name = "gcc_pcie_6b_phy_aux_clk",
4041 .ops = &clk_branch2_ops,
4042 },
4043 },
4044};
4045
4046static struct clk_branch gcc_pcie_6b_phy_rchng_clk = {
4047 .halt_reg = 0x8d05c,
4048 .halt_check = BRANCH_HALT_VOTED,
4049 .clkr = {
4050 .enable_reg = 0x52000,
4051 .enable_mask = BIT(23),
4052 .hw.init = &(const struct clk_init_data) {
4053 .name = "gcc_pcie_6b_phy_rchng_clk",
4054 .parent_hws = (const struct clk_hw*[]) {
4055 &gcc_pcie_6b_phy_rchng_clk_src.clkr.hw,
4056 },
4057 .num_parents = 1,
4058 .flags = CLK_SET_RATE_PARENT,
4059 .ops = &clk_branch2_ops,
4060 },
4061 },
4062};
4063
4064static struct clk_branch gcc_pcie_6b_pipe_clk = {
4065 .halt_reg = 0x8d050,
4066 .halt_check = BRANCH_HALT_SKIP,
4067 .clkr = {
4068 .enable_reg = 0x52000,
4069 .enable_mask = BIT(30),
4070 .hw.init = &(const struct clk_init_data) {
4071 .name = "gcc_pcie_6b_pipe_clk",
4072 .ops = &clk_branch2_ops,
4073 },
4074 },
4075};
4076
4077static struct clk_branch gcc_pcie_6b_pipediv2_clk = {
4078 .halt_reg = 0x8d060,
4079 .halt_check = BRANCH_HALT_SKIP,
4080 .clkr = {
4081 .enable_reg = 0x52010,
4082 .enable_mask = BIT(28),
4083 .hw.init = &(const struct clk_init_data) {
4084 .name = "gcc_pcie_6b_pipediv2_clk",
4085 .parent_hws = (const struct clk_hw*[]) {
4086 &gcc_pcie_6b_pipe_div_clk_src.clkr.hw,
4087 },
4088 .num_parents = 1,
4089 .flags = CLK_SET_RATE_PARENT,
4090 .ops = &clk_branch2_ops,
4091 },
4092 },
4093};
4094
4095static struct clk_branch gcc_pcie_6b_slv_axi_clk = {
4096 .halt_reg = 0x8d01c,
4097 .halt_check = BRANCH_HALT_VOTED,
4098 .hwcg_reg = 0x8d01c,
4099 .hwcg_bit = 1,
4100 .clkr = {
4101 .enable_reg = 0x52000,
4102 .enable_mask = BIT(26),
4103 .hw.init = &(const struct clk_init_data) {
4104 .name = "gcc_pcie_6b_slv_axi_clk",
4105 .ops = &clk_branch2_ops,
4106 },
4107 },
4108};
4109
4110static struct clk_branch gcc_pcie_6b_slv_q2a_axi_clk = {
4111 .halt_reg = 0x8d018,
4112 .halt_check = BRANCH_HALT_VOTED,
4113 .clkr = {
4114 .enable_reg = 0x52000,
4115 .enable_mask = BIT(25),
4116 .hw.init = &(const struct clk_init_data) {
4117 .name = "gcc_pcie_6b_slv_q2a_axi_clk",
4118 .ops = &clk_branch2_ops,
4119 },
4120 },
4121};
4122
4123static struct clk_branch gcc_pcie_rscc_ahb_clk = {
4124 .halt_reg = 0xa4008,
4125 .halt_check = BRANCH_HALT_VOTED,
4126 .hwcg_reg = 0xa4008,
4127 .hwcg_bit = 1,
4128 .clkr = {
4129 .enable_reg = 0x52028,
4130 .enable_mask = BIT(18),
4131 .hw.init = &(const struct clk_init_data) {
4132 .name = "gcc_pcie_rscc_ahb_clk",
4133 .ops = &clk_branch2_ops,
4134 },
4135 },
4136};
4137
4138static struct clk_branch gcc_pcie_rscc_xo_clk = {
4139 .halt_reg = 0xa4004,
4140 .halt_check = BRANCH_HALT_VOTED,
4141 .clkr = {
4142 .enable_reg = 0x52028,
4143 .enable_mask = BIT(17),
4144 .hw.init = &(const struct clk_init_data) {
4145 .name = "gcc_pcie_rscc_xo_clk",
4146 .parent_hws = (const struct clk_hw*[]) {
4147 &gcc_pcie_rscc_xo_clk_src.clkr.hw,
4148 },
4149 .num_parents = 1,
4150 .flags = CLK_SET_RATE_PARENT,
4151 .ops = &clk_branch2_ops,
4152 },
4153 },
4154};
4155
4156static struct clk_branch gcc_pdm2_clk = {
4157 .halt_reg = 0x3300c,
4158 .halt_check = BRANCH_HALT,
4159 .clkr = {
4160 .enable_reg = 0x3300c,
4161 .enable_mask = BIT(0),
4162 .hw.init = &(const struct clk_init_data) {
4163 .name = "gcc_pdm2_clk",
4164 .parent_hws = (const struct clk_hw*[]) {
4165 &gcc_pdm2_clk_src.clkr.hw,
4166 },
4167 .num_parents = 1,
4168 .flags = CLK_SET_RATE_PARENT,
4169 .ops = &clk_branch2_ops,
4170 },
4171 },
4172};
4173
4174static struct clk_branch gcc_pdm_ahb_clk = {
4175 .halt_reg = 0x33004,
4176 .halt_check = BRANCH_HALT_VOTED,
4177 .hwcg_reg = 0x33004,
4178 .hwcg_bit = 1,
4179 .clkr = {
4180 .enable_reg = 0x33004,
4181 .enable_mask = BIT(0),
4182 .hw.init = &(const struct clk_init_data) {
4183 .name = "gcc_pdm_ahb_clk",
4184 .ops = &clk_branch2_ops,
4185 },
4186 },
4187};
4188
4189static struct clk_branch gcc_pdm_xo4_clk = {
4190 .halt_reg = 0x33008,
4191 .halt_check = BRANCH_HALT,
4192 .clkr = {
4193 .enable_reg = 0x33008,
4194 .enable_mask = BIT(0),
4195 .hw.init = &(const struct clk_init_data) {
4196 .name = "gcc_pdm_xo4_clk",
4197 .ops = &clk_branch2_ops,
4198 },
4199 },
4200};
4201
4202static struct clk_branch gcc_qmip_av1e_ahb_clk = {
4203 .halt_reg = 0x4a018,
4204 .halt_check = BRANCH_HALT_VOTED,
4205 .hwcg_reg = 0x4a018,
4206 .hwcg_bit = 1,
4207 .clkr = {
4208 .enable_reg = 0x4a018,
4209 .enable_mask = BIT(0),
4210 .hw.init = &(const struct clk_init_data) {
4211 .name = "gcc_qmip_av1e_ahb_clk",
4212 .ops = &clk_branch2_ops,
4213 },
4214 },
4215};
4216
4217static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = {
4218 .halt_reg = 0x26008,
4219 .halt_check = BRANCH_HALT_VOTED,
4220 .hwcg_reg = 0x26008,
4221 .hwcg_bit = 1,
4222 .clkr = {
4223 .enable_reg = 0x26008,
4224 .enable_mask = BIT(0),
4225 .hw.init = &(const struct clk_init_data) {
4226 .name = "gcc_qmip_camera_nrt_ahb_clk",
4227 .ops = &clk_branch2_ops,
4228 },
4229 },
4230};
4231
4232static struct clk_branch gcc_qmip_camera_rt_ahb_clk = {
4233 .halt_reg = 0x2600c,
4234 .halt_check = BRANCH_HALT_VOTED,
4235 .hwcg_reg = 0x2600c,
4236 .hwcg_bit = 1,
4237 .clkr = {
4238 .enable_reg = 0x2600c,
4239 .enable_mask = BIT(0),
4240 .hw.init = &(const struct clk_init_data) {
4241 .name = "gcc_qmip_camera_rt_ahb_clk",
4242 .ops = &clk_branch2_ops,
4243 },
4244 },
4245};
4246
4247static struct clk_branch gcc_qmip_disp_ahb_clk = {
4248 .halt_reg = 0x27008,
4249 .halt_check = BRANCH_HALT_VOTED,
4250 .hwcg_reg = 0x27008,
4251 .hwcg_bit = 1,
4252 .clkr = {
4253 .enable_reg = 0x27008,
4254 .enable_mask = BIT(0),
4255 .hw.init = &(const struct clk_init_data) {
4256 .name = "gcc_qmip_disp_ahb_clk",
4257 .ops = &clk_branch2_ops,
4258 },
4259 },
4260};
4261
4262static struct clk_branch gcc_qmip_gpu_ahb_clk = {
4263 .halt_reg = 0x71008,
4264 .halt_check = BRANCH_HALT_VOTED,
4265 .hwcg_reg = 0x71008,
4266 .hwcg_bit = 1,
4267 .clkr = {
4268 .enable_reg = 0x71008,
4269 .enable_mask = BIT(0),
4270 .hw.init = &(const struct clk_init_data) {
4271 .name = "gcc_qmip_gpu_ahb_clk",
4272 .ops = &clk_branch2_ops,
4273 },
4274 },
4275};
4276
4277static struct clk_branch gcc_qmip_video_cv_cpu_ahb_clk = {
4278 .halt_reg = 0x32014,
4279 .halt_check = BRANCH_HALT_VOTED,
4280 .hwcg_reg = 0x32014,
4281 .hwcg_bit = 1,
4282 .clkr = {
4283 .enable_reg = 0x32014,
4284 .enable_mask = BIT(0),
4285 .hw.init = &(const struct clk_init_data) {
4286 .name = "gcc_qmip_video_cv_cpu_ahb_clk",
4287 .ops = &clk_branch2_ops,
4288 },
4289 },
4290};
4291
4292static struct clk_branch gcc_qmip_video_cvp_ahb_clk = {
4293 .halt_reg = 0x32008,
4294 .halt_check = BRANCH_HALT_VOTED,
4295 .hwcg_reg = 0x32008,
4296 .hwcg_bit = 1,
4297 .clkr = {
4298 .enable_reg = 0x32008,
4299 .enable_mask = BIT(0),
4300 .hw.init = &(const struct clk_init_data) {
4301 .name = "gcc_qmip_video_cvp_ahb_clk",
4302 .ops = &clk_branch2_ops,
4303 },
4304 },
4305};
4306
4307static struct clk_branch gcc_qmip_video_v_cpu_ahb_clk = {
4308 .halt_reg = 0x32010,
4309 .halt_check = BRANCH_HALT_VOTED,
4310 .hwcg_reg = 0x32010,
4311 .hwcg_bit = 1,
4312 .clkr = {
4313 .enable_reg = 0x32010,
4314 .enable_mask = BIT(0),
4315 .hw.init = &(const struct clk_init_data) {
4316 .name = "gcc_qmip_video_v_cpu_ahb_clk",
4317 .ops = &clk_branch2_ops,
4318 },
4319 },
4320};
4321
4322static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = {
4323 .halt_reg = 0x3200c,
4324 .halt_check = BRANCH_HALT_VOTED,
4325 .hwcg_reg = 0x3200c,
4326 .hwcg_bit = 1,
4327 .clkr = {
4328 .enable_reg = 0x3200c,
4329 .enable_mask = BIT(0),
4330 .hw.init = &(const struct clk_init_data) {
4331 .name = "gcc_qmip_video_vcodec_ahb_clk",
4332 .ops = &clk_branch2_ops,
4333 },
4334 },
4335};
4336
4337static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = {
4338 .halt_reg = 0x23018,
4339 .halt_check = BRANCH_HALT_VOTED,
4340 .clkr = {
4341 .enable_reg = 0x52020,
4342 .enable_mask = BIT(9),
4343 .hw.init = &(const struct clk_init_data) {
4344 .name = "gcc_qupv3_wrap0_core_2x_clk",
4345 .ops = &clk_branch2_ops,
4346 },
4347 },
4348};
4349
4350static struct clk_branch gcc_qupv3_wrap0_core_clk = {
4351 .halt_reg = 0x23008,
4352 .halt_check = BRANCH_HALT_VOTED,
4353 .clkr = {
4354 .enable_reg = 0x52020,
4355 .enable_mask = BIT(8),
4356 .hw.init = &(const struct clk_init_data) {
4357 .name = "gcc_qupv3_wrap0_core_clk",
4358 .ops = &clk_branch2_ops,
4359 },
4360 },
4361};
4362
4363static struct clk_branch gcc_qupv3_wrap0_qspi_s2_clk = {
4364 .halt_reg = 0x42280,
4365 .halt_check = BRANCH_HALT_VOTED,
4366 .clkr = {
4367 .enable_reg = 0x52028,
4368 .enable_mask = BIT(2),
4369 .hw.init = &(const struct clk_init_data) {
4370 .name = "gcc_qupv3_wrap0_qspi_s2_clk",
4371 .parent_hws = (const struct clk_hw*[]) {
4372 &gcc_qupv3_wrap0_s2_clk_src.clkr.hw,
4373 },
4374 .num_parents = 1,
4375 .flags = CLK_SET_RATE_PARENT,
4376 .ops = &clk_branch2_ops,
4377 },
4378 },
4379};
4380
4381static struct clk_branch gcc_qupv3_wrap0_qspi_s3_clk = {
4382 .halt_reg = 0x423c0,
4383 .halt_check = BRANCH_HALT_VOTED,
4384 .clkr = {
4385 .enable_reg = 0x52028,
4386 .enable_mask = BIT(3),
4387 .hw.init = &(const struct clk_init_data) {
4388 .name = "gcc_qupv3_wrap0_qspi_s3_clk",
4389 .parent_hws = (const struct clk_hw*[]) {
4390 &gcc_qupv3_wrap0_s3_clk_src.clkr.hw,
4391 },
4392 .num_parents = 1,
4393 .flags = CLK_SET_RATE_PARENT,
4394 .ops = &clk_branch2_ops,
4395 },
4396 },
4397};
4398
4399static struct clk_branch gcc_qupv3_wrap0_s0_clk = {
4400 .halt_reg = 0x42004,
4401 .halt_check = BRANCH_HALT_VOTED,
4402 .clkr = {
4403 .enable_reg = 0x52020,
4404 .enable_mask = BIT(10),
4405 .hw.init = &(const struct clk_init_data) {
4406 .name = "gcc_qupv3_wrap0_s0_clk",
4407 .parent_hws = (const struct clk_hw*[]) {
4408 &gcc_qupv3_wrap0_s0_clk_src.clkr.hw,
4409 },
4410 .num_parents = 1,
4411 .flags = CLK_SET_RATE_PARENT,
4412 .ops = &clk_branch2_ops,
4413 },
4414 },
4415};
4416
4417static struct clk_branch gcc_qupv3_wrap0_s1_clk = {
4418 .halt_reg = 0x4213c,
4419 .halt_check = BRANCH_HALT_VOTED,
4420 .clkr = {
4421 .enable_reg = 0x52020,
4422 .enable_mask = BIT(11),
4423 .hw.init = &(const struct clk_init_data) {
4424 .name = "gcc_qupv3_wrap0_s1_clk",
4425 .parent_hws = (const struct clk_hw*[]) {
4426 &gcc_qupv3_wrap0_s1_clk_src.clkr.hw,
4427 },
4428 .num_parents = 1,
4429 .flags = CLK_SET_RATE_PARENT,
4430 .ops = &clk_branch2_ops,
4431 },
4432 },
4433};
4434
4435static struct clk_branch gcc_qupv3_wrap0_s2_clk = {
4436 .halt_reg = 0x42274,
4437 .halt_check = BRANCH_HALT_VOTED,
4438 .clkr = {
4439 .enable_reg = 0x52020,
4440 .enable_mask = BIT(12),
4441 .hw.init = &(const struct clk_init_data) {
4442 .name = "gcc_qupv3_wrap0_s2_clk",
4443 .parent_hws = (const struct clk_hw*[]) {
4444 &gcc_qupv3_wrap0_s2_div_clk_src.clkr.hw,
4445 },
4446 .num_parents = 1,
4447 .flags = CLK_SET_RATE_PARENT,
4448 .ops = &clk_branch2_ops,
4449 },
4450 },
4451};
4452
4453static struct clk_branch gcc_qupv3_wrap0_s3_clk = {
4454 .halt_reg = 0x423b4,
4455 .halt_check = BRANCH_HALT_VOTED,
4456 .clkr = {
4457 .enable_reg = 0x52020,
4458 .enable_mask = BIT(13),
4459 .hw.init = &(const struct clk_init_data) {
4460 .name = "gcc_qupv3_wrap0_s3_clk",
4461 .parent_hws = (const struct clk_hw*[]) {
4462 &gcc_qupv3_wrap0_s3_div_clk_src.clkr.hw,
4463 },
4464 .num_parents = 1,
4465 .flags = CLK_SET_RATE_PARENT,
4466 .ops = &clk_branch2_ops,
4467 },
4468 },
4469};
4470
4471static struct clk_branch gcc_qupv3_wrap0_s4_clk = {
4472 .halt_reg = 0x424f4,
4473 .halt_check = BRANCH_HALT_VOTED,
4474 .clkr = {
4475 .enable_reg = 0x52020,
4476 .enable_mask = BIT(14),
4477 .hw.init = &(const struct clk_init_data) {
4478 .name = "gcc_qupv3_wrap0_s4_clk",
4479 .parent_hws = (const struct clk_hw*[]) {
4480 &gcc_qupv3_wrap0_s4_clk_src.clkr.hw,
4481 },
4482 .num_parents = 1,
4483 .flags = CLK_SET_RATE_PARENT,
4484 .ops = &clk_branch2_ops,
4485 },
4486 },
4487};
4488
4489static struct clk_branch gcc_qupv3_wrap0_s5_clk = {
4490 .halt_reg = 0x4262c,
4491 .halt_check = BRANCH_HALT_VOTED,
4492 .clkr = {
4493 .enable_reg = 0x52020,
4494 .enable_mask = BIT(15),
4495 .hw.init = &(const struct clk_init_data) {
4496 .name = "gcc_qupv3_wrap0_s5_clk",
4497 .parent_hws = (const struct clk_hw*[]) {
4498 &gcc_qupv3_wrap0_s5_clk_src.clkr.hw,
4499 },
4500 .num_parents = 1,
4501 .flags = CLK_SET_RATE_PARENT,
4502 .ops = &clk_branch2_ops,
4503 },
4504 },
4505};
4506
4507static struct clk_branch gcc_qupv3_wrap0_s6_clk = {
4508 .halt_reg = 0x42764,
4509 .halt_check = BRANCH_HALT_VOTED,
4510 .clkr = {
4511 .enable_reg = 0x52020,
4512 .enable_mask = BIT(16),
4513 .hw.init = &(const struct clk_init_data) {
4514 .name = "gcc_qupv3_wrap0_s6_clk",
4515 .parent_hws = (const struct clk_hw*[]) {
4516 &gcc_qupv3_wrap0_s6_clk_src.clkr.hw,
4517 },
4518 .num_parents = 1,
4519 .flags = CLK_SET_RATE_PARENT,
4520 .ops = &clk_branch2_ops,
4521 },
4522 },
4523};
4524
4525static struct clk_branch gcc_qupv3_wrap0_s7_clk = {
4526 .halt_reg = 0x4289c,
4527 .halt_check = BRANCH_HALT_VOTED,
4528 .clkr = {
4529 .enable_reg = 0x52020,
4530 .enable_mask = BIT(17),
4531 .hw.init = &(const struct clk_init_data) {
4532 .name = "gcc_qupv3_wrap0_s7_clk",
4533 .parent_hws = (const struct clk_hw*[]) {
4534 &gcc_qupv3_wrap0_s7_clk_src.clkr.hw,
4535 },
4536 .num_parents = 1,
4537 .flags = CLK_SET_RATE_PARENT,
4538 .ops = &clk_branch2_ops,
4539 },
4540 },
4541};
4542
4543static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = {
4544 .halt_reg = 0x23168,
4545 .halt_check = BRANCH_HALT_VOTED,
4546 .clkr = {
4547 .enable_reg = 0x52008,
4548 .enable_mask = BIT(18),
4549 .hw.init = &(const struct clk_init_data) {
4550 .name = "gcc_qupv3_wrap1_core_2x_clk",
4551 .ops = &clk_branch2_ops,
4552 },
4553 },
4554};
4555
4556static struct clk_branch gcc_qupv3_wrap1_core_clk = {
4557 .halt_reg = 0x23158,
4558 .halt_check = BRANCH_HALT_VOTED,
4559 .clkr = {
4560 .enable_reg = 0x52008,
4561 .enable_mask = BIT(19),
4562 .hw.init = &(const struct clk_init_data) {
4563 .name = "gcc_qupv3_wrap1_core_clk",
4564 .ops = &clk_branch2_ops,
4565 },
4566 },
4567};
4568
4569static struct clk_branch gcc_qupv3_wrap1_qspi_s2_clk = {
4570 .halt_reg = 0x18280,
4571 .halt_check = BRANCH_HALT_VOTED,
4572 .clkr = {
4573 .enable_reg = 0x52028,
4574 .enable_mask = BIT(4),
4575 .hw.init = &(const struct clk_init_data) {
4576 .name = "gcc_qupv3_wrap1_qspi_s2_clk",
4577 .parent_hws = (const struct clk_hw*[]) {
4578 &gcc_qupv3_wrap1_s2_clk_src.clkr.hw,
4579 },
4580 .num_parents = 1,
4581 .flags = CLK_SET_RATE_PARENT,
4582 .ops = &clk_branch2_ops,
4583 },
4584 },
4585};
4586
4587static struct clk_branch gcc_qupv3_wrap1_qspi_s3_clk = {
4588 .halt_reg = 0x183c0,
4589 .halt_check = BRANCH_HALT_VOTED,
4590 .clkr = {
4591 .enable_reg = 0x52028,
4592 .enable_mask = BIT(5),
4593 .hw.init = &(const struct clk_init_data) {
4594 .name = "gcc_qupv3_wrap1_qspi_s3_clk",
4595 .parent_hws = (const struct clk_hw*[]) {
4596 &gcc_qupv3_wrap1_s3_clk_src.clkr.hw,
4597 },
4598 .num_parents = 1,
4599 .flags = CLK_SET_RATE_PARENT,
4600 .ops = &clk_branch2_ops,
4601 },
4602 },
4603};
4604
4605static struct clk_branch gcc_qupv3_wrap1_s0_clk = {
4606 .halt_reg = 0x18004,
4607 .halt_check = BRANCH_HALT_VOTED,
4608 .clkr = {
4609 .enable_reg = 0x52008,
4610 .enable_mask = BIT(22),
4611 .hw.init = &(const struct clk_init_data) {
4612 .name = "gcc_qupv3_wrap1_s0_clk",
4613 .parent_hws = (const struct clk_hw*[]) {
4614 &gcc_qupv3_wrap1_s0_clk_src.clkr.hw,
4615 },
4616 .num_parents = 1,
4617 .flags = CLK_SET_RATE_PARENT,
4618 .ops = &clk_branch2_ops,
4619 },
4620 },
4621};
4622
4623static struct clk_branch gcc_qupv3_wrap1_s1_clk = {
4624 .halt_reg = 0x1813c,
4625 .halt_check = BRANCH_HALT_VOTED,
4626 .clkr = {
4627 .enable_reg = 0x52008,
4628 .enable_mask = BIT(23),
4629 .hw.init = &(const struct clk_init_data) {
4630 .name = "gcc_qupv3_wrap1_s1_clk",
4631 .parent_hws = (const struct clk_hw*[]) {
4632 &gcc_qupv3_wrap1_s1_clk_src.clkr.hw,
4633 },
4634 .num_parents = 1,
4635 .flags = CLK_SET_RATE_PARENT,
4636 .ops = &clk_branch2_ops,
4637 },
4638 },
4639};
4640
4641static struct clk_branch gcc_qupv3_wrap1_s2_clk = {
4642 .halt_reg = 0x18274,
4643 .halt_check = BRANCH_HALT_VOTED,
4644 .clkr = {
4645 .enable_reg = 0x52008,
4646 .enable_mask = BIT(24),
4647 .hw.init = &(const struct clk_init_data) {
4648 .name = "gcc_qupv3_wrap1_s2_clk",
4649 .parent_hws = (const struct clk_hw*[]) {
4650 &gcc_qupv3_wrap1_s2_div_clk_src.clkr.hw,
4651 },
4652 .num_parents = 1,
4653 .flags = CLK_SET_RATE_PARENT,
4654 .ops = &clk_branch2_ops,
4655 },
4656 },
4657};
4658
4659static struct clk_branch gcc_qupv3_wrap1_s3_clk = {
4660 .halt_reg = 0x183b4,
4661 .halt_check = BRANCH_HALT_VOTED,
4662 .clkr = {
4663 .enable_reg = 0x52008,
4664 .enable_mask = BIT(25),
4665 .hw.init = &(const struct clk_init_data) {
4666 .name = "gcc_qupv3_wrap1_s3_clk",
4667 .parent_hws = (const struct clk_hw*[]) {
4668 &gcc_qupv3_wrap1_s3_div_clk_src.clkr.hw,
4669 },
4670 .num_parents = 1,
4671 .flags = CLK_SET_RATE_PARENT,
4672 .ops = &clk_branch2_ops,
4673 },
4674 },
4675};
4676
4677static struct clk_branch gcc_qupv3_wrap1_s4_clk = {
4678 .halt_reg = 0x184f4,
4679 .halt_check = BRANCH_HALT_VOTED,
4680 .clkr = {
4681 .enable_reg = 0x52008,
4682 .enable_mask = BIT(26),
4683 .hw.init = &(const struct clk_init_data) {
4684 .name = "gcc_qupv3_wrap1_s4_clk",
4685 .parent_hws = (const struct clk_hw*[]) {
4686 &gcc_qupv3_wrap1_s4_clk_src.clkr.hw,
4687 },
4688 .num_parents = 1,
4689 .flags = CLK_SET_RATE_PARENT,
4690 .ops = &clk_branch2_ops,
4691 },
4692 },
4693};
4694
4695static struct clk_branch gcc_qupv3_wrap1_s5_clk = {
4696 .halt_reg = 0x1862c,
4697 .halt_check = BRANCH_HALT_VOTED,
4698 .clkr = {
4699 .enable_reg = 0x52008,
4700 .enable_mask = BIT(27),
4701 .hw.init = &(const struct clk_init_data) {
4702 .name = "gcc_qupv3_wrap1_s5_clk",
4703 .parent_hws = (const struct clk_hw*[]) {
4704 &gcc_qupv3_wrap1_s5_clk_src.clkr.hw,
4705 },
4706 .num_parents = 1,
4707 .flags = CLK_SET_RATE_PARENT,
4708 .ops = &clk_branch2_ops,
4709 },
4710 },
4711};
4712
4713static struct clk_branch gcc_qupv3_wrap1_s6_clk = {
4714 .halt_reg = 0x18764,
4715 .halt_check = BRANCH_HALT_VOTED,
4716 .clkr = {
4717 .enable_reg = 0x52008,
4718 .enable_mask = BIT(28),
4719 .hw.init = &(const struct clk_init_data) {
4720 .name = "gcc_qupv3_wrap1_s6_clk",
4721 .parent_hws = (const struct clk_hw*[]) {
4722 &gcc_qupv3_wrap1_s6_clk_src.clkr.hw,
4723 },
4724 .num_parents = 1,
4725 .flags = CLK_SET_RATE_PARENT,
4726 .ops = &clk_branch2_ops,
4727 },
4728 },
4729};
4730
4731static struct clk_branch gcc_qupv3_wrap1_s7_clk = {
4732 .halt_reg = 0x1889c,
4733 .halt_check = BRANCH_HALT_VOTED,
4734 .clkr = {
4735 .enable_reg = 0x52010,
4736 .enable_mask = BIT(16),
4737 .hw.init = &(const struct clk_init_data) {
4738 .name = "gcc_qupv3_wrap1_s7_clk",
4739 .parent_hws = (const struct clk_hw*[]) {
4740 &gcc_qupv3_wrap1_s7_clk_src.clkr.hw,
4741 },
4742 .num_parents = 1,
4743 .flags = CLK_SET_RATE_PARENT,
4744 .ops = &clk_branch2_ops,
4745 },
4746 },
4747};
4748
4749static struct clk_branch gcc_qupv3_wrap2_core_2x_clk = {
4750 .halt_reg = 0x232b8,
4751 .halt_check = BRANCH_HALT_VOTED,
4752 .clkr = {
4753 .enable_reg = 0x52010,
4754 .enable_mask = BIT(3),
4755 .hw.init = &(const struct clk_init_data) {
4756 .name = "gcc_qupv3_wrap2_core_2x_clk",
4757 .ops = &clk_branch2_ops,
4758 },
4759 },
4760};
4761
4762static struct clk_branch gcc_qupv3_wrap2_core_clk = {
4763 .halt_reg = 0x232a8,
4764 .halt_check = BRANCH_HALT_VOTED,
4765 .clkr = {
4766 .enable_reg = 0x52010,
4767 .enable_mask = BIT(0),
4768 .hw.init = &(const struct clk_init_data) {
4769 .name = "gcc_qupv3_wrap2_core_clk",
4770 .ops = &clk_branch2_ops,
4771 },
4772 },
4773};
4774
4775static struct clk_branch gcc_qupv3_wrap2_qspi_s2_clk = {
4776 .halt_reg = 0x1e280,
4777 .halt_check = BRANCH_HALT_VOTED,
4778 .clkr = {
4779 .enable_reg = 0x52028,
4780 .enable_mask = BIT(6),
4781 .hw.init = &(const struct clk_init_data) {
4782 .name = "gcc_qupv3_wrap2_qspi_s2_clk",
4783 .parent_hws = (const struct clk_hw*[]) {
4784 &gcc_qupv3_wrap2_s2_clk_src.clkr.hw,
4785 },
4786 .num_parents = 1,
4787 .flags = CLK_SET_RATE_PARENT,
4788 .ops = &clk_branch2_ops,
4789 },
4790 },
4791};
4792
4793static struct clk_branch gcc_qupv3_wrap2_qspi_s3_clk = {
4794 .halt_reg = 0x1e3c0,
4795 .halt_check = BRANCH_HALT_VOTED,
4796 .clkr = {
4797 .enable_reg = 0x52028,
4798 .enable_mask = BIT(7),
4799 .hw.init = &(const struct clk_init_data) {
4800 .name = "gcc_qupv3_wrap2_qspi_s3_clk",
4801 .parent_hws = (const struct clk_hw*[]) {
4802 &gcc_qupv3_wrap2_s3_clk_src.clkr.hw,
4803 },
4804 .num_parents = 1,
4805 .flags = CLK_SET_RATE_PARENT,
4806 .ops = &clk_branch2_ops,
4807 },
4808 },
4809};
4810
4811static struct clk_branch gcc_qupv3_wrap2_s0_clk = {
4812 .halt_reg = 0x1e004,
4813 .halt_check = BRANCH_HALT_VOTED,
4814 .clkr = {
4815 .enable_reg = 0x52010,
4816 .enable_mask = BIT(4),
4817 .hw.init = &(const struct clk_init_data) {
4818 .name = "gcc_qupv3_wrap2_s0_clk",
4819 .parent_hws = (const struct clk_hw*[]) {
4820 &gcc_qupv3_wrap2_s0_clk_src.clkr.hw,
4821 },
4822 .num_parents = 1,
4823 .flags = CLK_SET_RATE_PARENT,
4824 .ops = &clk_branch2_ops,
4825 },
4826 },
4827};
4828
4829static struct clk_branch gcc_qupv3_wrap2_s1_clk = {
4830 .halt_reg = 0x1e13c,
4831 .halt_check = BRANCH_HALT_VOTED,
4832 .clkr = {
4833 .enable_reg = 0x52010,
4834 .enable_mask = BIT(5),
4835 .hw.init = &(const struct clk_init_data) {
4836 .name = "gcc_qupv3_wrap2_s1_clk",
4837 .parent_hws = (const struct clk_hw*[]) {
4838 &gcc_qupv3_wrap2_s1_clk_src.clkr.hw,
4839 },
4840 .num_parents = 1,
4841 .flags = CLK_SET_RATE_PARENT,
4842 .ops = &clk_branch2_ops,
4843 },
4844 },
4845};
4846
4847static struct clk_branch gcc_qupv3_wrap2_s2_clk = {
4848 .halt_reg = 0x1e274,
4849 .halt_check = BRANCH_HALT_VOTED,
4850 .clkr = {
4851 .enable_reg = 0x52010,
4852 .enable_mask = BIT(6),
4853 .hw.init = &(const struct clk_init_data) {
4854 .name = "gcc_qupv3_wrap2_s2_clk",
4855 .parent_hws = (const struct clk_hw*[]) {
4856 &gcc_qupv3_wrap2_s2_div_clk_src.clkr.hw,
4857 },
4858 .num_parents = 1,
4859 .flags = CLK_SET_RATE_PARENT,
4860 .ops = &clk_branch2_ops,
4861 },
4862 },
4863};
4864
4865static struct clk_branch gcc_qupv3_wrap2_s3_clk = {
4866 .halt_reg = 0x1e3b4,
4867 .halt_check = BRANCH_HALT_VOTED,
4868 .clkr = {
4869 .enable_reg = 0x52010,
4870 .enable_mask = BIT(7),
4871 .hw.init = &(const struct clk_init_data) {
4872 .name = "gcc_qupv3_wrap2_s3_clk",
4873 .parent_hws = (const struct clk_hw*[]) {
4874 &gcc_qupv3_wrap2_s3_div_clk_src.clkr.hw,
4875 },
4876 .num_parents = 1,
4877 .flags = CLK_SET_RATE_PARENT,
4878 .ops = &clk_branch2_ops,
4879 },
4880 },
4881};
4882
4883static struct clk_branch gcc_qupv3_wrap2_s4_clk = {
4884 .halt_reg = 0x1e4f4,
4885 .halt_check = BRANCH_HALT_VOTED,
4886 .clkr = {
4887 .enable_reg = 0x52010,
4888 .enable_mask = BIT(8),
4889 .hw.init = &(const struct clk_init_data) {
4890 .name = "gcc_qupv3_wrap2_s4_clk",
4891 .parent_hws = (const struct clk_hw*[]) {
4892 &gcc_qupv3_wrap2_s4_clk_src.clkr.hw,
4893 },
4894 .num_parents = 1,
4895 .flags = CLK_SET_RATE_PARENT,
4896 .ops = &clk_branch2_ops,
4897 },
4898 },
4899};
4900
4901static struct clk_branch gcc_qupv3_wrap2_s5_clk = {
4902 .halt_reg = 0x1e62c,
4903 .halt_check = BRANCH_HALT_VOTED,
4904 .clkr = {
4905 .enable_reg = 0x52010,
4906 .enable_mask = BIT(9),
4907 .hw.init = &(const struct clk_init_data) {
4908 .name = "gcc_qupv3_wrap2_s5_clk",
4909 .parent_hws = (const struct clk_hw*[]) {
4910 &gcc_qupv3_wrap2_s5_clk_src.clkr.hw,
4911 },
4912 .num_parents = 1,
4913 .flags = CLK_SET_RATE_PARENT,
4914 .ops = &clk_branch2_ops,
4915 },
4916 },
4917};
4918
4919static struct clk_branch gcc_qupv3_wrap2_s6_clk = {
4920 .halt_reg = 0x1e764,
4921 .halt_check = BRANCH_HALT_VOTED,
4922 .clkr = {
4923 .enable_reg = 0x52010,
4924 .enable_mask = BIT(10),
4925 .hw.init = &(const struct clk_init_data) {
4926 .name = "gcc_qupv3_wrap2_s6_clk",
4927 .parent_hws = (const struct clk_hw*[]) {
4928 &gcc_qupv3_wrap2_s6_clk_src.clkr.hw,
4929 },
4930 .num_parents = 1,
4931 .flags = CLK_SET_RATE_PARENT,
4932 .ops = &clk_branch2_ops,
4933 },
4934 },
4935};
4936
4937static struct clk_branch gcc_qupv3_wrap2_s7_clk = {
4938 .halt_reg = 0x1e89c,
4939 .halt_check = BRANCH_HALT_VOTED,
4940 .clkr = {
4941 .enable_reg = 0x52010,
4942 .enable_mask = BIT(17),
4943 .hw.init = &(const struct clk_init_data) {
4944 .name = "gcc_qupv3_wrap2_s7_clk",
4945 .parent_hws = (const struct clk_hw*[]) {
4946 &gcc_qupv3_wrap2_s7_clk_src.clkr.hw,
4947 },
4948 .num_parents = 1,
4949 .flags = CLK_SET_RATE_PARENT,
4950 .ops = &clk_branch2_ops,
4951 },
4952 },
4953};
4954
4955static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = {
4956 .halt_reg = 0x23000,
4957 .halt_check = BRANCH_HALT_VOTED,
4958 .hwcg_reg = 0x23000,
4959 .hwcg_bit = 1,
4960 .clkr = {
4961 .enable_reg = 0x52020,
4962 .enable_mask = BIT(6),
4963 .hw.init = &(const struct clk_init_data) {
4964 .name = "gcc_qupv3_wrap_0_m_ahb_clk",
4965 .ops = &clk_branch2_ops,
4966 },
4967 },
4968};
4969
4970static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {
4971 .halt_reg = 0x23004,
4972 .halt_check = BRANCH_HALT_VOTED,
4973 .hwcg_reg = 0x23004,
4974 .hwcg_bit = 1,
4975 .clkr = {
4976 .enable_reg = 0x52020,
4977 .enable_mask = BIT(7),
4978 .hw.init = &(const struct clk_init_data) {
4979 .name = "gcc_qupv3_wrap_0_s_ahb_clk",
4980 .ops = &clk_branch2_ops,
4981 },
4982 },
4983};
4984
4985static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = {
4986 .halt_reg = 0x23150,
4987 .halt_check = BRANCH_HALT_VOTED,
4988 .hwcg_reg = 0x23150,
4989 .hwcg_bit = 1,
4990 .clkr = {
4991 .enable_reg = 0x52008,
4992 .enable_mask = BIT(20),
4993 .hw.init = &(const struct clk_init_data) {
4994 .name = "gcc_qupv3_wrap_1_m_ahb_clk",
4995 .ops = &clk_branch2_ops,
4996 },
4997 },
4998};
4999
5000static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = {
5001 .halt_reg = 0x23154,
5002 .halt_check = BRANCH_HALT_VOTED,
5003 .hwcg_reg = 0x23154,
5004 .hwcg_bit = 1,
5005 .clkr = {
5006 .enable_reg = 0x52008,
5007 .enable_mask = BIT(21),
5008 .hw.init = &(const struct clk_init_data) {
5009 .name = "gcc_qupv3_wrap_1_s_ahb_clk",
5010 .ops = &clk_branch2_ops,
5011 },
5012 },
5013};
5014
5015static struct clk_branch gcc_qupv3_wrap_2_m_ahb_clk = {
5016 .halt_reg = 0x232a0,
5017 .halt_check = BRANCH_HALT_VOTED,
5018 .hwcg_reg = 0x232a0,
5019 .hwcg_bit = 1,
5020 .clkr = {
5021 .enable_reg = 0x52010,
5022 .enable_mask = BIT(2),
5023 .hw.init = &(const struct clk_init_data) {
5024 .name = "gcc_qupv3_wrap_2_m_ahb_clk",
5025 .ops = &clk_branch2_ops,
5026 },
5027 },
5028};
5029
5030static struct clk_branch gcc_qupv3_wrap_2_s_ahb_clk = {
5031 .halt_reg = 0x232a4,
5032 .halt_check = BRANCH_HALT_VOTED,
5033 .hwcg_reg = 0x232a4,
5034 .hwcg_bit = 1,
5035 .clkr = {
5036 .enable_reg = 0x52010,
5037 .enable_mask = BIT(1),
5038 .hw.init = &(const struct clk_init_data) {
5039 .name = "gcc_qupv3_wrap_2_s_ahb_clk",
5040 .ops = &clk_branch2_ops,
5041 },
5042 },
5043};
5044
5045static struct clk_branch gcc_sdcc2_ahb_clk = {
5046 .halt_reg = 0x14010,
5047 .halt_check = BRANCH_HALT,
5048 .clkr = {
5049 .enable_reg = 0x14010,
5050 .enable_mask = BIT(0),
5051 .hw.init = &(const struct clk_init_data) {
5052 .name = "gcc_sdcc2_ahb_clk",
5053 .ops = &clk_branch2_ops,
5054 },
5055 },
5056};
5057
5058static struct clk_branch gcc_sdcc2_apps_clk = {
5059 .halt_reg = 0x14004,
5060 .halt_check = BRANCH_HALT,
5061 .clkr = {
5062 .enable_reg = 0x14004,
5063 .enable_mask = BIT(0),
5064 .hw.init = &(const struct clk_init_data) {
5065 .name = "gcc_sdcc2_apps_clk",
5066 .parent_hws = (const struct clk_hw*[]) {
5067 &gcc_sdcc2_apps_clk_src.clkr.hw,
5068 },
5069 .num_parents = 1,
5070 .flags = CLK_SET_RATE_PARENT,
5071 .ops = &clk_branch2_ops,
5072 },
5073 },
5074};
5075
5076static struct clk_branch gcc_sdcc4_ahb_clk = {
5077 .halt_reg = 0x16010,
5078 .halt_check = BRANCH_HALT,
5079 .clkr = {
5080 .enable_reg = 0x16010,
5081 .enable_mask = BIT(0),
5082 .hw.init = &(const struct clk_init_data) {
5083 .name = "gcc_sdcc4_ahb_clk",
5084 .ops = &clk_branch2_ops,
5085 },
5086 },
5087};
5088
5089static struct clk_branch gcc_sdcc4_apps_clk = {
5090 .halt_reg = 0x16004,
5091 .halt_check = BRANCH_HALT,
5092 .clkr = {
5093 .enable_reg = 0x16004,
5094 .enable_mask = BIT(0),
5095 .hw.init = &(const struct clk_init_data) {
5096 .name = "gcc_sdcc4_apps_clk",
5097 .parent_hws = (const struct clk_hw*[]) {
5098 &gcc_sdcc4_apps_clk_src.clkr.hw,
5099 },
5100 .num_parents = 1,
5101 .flags = CLK_SET_RATE_PARENT,
5102 .ops = &clk_branch2_ops,
5103 },
5104 },
5105};
5106
5107static struct clk_branch gcc_sys_noc_usb_axi_clk = {
5108 .halt_reg = 0x2d014,
5109 .halt_check = BRANCH_HALT_VOTED,
5110 .hwcg_reg = 0x2d014,
5111 .hwcg_bit = 1,
5112 .clkr = {
5113 .enable_reg = 0x2d014,
5114 .enable_mask = BIT(0),
5115 .hw.init = &(const struct clk_init_data) {
5116 .name = "gcc_sys_noc_usb_axi_clk",
5117 .ops = &clk_branch2_ops,
5118 },
5119 },
5120};
5121
5122static struct clk_branch gcc_ufs_phy_ahb_clk = {
5123 .halt_reg = 0x77024,
5124 .halt_check = BRANCH_HALT_VOTED,
5125 .hwcg_reg = 0x77024,
5126 .hwcg_bit = 1,
5127 .clkr = {
5128 .enable_reg = 0x77024,
5129 .enable_mask = BIT(0),
5130 .hw.init = &(const struct clk_init_data) {
5131 .name = "gcc_ufs_phy_ahb_clk",
5132 .ops = &clk_branch2_ops,
5133 },
5134 },
5135};
5136
5137static struct clk_branch gcc_ufs_phy_axi_clk = {
5138 .halt_reg = 0x77018,
5139 .halt_check = BRANCH_HALT_VOTED,
5140 .hwcg_reg = 0x77018,
5141 .hwcg_bit = 1,
5142 .clkr = {
5143 .enable_reg = 0x77018,
5144 .enable_mask = BIT(0),
5145 .hw.init = &(const struct clk_init_data) {
5146 .name = "gcc_ufs_phy_axi_clk",
5147 .parent_hws = (const struct clk_hw*[]) {
5148 &gcc_ufs_phy_axi_clk_src.clkr.hw,
5149 },
5150 .num_parents = 1,
5151 .flags = CLK_SET_RATE_PARENT,
5152 .ops = &clk_branch2_ops,
5153 },
5154 },
5155};
5156
5157static struct clk_branch gcc_ufs_phy_ice_core_clk = {
5158 .halt_reg = 0x77074,
5159 .halt_check = BRANCH_HALT_VOTED,
5160 .hwcg_reg = 0x77074,
5161 .hwcg_bit = 1,
5162 .clkr = {
5163 .enable_reg = 0x77074,
5164 .enable_mask = BIT(0),
5165 .hw.init = &(const struct clk_init_data) {
5166 .name = "gcc_ufs_phy_ice_core_clk",
5167 .parent_hws = (const struct clk_hw*[]) {
5168 &gcc_ufs_phy_ice_core_clk_src.clkr.hw,
5169 },
5170 .num_parents = 1,
5171 .flags = CLK_SET_RATE_PARENT,
5172 .ops = &clk_branch2_ops,
5173 },
5174 },
5175};
5176
5177static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
5178 .halt_reg = 0x770b0,
5179 .halt_check = BRANCH_HALT_VOTED,
5180 .hwcg_reg = 0x770b0,
5181 .hwcg_bit = 1,
5182 .clkr = {
5183 .enable_reg = 0x770b0,
5184 .enable_mask = BIT(0),
5185 .hw.init = &(const struct clk_init_data) {
5186 .name = "gcc_ufs_phy_phy_aux_clk",
5187 .parent_hws = (const struct clk_hw*[]) {
5188 &gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
5189 },
5190 .num_parents = 1,
5191 .flags = CLK_SET_RATE_PARENT,
5192 .ops = &clk_branch2_ops,
5193 },
5194 },
5195};
5196
5197static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
5198 .halt_reg = 0x7702c,
5199 .halt_check = BRANCH_HALT_DELAY,
5200 .clkr = {
5201 .enable_reg = 0x7702c,
5202 .enable_mask = BIT(0),
5203 .hw.init = &(const struct clk_init_data) {
5204 .name = "gcc_ufs_phy_rx_symbol_0_clk",
5205 .parent_hws = (const struct clk_hw*[]) {
5206 &gcc_ufs_phy_rx_symbol_0_clk_src.clkr.hw,
5207 },
5208 .num_parents = 1,
5209 .flags = CLK_SET_RATE_PARENT,
5210 .ops = &clk_branch2_ops,
5211 },
5212 },
5213};
5214
5215static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = {
5216 .halt_reg = 0x770cc,
5217 .halt_check = BRANCH_HALT_DELAY,
5218 .clkr = {
5219 .enable_reg = 0x770cc,
5220 .enable_mask = BIT(0),
5221 .hw.init = &(const struct clk_init_data) {
5222 .name = "gcc_ufs_phy_rx_symbol_1_clk",
5223 .parent_hws = (const struct clk_hw*[]) {
5224 &gcc_ufs_phy_rx_symbol_1_clk_src.clkr.hw,
5225 },
5226 .num_parents = 1,
5227 .flags = CLK_SET_RATE_PARENT,
5228 .ops = &clk_branch2_ops,
5229 },
5230 },
5231};
5232
5233static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {
5234 .halt_reg = 0x77028,
5235 .halt_check = BRANCH_HALT_DELAY,
5236 .clkr = {
5237 .enable_reg = 0x77028,
5238 .enable_mask = BIT(0),
5239 .hw.init = &(const struct clk_init_data) {
5240 .name = "gcc_ufs_phy_tx_symbol_0_clk",
5241 .parent_hws = (const struct clk_hw*[]) {
5242 &gcc_ufs_phy_tx_symbol_0_clk_src.clkr.hw,
5243 },
5244 .num_parents = 1,
5245 .flags = CLK_SET_RATE_PARENT,
5246 .ops = &clk_branch2_ops,
5247 },
5248 },
5249};
5250
5251static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
5252 .halt_reg = 0x77068,
5253 .halt_check = BRANCH_HALT_VOTED,
5254 .hwcg_reg = 0x77068,
5255 .hwcg_bit = 1,
5256 .clkr = {
5257 .enable_reg = 0x77068,
5258 .enable_mask = BIT(0),
5259 .hw.init = &(const struct clk_init_data) {
5260 .name = "gcc_ufs_phy_unipro_core_clk",
5261 .parent_hws = (const struct clk_hw*[]) {
5262 &gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
5263 },
5264 .num_parents = 1,
5265 .flags = CLK_SET_RATE_PARENT,
5266 .ops = &clk_branch2_ops,
5267 },
5268 },
5269};
5270
5271static struct clk_branch gcc_usb20_master_clk = {
5272 .halt_reg = 0x29018,
5273 .halt_check = BRANCH_HALT,
5274 .clkr = {
5275 .enable_reg = 0x29018,
5276 .enable_mask = BIT(0),
5277 .hw.init = &(const struct clk_init_data) {
5278 .name = "gcc_usb20_master_clk",
5279 .parent_hws = (const struct clk_hw*[]) {
5280 &gcc_usb20_master_clk_src.clkr.hw,
5281 },
5282 .num_parents = 1,
5283 .flags = CLK_SET_RATE_PARENT,
5284 .ops = &clk_branch2_ops,
5285 },
5286 },
5287};
5288
5289static struct clk_branch gcc_usb20_mock_utmi_clk = {
5290 .halt_reg = 0x29028,
5291 .halt_check = BRANCH_HALT,
5292 .clkr = {
5293 .enable_reg = 0x29028,
5294 .enable_mask = BIT(0),
5295 .hw.init = &(const struct clk_init_data) {
5296 .name = "gcc_usb20_mock_utmi_clk",
5297 .parent_hws = (const struct clk_hw*[]) {
5298 &gcc_usb20_mock_utmi_postdiv_clk_src.clkr.hw,
5299 },
5300 .num_parents = 1,
5301 .flags = CLK_SET_RATE_PARENT,
5302 .ops = &clk_branch2_ops,
5303 },
5304 },
5305};
5306
5307static struct clk_branch gcc_usb20_sleep_clk = {
5308 .halt_reg = 0x29024,
5309 .halt_check = BRANCH_HALT,
5310 .clkr = {
5311 .enable_reg = 0x29024,
5312 .enable_mask = BIT(0),
5313 .hw.init = &(const struct clk_init_data) {
5314 .name = "gcc_usb20_sleep_clk",
5315 .ops = &clk_branch2_ops,
5316 },
5317 },
5318};
5319
5320static struct clk_branch gcc_usb30_mp_master_clk = {
5321 .halt_reg = 0x17018,
5322 .halt_check = BRANCH_HALT,
5323 .clkr = {
5324 .enable_reg = 0x17018,
5325 .enable_mask = BIT(0),
5326 .hw.init = &(const struct clk_init_data) {
5327 .name = "gcc_usb30_mp_master_clk",
5328 .parent_hws = (const struct clk_hw*[]) {
5329 &gcc_usb30_mp_master_clk_src.clkr.hw,
5330 },
5331 .num_parents = 1,
5332 .flags = CLK_SET_RATE_PARENT,
5333 .ops = &clk_branch2_ops,
5334 },
5335 },
5336};
5337
5338static struct clk_branch gcc_usb30_mp_mock_utmi_clk = {
5339 .halt_reg = 0x17028,
5340 .halt_check = BRANCH_HALT,
5341 .clkr = {
5342 .enable_reg = 0x17028,
5343 .enable_mask = BIT(0),
5344 .hw.init = &(const struct clk_init_data) {
5345 .name = "gcc_usb30_mp_mock_utmi_clk",
5346 .parent_hws = (const struct clk_hw*[]) {
5347 &gcc_usb30_mp_mock_utmi_postdiv_clk_src.clkr.hw,
5348 },
5349 .num_parents = 1,
5350 .flags = CLK_SET_RATE_PARENT,
5351 .ops = &clk_branch2_ops,
5352 },
5353 },
5354};
5355
5356static struct clk_branch gcc_usb30_mp_sleep_clk = {
5357 .halt_reg = 0x17024,
5358 .halt_check = BRANCH_HALT,
5359 .clkr = {
5360 .enable_reg = 0x17024,
5361 .enable_mask = BIT(0),
5362 .hw.init = &(const struct clk_init_data) {
5363 .name = "gcc_usb30_mp_sleep_clk",
5364 .ops = &clk_branch2_ops,
5365 },
5366 },
5367};
5368
5369static struct clk_branch gcc_usb30_prim_master_clk = {
5370 .halt_reg = 0x39018,
5371 .halt_check = BRANCH_HALT,
5372 .clkr = {
5373 .enable_reg = 0x39018,
5374 .enable_mask = BIT(0),
5375 .hw.init = &(const struct clk_init_data) {
5376 .name = "gcc_usb30_prim_master_clk",
5377 .parent_hws = (const struct clk_hw*[]) {
5378 &gcc_usb30_prim_master_clk_src.clkr.hw,
5379 },
5380 .num_parents = 1,
5381 .flags = CLK_SET_RATE_PARENT,
5382 .ops = &clk_branch2_ops,
5383 },
5384 },
5385};
5386
5387static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
5388 .halt_reg = 0x39028,
5389 .halt_check = BRANCH_HALT,
5390 .clkr = {
5391 .enable_reg = 0x39028,
5392 .enable_mask = BIT(0),
5393 .hw.init = &(const struct clk_init_data) {
5394 .name = "gcc_usb30_prim_mock_utmi_clk",
5395 .parent_hws = (const struct clk_hw*[]) {
5396 &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw,
5397 },
5398 .num_parents = 1,
5399 .flags = CLK_SET_RATE_PARENT,
5400 .ops = &clk_branch2_ops,
5401 },
5402 },
5403};
5404
5405static struct clk_branch gcc_usb30_prim_sleep_clk = {
5406 .halt_reg = 0x39024,
5407 .halt_check = BRANCH_HALT,
5408 .clkr = {
5409 .enable_reg = 0x39024,
5410 .enable_mask = BIT(0),
5411 .hw.init = &(const struct clk_init_data) {
5412 .name = "gcc_usb30_prim_sleep_clk",
5413 .ops = &clk_branch2_ops,
5414 },
5415 },
5416};
5417
5418static struct clk_branch gcc_usb30_sec_master_clk = {
5419 .halt_reg = 0xa1018,
5420 .halt_check = BRANCH_HALT,
5421 .clkr = {
5422 .enable_reg = 0xa1018,
5423 .enable_mask = BIT(0),
5424 .hw.init = &(const struct clk_init_data) {
5425 .name = "gcc_usb30_sec_master_clk",
5426 .parent_hws = (const struct clk_hw*[]) {
5427 &gcc_usb30_sec_master_clk_src.clkr.hw,
5428 },
5429 .num_parents = 1,
5430 .flags = CLK_SET_RATE_PARENT,
5431 .ops = &clk_branch2_ops,
5432 },
5433 },
5434};
5435
5436static struct clk_branch gcc_usb30_sec_mock_utmi_clk = {
5437 .halt_reg = 0xa1028,
5438 .halt_check = BRANCH_HALT,
5439 .clkr = {
5440 .enable_reg = 0xa1028,
5441 .enable_mask = BIT(0),
5442 .hw.init = &(const struct clk_init_data) {
5443 .name = "gcc_usb30_sec_mock_utmi_clk",
5444 .parent_hws = (const struct clk_hw*[]) {
5445 &gcc_usb30_sec_mock_utmi_postdiv_clk_src.clkr.hw,
5446 },
5447 .num_parents = 1,
5448 .flags = CLK_SET_RATE_PARENT,
5449 .ops = &clk_branch2_ops,
5450 },
5451 },
5452};
5453
5454static struct clk_branch gcc_usb30_sec_sleep_clk = {
5455 .halt_reg = 0xa1024,
5456 .halt_check = BRANCH_HALT,
5457 .clkr = {
5458 .enable_reg = 0xa1024,
5459 .enable_mask = BIT(0),
5460 .hw.init = &(const struct clk_init_data) {
5461 .name = "gcc_usb30_sec_sleep_clk",
5462 .ops = &clk_branch2_ops,
5463 },
5464 },
5465};
5466
5467static struct clk_branch gcc_usb30_tert_master_clk = {
5468 .halt_reg = 0xa2018,
5469 .halt_check = BRANCH_HALT,
5470 .clkr = {
5471 .enable_reg = 0xa2018,
5472 .enable_mask = BIT(0),
5473 .hw.init = &(const struct clk_init_data) {
5474 .name = "gcc_usb30_tert_master_clk",
5475 .parent_hws = (const struct clk_hw*[]) {
5476 &gcc_usb30_tert_master_clk_src.clkr.hw,
5477 },
5478 .num_parents = 1,
5479 .flags = CLK_SET_RATE_PARENT,
5480 .ops = &clk_branch2_ops,
5481 },
5482 },
5483};
5484
5485static struct clk_branch gcc_usb30_tert_mock_utmi_clk = {
5486 .halt_reg = 0xa2028,
5487 .halt_check = BRANCH_HALT,
5488 .clkr = {
5489 .enable_reg = 0xa2028,
5490 .enable_mask = BIT(0),
5491 .hw.init = &(const struct clk_init_data) {
5492 .name = "gcc_usb30_tert_mock_utmi_clk",
5493 .parent_hws = (const struct clk_hw*[]) {
5494 &gcc_usb30_tert_mock_utmi_postdiv_clk_src.clkr.hw,
5495 },
5496 .num_parents = 1,
5497 .flags = CLK_SET_RATE_PARENT,
5498 .ops = &clk_branch2_ops,
5499 },
5500 },
5501};
5502
5503static struct clk_branch gcc_usb30_tert_sleep_clk = {
5504 .halt_reg = 0xa2024,
5505 .halt_check = BRANCH_HALT,
5506 .clkr = {
5507 .enable_reg = 0xa2024,
5508 .enable_mask = BIT(0),
5509 .hw.init = &(const struct clk_init_data) {
5510 .name = "gcc_usb30_tert_sleep_clk",
5511 .ops = &clk_branch2_ops,
5512 },
5513 },
5514};
5515
5516static struct clk_branch gcc_usb3_mp_phy_aux_clk = {
5517 .halt_reg = 0x17288,
5518 .halt_check = BRANCH_HALT,
5519 .clkr = {
5520 .enable_reg = 0x17288,
5521 .enable_mask = BIT(0),
5522 .hw.init = &(const struct clk_init_data) {
5523 .name = "gcc_usb3_mp_phy_aux_clk",
5524 .parent_hws = (const struct clk_hw*[]) {
5525 &gcc_usb3_mp_phy_aux_clk_src.clkr.hw,
5526 },
5527 .num_parents = 1,
5528 .flags = CLK_SET_RATE_PARENT,
5529 .ops = &clk_branch2_ops,
5530 },
5531 },
5532};
5533
5534static struct clk_branch gcc_usb3_mp_phy_com_aux_clk = {
5535 .halt_reg = 0x1728c,
5536 .halt_check = BRANCH_HALT,
5537 .clkr = {
5538 .enable_reg = 0x1728c,
5539 .enable_mask = BIT(0),
5540 .hw.init = &(const struct clk_init_data) {
5541 .name = "gcc_usb3_mp_phy_com_aux_clk",
5542 .parent_hws = (const struct clk_hw*[]) {
5543 &gcc_usb3_mp_phy_aux_clk_src.clkr.hw,
5544 },
5545 .num_parents = 1,
5546 .flags = CLK_SET_RATE_PARENT,
5547 .ops = &clk_branch2_ops,
5548 },
5549 },
5550};
5551
5552static struct clk_branch gcc_usb3_mp_phy_pipe_0_clk = {
5553 .halt_reg = 0x17290,
5554 .halt_check = BRANCH_HALT_SKIP,
5555 .clkr = {
5556 .enable_reg = 0x17290,
5557 .enable_mask = BIT(0),
5558 .hw.init = &(const struct clk_init_data) {
5559 .name = "gcc_usb3_mp_phy_pipe_0_clk",
5560 .ops = &clk_branch2_ops,
5561 },
5562 },
5563};
5564
5565static struct clk_branch gcc_usb3_mp_phy_pipe_1_clk = {
5566 .halt_reg = 0x17298,
5567 .halt_check = BRANCH_HALT_SKIP,
5568 .clkr = {
5569 .enable_reg = 0x17298,
5570 .enable_mask = BIT(0),
5571 .hw.init = &(const struct clk_init_data) {
5572 .name = "gcc_usb3_mp_phy_pipe_1_clk",
5573 .ops = &clk_branch2_ops,
5574 },
5575 },
5576};
5577
5578static struct clk_branch gcc_usb3_prim_phy_aux_clk = {
5579 .halt_reg = 0x39060,
5580 .halt_check = BRANCH_HALT,
5581 .clkr = {
5582 .enable_reg = 0x39060,
5583 .enable_mask = BIT(0),
5584 .hw.init = &(const struct clk_init_data) {
5585 .name = "gcc_usb3_prim_phy_aux_clk",
5586 .parent_hws = (const struct clk_hw*[]) {
5587 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
5588 },
5589 .num_parents = 1,
5590 .flags = CLK_SET_RATE_PARENT,
5591 .ops = &clk_branch2_ops,
5592 },
5593 },
5594};
5595
5596static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
5597 .halt_reg = 0x39064,
5598 .halt_check = BRANCH_HALT,
5599 .clkr = {
5600 .enable_reg = 0x39064,
5601 .enable_mask = BIT(0),
5602 .hw.init = &(const struct clk_init_data) {
5603 .name = "gcc_usb3_prim_phy_com_aux_clk",
5604 .parent_hws = (const struct clk_hw*[]) {
5605 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
5606 },
5607 .num_parents = 1,
5608 .flags = CLK_SET_RATE_PARENT,
5609 .ops = &clk_branch2_ops,
5610 },
5611 },
5612};
5613
5614static struct clk_regmap_mux gcc_usb3_prim_phy_pipe_clk_src = {
5615 .reg = 0x3906c,
5616 .shift = 0,
5617 .width = 2,
5618 .parent_map = gcc_parent_map_10,
5619 .clkr = {
5620 .hw.init = &(struct clk_init_data){
5621 .name = "gcc_usb3_prim_phy_pipe_clk_src",
5622 .parent_data = gcc_parent_data_10,
5623 .num_parents = ARRAY_SIZE(gcc_parent_data_10),
5624 .ops = &clk_regmap_mux_closest_ops,
5625 },
5626 },
5627};
5628
5629static const struct parent_map gcc_parent_map_34[] = {
5630 { P_GCC_USB3_PRIM_PHY_PIPE_CLK_SRC, 0 },
5631 { P_USB4_0_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 1 },
5632 { P_GCC_USB4_0_PHY_PIPEGMUX_CLK_SRC, 3 },
5633};
5634
5635static const struct clk_parent_data gcc_parent_data_34[] = {
5636 { .hw = &gcc_usb3_prim_phy_pipe_clk_src.clkr.hw },
5637 { .index = DT_USB4_0_PHY_GCC_USB4RTR_MAX_PIPE_CLK },
5638 { .index = DT_GCC_USB4_0_PHY_PIPEGMUX_CLK_SRC },
5639};
5640
5641static struct clk_regmap_mux gcc_usb34_prim_phy_pipe_clk_src = {
5642 .reg = 0x39070,
5643 .shift = 0,
5644 .width = 2,
5645 .parent_map = gcc_parent_map_34,
5646 .clkr = {
5647 .hw.init = &(const struct clk_init_data) {
5648 .name = "gcc_usb34_prim_phy_pipe_clk_src",
5649 .parent_data = gcc_parent_data_34,
5650 .num_parents = ARRAY_SIZE(gcc_parent_data_34),
5651 .ops = &clk_regmap_mux_closest_ops,
5652 },
5653 },
5654};
5655
5656static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
5657 .halt_reg = 0x39068,
5658 .halt_check = BRANCH_HALT_SKIP,
5659 .hwcg_reg = 0x39068,
5660 .hwcg_bit = 1,
5661 .clkr = {
5662 .enable_reg = 0x39068,
5663 .enable_mask = BIT(0),
5664 .hw.init = &(const struct clk_init_data) {
5665 .name = "gcc_usb3_prim_phy_pipe_clk",
5666 .parent_hws = (const struct clk_hw*[]) {
5667 &gcc_usb34_prim_phy_pipe_clk_src.clkr.hw,
5668 },
5669 .num_parents = 1,
5670 .flags = CLK_SET_RATE_PARENT,
5671 .ops = &clk_branch2_ops,
5672 },
5673 },
5674};
5675
5676static struct clk_branch gcc_usb3_sec_phy_aux_clk = {
5677 .halt_reg = 0xa1060,
5678 .halt_check = BRANCH_HALT,
5679 .clkr = {
5680 .enable_reg = 0xa1060,
5681 .enable_mask = BIT(0),
5682 .hw.init = &(const struct clk_init_data) {
5683 .name = "gcc_usb3_sec_phy_aux_clk",
5684 .parent_hws = (const struct clk_hw*[]) {
5685 &gcc_usb3_sec_phy_aux_clk_src.clkr.hw,
5686 },
5687 .num_parents = 1,
5688 .flags = CLK_SET_RATE_PARENT,
5689 .ops = &clk_branch2_ops,
5690 },
5691 },
5692};
5693
5694static struct clk_branch gcc_usb3_sec_phy_com_aux_clk = {
5695 .halt_reg = 0xa1064,
5696 .halt_check = BRANCH_HALT,
5697 .clkr = {
5698 .enable_reg = 0xa1064,
5699 .enable_mask = BIT(0),
5700 .hw.init = &(const struct clk_init_data) {
5701 .name = "gcc_usb3_sec_phy_com_aux_clk",
5702 .parent_hws = (const struct clk_hw*[]) {
5703 &gcc_usb3_sec_phy_aux_clk_src.clkr.hw,
5704 },
5705 .num_parents = 1,
5706 .flags = CLK_SET_RATE_PARENT,
5707 .ops = &clk_branch2_ops,
5708 },
5709 },
5710};
5711
5712static struct clk_regmap_mux gcc_usb3_sec_phy_pipe_clk_src = {
5713 .reg = 0xa106c,
5714 .shift = 0,
5715 .width = 2,
5716 .parent_map = gcc_parent_map_11,
5717 .clkr = {
5718 .hw.init = &(struct clk_init_data){
5719 .name = "gcc_usb3_sec_phy_pipe_clk_src",
5720 .parent_data = gcc_parent_data_11,
5721 .num_parents = ARRAY_SIZE(gcc_parent_data_11),
5722 .ops = &clk_regmap_mux_closest_ops,
5723 },
5724 },
5725};
5726
5727static const struct parent_map gcc_parent_map_35[] = {
5728 { P_GCC_USB3_SEC_PHY_PIPE_CLK_SRC, 0 },
5729 { P_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 1 },
5730 { P_GCC_USB4_1_PHY_PIPEGMUX_CLK_SRC, 3 },
5731};
5732
5733static const struct clk_parent_data gcc_parent_data_35[] = {
5734 { .hw = &gcc_usb3_sec_phy_pipe_clk_src.clkr.hw },
5735 { .index = DT_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK },
5736 { .index = DT_GCC_USB4_1_PHY_PIPEGMUX_CLK_SRC },
5737};
5738
5739static struct clk_regmap_mux gcc_usb34_sec_phy_pipe_clk_src = {
5740 .reg = 0xa1070,
5741 .shift = 0,
5742 .width = 2,
5743 .parent_map = gcc_parent_map_35,
5744 .clkr = {
5745 .hw.init = &(const struct clk_init_data) {
5746 .name = "gcc_usb34_sec_phy_pipe_clk_src",
5747 .parent_data = gcc_parent_data_35,
5748 .num_parents = ARRAY_SIZE(gcc_parent_data_35),
5749 .ops = &clk_regmap_mux_closest_ops,
5750 },
5751 },
5752};
5753
5754static struct clk_branch gcc_usb3_sec_phy_pipe_clk = {
5755 .halt_reg = 0xa1068,
5756 .halt_check = BRANCH_HALT_SKIP,
5757 .hwcg_reg = 0xa1068,
5758 .hwcg_bit = 1,
5759 .clkr = {
5760 .enable_reg = 0xa1068,
5761 .enable_mask = BIT(0),
5762 .hw.init = &(const struct clk_init_data) {
5763 .name = "gcc_usb3_sec_phy_pipe_clk",
5764 .parent_hws = (const struct clk_hw*[]) {
5765 &gcc_usb34_sec_phy_pipe_clk_src.clkr.hw,
5766 },
5767 .num_parents = 1,
5768 .flags = CLK_SET_RATE_PARENT,
5769 .ops = &clk_branch2_ops,
5770 },
5771 },
5772};
5773
5774static struct clk_branch gcc_usb3_tert_phy_aux_clk = {
5775 .halt_reg = 0xa2060,
5776 .halt_check = BRANCH_HALT,
5777 .clkr = {
5778 .enable_reg = 0xa2060,
5779 .enable_mask = BIT(0),
5780 .hw.init = &(const struct clk_init_data) {
5781 .name = "gcc_usb3_tert_phy_aux_clk",
5782 .parent_hws = (const struct clk_hw*[]) {
5783 &gcc_usb3_tert_phy_aux_clk_src.clkr.hw,
5784 },
5785 .num_parents = 1,
5786 .flags = CLK_SET_RATE_PARENT,
5787 .ops = &clk_branch2_ops,
5788 },
5789 },
5790};
5791
5792static struct clk_branch gcc_usb3_tert_phy_com_aux_clk = {
5793 .halt_reg = 0xa2064,
5794 .halt_check = BRANCH_HALT,
5795 .clkr = {
5796 .enable_reg = 0xa2064,
5797 .enable_mask = BIT(0),
5798 .hw.init = &(const struct clk_init_data) {
5799 .name = "gcc_usb3_tert_phy_com_aux_clk",
5800 .parent_hws = (const struct clk_hw*[]) {
5801 &gcc_usb3_tert_phy_aux_clk_src.clkr.hw,
5802 },
5803 .num_parents = 1,
5804 .flags = CLK_SET_RATE_PARENT,
5805 .ops = &clk_branch2_ops,
5806 },
5807 },
5808};
5809
5810static struct clk_regmap_mux gcc_usb3_tert_phy_pipe_clk_src = {
5811 .reg = 0xa206c,
5812 .shift = 0,
5813 .width = 2,
5814 .parent_map = gcc_parent_map_12,
5815 .clkr = {
5816 .hw.init = &(struct clk_init_data){
5817 .name = "gcc_usb3_tert_phy_pipe_clk_src",
5818 .parent_data = gcc_parent_data_12,
5819 .num_parents = ARRAY_SIZE(gcc_parent_data_12),
5820 .ops = &clk_regmap_mux_closest_ops,
5821 },
5822 },
5823};
5824
5825static const struct parent_map gcc_parent_map_36[] = {
5826 { P_GCC_USB3_TERT_PHY_PIPE_CLK_SRC, 0 },
5827 { P_USB4_2_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 1 },
5828 { P_GCC_USB4_2_PHY_PIPEGMUX_CLK_SRC, 3 },
5829};
5830
5831static const struct clk_parent_data gcc_parent_data_36[] = {
5832 { .hw = &gcc_usb3_tert_phy_pipe_clk_src.clkr.hw },
5833 { .index = DT_USB4_2_PHY_GCC_USB4RTR_MAX_PIPE_CLK },
5834 { .index = DT_GCC_USB4_2_PHY_PIPEGMUX_CLK_SRC },
5835};
5836
5837static struct clk_regmap_mux gcc_usb34_tert_phy_pipe_clk_src = {
5838 .reg = 0xa2070,
5839 .shift = 0,
5840 .width = 2,
5841 .parent_map = gcc_parent_map_36,
5842 .clkr = {
5843 .hw.init = &(const struct clk_init_data) {
5844 .name = "gcc_usb34_tert_phy_pipe_clk_src",
5845 .parent_data = gcc_parent_data_36,
5846 .num_parents = ARRAY_SIZE(gcc_parent_data_36),
5847 .ops = &clk_regmap_mux_closest_ops,
5848 },
5849 },
5850};
5851
5852static struct clk_branch gcc_usb3_tert_phy_pipe_clk = {
5853 .halt_reg = 0xa2068,
5854 .halt_check = BRANCH_HALT_SKIP,
5855 .hwcg_reg = 0xa2068,
5856 .hwcg_bit = 1,
5857 .clkr = {
5858 .enable_reg = 0xa2068,
5859 .enable_mask = BIT(0),
5860 .hw.init = &(const struct clk_init_data) {
5861 .name = "gcc_usb3_tert_phy_pipe_clk",
5862 .parent_hws = (const struct clk_hw*[]) {
5863 &gcc_usb34_tert_phy_pipe_clk_src.clkr.hw,
5864 },
5865 .num_parents = 1,
5866 .flags = CLK_SET_RATE_PARENT,
5867 .ops = &clk_branch2_ops,
5868 },
5869 },
5870};
5871
5872static struct clk_branch gcc_usb4_0_cfg_ahb_clk = {
5873 .halt_reg = 0x9f0a8,
5874 .halt_check = BRANCH_HALT_VOTED,
5875 .hwcg_reg = 0x9f0a8,
5876 .hwcg_bit = 1,
5877 .clkr = {
5878 .enable_reg = 0x9f0a8,
5879 .enable_mask = BIT(0),
5880 .hw.init = &(const struct clk_init_data) {
5881 .name = "gcc_usb4_0_cfg_ahb_clk",
5882 .ops = &clk_branch2_ops,
5883 },
5884 },
5885};
5886
5887static struct clk_branch gcc_usb4_0_dp0_clk = {
5888 .halt_reg = 0x9f060,
5889 .halt_check = BRANCH_HALT_SKIP,
5890 .clkr = {
5891 .enable_reg = 0x9f060,
5892 .enable_mask = BIT(0),
5893 .hw.init = &(const struct clk_init_data) {
5894 .name = "gcc_usb4_0_dp0_clk",
5895 .parent_hws = (const struct clk_hw*[]) {
5896 &gcc_usb4_0_phy_dp0_clk_src.clkr.hw,
5897 },
5898 .num_parents = 1,
5899 .flags = CLK_SET_RATE_PARENT,
5900 .ops = &clk_branch2_ops,
5901 },
5902 },
5903};
5904
5905static struct clk_branch gcc_usb4_0_dp1_clk = {
5906 .halt_reg = 0x9f108,
5907 .halt_check = BRANCH_HALT_SKIP,
5908 .clkr = {
5909 .enable_reg = 0x9f108,
5910 .enable_mask = BIT(0),
5911 .hw.init = &(const struct clk_init_data) {
5912 .name = "gcc_usb4_0_dp1_clk",
5913 .parent_hws = (const struct clk_hw*[]) {
5914 &gcc_usb4_0_phy_dp1_clk_src.clkr.hw,
5915 },
5916 .num_parents = 1,
5917 .flags = CLK_SET_RATE_PARENT,
5918 .ops = &clk_branch2_ops,
5919 },
5920 },
5921};
5922
5923static struct clk_branch gcc_usb4_0_master_clk = {
5924 .halt_reg = 0x9f018,
5925 .halt_check = BRANCH_HALT,
5926 .clkr = {
5927 .enable_reg = 0x9f018,
5928 .enable_mask = BIT(0),
5929 .hw.init = &(const struct clk_init_data) {
5930 .name = "gcc_usb4_0_master_clk",
5931 .parent_hws = (const struct clk_hw*[]) {
5932 &gcc_usb4_0_master_clk_src.clkr.hw,
5933 },
5934 .num_parents = 1,
5935 .flags = CLK_SET_RATE_PARENT,
5936 .ops = &clk_branch2_ops,
5937 },
5938 },
5939};
5940
5941static struct clk_branch gcc_usb4_0_phy_p2rr2p_pipe_clk = {
5942 .halt_reg = 0x9f0d8,
5943 .halt_check = BRANCH_HALT_SKIP,
5944 .clkr = {
5945 .enable_reg = 0x9f0d8,
5946 .enable_mask = BIT(0),
5947 .hw.init = &(const struct clk_init_data) {
5948 .name = "gcc_usb4_0_phy_p2rr2p_pipe_clk",
5949 .parent_hws = (const struct clk_hw*[]) {
5950 &gcc_usb4_0_phy_p2rr2p_pipe_clk_src.clkr.hw,
5951 },
5952 .num_parents = 1,
5953 .flags = CLK_SET_RATE_PARENT,
5954 .ops = &clk_branch2_ops,
5955 },
5956 },
5957};
5958
5959static struct clk_branch gcc_usb4_0_phy_pcie_pipe_clk = {
5960 .halt_reg = 0x9f048,
5961 .halt_check = BRANCH_HALT_SKIP,
5962 .clkr = {
5963 .enable_reg = 0x52010,
5964 .enable_mask = BIT(19),
5965 .hw.init = &(const struct clk_init_data) {
5966 .name = "gcc_usb4_0_phy_pcie_pipe_clk",
5967 .parent_hws = (const struct clk_hw*[]) {
5968 &gcc_usb4_0_phy_pcie_pipe_mux_clk_src.clkr.hw,
5969 },
5970 .num_parents = 1,
5971 .flags = CLK_SET_RATE_PARENT,
5972 .ops = &clk_branch2_ops,
5973 },
5974 },
5975};
5976
5977static struct clk_branch gcc_usb4_0_phy_rx0_clk = {
5978 .halt_reg = 0x9f0b0,
5979 .halt_check = BRANCH_HALT_SKIP,
5980 .clkr = {
5981 .enable_reg = 0x9f0b0,
5982 .enable_mask = BIT(0),
5983 .hw.init = &(const struct clk_init_data) {
5984 .name = "gcc_usb4_0_phy_rx0_clk",
5985 .parent_hws = (const struct clk_hw*[]) {
5986 &gcc_usb4_0_phy_rx0_clk_src.clkr.hw,
5987 },
5988 .num_parents = 1,
5989 .flags = CLK_SET_RATE_PARENT,
5990 .ops = &clk_branch2_ops,
5991 },
5992 },
5993};
5994
5995static struct clk_branch gcc_usb4_0_phy_rx1_clk = {
5996 .halt_reg = 0x9f0c0,
5997 .halt_check = BRANCH_HALT_SKIP,
5998 .clkr = {
5999 .enable_reg = 0x9f0c0,
6000 .enable_mask = BIT(0),
6001 .hw.init = &(const struct clk_init_data) {
6002 .name = "gcc_usb4_0_phy_rx1_clk",
6003 .parent_hws = (const struct clk_hw*[]) {
6004 &gcc_usb4_0_phy_rx1_clk_src.clkr.hw,
6005 },
6006 .num_parents = 1,
6007 .flags = CLK_SET_RATE_PARENT,
6008 .ops = &clk_branch2_ops,
6009 },
6010 },
6011};
6012
6013static struct clk_branch gcc_usb4_0_phy_usb_pipe_clk = {
6014 .halt_reg = 0x9f0a4,
6015 .halt_check = BRANCH_HALT_SKIP,
6016 .hwcg_reg = 0x9f0a4,
6017 .hwcg_bit = 1,
6018 .clkr = {
6019 .enable_reg = 0x9f0a4,
6020 .enable_mask = BIT(0),
6021 .hw.init = &(const struct clk_init_data) {
6022 .name = "gcc_usb4_0_phy_usb_pipe_clk",
6023 .parent_hws = (const struct clk_hw*[]) {
6024 &gcc_usb34_prim_phy_pipe_clk_src.clkr.hw,
6025 },
6026 .num_parents = 1,
6027 .flags = CLK_SET_RATE_PARENT,
6028 .ops = &clk_branch2_ops,
6029 },
6030 },
6031};
6032
6033static struct clk_branch gcc_usb4_0_sb_if_clk = {
6034 .halt_reg = 0x9f044,
6035 .halt_check = BRANCH_HALT,
6036 .clkr = {
6037 .enable_reg = 0x9f044,
6038 .enable_mask = BIT(0),
6039 .hw.init = &(const struct clk_init_data) {
6040 .name = "gcc_usb4_0_sb_if_clk",
6041 .parent_hws = (const struct clk_hw*[]) {
6042 &gcc_usb4_0_sb_if_clk_src.clkr.hw,
6043 },
6044 .num_parents = 1,
6045 .flags = CLK_SET_RATE_PARENT,
6046 .ops = &clk_branch2_ops,
6047 },
6048 },
6049};
6050
6051static struct clk_branch gcc_usb4_0_sys_clk = {
6052 .halt_reg = 0x9f054,
6053 .halt_check = BRANCH_HALT,
6054 .clkr = {
6055 .enable_reg = 0x9f054,
6056 .enable_mask = BIT(0),
6057 .hw.init = &(const struct clk_init_data) {
6058 .name = "gcc_usb4_0_sys_clk",
6059 .parent_hws = (const struct clk_hw*[]) {
6060 &gcc_usb4_0_phy_sys_clk_src.clkr.hw,
6061 },
6062 .num_parents = 1,
6063 .flags = CLK_SET_RATE_PARENT,
6064 .ops = &clk_branch2_ops,
6065 },
6066 },
6067};
6068
6069static struct clk_branch gcc_usb4_0_tmu_clk = {
6070 .halt_reg = 0x9f088,
6071 .halt_check = BRANCH_HALT_VOTED,
6072 .hwcg_reg = 0x9f088,
6073 .hwcg_bit = 1,
6074 .clkr = {
6075 .enable_reg = 0x9f088,
6076 .enable_mask = BIT(0),
6077 .hw.init = &(const struct clk_init_data) {
6078 .name = "gcc_usb4_0_tmu_clk",
6079 .parent_hws = (const struct clk_hw*[]) {
6080 &gcc_usb4_0_tmu_clk_src.clkr.hw,
6081 },
6082 .num_parents = 1,
6083 .flags = CLK_SET_RATE_PARENT,
6084 .ops = &clk_branch2_ops,
6085 },
6086 },
6087};
6088
6089static struct clk_branch gcc_usb4_1_cfg_ahb_clk = {
6090 .halt_reg = 0x2b0a8,
6091 .halt_check = BRANCH_HALT_VOTED,
6092 .hwcg_reg = 0x2b0a8,
6093 .hwcg_bit = 1,
6094 .clkr = {
6095 .enable_reg = 0x2b0a8,
6096 .enable_mask = BIT(0),
6097 .hw.init = &(const struct clk_init_data) {
6098 .name = "gcc_usb4_1_cfg_ahb_clk",
6099 .ops = &clk_branch2_ops,
6100 },
6101 },
6102};
6103
6104static struct clk_branch gcc_usb4_1_dp0_clk = {
6105 .halt_reg = 0x2b060,
6106 .halt_check = BRANCH_HALT_SKIP,
6107 .clkr = {
6108 .enable_reg = 0x2b060,
6109 .enable_mask = BIT(0),
6110 .hw.init = &(const struct clk_init_data) {
6111 .name = "gcc_usb4_1_dp0_clk",
6112 .parent_hws = (const struct clk_hw*[]) {
6113 &gcc_usb4_1_phy_dp0_clk_src.clkr.hw,
6114 },
6115 .num_parents = 1,
6116 .flags = CLK_SET_RATE_PARENT,
6117 .ops = &clk_branch2_ops,
6118 },
6119 },
6120};
6121
6122static struct clk_branch gcc_usb4_1_dp1_clk = {
6123 .halt_reg = 0x2b108,
6124 .halt_check = BRANCH_HALT_SKIP,
6125 .clkr = {
6126 .enable_reg = 0x2b108,
6127 .enable_mask = BIT(0),
6128 .hw.init = &(const struct clk_init_data) {
6129 .name = "gcc_usb4_1_dp1_clk",
6130 .parent_hws = (const struct clk_hw*[]) {
6131 &gcc_usb4_1_phy_dp1_clk_src.clkr.hw,
6132 },
6133 .num_parents = 1,
6134 .flags = CLK_SET_RATE_PARENT,
6135 .ops = &clk_branch2_ops,
6136 },
6137 },
6138};
6139
6140static struct clk_branch gcc_usb4_1_master_clk = {
6141 .halt_reg = 0x2b018,
6142 .halt_check = BRANCH_HALT,
6143 .clkr = {
6144 .enable_reg = 0x2b018,
6145 .enable_mask = BIT(0),
6146 .hw.init = &(const struct clk_init_data) {
6147 .name = "gcc_usb4_1_master_clk",
6148 .parent_hws = (const struct clk_hw*[]) {
6149 &gcc_usb4_1_master_clk_src.clkr.hw,
6150 },
6151 .num_parents = 1,
6152 .flags = CLK_SET_RATE_PARENT,
6153 .ops = &clk_branch2_ops,
6154 },
6155 },
6156};
6157
6158static struct clk_branch gcc_usb4_1_phy_p2rr2p_pipe_clk = {
6159 .halt_reg = 0x2b0d8,
6160 .halt_check = BRANCH_HALT_SKIP,
6161 .clkr = {
6162 .enable_reg = 0x2b0d8,
6163 .enable_mask = BIT(0),
6164 .hw.init = &(const struct clk_init_data) {
6165 .name = "gcc_usb4_1_phy_p2rr2p_pipe_clk",
6166 .parent_hws = (const struct clk_hw*[]) {
6167 &gcc_usb4_1_phy_p2rr2p_pipe_clk_src.clkr.hw,
6168 },
6169 .num_parents = 1,
6170 .flags = CLK_SET_RATE_PARENT,
6171 .ops = &clk_branch2_ops,
6172 },
6173 },
6174};
6175
6176static struct clk_branch gcc_usb4_1_phy_pcie_pipe_clk = {
6177 .halt_reg = 0x2b048,
6178 .halt_check = BRANCH_HALT_SKIP,
6179 .clkr = {
6180 .enable_reg = 0x52028,
6181 .enable_mask = BIT(0),
6182 .hw.init = &(const struct clk_init_data) {
6183 .name = "gcc_usb4_1_phy_pcie_pipe_clk",
6184 .parent_hws = (const struct clk_hw*[]) {
6185 &gcc_usb4_1_phy_pcie_pipe_mux_clk_src.clkr.hw,
6186 },
6187 .num_parents = 1,
6188 .flags = CLK_SET_RATE_PARENT,
6189 .ops = &clk_branch2_ops,
6190 },
6191 },
6192};
6193
6194static struct clk_branch gcc_usb4_1_phy_rx0_clk = {
6195 .halt_reg = 0x2b0b0,
6196 .halt_check = BRANCH_HALT_SKIP,
6197 .clkr = {
6198 .enable_reg = 0x2b0b0,
6199 .enable_mask = BIT(0),
6200 .hw.init = &(const struct clk_init_data) {
6201 .name = "gcc_usb4_1_phy_rx0_clk",
6202 .parent_hws = (const struct clk_hw*[]) {
6203 &gcc_usb4_1_phy_rx0_clk_src.clkr.hw,
6204 },
6205 .num_parents = 1,
6206 .flags = CLK_SET_RATE_PARENT,
6207 .ops = &clk_branch2_ops,
6208 },
6209 },
6210};
6211
6212static struct clk_branch gcc_usb4_1_phy_rx1_clk = {
6213 .halt_reg = 0x2b0c0,
6214 .halt_check = BRANCH_HALT_SKIP,
6215 .clkr = {
6216 .enable_reg = 0x2b0c0,
6217 .enable_mask = BIT(0),
6218 .hw.init = &(const struct clk_init_data) {
6219 .name = "gcc_usb4_1_phy_rx1_clk",
6220 .parent_hws = (const struct clk_hw*[]) {
6221 &gcc_usb4_1_phy_rx1_clk_src.clkr.hw,
6222 },
6223 .num_parents = 1,
6224 .flags = CLK_SET_RATE_PARENT,
6225 .ops = &clk_branch2_ops,
6226 },
6227 },
6228};
6229
6230static struct clk_branch gcc_usb4_1_phy_usb_pipe_clk = {
6231 .halt_reg = 0x2b0a4,
6232 .halt_check = BRANCH_HALT_SKIP,
6233 .hwcg_reg = 0x2b0a4,
6234 .hwcg_bit = 1,
6235 .clkr = {
6236 .enable_reg = 0x2b0a4,
6237 .enable_mask = BIT(0),
6238 .hw.init = &(const struct clk_init_data) {
6239 .name = "gcc_usb4_1_phy_usb_pipe_clk",
6240 .parent_hws = (const struct clk_hw*[]) {
6241 &gcc_usb34_sec_phy_pipe_clk_src.clkr.hw,
6242 },
6243 .num_parents = 1,
6244 .flags = CLK_SET_RATE_PARENT,
6245 .ops = &clk_branch2_ops,
6246 },
6247 },
6248};
6249
6250static struct clk_branch gcc_usb4_1_sb_if_clk = {
6251 .halt_reg = 0x2b044,
6252 .halt_check = BRANCH_HALT,
6253 .clkr = {
6254 .enable_reg = 0x2b044,
6255 .enable_mask = BIT(0),
6256 .hw.init = &(const struct clk_init_data) {
6257 .name = "gcc_usb4_1_sb_if_clk",
6258 .parent_hws = (const struct clk_hw*[]) {
6259 &gcc_usb4_1_sb_if_clk_src.clkr.hw,
6260 },
6261 .num_parents = 1,
6262 .flags = CLK_SET_RATE_PARENT,
6263 .ops = &clk_branch2_ops,
6264 },
6265 },
6266};
6267
6268static struct clk_branch gcc_usb4_1_sys_clk = {
6269 .halt_reg = 0x2b054,
6270 .halt_check = BRANCH_HALT,
6271 .clkr = {
6272 .enable_reg = 0x2b054,
6273 .enable_mask = BIT(0),
6274 .hw.init = &(const struct clk_init_data) {
6275 .name = "gcc_usb4_1_sys_clk",
6276 .parent_hws = (const struct clk_hw*[]) {
6277 &gcc_usb4_1_phy_sys_clk_src.clkr.hw,
6278 },
6279 .num_parents = 1,
6280 .flags = CLK_SET_RATE_PARENT,
6281 .ops = &clk_branch2_ops,
6282 },
6283 },
6284};
6285
6286static struct clk_branch gcc_usb4_1_tmu_clk = {
6287 .halt_reg = 0x2b088,
6288 .halt_check = BRANCH_HALT_VOTED,
6289 .hwcg_reg = 0x2b088,
6290 .hwcg_bit = 1,
6291 .clkr = {
6292 .enable_reg = 0x2b088,
6293 .enable_mask = BIT(0),
6294 .hw.init = &(const struct clk_init_data) {
6295 .name = "gcc_usb4_1_tmu_clk",
6296 .parent_hws = (const struct clk_hw*[]) {
6297 &gcc_usb4_1_tmu_clk_src.clkr.hw,
6298 },
6299 .num_parents = 1,
6300 .flags = CLK_SET_RATE_PARENT,
6301 .ops = &clk_branch2_ops,
6302 },
6303 },
6304};
6305
6306static struct clk_branch gcc_usb4_2_cfg_ahb_clk = {
6307 .halt_reg = 0x110a8,
6308 .halt_check = BRANCH_HALT_VOTED,
6309 .hwcg_reg = 0x110a8,
6310 .hwcg_bit = 1,
6311 .clkr = {
6312 .enable_reg = 0x110a8,
6313 .enable_mask = BIT(0),
6314 .hw.init = &(const struct clk_init_data) {
6315 .name = "gcc_usb4_2_cfg_ahb_clk",
6316 .ops = &clk_branch2_ops,
6317 },
6318 },
6319};
6320
6321static struct clk_branch gcc_usb4_2_dp0_clk = {
6322 .halt_reg = 0x11060,
6323 .halt_check = BRANCH_HALT_SKIP,
6324 .clkr = {
6325 .enable_reg = 0x11060,
6326 .enable_mask = BIT(0),
6327 .hw.init = &(const struct clk_init_data) {
6328 .name = "gcc_usb4_2_dp0_clk",
6329 .parent_hws = (const struct clk_hw*[]) {
6330 &gcc_usb4_2_phy_dp0_clk_src.clkr.hw,
6331 },
6332 .num_parents = 1,
6333 .flags = CLK_SET_RATE_PARENT,
6334 .ops = &clk_branch2_ops,
6335 },
6336 },
6337};
6338
6339static struct clk_branch gcc_usb4_2_dp1_clk = {
6340 .halt_reg = 0x11108,
6341 .halt_check = BRANCH_HALT_SKIP,
6342 .clkr = {
6343 .enable_reg = 0x11108,
6344 .enable_mask = BIT(0),
6345 .hw.init = &(const struct clk_init_data) {
6346 .name = "gcc_usb4_2_dp1_clk",
6347 .parent_hws = (const struct clk_hw*[]) {
6348 &gcc_usb4_2_phy_dp1_clk_src.clkr.hw,
6349 },
6350 .num_parents = 1,
6351 .flags = CLK_SET_RATE_PARENT,
6352 .ops = &clk_branch2_ops,
6353 },
6354 },
6355};
6356
6357static struct clk_branch gcc_usb4_2_master_clk = {
6358 .halt_reg = 0x11018,
6359 .halt_check = BRANCH_HALT,
6360 .clkr = {
6361 .enable_reg = 0x11018,
6362 .enable_mask = BIT(0),
6363 .hw.init = &(const struct clk_init_data) {
6364 .name = "gcc_usb4_2_master_clk",
6365 .parent_hws = (const struct clk_hw*[]) {
6366 &gcc_usb4_2_master_clk_src.clkr.hw,
6367 },
6368 .num_parents = 1,
6369 .flags = CLK_SET_RATE_PARENT,
6370 .ops = &clk_branch2_ops,
6371 },
6372 },
6373};
6374
6375static struct clk_branch gcc_usb4_2_phy_p2rr2p_pipe_clk = {
6376 .halt_reg = 0x110d8,
6377 .halt_check = BRANCH_HALT_SKIP,
6378 .clkr = {
6379 .enable_reg = 0x110d8,
6380 .enable_mask = BIT(0),
6381 .hw.init = &(const struct clk_init_data) {
6382 .name = "gcc_usb4_2_phy_p2rr2p_pipe_clk",
6383 .parent_hws = (const struct clk_hw*[]) {
6384 &gcc_usb4_2_phy_p2rr2p_pipe_clk_src.clkr.hw,
6385 },
6386 .num_parents = 1,
6387 .flags = CLK_SET_RATE_PARENT,
6388 .ops = &clk_branch2_ops,
6389 },
6390 },
6391};
6392
6393static struct clk_branch gcc_usb4_2_phy_pcie_pipe_clk = {
6394 .halt_reg = 0x11048,
6395 .halt_check = BRANCH_HALT_SKIP,
6396 .clkr = {
6397 .enable_reg = 0x52028,
6398 .enable_mask = BIT(1),
6399 .hw.init = &(const struct clk_init_data) {
6400 .name = "gcc_usb4_2_phy_pcie_pipe_clk",
6401 .parent_hws = (const struct clk_hw*[]) {
6402 &gcc_usb4_2_phy_pcie_pipe_mux_clk_src.clkr.hw,
6403 },
6404 .num_parents = 1,
6405 .flags = CLK_SET_RATE_PARENT,
6406 .ops = &clk_branch2_ops,
6407 },
6408 },
6409};
6410
6411static struct clk_branch gcc_usb4_2_phy_rx0_clk = {
6412 .halt_reg = 0x110b0,
6413 .halt_check = BRANCH_HALT_SKIP,
6414 .clkr = {
6415 .enable_reg = 0x110b0,
6416 .enable_mask = BIT(0),
6417 .hw.init = &(const struct clk_init_data) {
6418 .name = "gcc_usb4_2_phy_rx0_clk",
6419 .parent_hws = (const struct clk_hw*[]) {
6420 &gcc_usb4_2_phy_rx0_clk_src.clkr.hw,
6421 },
6422 .num_parents = 1,
6423 .flags = CLK_SET_RATE_PARENT,
6424 .ops = &clk_branch2_ops,
6425 },
6426 },
6427};
6428
6429static struct clk_branch gcc_usb4_2_phy_rx1_clk = {
6430 .halt_reg = 0x110c0,
6431 .halt_check = BRANCH_HALT_SKIP,
6432 .clkr = {
6433 .enable_reg = 0x110c0,
6434 .enable_mask = BIT(0),
6435 .hw.init = &(const struct clk_init_data) {
6436 .name = "gcc_usb4_2_phy_rx1_clk",
6437 .parent_hws = (const struct clk_hw*[]) {
6438 &gcc_usb4_2_phy_rx1_clk_src.clkr.hw,
6439 },
6440 .num_parents = 1,
6441 .flags = CLK_SET_RATE_PARENT,
6442 .ops = &clk_branch2_ops,
6443 },
6444 },
6445};
6446
6447static struct clk_branch gcc_usb4_2_phy_usb_pipe_clk = {
6448 .halt_reg = 0x110a4,
6449 .halt_check = BRANCH_HALT_SKIP,
6450 .hwcg_reg = 0x110a4,
6451 .hwcg_bit = 1,
6452 .clkr = {
6453 .enable_reg = 0x110a4,
6454 .enable_mask = BIT(0),
6455 .hw.init = &(const struct clk_init_data) {
6456 .name = "gcc_usb4_2_phy_usb_pipe_clk",
6457 .parent_hws = (const struct clk_hw*[]) {
6458 &gcc_usb34_tert_phy_pipe_clk_src.clkr.hw,
6459 },
6460 .num_parents = 1,
6461 .flags = CLK_SET_RATE_PARENT,
6462 .ops = &clk_branch2_ops,
6463 },
6464 },
6465};
6466
6467static struct clk_branch gcc_usb4_2_sb_if_clk = {
6468 .halt_reg = 0x11044,
6469 .halt_check = BRANCH_HALT,
6470 .clkr = {
6471 .enable_reg = 0x11044,
6472 .enable_mask = BIT(0),
6473 .hw.init = &(const struct clk_init_data) {
6474 .name = "gcc_usb4_2_sb_if_clk",
6475 .parent_hws = (const struct clk_hw*[]) {
6476 &gcc_usb4_2_sb_if_clk_src.clkr.hw,
6477 },
6478 .num_parents = 1,
6479 .flags = CLK_SET_RATE_PARENT,
6480 .ops = &clk_branch2_ops,
6481 },
6482 },
6483};
6484
6485static struct clk_branch gcc_usb4_2_sys_clk = {
6486 .halt_reg = 0x11054,
6487 .halt_check = BRANCH_HALT,
6488 .clkr = {
6489 .enable_reg = 0x11054,
6490 .enable_mask = BIT(0),
6491 .hw.init = &(const struct clk_init_data) {
6492 .name = "gcc_usb4_2_sys_clk",
6493 .ops = &clk_branch2_ops,
6494 },
6495 },
6496};
6497
6498static struct clk_branch gcc_usb4_2_tmu_clk = {
6499 .halt_reg = 0x11088,
6500 .halt_check = BRANCH_HALT_VOTED,
6501 .hwcg_reg = 0x11088,
6502 .hwcg_bit = 1,
6503 .clkr = {
6504 .enable_reg = 0x11088,
6505 .enable_mask = BIT(0),
6506 .hw.init = &(const struct clk_init_data) {
6507 .name = "gcc_usb4_2_tmu_clk",
6508 .parent_hws = (const struct clk_hw*[]) {
6509 &gcc_usb4_2_tmu_clk_src.clkr.hw,
6510 },
6511 .num_parents = 1,
6512 .flags = CLK_SET_RATE_PARENT,
6513 .ops = &clk_branch2_ops,
6514 },
6515 },
6516};
6517
6518static struct clk_branch gcc_video_axi0_clk = {
6519 .halt_reg = 0x32018,
6520 .halt_check = BRANCH_HALT_SKIP,
6521 .hwcg_reg = 0x32018,
6522 .hwcg_bit = 1,
6523 .clkr = {
6524 .enable_reg = 0x32018,
6525 .enable_mask = BIT(0),
6526 .hw.init = &(const struct clk_init_data) {
6527 .name = "gcc_video_axi0_clk",
6528 .ops = &clk_branch2_ops,
6529 },
6530 },
6531};
6532
6533static struct clk_branch gcc_video_axi1_clk = {
6534 .halt_reg = 0x32024,
6535 .halt_check = BRANCH_HALT_SKIP,
6536 .hwcg_reg = 0x32024,
6537 .hwcg_bit = 1,
6538 .clkr = {
6539 .enable_reg = 0x32024,
6540 .enable_mask = BIT(0),
6541 .hw.init = &(const struct clk_init_data) {
6542 .name = "gcc_video_axi1_clk",
6543 .ops = &clk_branch2_ops,
6544 },
6545 },
6546};
6547
6548static struct gdsc gcc_pcie_0_tunnel_gdsc = {
6549 .gdscr = 0xa0004,
6550 .en_rest_wait_val = 0x2,
6551 .en_few_wait_val = 0x2,
6552 .clk_dis_wait_val = 0xf,
6553 .pd = {
6554 .name = "gcc_pcie_0_tunnel_gdsc",
6555 },
6556 .pwrsts = PWRSTS_OFF_ON,
6557 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,
6558};
6559
6560static struct gdsc gcc_pcie_1_tunnel_gdsc = {
6561 .gdscr = 0x2c004,
6562 .en_rest_wait_val = 0x2,
6563 .en_few_wait_val = 0x2,
6564 .clk_dis_wait_val = 0xf,
6565 .pd = {
6566 .name = "gcc_pcie_1_tunnel_gdsc",
6567 },
6568 .pwrsts = PWRSTS_OFF_ON,
6569 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,
6570};
6571
6572static struct gdsc gcc_pcie_2_tunnel_gdsc = {
6573 .gdscr = 0x13004,
6574 .en_rest_wait_val = 0x2,
6575 .en_few_wait_val = 0x2,
6576 .clk_dis_wait_val = 0xf,
6577 .pd = {
6578 .name = "gcc_pcie_2_tunnel_gdsc",
6579 },
6580 .pwrsts = PWRSTS_OFF_ON,
6581 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,
6582};
6583
6584static struct gdsc gcc_pcie_3_gdsc = {
6585 .gdscr = 0x58004,
6586 .en_rest_wait_val = 0x2,
6587 .en_few_wait_val = 0x2,
6588 .clk_dis_wait_val = 0xf,
6589 .pd = {
6590 .name = "gcc_pcie_3_gdsc",
6591 },
6592 .pwrsts = PWRSTS_OFF_ON,
6593 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,
6594};
6595
6596static struct gdsc gcc_pcie_3_phy_gdsc = {
6597 .gdscr = 0x3e000,
6598 .en_rest_wait_val = 0x2,
6599 .en_few_wait_val = 0x2,
6600 .clk_dis_wait_val = 0x2,
6601 .pd = {
6602 .name = "gcc_pcie_3_phy_gdsc",
6603 },
6604 .pwrsts = PWRSTS_OFF_ON,
6605 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,
6606};
6607
6608static struct gdsc gcc_pcie_4_gdsc = {
6609 .gdscr = 0x6b004,
6610 .en_rest_wait_val = 0x2,
6611 .en_few_wait_val = 0x2,
6612 .clk_dis_wait_val = 0xf,
6613 .pd = {
6614 .name = "gcc_pcie_4_gdsc",
6615 },
6616 .pwrsts = PWRSTS_OFF_ON,
6617 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,
6618};
6619
6620static struct gdsc gcc_pcie_4_phy_gdsc = {
6621 .gdscr = 0x6c000,
6622 .en_rest_wait_val = 0x2,
6623 .en_few_wait_val = 0x2,
6624 .clk_dis_wait_val = 0x2,
6625 .pd = {
6626 .name = "gcc_pcie_4_phy_gdsc",
6627 },
6628 .pwrsts = PWRSTS_OFF_ON,
6629 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,
6630};
6631
6632static struct gdsc gcc_pcie_5_gdsc = {
6633 .gdscr = 0x2f004,
6634 .en_rest_wait_val = 0x2,
6635 .en_few_wait_val = 0x2,
6636 .clk_dis_wait_val = 0xf,
6637 .pd = {
6638 .name = "gcc_pcie_5_gdsc",
6639 },
6640 .pwrsts = PWRSTS_OFF_ON,
6641 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,
6642};
6643
6644static struct gdsc gcc_pcie_5_phy_gdsc = {
6645 .gdscr = 0x30000,
6646 .en_rest_wait_val = 0x2,
6647 .en_few_wait_val = 0x2,
6648 .clk_dis_wait_val = 0x2,
6649 .pd = {
6650 .name = "gcc_pcie_5_phy_gdsc",
6651 },
6652 .pwrsts = PWRSTS_OFF_ON,
6653 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,
6654};
6655
6656static struct gdsc gcc_pcie_6_phy_gdsc = {
6657 .gdscr = 0x8e000,
6658 .en_rest_wait_val = 0x2,
6659 .en_few_wait_val = 0x2,
6660 .clk_dis_wait_val = 0x2,
6661 .pd = {
6662 .name = "gcc_pcie_6_phy_gdsc",
6663 },
6664 .pwrsts = PWRSTS_OFF_ON,
6665 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,
6666};
6667
6668static struct gdsc gcc_pcie_6a_gdsc = {
6669 .gdscr = 0x31004,
6670 .en_rest_wait_val = 0x2,
6671 .en_few_wait_val = 0x2,
6672 .clk_dis_wait_val = 0xf,
6673 .pd = {
6674 .name = "gcc_pcie_6a_gdsc",
6675 },
6676 .pwrsts = PWRSTS_OFF_ON,
6677 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,
6678};
6679
6680static struct gdsc gcc_pcie_6b_gdsc = {
6681 .gdscr = 0x8d004,
6682 .en_rest_wait_val = 0x2,
6683 .en_few_wait_val = 0x2,
6684 .clk_dis_wait_val = 0xf,
6685 .pd = {
6686 .name = "gcc_pcie_6b_gdsc",
6687 },
6688 .pwrsts = PWRSTS_OFF_ON,
6689 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,
6690};
6691
6692static struct gdsc gcc_ufs_mem_phy_gdsc = {
6693 .gdscr = 0x9e000,
6694 .en_rest_wait_val = 0x2,
6695 .en_few_wait_val = 0x2,
6696 .clk_dis_wait_val = 0x2,
6697 .pd = {
6698 .name = "gcc_ufs_mem_phy_gdsc",
6699 },
6700 .pwrsts = PWRSTS_OFF_ON,
6701 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
6702};
6703
6704static struct gdsc gcc_ufs_phy_gdsc = {
6705 .gdscr = 0x77004,
6706 .en_rest_wait_val = 0x2,
6707 .en_few_wait_val = 0x2,
6708 .clk_dis_wait_val = 0xf,
6709 .pd = {
6710 .name = "gcc_ufs_phy_gdsc",
6711 },
6712 .pwrsts = PWRSTS_OFF_ON,
6713 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
6714};
6715
6716static struct gdsc gcc_usb20_prim_gdsc = {
6717 .gdscr = 0x29004,
6718 .en_rest_wait_val = 0x2,
6719 .en_few_wait_val = 0x2,
6720 .clk_dis_wait_val = 0xf,
6721 .pd = {
6722 .name = "gcc_usb20_prim_gdsc",
6723 },
6724 .pwrsts = PWRSTS_RET_ON,
6725 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
6726};
6727
6728static struct gdsc gcc_usb30_mp_gdsc = {
6729 .gdscr = 0x17004,
6730 .en_rest_wait_val = 0x2,
6731 .en_few_wait_val = 0x2,
6732 .clk_dis_wait_val = 0xf,
6733 .pd = {
6734 .name = "gcc_usb30_mp_gdsc",
6735 },
6736 .pwrsts = PWRSTS_RET_ON,
6737 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
6738};
6739
6740static struct gdsc gcc_usb30_prim_gdsc = {
6741 .gdscr = 0x39004,
6742 .en_rest_wait_val = 0x2,
6743 .en_few_wait_val = 0x2,
6744 .clk_dis_wait_val = 0xf,
6745 .pd = {
6746 .name = "gcc_usb30_prim_gdsc",
6747 },
6748 .pwrsts = PWRSTS_RET_ON,
6749 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
6750};
6751
6752static struct gdsc gcc_usb30_sec_gdsc = {
6753 .gdscr = 0xa1004,
6754 .en_rest_wait_val = 0x2,
6755 .en_few_wait_val = 0x2,
6756 .clk_dis_wait_val = 0xf,
6757 .pd = {
6758 .name = "gcc_usb30_sec_gdsc",
6759 },
6760 .pwrsts = PWRSTS_RET_ON,
6761 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
6762};
6763
6764static struct gdsc gcc_usb30_tert_gdsc = {
6765 .gdscr = 0xa2004,
6766 .en_rest_wait_val = 0x2,
6767 .en_few_wait_val = 0x2,
6768 .clk_dis_wait_val = 0xf,
6769 .pd = {
6770 .name = "gcc_usb30_tert_gdsc",
6771 },
6772 .pwrsts = PWRSTS_RET_ON,
6773 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
6774};
6775
6776static struct gdsc gcc_usb3_mp_ss0_phy_gdsc = {
6777 .gdscr = 0x1900c,
6778 .en_rest_wait_val = 0x2,
6779 .en_few_wait_val = 0x2,
6780 .clk_dis_wait_val = 0x2,
6781 .pd = {
6782 .name = "gcc_usb3_mp_ss0_phy_gdsc",
6783 },
6784 .pwrsts = PWRSTS_RET_ON,
6785 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
6786};
6787
6788static struct gdsc gcc_usb3_mp_ss1_phy_gdsc = {
6789 .gdscr = 0x5400c,
6790 .en_rest_wait_val = 0x2,
6791 .en_few_wait_val = 0x2,
6792 .clk_dis_wait_val = 0x2,
6793 .pd = {
6794 .name = "gcc_usb3_mp_ss1_phy_gdsc",
6795 },
6796 .pwrsts = PWRSTS_RET_ON,
6797 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
6798};
6799
6800static struct gdsc gcc_usb4_0_gdsc = {
6801 .gdscr = 0x9f004,
6802 .en_rest_wait_val = 0x2,
6803 .en_few_wait_val = 0x2,
6804 .clk_dis_wait_val = 0xf,
6805 .pd = {
6806 .name = "gcc_usb4_0_gdsc",
6807 },
6808 .pwrsts = PWRSTS_OFF_ON,
6809 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
6810};
6811
6812static struct gdsc gcc_usb4_1_gdsc = {
6813 .gdscr = 0x2b004,
6814 .en_rest_wait_val = 0x2,
6815 .en_few_wait_val = 0x2,
6816 .clk_dis_wait_val = 0xf,
6817 .pd = {
6818 .name = "gcc_usb4_1_gdsc",
6819 },
6820 .pwrsts = PWRSTS_OFF_ON,
6821 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
6822};
6823
6824static struct gdsc gcc_usb4_2_gdsc = {
6825 .gdscr = 0x11004,
6826 .en_rest_wait_val = 0x2,
6827 .en_few_wait_val = 0x2,
6828 .clk_dis_wait_val = 0xf,
6829 .pd = {
6830 .name = "gcc_usb4_2_gdsc",
6831 },
6832 .pwrsts = PWRSTS_OFF_ON,
6833 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
6834};
6835
6836static struct gdsc gcc_usb_0_phy_gdsc = {
6837 .gdscr = 0x50024,
6838 .en_rest_wait_val = 0x2,
6839 .en_few_wait_val = 0x2,
6840 .clk_dis_wait_val = 0x2,
6841 .pd = {
6842 .name = "gcc_usb_0_phy_gdsc",
6843 },
6844 .pwrsts = PWRSTS_RET_ON,
6845 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
6846};
6847
6848static struct gdsc gcc_usb_1_phy_gdsc = {
6849 .gdscr = 0x2a024,
6850 .en_rest_wait_val = 0x2,
6851 .en_few_wait_val = 0x2,
6852 .clk_dis_wait_val = 0x2,
6853 .pd = {
6854 .name = "gcc_usb_1_phy_gdsc",
6855 },
6856 .pwrsts = PWRSTS_RET_ON,
6857 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
6858};
6859
6860static struct gdsc gcc_usb_2_phy_gdsc = {
6861 .gdscr = 0xa3024,
6862 .en_rest_wait_val = 0x2,
6863 .en_few_wait_val = 0x2,
6864 .clk_dis_wait_val = 0x2,
6865 .pd = {
6866 .name = "gcc_usb_2_phy_gdsc",
6867 },
6868 .pwrsts = PWRSTS_RET_ON,
6869 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
6870};
6871
6872static struct clk_regmap *gcc_x1e80100_clocks[] = {
6873 [GCC_AGGRE_NOC_USB_NORTH_AXI_CLK] = &gcc_aggre_noc_usb_north_axi_clk.clkr,
6874 [GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK] = &gcc_aggre_noc_usb_south_axi_clk.clkr,
6875 [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr,
6876 [GCC_AGGRE_USB2_PRIM_AXI_CLK] = &gcc_aggre_usb2_prim_axi_clk.clkr,
6877 [GCC_AGGRE_USB3_MP_AXI_CLK] = &gcc_aggre_usb3_mp_axi_clk.clkr,
6878 [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr,
6879 [GCC_AGGRE_USB3_SEC_AXI_CLK] = &gcc_aggre_usb3_sec_axi_clk.clkr,
6880 [GCC_AGGRE_USB3_TERT_AXI_CLK] = &gcc_aggre_usb3_tert_axi_clk.clkr,
6881 [GCC_AGGRE_USB4_0_AXI_CLK] = &gcc_aggre_usb4_0_axi_clk.clkr,
6882 [GCC_AGGRE_USB4_1_AXI_CLK] = &gcc_aggre_usb4_1_axi_clk.clkr,
6883 [GCC_AGGRE_USB4_2_AXI_CLK] = &gcc_aggre_usb4_2_axi_clk.clkr,
6884 [GCC_AGGRE_USB_NOC_AXI_CLK] = &gcc_aggre_usb_noc_axi_clk.clkr,
6885 [GCC_AV1E_AHB_CLK] = &gcc_av1e_ahb_clk.clkr,
6886 [GCC_AV1E_AXI_CLK] = &gcc_av1e_axi_clk.clkr,
6887 [GCC_AV1E_XO_CLK] = &gcc_av1e_xo_clk.clkr,
6888 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
6889 [GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr,
6890 [GCC_CAMERA_SF_AXI_CLK] = &gcc_camera_sf_axi_clk.clkr,
6891 [GCC_CFG_NOC_PCIE_ANOC_AHB_CLK] = &gcc_cfg_noc_pcie_anoc_ahb_clk.clkr,
6892 [GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK] = &gcc_cfg_noc_pcie_anoc_north_ahb_clk.clkr,
6893 [GCC_CFG_NOC_PCIE_ANOC_SOUTH_AHB_CLK] = &gcc_cfg_noc_pcie_anoc_south_ahb_clk.clkr,
6894 [GCC_CFG_NOC_USB2_PRIM_AXI_CLK] = &gcc_cfg_noc_usb2_prim_axi_clk.clkr,
6895 [GCC_CFG_NOC_USB3_MP_AXI_CLK] = &gcc_cfg_noc_usb3_mp_axi_clk.clkr,
6896 [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
6897 [GCC_CFG_NOC_USB3_SEC_AXI_CLK] = &gcc_cfg_noc_usb3_sec_axi_clk.clkr,
6898 [GCC_CFG_NOC_USB3_TERT_AXI_CLK] = &gcc_cfg_noc_usb3_tert_axi_clk.clkr,
6899 [GCC_CFG_NOC_USB_ANOC_AHB_CLK] = &gcc_cfg_noc_usb_anoc_ahb_clk.clkr,
6900 [GCC_CFG_NOC_USB_ANOC_NORTH_AHB_CLK] = &gcc_cfg_noc_usb_anoc_north_ahb_clk.clkr,
6901 [GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK] = &gcc_cfg_noc_usb_anoc_south_ahb_clk.clkr,
6902 [GCC_CNOC_PCIE1_TUNNEL_CLK] = &gcc_cnoc_pcie1_tunnel_clk.clkr,
6903 [GCC_CNOC_PCIE2_TUNNEL_CLK] = &gcc_cnoc_pcie2_tunnel_clk.clkr,
6904 [GCC_CNOC_PCIE_NORTH_SF_AXI_CLK] = &gcc_cnoc_pcie_north_sf_axi_clk.clkr,
6905 [GCC_CNOC_PCIE_SOUTH_SF_AXI_CLK] = &gcc_cnoc_pcie_south_sf_axi_clk.clkr,
6906 [GCC_CNOC_PCIE_TUNNEL_CLK] = &gcc_cnoc_pcie_tunnel_clk.clkr,
6907 [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr,
6908 [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr,
6909 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
6910 [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
6911 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
6912 [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
6913 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
6914 [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
6915 [GCC_GPLL0] = &gcc_gpll0.clkr,
6916 [GCC_GPLL0_OUT_EVEN] = &gcc_gpll0_out_even.clkr,
6917 [GCC_GPLL4] = &gcc_gpll4.clkr,
6918 [GCC_GPLL7] = &gcc_gpll7.clkr,
6919 [GCC_GPLL8] = &gcc_gpll8.clkr,
6920 [GCC_GPLL9] = &gcc_gpll9.clkr,
6921 [GCC_GPU_GPLL0_CPH_CLK_SRC] = &gcc_gpu_gpll0_cph_clk_src.clkr,
6922 [GCC_GPU_GPLL0_DIV_CPH_CLK_SRC] = &gcc_gpu_gpll0_div_cph_clk_src.clkr,
6923 [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,
6924 [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
6925 [GCC_PCIE0_PHY_RCHNG_CLK] = &gcc_pcie0_phy_rchng_clk.clkr,
6926 [GCC_PCIE1_PHY_RCHNG_CLK] = &gcc_pcie1_phy_rchng_clk.clkr,
6927 [GCC_PCIE2_PHY_RCHNG_CLK] = &gcc_pcie2_phy_rchng_clk.clkr,
6928 [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
6929 [GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr,
6930 [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
6931 [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
6932 [GCC_PCIE_0_PHY_RCHNG_CLK_SRC] = &gcc_pcie_0_phy_rchng_clk_src.clkr,
6933 [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
6934 [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
6935 [GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr,
6936 [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
6937 [GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr,
6938 [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,
6939 [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,
6940 [GCC_PCIE_1_PHY_RCHNG_CLK_SRC] = &gcc_pcie_1_phy_rchng_clk_src.clkr,
6941 [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
6942 [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,
6943 [GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr,
6944 [GCC_PCIE_2_AUX_CLK] = &gcc_pcie_2_aux_clk.clkr,
6945 [GCC_PCIE_2_AUX_CLK_SRC] = &gcc_pcie_2_aux_clk_src.clkr,
6946 [GCC_PCIE_2_CFG_AHB_CLK] = &gcc_pcie_2_cfg_ahb_clk.clkr,
6947 [GCC_PCIE_2_MSTR_AXI_CLK] = &gcc_pcie_2_mstr_axi_clk.clkr,
6948 [GCC_PCIE_2_PHY_RCHNG_CLK_SRC] = &gcc_pcie_2_phy_rchng_clk_src.clkr,
6949 [GCC_PCIE_2_PIPE_CLK] = &gcc_pcie_2_pipe_clk.clkr,
6950 [GCC_PCIE_2_SLV_AXI_CLK] = &gcc_pcie_2_slv_axi_clk.clkr,
6951 [GCC_PCIE_2_SLV_Q2A_AXI_CLK] = &gcc_pcie_2_slv_q2a_axi_clk.clkr,
6952 [GCC_PCIE_3_AUX_CLK] = &gcc_pcie_3_aux_clk.clkr,
6953 [GCC_PCIE_3_AUX_CLK_SRC] = &gcc_pcie_3_aux_clk_src.clkr,
6954 [GCC_PCIE_3_CFG_AHB_CLK] = &gcc_pcie_3_cfg_ahb_clk.clkr,
6955 [GCC_PCIE_3_MSTR_AXI_CLK] = &gcc_pcie_3_mstr_axi_clk.clkr,
6956 [GCC_PCIE_3_PHY_AUX_CLK] = &gcc_pcie_3_phy_aux_clk.clkr,
6957 [GCC_PCIE_3_PHY_RCHNG_CLK] = &gcc_pcie_3_phy_rchng_clk.clkr,
6958 [GCC_PCIE_3_PHY_RCHNG_CLK_SRC] = &gcc_pcie_3_phy_rchng_clk_src.clkr,
6959 [GCC_PCIE_3_PIPE_CLK] = &gcc_pcie_3_pipe_clk.clkr,
6960 [GCC_PCIE_3_PIPE_CLK_SRC] = &gcc_pcie_3_pipe_clk_src.clkr,
6961 [GCC_PCIE_3_PIPE_DIV_CLK_SRC] = &gcc_pcie_3_pipe_div_clk_src.clkr,
6962 [GCC_PCIE_3_PIPEDIV2_CLK] = &gcc_pcie_3_pipediv2_clk.clkr,
6963 [GCC_PCIE_3_SLV_AXI_CLK] = &gcc_pcie_3_slv_axi_clk.clkr,
6964 [GCC_PCIE_3_SLV_Q2A_AXI_CLK] = &gcc_pcie_3_slv_q2a_axi_clk.clkr,
6965 [GCC_PCIE_4_AUX_CLK] = &gcc_pcie_4_aux_clk.clkr,
6966 [GCC_PCIE_4_AUX_CLK_SRC] = &gcc_pcie_4_aux_clk_src.clkr,
6967 [GCC_PCIE_4_CFG_AHB_CLK] = &gcc_pcie_4_cfg_ahb_clk.clkr,
6968 [GCC_PCIE_4_MSTR_AXI_CLK] = &gcc_pcie_4_mstr_axi_clk.clkr,
6969 [GCC_PCIE_4_PHY_RCHNG_CLK] = &gcc_pcie_4_phy_rchng_clk.clkr,
6970 [GCC_PCIE_4_PHY_RCHNG_CLK_SRC] = &gcc_pcie_4_phy_rchng_clk_src.clkr,
6971 [GCC_PCIE_4_PIPE_CLK] = &gcc_pcie_4_pipe_clk.clkr,
6972 [GCC_PCIE_4_PIPE_CLK_SRC] = &gcc_pcie_4_pipe_clk_src.clkr,
6973 [GCC_PCIE_4_PIPE_DIV_CLK_SRC] = &gcc_pcie_4_pipe_div_clk_src.clkr,
6974 [GCC_PCIE_4_PIPEDIV2_CLK] = &gcc_pcie_4_pipediv2_clk.clkr,
6975 [GCC_PCIE_4_SLV_AXI_CLK] = &gcc_pcie_4_slv_axi_clk.clkr,
6976 [GCC_PCIE_4_SLV_Q2A_AXI_CLK] = &gcc_pcie_4_slv_q2a_axi_clk.clkr,
6977 [GCC_PCIE_5_AUX_CLK] = &gcc_pcie_5_aux_clk.clkr,
6978 [GCC_PCIE_5_AUX_CLK_SRC] = &gcc_pcie_5_aux_clk_src.clkr,
6979 [GCC_PCIE_5_CFG_AHB_CLK] = &gcc_pcie_5_cfg_ahb_clk.clkr,
6980 [GCC_PCIE_5_MSTR_AXI_CLK] = &gcc_pcie_5_mstr_axi_clk.clkr,
6981 [GCC_PCIE_5_PHY_RCHNG_CLK] = &gcc_pcie_5_phy_rchng_clk.clkr,
6982 [GCC_PCIE_5_PHY_RCHNG_CLK_SRC] = &gcc_pcie_5_phy_rchng_clk_src.clkr,
6983 [GCC_PCIE_5_PIPE_CLK] = &gcc_pcie_5_pipe_clk.clkr,
6984 [GCC_PCIE_5_PIPE_CLK_SRC] = &gcc_pcie_5_pipe_clk_src.clkr,
6985 [GCC_PCIE_5_PIPE_DIV_CLK_SRC] = &gcc_pcie_5_pipe_div_clk_src.clkr,
6986 [GCC_PCIE_5_PIPEDIV2_CLK] = &gcc_pcie_5_pipediv2_clk.clkr,
6987 [GCC_PCIE_5_SLV_AXI_CLK] = &gcc_pcie_5_slv_axi_clk.clkr,
6988 [GCC_PCIE_5_SLV_Q2A_AXI_CLK] = &gcc_pcie_5_slv_q2a_axi_clk.clkr,
6989 [GCC_PCIE_6A_AUX_CLK] = &gcc_pcie_6a_aux_clk.clkr,
6990 [GCC_PCIE_6A_AUX_CLK_SRC] = &gcc_pcie_6a_aux_clk_src.clkr,
6991 [GCC_PCIE_6A_CFG_AHB_CLK] = &gcc_pcie_6a_cfg_ahb_clk.clkr,
6992 [GCC_PCIE_6A_MSTR_AXI_CLK] = &gcc_pcie_6a_mstr_axi_clk.clkr,
6993 [GCC_PCIE_6A_PHY_AUX_CLK] = &gcc_pcie_6a_phy_aux_clk.clkr,
6994 [GCC_PCIE_6A_PHY_RCHNG_CLK] = &gcc_pcie_6a_phy_rchng_clk.clkr,
6995 [GCC_PCIE_6A_PHY_RCHNG_CLK_SRC] = &gcc_pcie_6a_phy_rchng_clk_src.clkr,
6996 [GCC_PCIE_6A_PIPE_CLK] = &gcc_pcie_6a_pipe_clk.clkr,
6997 [GCC_PCIE_6A_PIPE_CLK_SRC] = &gcc_pcie_6a_pipe_clk_src.clkr,
6998 [GCC_PCIE_6A_PIPE_DIV_CLK_SRC] = &gcc_pcie_6a_pipe_div_clk_src.clkr,
6999 [GCC_PCIE_6A_PIPEDIV2_CLK] = &gcc_pcie_6a_pipediv2_clk.clkr,
7000 [GCC_PCIE_6A_SLV_AXI_CLK] = &gcc_pcie_6a_slv_axi_clk.clkr,
7001 [GCC_PCIE_6A_SLV_Q2A_AXI_CLK] = &gcc_pcie_6a_slv_q2a_axi_clk.clkr,
7002 [GCC_PCIE_6B_AUX_CLK] = &gcc_pcie_6b_aux_clk.clkr,
7003 [GCC_PCIE_6B_AUX_CLK_SRC] = &gcc_pcie_6b_aux_clk_src.clkr,
7004 [GCC_PCIE_6B_CFG_AHB_CLK] = &gcc_pcie_6b_cfg_ahb_clk.clkr,
7005 [GCC_PCIE_6B_MSTR_AXI_CLK] = &gcc_pcie_6b_mstr_axi_clk.clkr,
7006 [GCC_PCIE_6B_PHY_AUX_CLK] = &gcc_pcie_6b_phy_aux_clk.clkr,
7007 [GCC_PCIE_6B_PHY_RCHNG_CLK] = &gcc_pcie_6b_phy_rchng_clk.clkr,
7008 [GCC_PCIE_6B_PHY_RCHNG_CLK_SRC] = &gcc_pcie_6b_phy_rchng_clk_src.clkr,
7009 [GCC_PCIE_6B_PIPE_CLK] = &gcc_pcie_6b_pipe_clk.clkr,
7010 [GCC_PCIE_6B_PIPE_CLK_SRC] = &gcc_pcie_6b_pipe_clk_src.clkr,
7011 [GCC_PCIE_6B_PIPE_DIV_CLK_SRC] = &gcc_pcie_6b_pipe_div_clk_src.clkr,
7012 [GCC_PCIE_6B_PIPEDIV2_CLK] = &gcc_pcie_6b_pipediv2_clk.clkr,
7013 [GCC_PCIE_6B_SLV_AXI_CLK] = &gcc_pcie_6b_slv_axi_clk.clkr,
7014 [GCC_PCIE_6B_SLV_Q2A_AXI_CLK] = &gcc_pcie_6b_slv_q2a_axi_clk.clkr,
7015 [GCC_PCIE_RSCC_AHB_CLK] = &gcc_pcie_rscc_ahb_clk.clkr,
7016 [GCC_PCIE_RSCC_XO_CLK] = &gcc_pcie_rscc_xo_clk.clkr,
7017 [GCC_PCIE_RSCC_XO_CLK_SRC] = &gcc_pcie_rscc_xo_clk_src.clkr,
7018 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
7019 [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
7020 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
7021 [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
7022 [GCC_QMIP_AV1E_AHB_CLK] = &gcc_qmip_av1e_ahb_clk.clkr,
7023 [GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr,
7024 [GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr,
7025 [GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr,
7026 [GCC_QMIP_GPU_AHB_CLK] = &gcc_qmip_gpu_ahb_clk.clkr,
7027 [GCC_QMIP_VIDEO_CV_CPU_AHB_CLK] = &gcc_qmip_video_cv_cpu_ahb_clk.clkr,
7028 [GCC_QMIP_VIDEO_CVP_AHB_CLK] = &gcc_qmip_video_cvp_ahb_clk.clkr,
7029 [GCC_QMIP_VIDEO_V_CPU_AHB_CLK] = &gcc_qmip_video_v_cpu_ahb_clk.clkr,
7030 [GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr,
7031 [GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr,
7032 [GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr,
7033 [GCC_QUPV3_WRAP0_QSPI_S2_CLK] = &gcc_qupv3_wrap0_qspi_s2_clk.clkr,
7034 [GCC_QUPV3_WRAP0_QSPI_S3_CLK] = &gcc_qupv3_wrap0_qspi_s3_clk.clkr,
7035 [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,
7036 [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,
7037 [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,
7038 [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,
7039 [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,
7040 [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,
7041 [GCC_QUPV3_WRAP0_S2_DIV_CLK_SRC] = &gcc_qupv3_wrap0_s2_div_clk_src.clkr,
7042 [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,
7043 [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,
7044 [GCC_QUPV3_WRAP0_S3_DIV_CLK_SRC] = &gcc_qupv3_wrap0_s3_div_clk_src.clkr,
7045 [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,
7046 [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,
7047 [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr,
7048 [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr,
7049 [GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr,
7050 [GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr,
7051 [GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr,
7052 [GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr,
7053 [GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr,
7054 [GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr,
7055 [GCC_QUPV3_WRAP1_QSPI_S2_CLK] = &gcc_qupv3_wrap1_qspi_s2_clk.clkr,
7056 [GCC_QUPV3_WRAP1_QSPI_S3_CLK] = &gcc_qupv3_wrap1_qspi_s3_clk.clkr,
7057 [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr,
7058 [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr,
7059 [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr,
7060 [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr,
7061 [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr,
7062 [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr,
7063 [GCC_QUPV3_WRAP1_S2_DIV_CLK_SRC] = &gcc_qupv3_wrap1_s2_div_clk_src.clkr,
7064 [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr,
7065 [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr,
7066 [GCC_QUPV3_WRAP1_S3_DIV_CLK_SRC] = &gcc_qupv3_wrap1_s3_div_clk_src.clkr,
7067 [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr,
7068 [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr,
7069 [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr,
7070 [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr,
7071 [GCC_QUPV3_WRAP1_S6_CLK] = &gcc_qupv3_wrap1_s6_clk.clkr,
7072 [GCC_QUPV3_WRAP1_S6_CLK_SRC] = &gcc_qupv3_wrap1_s6_clk_src.clkr,
7073 [GCC_QUPV3_WRAP1_S7_CLK] = &gcc_qupv3_wrap1_s7_clk.clkr,
7074 [GCC_QUPV3_WRAP1_S7_CLK_SRC] = &gcc_qupv3_wrap1_s7_clk_src.clkr,
7075 [GCC_QUPV3_WRAP2_CORE_2X_CLK] = &gcc_qupv3_wrap2_core_2x_clk.clkr,
7076 [GCC_QUPV3_WRAP2_CORE_CLK] = &gcc_qupv3_wrap2_core_clk.clkr,
7077 [GCC_QUPV3_WRAP2_QSPI_S2_CLK] = &gcc_qupv3_wrap2_qspi_s2_clk.clkr,
7078 [GCC_QUPV3_WRAP2_QSPI_S3_CLK] = &gcc_qupv3_wrap2_qspi_s3_clk.clkr,
7079 [GCC_QUPV3_WRAP2_S0_CLK] = &gcc_qupv3_wrap2_s0_clk.clkr,
7080 [GCC_QUPV3_WRAP2_S0_CLK_SRC] = &gcc_qupv3_wrap2_s0_clk_src.clkr,
7081 [GCC_QUPV3_WRAP2_S1_CLK] = &gcc_qupv3_wrap2_s1_clk.clkr,
7082 [GCC_QUPV3_WRAP2_S1_CLK_SRC] = &gcc_qupv3_wrap2_s1_clk_src.clkr,
7083 [GCC_QUPV3_WRAP2_S2_CLK] = &gcc_qupv3_wrap2_s2_clk.clkr,
7084 [GCC_QUPV3_WRAP2_S2_CLK_SRC] = &gcc_qupv3_wrap2_s2_clk_src.clkr,
7085 [GCC_QUPV3_WRAP2_S2_DIV_CLK_SRC] = &gcc_qupv3_wrap2_s2_div_clk_src.clkr,
7086 [GCC_QUPV3_WRAP2_S3_CLK] = &gcc_qupv3_wrap2_s3_clk.clkr,
7087 [GCC_QUPV3_WRAP2_S3_CLK_SRC] = &gcc_qupv3_wrap2_s3_clk_src.clkr,
7088 [GCC_QUPV3_WRAP2_S3_DIV_CLK_SRC] = &gcc_qupv3_wrap2_s3_div_clk_src.clkr,
7089 [GCC_QUPV3_WRAP2_S4_CLK] = &gcc_qupv3_wrap2_s4_clk.clkr,
7090 [GCC_QUPV3_WRAP2_S4_CLK_SRC] = &gcc_qupv3_wrap2_s4_clk_src.clkr,
7091 [GCC_QUPV3_WRAP2_S5_CLK] = &gcc_qupv3_wrap2_s5_clk.clkr,
7092 [GCC_QUPV3_WRAP2_S5_CLK_SRC] = &gcc_qupv3_wrap2_s5_clk_src.clkr,
7093 [GCC_QUPV3_WRAP2_S6_CLK] = &gcc_qupv3_wrap2_s6_clk.clkr,
7094 [GCC_QUPV3_WRAP2_S6_CLK_SRC] = &gcc_qupv3_wrap2_s6_clk_src.clkr,
7095 [GCC_QUPV3_WRAP2_S7_CLK] = &gcc_qupv3_wrap2_s7_clk.clkr,
7096 [GCC_QUPV3_WRAP2_S7_CLK_SRC] = &gcc_qupv3_wrap2_s7_clk_src.clkr,
7097 [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,
7098 [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,
7099 [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr,
7100 [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,
7101 [GCC_QUPV3_WRAP_2_M_AHB_CLK] = &gcc_qupv3_wrap_2_m_ahb_clk.clkr,
7102 [GCC_QUPV3_WRAP_2_S_AHB_CLK] = &gcc_qupv3_wrap_2_s_ahb_clk.clkr,
7103 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
7104 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
7105 [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,
7106 [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
7107 [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
7108 [GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr,
7109 [GCC_SYS_NOC_USB_AXI_CLK] = &gcc_sys_noc_usb_axi_clk.clkr,
7110 [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
7111 [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
7112 [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
7113 [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,
7114 [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,
7115 [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,
7116 [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,
7117 [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,
7118 [GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr,
7119 [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr,
7120 [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,
7121 [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_phy_unipro_core_clk_src.clkr,
7122 [GCC_USB20_MASTER_CLK] = &gcc_usb20_master_clk.clkr,
7123 [GCC_USB20_MASTER_CLK_SRC] = &gcc_usb20_master_clk_src.clkr,
7124 [GCC_USB20_MOCK_UTMI_CLK] = &gcc_usb20_mock_utmi_clk.clkr,
7125 [GCC_USB20_MOCK_UTMI_CLK_SRC] = &gcc_usb20_mock_utmi_clk_src.clkr,
7126 [GCC_USB20_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb20_mock_utmi_postdiv_clk_src.clkr,
7127 [GCC_USB20_SLEEP_CLK] = &gcc_usb20_sleep_clk.clkr,
7128 [GCC_USB30_MP_MASTER_CLK] = &gcc_usb30_mp_master_clk.clkr,
7129 [GCC_USB30_MP_MASTER_CLK_SRC] = &gcc_usb30_mp_master_clk_src.clkr,
7130 [GCC_USB30_MP_MOCK_UTMI_CLK] = &gcc_usb30_mp_mock_utmi_clk.clkr,
7131 [GCC_USB30_MP_MOCK_UTMI_CLK_SRC] = &gcc_usb30_mp_mock_utmi_clk_src.clkr,
7132 [GCC_USB30_MP_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_mp_mock_utmi_postdiv_clk_src.clkr,
7133 [GCC_USB30_MP_SLEEP_CLK] = &gcc_usb30_mp_sleep_clk.clkr,
7134 [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
7135 [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
7136 [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
7137 [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = &gcc_usb30_prim_mock_utmi_clk_src.clkr,
7138 [GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr,
7139 [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
7140 [GCC_USB30_SEC_MASTER_CLK] = &gcc_usb30_sec_master_clk.clkr,
7141 [GCC_USB30_SEC_MASTER_CLK_SRC] = &gcc_usb30_sec_master_clk_src.clkr,
7142 [GCC_USB30_SEC_MOCK_UTMI_CLK] = &gcc_usb30_sec_mock_utmi_clk.clkr,
7143 [GCC_USB30_SEC_MOCK_UTMI_CLK_SRC] = &gcc_usb30_sec_mock_utmi_clk_src.clkr,
7144 [GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_sec_mock_utmi_postdiv_clk_src.clkr,
7145 [GCC_USB30_SEC_SLEEP_CLK] = &gcc_usb30_sec_sleep_clk.clkr,
7146 [GCC_USB30_TERT_MASTER_CLK] = &gcc_usb30_tert_master_clk.clkr,
7147 [GCC_USB30_TERT_MASTER_CLK_SRC] = &gcc_usb30_tert_master_clk_src.clkr,
7148 [GCC_USB30_TERT_MOCK_UTMI_CLK] = &gcc_usb30_tert_mock_utmi_clk.clkr,
7149 [GCC_USB30_TERT_MOCK_UTMI_CLK_SRC] = &gcc_usb30_tert_mock_utmi_clk_src.clkr,
7150 [GCC_USB30_TERT_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_tert_mock_utmi_postdiv_clk_src.clkr,
7151 [GCC_USB30_TERT_SLEEP_CLK] = &gcc_usb30_tert_sleep_clk.clkr,
7152 [GCC_USB34_PRIM_PHY_PIPE_CLK_SRC] = &gcc_usb34_prim_phy_pipe_clk_src.clkr,
7153 [GCC_USB34_SEC_PHY_PIPE_CLK_SRC] = &gcc_usb34_sec_phy_pipe_clk_src.clkr,
7154 [GCC_USB34_TERT_PHY_PIPE_CLK_SRC] = &gcc_usb34_tert_phy_pipe_clk_src.clkr,
7155 [GCC_USB3_MP_PHY_AUX_CLK] = &gcc_usb3_mp_phy_aux_clk.clkr,
7156 [GCC_USB3_MP_PHY_AUX_CLK_SRC] = &gcc_usb3_mp_phy_aux_clk_src.clkr,
7157 [GCC_USB3_MP_PHY_COM_AUX_CLK] = &gcc_usb3_mp_phy_com_aux_clk.clkr,
7158 [GCC_USB3_MP_PHY_PIPE_0_CLK] = &gcc_usb3_mp_phy_pipe_0_clk.clkr,
7159 [GCC_USB3_MP_PHY_PIPE_1_CLK] = &gcc_usb3_mp_phy_pipe_1_clk.clkr,
7160 [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr,
7161 [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
7162 [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
7163 [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,
7164 [GCC_USB3_PRIM_PHY_PIPE_CLK_SRC] = &gcc_usb3_prim_phy_pipe_clk_src.clkr,
7165 [GCC_USB3_SEC_PHY_AUX_CLK] = &gcc_usb3_sec_phy_aux_clk.clkr,
7166 [GCC_USB3_SEC_PHY_AUX_CLK_SRC] = &gcc_usb3_sec_phy_aux_clk_src.clkr,
7167 [GCC_USB3_SEC_PHY_COM_AUX_CLK] = &gcc_usb3_sec_phy_com_aux_clk.clkr,
7168 [GCC_USB3_SEC_PHY_PIPE_CLK] = &gcc_usb3_sec_phy_pipe_clk.clkr,
7169 [GCC_USB3_SEC_PHY_PIPE_CLK_SRC] = &gcc_usb3_sec_phy_pipe_clk_src.clkr,
7170 [GCC_USB3_TERT_PHY_AUX_CLK] = &gcc_usb3_tert_phy_aux_clk.clkr,
7171 [GCC_USB3_TERT_PHY_AUX_CLK_SRC] = &gcc_usb3_tert_phy_aux_clk_src.clkr,
7172 [GCC_USB3_TERT_PHY_COM_AUX_CLK] = &gcc_usb3_tert_phy_com_aux_clk.clkr,
7173 [GCC_USB3_TERT_PHY_PIPE_CLK] = &gcc_usb3_tert_phy_pipe_clk.clkr,
7174 [GCC_USB3_TERT_PHY_PIPE_CLK_SRC] = &gcc_usb3_tert_phy_pipe_clk_src.clkr,
7175 [GCC_USB4_0_CFG_AHB_CLK] = &gcc_usb4_0_cfg_ahb_clk.clkr,
7176 [GCC_USB4_0_DP0_CLK] = &gcc_usb4_0_dp0_clk.clkr,
7177 [GCC_USB4_0_DP1_CLK] = &gcc_usb4_0_dp1_clk.clkr,
7178 [GCC_USB4_0_MASTER_CLK] = &gcc_usb4_0_master_clk.clkr,
7179 [GCC_USB4_0_MASTER_CLK_SRC] = &gcc_usb4_0_master_clk_src.clkr,
7180 [GCC_USB4_0_PHY_DP0_CLK_SRC] = &gcc_usb4_0_phy_dp0_clk_src.clkr,
7181 [GCC_USB4_0_PHY_DP1_CLK_SRC] = &gcc_usb4_0_phy_dp1_clk_src.clkr,
7182 [GCC_USB4_0_PHY_P2RR2P_PIPE_CLK] = &gcc_usb4_0_phy_p2rr2p_pipe_clk.clkr,
7183 [GCC_USB4_0_PHY_P2RR2P_PIPE_CLK_SRC] = &gcc_usb4_0_phy_p2rr2p_pipe_clk_src.clkr,
7184 [GCC_USB4_0_PHY_PCIE_PIPE_CLK] = &gcc_usb4_0_phy_pcie_pipe_clk.clkr,
7185 [GCC_USB4_0_PHY_PCIE_PIPE_CLK_SRC] = &gcc_usb4_0_phy_pcie_pipe_clk_src.clkr,
7186 [GCC_USB4_0_PHY_PCIE_PIPE_MUX_CLK_SRC] = &gcc_usb4_0_phy_pcie_pipe_mux_clk_src.clkr,
7187 [GCC_USB4_0_PHY_RX0_CLK] = &gcc_usb4_0_phy_rx0_clk.clkr,
7188 [GCC_USB4_0_PHY_RX0_CLK_SRC] = &gcc_usb4_0_phy_rx0_clk_src.clkr,
7189 [GCC_USB4_0_PHY_RX1_CLK] = &gcc_usb4_0_phy_rx1_clk.clkr,
7190 [GCC_USB4_0_PHY_RX1_CLK_SRC] = &gcc_usb4_0_phy_rx1_clk_src.clkr,
7191 [GCC_USB4_0_PHY_SYS_CLK_SRC] = &gcc_usb4_0_phy_sys_clk_src.clkr,
7192 [GCC_USB4_0_PHY_USB_PIPE_CLK] = &gcc_usb4_0_phy_usb_pipe_clk.clkr,
7193 [GCC_USB4_0_SB_IF_CLK] = &gcc_usb4_0_sb_if_clk.clkr,
7194 [GCC_USB4_0_SB_IF_CLK_SRC] = &gcc_usb4_0_sb_if_clk_src.clkr,
7195 [GCC_USB4_0_SYS_CLK] = &gcc_usb4_0_sys_clk.clkr,
7196 [GCC_USB4_0_TMU_CLK] = &gcc_usb4_0_tmu_clk.clkr,
7197 [GCC_USB4_0_TMU_CLK_SRC] = &gcc_usb4_0_tmu_clk_src.clkr,
7198 [GCC_USB4_1_CFG_AHB_CLK] = &gcc_usb4_1_cfg_ahb_clk.clkr,
7199 [GCC_USB4_1_DP0_CLK] = &gcc_usb4_1_dp0_clk.clkr,
7200 [GCC_USB4_1_DP1_CLK] = &gcc_usb4_1_dp1_clk.clkr,
7201 [GCC_USB4_1_MASTER_CLK] = &gcc_usb4_1_master_clk.clkr,
7202 [GCC_USB4_1_MASTER_CLK_SRC] = &gcc_usb4_1_master_clk_src.clkr,
7203 [GCC_USB4_1_PHY_DP0_CLK_SRC] = &gcc_usb4_1_phy_dp0_clk_src.clkr,
7204 [GCC_USB4_1_PHY_DP1_CLK_SRC] = &gcc_usb4_1_phy_dp1_clk_src.clkr,
7205 [GCC_USB4_1_PHY_P2RR2P_PIPE_CLK] = &gcc_usb4_1_phy_p2rr2p_pipe_clk.clkr,
7206 [GCC_USB4_1_PHY_P2RR2P_PIPE_CLK_SRC] = &gcc_usb4_1_phy_p2rr2p_pipe_clk_src.clkr,
7207 [GCC_USB4_1_PHY_PCIE_PIPE_CLK] = &gcc_usb4_1_phy_pcie_pipe_clk.clkr,
7208 [GCC_USB4_1_PHY_PCIE_PIPE_CLK_SRC] = &gcc_usb4_1_phy_pcie_pipe_clk_src.clkr,
7209 [GCC_USB4_1_PHY_PCIE_PIPE_MUX_CLK_SRC] = &gcc_usb4_1_phy_pcie_pipe_mux_clk_src.clkr,
7210 [GCC_USB4_1_PHY_RX0_CLK] = &gcc_usb4_1_phy_rx0_clk.clkr,
7211 [GCC_USB4_1_PHY_RX0_CLK_SRC] = &gcc_usb4_1_phy_rx0_clk_src.clkr,
7212 [GCC_USB4_1_PHY_RX1_CLK] = &gcc_usb4_1_phy_rx1_clk.clkr,
7213 [GCC_USB4_1_PHY_RX1_CLK_SRC] = &gcc_usb4_1_phy_rx1_clk_src.clkr,
7214 [GCC_USB4_1_PHY_SYS_CLK_SRC] = &gcc_usb4_1_phy_sys_clk_src.clkr,
7215 [GCC_USB4_1_PHY_USB_PIPE_CLK] = &gcc_usb4_1_phy_usb_pipe_clk.clkr,
7216 [GCC_USB4_1_SB_IF_CLK] = &gcc_usb4_1_sb_if_clk.clkr,
7217 [GCC_USB4_1_SB_IF_CLK_SRC] = &gcc_usb4_1_sb_if_clk_src.clkr,
7218 [GCC_USB4_1_SYS_CLK] = &gcc_usb4_1_sys_clk.clkr,
7219 [GCC_USB4_1_TMU_CLK] = &gcc_usb4_1_tmu_clk.clkr,
7220 [GCC_USB4_1_TMU_CLK_SRC] = &gcc_usb4_1_tmu_clk_src.clkr,
7221 [GCC_USB4_2_CFG_AHB_CLK] = &gcc_usb4_2_cfg_ahb_clk.clkr,
7222 [GCC_USB4_2_DP0_CLK] = &gcc_usb4_2_dp0_clk.clkr,
7223 [GCC_USB4_2_DP1_CLK] = &gcc_usb4_2_dp1_clk.clkr,
7224 [GCC_USB4_2_MASTER_CLK] = &gcc_usb4_2_master_clk.clkr,
7225 [GCC_USB4_2_MASTER_CLK_SRC] = &gcc_usb4_2_master_clk_src.clkr,
7226 [GCC_USB4_2_PHY_DP0_CLK_SRC] = &gcc_usb4_2_phy_dp0_clk_src.clkr,
7227 [GCC_USB4_2_PHY_DP1_CLK_SRC] = &gcc_usb4_2_phy_dp1_clk_src.clkr,
7228 [GCC_USB4_2_PHY_P2RR2P_PIPE_CLK] = &gcc_usb4_2_phy_p2rr2p_pipe_clk.clkr,
7229 [GCC_USB4_2_PHY_P2RR2P_PIPE_CLK_SRC] = &gcc_usb4_2_phy_p2rr2p_pipe_clk_src.clkr,
7230 [GCC_USB4_2_PHY_PCIE_PIPE_CLK] = &gcc_usb4_2_phy_pcie_pipe_clk.clkr,
7231 [GCC_USB4_2_PHY_PCIE_PIPE_CLK_SRC] = &gcc_usb4_2_phy_pcie_pipe_clk_src.clkr,
7232 [GCC_USB4_2_PHY_PCIE_PIPE_MUX_CLK_SRC] = &gcc_usb4_2_phy_pcie_pipe_mux_clk_src.clkr,
7233 [GCC_USB4_2_PHY_RX0_CLK] = &gcc_usb4_2_phy_rx0_clk.clkr,
7234 [GCC_USB4_2_PHY_RX0_CLK_SRC] = &gcc_usb4_2_phy_rx0_clk_src.clkr,
7235 [GCC_USB4_2_PHY_RX1_CLK] = &gcc_usb4_2_phy_rx1_clk.clkr,
7236 [GCC_USB4_2_PHY_RX1_CLK_SRC] = &gcc_usb4_2_phy_rx1_clk_src.clkr,
7237 [GCC_USB4_2_PHY_SYS_CLK_SRC] = &gcc_usb4_2_phy_sys_clk_src.clkr,
7238 [GCC_USB4_2_PHY_USB_PIPE_CLK] = &gcc_usb4_2_phy_usb_pipe_clk.clkr,
7239 [GCC_USB4_2_SB_IF_CLK] = &gcc_usb4_2_sb_if_clk.clkr,
7240 [GCC_USB4_2_SB_IF_CLK_SRC] = &gcc_usb4_2_sb_if_clk_src.clkr,
7241 [GCC_USB4_2_SYS_CLK] = &gcc_usb4_2_sys_clk.clkr,
7242 [GCC_USB4_2_TMU_CLK] = &gcc_usb4_2_tmu_clk.clkr,
7243 [GCC_USB4_2_TMU_CLK_SRC] = &gcc_usb4_2_tmu_clk_src.clkr,
7244 [GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr,
7245 [GCC_VIDEO_AXI1_CLK] = &gcc_video_axi1_clk.clkr,
7246 [GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_rx_symbol_0_clk_src.clkr,
7247 [GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC] = &gcc_ufs_phy_rx_symbol_1_clk_src.clkr,
7248 [GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_tx_symbol_0_clk_src.clkr,
7249};
7250
7251static struct gdsc *gcc_x1e80100_gdscs[] = {
7252 [GCC_PCIE_0_TUNNEL_GDSC] = &gcc_pcie_0_tunnel_gdsc,
7253 [GCC_PCIE_1_TUNNEL_GDSC] = &gcc_pcie_1_tunnel_gdsc,
7254 [GCC_PCIE_2_TUNNEL_GDSC] = &gcc_pcie_2_tunnel_gdsc,
7255 [GCC_PCIE_3_GDSC] = &gcc_pcie_3_gdsc,
7256 [GCC_PCIE_3_PHY_GDSC] = &gcc_pcie_3_phy_gdsc,
7257 [GCC_PCIE_4_GDSC] = &gcc_pcie_4_gdsc,
7258 [GCC_PCIE_4_PHY_GDSC] = &gcc_pcie_4_phy_gdsc,
7259 [GCC_PCIE_5_GDSC] = &gcc_pcie_5_gdsc,
7260 [GCC_PCIE_5_PHY_GDSC] = &gcc_pcie_5_phy_gdsc,
7261 [GCC_PCIE_6_PHY_GDSC] = &gcc_pcie_6_phy_gdsc,
7262 [GCC_PCIE_6A_GDSC] = &gcc_pcie_6a_gdsc,
7263 [GCC_PCIE_6B_GDSC] = &gcc_pcie_6b_gdsc,
7264 [GCC_UFS_MEM_PHY_GDSC] = &gcc_ufs_mem_phy_gdsc,
7265 [GCC_UFS_PHY_GDSC] = &gcc_ufs_phy_gdsc,
7266 [GCC_USB20_PRIM_GDSC] = &gcc_usb20_prim_gdsc,
7267 [GCC_USB30_MP_GDSC] = &gcc_usb30_mp_gdsc,
7268 [GCC_USB30_PRIM_GDSC] = &gcc_usb30_prim_gdsc,
7269 [GCC_USB30_SEC_GDSC] = &gcc_usb30_sec_gdsc,
7270 [GCC_USB30_TERT_GDSC] = &gcc_usb30_tert_gdsc,
7271 [GCC_USB3_MP_SS0_PHY_GDSC] = &gcc_usb3_mp_ss0_phy_gdsc,
7272 [GCC_USB3_MP_SS1_PHY_GDSC] = &gcc_usb3_mp_ss1_phy_gdsc,
7273 [GCC_USB4_0_GDSC] = &gcc_usb4_0_gdsc,
7274 [GCC_USB4_1_GDSC] = &gcc_usb4_1_gdsc,
7275 [GCC_USB4_2_GDSC] = &gcc_usb4_2_gdsc,
7276 [GCC_USB_0_PHY_GDSC] = &gcc_usb_0_phy_gdsc,
7277 [GCC_USB_1_PHY_GDSC] = &gcc_usb_1_phy_gdsc,
7278 [GCC_USB_2_PHY_GDSC] = &gcc_usb_2_phy_gdsc,
7279};
7280
7281static const struct qcom_reset_map gcc_x1e80100_resets[] = {
7282 [GCC_AV1E_BCR] = { 0x4a000 },
7283 [GCC_CAMERA_BCR] = { 0x26000 },
7284 [GCC_DISPLAY_BCR] = { 0x27000 },
7285 [GCC_GPU_BCR] = { 0x71000 },
7286 [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x6c014 },
7287 [GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x6c020 },
7288 [GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
7289 [GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0x6c028 },
7290 [GCC_PCIE_0_TUNNEL_BCR] = { 0xa0000 },
7291 [GCC_PCIE_1_LINK_DOWN_BCR] = { 0x8e014 },
7292 [GCC_PCIE_1_NOCSR_COM_PHY_BCR] = { 0x8e020 },
7293 [GCC_PCIE_1_PHY_BCR] = { 0x8e01c },
7294 [GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR] = { 0x8e024 },
7295 [GCC_PCIE_1_TUNNEL_BCR] = { 0x2c000 },
7296 [GCC_PCIE_2_LINK_DOWN_BCR] = { 0xa5014 },
7297 [GCC_PCIE_2_NOCSR_COM_PHY_BCR] = { 0xa5020 },
7298 [GCC_PCIE_2_PHY_BCR] = { 0xa501c },
7299 [GCC_PCIE_2_PHY_NOCSR_COM_PHY_BCR] = { 0xa5028 },
7300 [GCC_PCIE_2_TUNNEL_BCR] = { 0x13000 },
7301 [GCC_PCIE_3_BCR] = { 0x58000 },
7302 [GCC_PCIE_3_LINK_DOWN_BCR] = { 0xab014 },
7303 [GCC_PCIE_3_NOCSR_COM_PHY_BCR] = { 0xab020 },
7304 [GCC_PCIE_3_PHY_BCR] = { 0xab01c },
7305 [GCC_PCIE_3_PHY_NOCSR_COM_PHY_BCR] = { 0xab024 },
7306 [GCC_PCIE_4_BCR] = { 0x6b000 },
7307 [GCC_PCIE_4_LINK_DOWN_BCR] = { 0xb3014 },
7308 [GCC_PCIE_4_NOCSR_COM_PHY_BCR] = { 0xb3020 },
7309 [GCC_PCIE_4_PHY_BCR] = { 0xb301c },
7310 [GCC_PCIE_4_PHY_NOCSR_COM_PHY_BCR] = { 0xb3028 },
7311 [GCC_PCIE_5_BCR] = { 0x2f000 },
7312 [GCC_PCIE_5_LINK_DOWN_BCR] = { 0xaa014 },
7313 [GCC_PCIE_5_NOCSR_COM_PHY_BCR] = { 0xaa020 },
7314 [GCC_PCIE_5_PHY_BCR] = { 0xaa01c },
7315 [GCC_PCIE_5_PHY_NOCSR_COM_PHY_BCR] = { 0xaa028 },
7316 [GCC_PCIE_6A_BCR] = { 0x31000 },
7317 [GCC_PCIE_6A_LINK_DOWN_BCR] = { 0xac014 },
7318 [GCC_PCIE_6A_NOCSR_COM_PHY_BCR] = { 0xac020 },
7319 [GCC_PCIE_6A_PHY_BCR] = { 0xac01c },
7320 [GCC_PCIE_6A_PHY_NOCSR_COM_PHY_BCR] = { 0xac024 },
7321 [GCC_PCIE_6B_BCR] = { 0x8d000 },
7322 [GCC_PCIE_6B_LINK_DOWN_BCR] = { 0xb5014 },
7323 [GCC_PCIE_6B_NOCSR_COM_PHY_BCR] = { 0xb5020 },
7324 [GCC_PCIE_6B_PHY_BCR] = { 0xb501c },
7325 [GCC_PCIE_6B_PHY_NOCSR_COM_PHY_BCR] = { 0xb5024 },
7326 [GCC_PCIE_PHY_BCR] = { 0x6f000 },
7327 [GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x6f00c },
7328 [GCC_PCIE_PHY_COM_BCR] = { 0x6f010 },
7329 [GCC_PCIE_RSCC_BCR] = { 0xa4000 },
7330 [GCC_PDM_BCR] = { 0x33000 },
7331 [GCC_QUPV3_WRAPPER_0_BCR] = { 0x42000 },
7332 [GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 },
7333 [GCC_QUPV3_WRAPPER_2_BCR] = { 0x1e000 },
7334 [GCC_QUSB2PHY_HS0_MP_BCR] = { 0x1200c },
7335 [GCC_QUSB2PHY_HS1_MP_BCR] = { 0x12010 },
7336 [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
7337 [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
7338 [GCC_QUSB2PHY_TERT_BCR] = { 0x12008 },
7339 [GCC_QUSB2PHY_USB20_HS_BCR] = { 0x12014 },
7340 [GCC_SDCC2_BCR] = { 0x14000 },
7341 [GCC_SDCC4_BCR] = { 0x16000 },
7342 [GCC_UFS_PHY_BCR] = { 0x77000 },
7343 [GCC_USB20_PRIM_BCR] = { 0x29000 },
7344 [GCC_USB30_MP_BCR] = { 0x17000 },
7345 [GCC_USB30_PRIM_BCR] = { 0x39000 },
7346 [GCC_USB30_SEC_BCR] = { 0xa1000 },
7347 [GCC_USB30_TERT_BCR] = { 0xa2000 },
7348 [GCC_USB3_MP_SS0_PHY_BCR] = { 0x19008 },
7349 [GCC_USB3_MP_SS1_PHY_BCR] = { 0x54008 },
7350 [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },
7351 [GCC_USB3_PHY_SEC_BCR] = { 0x2a000 },
7352 [GCC_USB3_PHY_TERT_BCR] = { 0xa3000 },
7353 [GCC_USB3_UNIPHY_MP0_BCR] = { 0x19000 },
7354 [GCC_USB3_UNIPHY_MP1_BCR] = { 0x54000 },
7355 [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 },
7356 [GCC_USB4PHY_PHY_PRIM_BCR] = { 0x5000c },
7357 [GCC_USB3PHY_PHY_SEC_BCR] = { 0x2a004 },
7358 [GCC_USB4PHY_PHY_SEC_BCR] = { 0x2a00c },
7359 [GCC_USB3PHY_PHY_TERT_BCR] = { 0xa3004 },
7360 [GCC_USB4PHY_PHY_TERT_BCR] = { 0xa300c },
7361 [GCC_USB3UNIPHY_PHY_MP0_BCR] = { 0x19004 },
7362 [GCC_USB3UNIPHY_PHY_MP1_BCR] = { 0x54004 },
7363 [GCC_USB4_0_BCR] = { 0x9f000 },
7364 [GCC_USB4_0_DP0_PHY_PRIM_BCR] = { 0x50010 },
7365 [GCC_USB4_0_MISC_USB4_SYS_BCR] = { .reg = 0xad0f8, .bit = 0 },
7366 [GCC_USB4_0_MISC_RX_CLK_0_BCR] = { .reg = 0xad0f8, .bit = 1 },
7367 [GCC_USB4_0_MISC_RX_CLK_1_BCR] = { .reg = 0xad0f8, .bit = 2 },
7368 [GCC_USB4_0_MISC_USB_PIPE_BCR] = { .reg = 0xad0f8, .bit = 3 },
7369 [GCC_USB4_0_MISC_PCIE_PIPE_BCR] = { .reg = 0xad0f8, .bit = 4 },
7370 [GCC_USB4_0_MISC_TMU_BCR] = { .reg = 0xad0f8, .bit = 5 },
7371 [GCC_USB4_0_MISC_SB_IF_BCR] = { .reg = 0xad0f8, .bit = 6 },
7372 [GCC_USB4_0_MISC_HIA_MSTR_BCR] = { .reg = 0xad0f8, .bit = 7 },
7373 [GCC_USB4_0_MISC_AHB_BCR] = { .reg = 0xad0f8, .bit = 8 },
7374 [GCC_USB4_0_MISC_DP0_MAX_PCLK_BCR] = { .reg = 0xad0f8, .bit = 9 },
7375 [GCC_USB4_0_MISC_DP1_MAX_PCLK_BCR] = { .reg = 0xad0f8, .bit = 10 },
7376 [GCC_USB4_1_BCR] = { 0x2b000 },
7377 [GCC_USB4_1_DP0_PHY_SEC_BCR] = { 0x2a010 },
7378 [GCC_USB4_1_MISC_USB4_SYS_BCR] = { .reg = 0xae0f8, .bit = 0 },
7379 [GCC_USB4_1_MISC_RX_CLK_0_BCR] = { .reg = 0xae0f8, .bit = 1 },
7380 [GCC_USB4_1_MISC_RX_CLK_1_BCR] = { .reg = 0xae0f8, .bit = 2 },
7381 [GCC_USB4_1_MISC_USB_PIPE_BCR] = { .reg = 0xae0f8, .bit = 3 },
7382 [GCC_USB4_1_MISC_PCIE_PIPE_BCR] = { .reg = 0xae0f8, .bit = 4 },
7383 [GCC_USB4_1_MISC_TMU_BCR] = { .reg = 0xae0f8, .bit = 5 },
7384 [GCC_USB4_1_MISC_SB_IF_BCR] = { .reg = 0xae0f8, .bit = 6 },
7385 [GCC_USB4_1_MISC_HIA_MSTR_BCR] = { .reg = 0xae0f8, .bit = 7 },
7386 [GCC_USB4_1_MISC_AHB_BCR] = { .reg = 0xae0f8, .bit = 8 },
7387 [GCC_USB4_1_MISC_DP0_MAX_PCLK_BCR] = { .reg = 0xae0f8, .bit = 9 },
7388 [GCC_USB4_1_MISC_DP1_MAX_PCLK_BCR] = { .reg = 0xae0f8, .bit = 10 },
7389 [GCC_USB4_2_BCR] = { 0x11000 },
7390 [GCC_USB4_2_DP0_PHY_TERT_BCR] = { 0xa3010 },
7391 [GCC_USB4_2_MISC_USB4_SYS_BCR] = { .reg = 0xaf0f8, .bit = 0 },
7392 [GCC_USB4_2_MISC_RX_CLK_0_BCR] = { .reg = 0xaf0f8, .bit = 1 },
7393 [GCC_USB4_2_MISC_RX_CLK_1_BCR] = { .reg = 0xaf0f8, .bit = 2 },
7394 [GCC_USB4_2_MISC_USB_PIPE_BCR] = { .reg = 0xaf0f8, .bit = 3 },
7395 [GCC_USB4_2_MISC_PCIE_PIPE_BCR] = { .reg = 0xaf0f8, .bit = 4 },
7396 [GCC_USB4_2_MISC_TMU_BCR] = { .reg = 0xaf0f8, .bit = 5 },
7397 [GCC_USB4_2_MISC_SB_IF_BCR] = { .reg = 0xaf0f8, .bit = 6 },
7398 [GCC_USB4_2_MISC_HIA_MSTR_BCR] = { .reg = 0xaf0f8, .bit = 7 },
7399 [GCC_USB4_2_MISC_AHB_BCR] = { .reg = 0xaf0f8, .bit = 8 },
7400 [GCC_USB4_2_MISC_DP0_MAX_PCLK_BCR] = { .reg = 0xaf0f8, .bit = 9 },
7401 [GCC_USB4_2_MISC_DP1_MAX_PCLK_BCR] = { .reg = 0xaf0f8, .bit = 10 },
7402 [GCC_USB_0_PHY_BCR] = { 0x50020 },
7403 [GCC_USB_1_PHY_BCR] = { 0x2a020 },
7404 [GCC_USB_2_PHY_BCR] = { 0xa3020 },
7405 [GCC_VIDEO_BCR] = { 0x32000 },
7406 [GCC_VIDEO_AXI0_CLK_ARES] = { .reg = 0x32018, .bit = 2, .udelay = 1000 },
7407 [GCC_VIDEO_AXI1_CLK_ARES] = { .reg = 0x32024, .bit = 2, .udelay = 1000 },
7408};
7409
7410static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
7411 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),
7412 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src),
7413 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src),
7414 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src),
7415 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src),
7416 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src),
7417 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk_src),
7418 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s7_clk_src),
7419 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src),
7420 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src),
7421 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src),
7422 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src),
7423 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src),
7424 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src),
7425 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s6_clk_src),
7426 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s7_clk_src),
7427 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s0_clk_src),
7428 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s1_clk_src),
7429 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s2_clk_src),
7430 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s3_clk_src),
7431 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s4_clk_src),
7432 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s5_clk_src),
7433 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s6_clk_src),
7434 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s7_clk_src),
7435};
7436
7437static const struct regmap_config gcc_x1e80100_regmap_config = {
7438 .reg_bits = 32,
7439 .reg_stride = 4,
7440 .val_bits = 32,
7441 .max_register = 0x1f41f0,
7442 .fast_io = true,
7443};
7444
7445static const struct qcom_cc_desc gcc_x1e80100_desc = {
7446 .config = &gcc_x1e80100_regmap_config,
7447 .clks = gcc_x1e80100_clocks,
7448 .num_clks = ARRAY_SIZE(gcc_x1e80100_clocks),
7449 .resets = gcc_x1e80100_resets,
7450 .num_resets = ARRAY_SIZE(gcc_x1e80100_resets),
7451 .gdscs = gcc_x1e80100_gdscs,
7452 .num_gdscs = ARRAY_SIZE(gcc_x1e80100_gdscs),
7453};
7454
7455static const struct of_device_id gcc_x1e80100_match_table[] = {
7456 { .compatible = "qcom,x1e80100-gcc" },
7457 { }
7458};
7459MODULE_DEVICE_TABLE(of, gcc_x1e80100_match_table);
7460
7461static int gcc_x1e80100_probe(struct platform_device *pdev)
7462{
7463 struct regmap *regmap;
7464 int ret;
7465
7466 regmap = qcom_cc_map(pdev, &gcc_x1e80100_desc);
7467 if (IS_ERR(regmap))
7468 return PTR_ERR(regmap);
7469
7470 ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
7471 ARRAY_SIZE(gcc_dfs_clocks));
7472 if (ret)
7473 return ret;
7474
7475 /* Keep some clocks always-on */
7476 qcom_branch_set_clk_en(regmap, 0x26004); /* GCC_CAMERA_AHB_CLK */
7477 qcom_branch_set_clk_en(regmap, 0x26028); /* GCC_CAMERA_XO_CLK */
7478 qcom_branch_set_clk_en(regmap, 0x27004); /* GCC_DISP_AHB_CLK */
7479 qcom_branch_set_clk_en(regmap, 0x27018); /* GCC_DISP_XO_CLK */
7480 qcom_branch_set_clk_en(regmap, 0x32004); /* GCC_VIDEO_AHB_CLK */
7481 qcom_branch_set_clk_en(regmap, 0x32030); /* GCC_VIDEO_XO_CLK */
7482 qcom_branch_set_clk_en(regmap, 0x71004); /* GCC_GPU_CFG_AHB_CLK */
7483 qcom_branch_set_clk_en(regmap, 0x7d01c); /* GCC_HLOS1_VOTE_AGGRE_NOC_MMU_USB_QTB_CLK */
7484
7485 /* Clear GDSC_SLEEP_ENA_VOTE to stop votes being auto-removed in sleep. */
7486 regmap_write(regmap, 0x52224, 0x0);
7487
7488 /* FORCE_MEM_CORE_ON for ufs phy ice core and gcc ufs phy axi clocks */
7489 qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_ice_core_clk, true);
7490 qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_axi_clk, true);
7491
7492 return qcom_cc_really_probe(&pdev->dev, &gcc_x1e80100_desc, regmap);
7493}
7494
7495static struct platform_driver gcc_x1e80100_driver = {
7496 .probe = gcc_x1e80100_probe,
7497 .driver = {
7498 .name = "gcc-x1e80100",
7499 .of_match_table = gcc_x1e80100_match_table,
7500 },
7501};
7502
7503static int __init gcc_x1e80100_init(void)
7504{
7505 return platform_driver_register(&gcc_x1e80100_driver);
7506}
7507subsys_initcall(gcc_x1e80100_init);
7508
7509static void __exit gcc_x1e80100_exit(void)
7510{
7511 platform_driver_unregister(&gcc_x1e80100_driver);
7512}
7513module_exit(gcc_x1e80100_exit);
7514
7515MODULE_DESCRIPTION("QTI GCC X1E80100 Driver");
7516MODULE_LICENSE("GPL");