Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * Copyright (c) 2014 MundoReader S.L.
4 * Author: Heiko Stuebner <heiko@sntech.de>
5 *
6 * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
7 * Author: Xing Zheng <zhengxing@rock-chips.com>
8 *
9 * based on
10 *
11 * samsung/clk.h
12 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
13 * Copyright (c) 2013 Linaro Ltd.
14 * Author: Thomas Abraham <thomas.ab@samsung.com>
15 */
16
17#ifndef CLK_ROCKCHIP_CLK_H
18#define CLK_ROCKCHIP_CLK_H
19
20#include <linux/io.h>
21#include <linux/clk-provider.h>
22#include <linux/hashtable.h>
23
24struct clk;
25
26#define HIWORD_UPDATE(val, mask, shift) \
27 ((val) << (shift) | (mask) << ((shift) + 16))
28
29/* register positions shared by PX30, RV1108, RK2928, RK3036, RK3066, RK3188 and RK3228 */
30#define BOOST_PLL_H_CON(x) ((x) * 0x4)
31#define BOOST_CLK_CON 0x0008
32#define BOOST_BOOST_CON 0x000c
33#define BOOST_SWITCH_CNT 0x0010
34#define BOOST_HIGH_PERF_CNT0 0x0014
35#define BOOST_HIGH_PERF_CNT1 0x0018
36#define BOOST_STATIS_THRESHOLD 0x001c
37#define BOOST_SHORT_SWITCH_CNT 0x0020
38#define BOOST_SWITCH_THRESHOLD 0x0024
39#define BOOST_FSM_STATUS 0x0028
40#define BOOST_PLL_L_CON(x) ((x) * 0x4 + 0x2c)
41#define BOOST_RECOVERY_MASK 0x1
42#define BOOST_RECOVERY_SHIFT 1
43#define BOOST_SW_CTRL_MASK 0x1
44#define BOOST_SW_CTRL_SHIFT 2
45#define BOOST_LOW_FREQ_EN_MASK 0x1
46#define BOOST_LOW_FREQ_EN_SHIFT 3
47#define BOOST_BUSY_STATE BIT(8)
48
49#define PX30_PLL_CON(x) ((x) * 0x4)
50#define PX30_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
51#define PX30_CLKGATE_CON(x) ((x) * 0x4 + 0x200)
52#define PX30_GLB_SRST_FST 0xb8
53#define PX30_GLB_SRST_SND 0xbc
54#define PX30_SOFTRST_CON(x) ((x) * 0x4 + 0x300)
55#define PX30_MODE_CON 0xa0
56#define PX30_MISC_CON 0xa4
57#define PX30_SDMMC_CON0 0x380
58#define PX30_SDMMC_CON1 0x384
59#define PX30_SDIO_CON0 0x388
60#define PX30_SDIO_CON1 0x38c
61#define PX30_EMMC_CON0 0x390
62#define PX30_EMMC_CON1 0x394
63
64#define PX30_PMU_PLL_CON(x) ((x) * 0x4)
65#define PX30_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x40)
66#define PX30_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x80)
67#define PX30_PMU_MODE 0x0020
68
69#define RV1103B_TOPCRU_BASE 0x60000
70#define RV1103B_PERICRU_BASE 0x0
71#define RV1103B_VICRU_BASE 0x30000
72#define RV1103B_NPUCRU_BASE 0x20000
73#define RV1103B_CORECRU_BASE 0x40000
74#define RV1103B_VEPUCRU_BASE 0x10000
75#define RV1103B_DDRCRU_BASE 0x50000
76#define RV1103B_SUBDDRCRU_BASE 0x58000
77#define RV1103B_PMUCRU_BASE 0x70000
78#define RV1103B_PMU1CRU_BASE 0x80000
79
80#define RV1103B_PMUCLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1103B_PMUCRU_BASE)
81#define RV1103B_PMUCLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1103B_PMUCRU_BASE)
82#define RV1103B_PMUSOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1103B_PMUCRU_BASE)
83#define RV1103B_PMU1CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1103B_PMU1CRU_BASE)
84#define RV1103B_PMU1CLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1103B_PMU1CRU_BASE)
85#define RV1103B_PMU1SOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1103B_PMU1CRU_BASE)
86#define RV1103B_PLL_CON(x) ((x) * 0x4 + RV1103B_TOPCRU_BASE)
87#define RV1103B_MODE_CON (0x280 + RV1103B_TOPCRU_BASE)
88#define RV1103B_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1103B_TOPCRU_BASE)
89#define RV1103B_CLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1103B_TOPCRU_BASE)
90#define RV1103B_SOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1103B_TOPCRU_BASE)
91#define RV1103B_GLB_SRST_FST (0xc08 + RV1103B_TOPCRU_BASE)
92#define RV1103B_GLB_SRST_SND (0xc0c + RV1103B_TOPCRU_BASE)
93#define RV1103B_CLK_SAI_FRAC_DIV_HIGH (0xcc0 + RV1103B_TOPCRU_BASE)
94#define RV1103B_PERICLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1103B_PERICRU_BASE)
95#define RV1103B_PERICLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1103B_PERICRU_BASE)
96#define RV1103B_PERISOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1103B_PERICRU_BASE)
97#define RV1103B_PERICRU_IP_CON (0xc08 + RV1103B_PERICRU_BASE)
98#define RV1103B_VICLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1103B_VICRU_BASE)
99#define RV1103B_VICLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1103B_VICRU_BASE)
100#define RV1103B_VISOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1103B_VICRU_BASE)
101#define RV1103B_NPUCLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1103B_NPUCRU_BASE)
102#define RV1103B_NPUCLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1103B_NPUCRU_BASE)
103#define RV1103B_NPUSOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1103B_NPUCRU_BASE)
104#define RV1103B_CORECLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1103B_CORECRU_BASE)
105#define RV1103B_CORECLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1103B_CORECRU_BASE)
106#define RV1103B_CORESOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1103B_CORECRU_BASE)
107#define RV1103B_VEPUCLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1103B_VEPUCRU_BASE)
108#define RV1103B_VEPUCLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1103B_VEPUCRU_BASE)
109#define RV1103B_VEPUSOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1103B_VEPUCRU_BASE)
110#define RV1103B_DDRCLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1103B_DDRCRU_BASE)
111#define RV1103B_DDRCLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1103B_DDRCRU_BASE)
112#define RV1103B_DDRSOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1103B_DDRCRU_BASE)
113#define RV1103B_SUBDDRCLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1103B_SUBDDRCRU_BASE)
114#define RV1103B_SUBDDRCLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1103B_SUBDDRCRU_BASE)
115#define RV1103B_SUBDDRSOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1103B_SUBDDRCRU_BASE)
116#define RV1103B_SUBDDRMODE_CON (0x280 + RV1103B_SUBDDRCRU_BASE)
117
118#define RV1108_PLL_CON(x) ((x) * 0x4)
119#define RV1108_CLKSEL_CON(x) ((x) * 0x4 + 0x60)
120#define RV1108_CLKGATE_CON(x) ((x) * 0x4 + 0x120)
121#define RV1108_SOFTRST_CON(x) ((x) * 0x4 + 0x180)
122#define RV1108_GLB_SRST_FST 0x1c0
123#define RV1108_GLB_SRST_SND 0x1c4
124#define RV1108_MISC_CON 0x1cc
125#define RV1108_SDMMC_CON0 0x1d8
126#define RV1108_SDMMC_CON1 0x1dc
127#define RV1108_SDIO_CON0 0x1e0
128#define RV1108_SDIO_CON1 0x1e4
129#define RV1108_EMMC_CON0 0x1e8
130#define RV1108_EMMC_CON1 0x1ec
131
132#define RV1126_PMU_MODE 0x0
133#define RV1126_PMU_PLL_CON(x) ((x) * 0x4 + 0x10)
134#define RV1126_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
135#define RV1126_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x180)
136#define RV1126_PMU_SOFTRST_CON(x) ((x) * 0x4 + 0x200)
137#define RV1126_PLL_CON(x) ((x) * 0x4)
138#define RV1126_MODE_CON 0x90
139#define RV1126_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
140#define RV1126_CLKGATE_CON(x) ((x) * 0x4 + 0x280)
141#define RV1126_SOFTRST_CON(x) ((x) * 0x4 + 0x300)
142#define RV1126_GLB_SRST_FST 0x408
143#define RV1126_GLB_SRST_SND 0x40c
144#define RV1126_SDMMC_CON0 0x440
145#define RV1126_SDMMC_CON1 0x444
146#define RV1126_SDIO_CON0 0x448
147#define RV1126_SDIO_CON1 0x44c
148#define RV1126_EMMC_CON0 0x450
149#define RV1126_EMMC_CON1 0x454
150
151#define RV1126B_TOPCRU_BASE 0x0
152#define RV1126B_BUSCRU_BASE 0x10000
153#define RV1126B_PERICRU_BASE 0x20000
154#define RV1126B_CORECRU_BASE 0x30000
155#define RV1126B_PMUCRU_BASE 0x40000
156#define RV1126B_PMU1CRU_BASE 0x50000
157#define RV1126B_DDRCRU_BASE 0x60000
158#define RV1126B_SUBDDRCRU_BASE 0x68000
159#define RV1126B_VICRU_BASE 0x70000
160#define RV1126B_VEPUCRU_BASE 0x80000
161#define RV1126B_NPUCRU_BASE 0x90000
162#define RV1126B_VDOCRU_BASE 0xA0000
163#define RV1126B_VCPCRU_BASE 0xB0000
164
165#define RV1126B_PLL_CON(x) ((x) * 0x4 + RV1126B_TOPCRU_BASE)
166#define RV1126B_MODE_CON (0x280 + RV1126B_TOPCRU_BASE)
167#define RV1126B_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1126B_TOPCRU_BASE)
168#define RV1126B_CLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1126B_TOPCRU_BASE)
169#define RV1126B_SOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1126B_TOPCRU_BASE)
170#define RV1126B_GLB_SRST_FST (0xc08 + RV1126B_TOPCRU_BASE)
171#define RV1126B_GLB_SRST_SND (0xc0c + RV1126B_TOPCRU_BASE)
172#define RV1126B_CLK_CM_FRAC0_DIV_H (0xcc0 + RV1126B_TOPCRU_BASE)
173#define RV1126B_CLK_CM_FRAC1_DIV_H (0xcc4 + RV1126B_TOPCRU_BASE)
174#define RV1126B_CLK_CM_FRAC2_DIV_H (0xcc8 + RV1126B_TOPCRU_BASE)
175#define RV1126B_CLK_UART_FRAC0_DIV_H (0xccc + RV1126B_TOPCRU_BASE)
176#define RV1126B_CLK_UART_FRAC1_DIV_H (0xcd0 + RV1126B_TOPCRU_BASE)
177#define RV1126B_CLK_AUDIO_FRAC0_DIV_H (0xcd4 + RV1126B_TOPCRU_BASE)
178#define RV1126B_CLK_AUDIO_FRAC1_DIV_H (0xcd8 + RV1126B_TOPCRU_BASE)
179#define RV1126B_BUSCLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1126B_BUSCRU_BASE)
180#define RV1126B_BUSCLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1126B_BUSCRU_BASE)
181#define RV1126B_BUSSOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1126B_BUSCRU_BASE)
182#define RV1126B_PERIPLL_CON(x) ((x) * 0x4 + RV1126B_PERICRU_BASE)
183#define RV1126B_PERICLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1126B_PERICRU_BASE)
184#define RV1126B_PERICLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1126B_PERICRU_BASE)
185#define RV1126B_PERISOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1126B_PERICRU_BASE)
186#define RV1126B_CORECLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1126B_CORECRU_BASE)
187#define RV1126B_CORECLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1126B_CORECRU_BASE)
188#define RV1126B_CORESOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1126B_CORECRU_BASE)
189#define RV1126B_PMUCLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1126B_PMUCRU_BASE)
190#define RV1126B_PMUCLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1126B_PMUCRU_BASE)
191#define RV1126B_PMUSOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1126B_PMUCRU_BASE)
192#define RV1126B_PMU1CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1126B_PMU1CRU_BASE)
193#define RV1126B_PMU1CLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1126B_PMU1CRU_BASE)
194#define RV1126B_PMU1SOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1126B_PMU1CRU_BASE)
195#define RV1126B_DDRCLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1126B_DDRCRU_BASE)
196#define RV1126B_DDRCLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1126B_DDRCRU_BASE)
197#define RV1126B_DDRSOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1126B_DDRCRU_BASE)
198#define RV1126B_SUBDDRPLL_CON(x) ((x) * 0x4 + RV1126B_SUBDDRCRU_BASE)
199#define RV1126B_SUBDDRCLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1126B_SUBDDRCRU_BASE)
200#define RV1126B_SUBDDRCLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1126B_SUBDDRCRU_BASE)
201#define RV1126B_SUBDDRSOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1126B_SUBDDRCRU_BASE)
202#define RV1126B_VICLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1126B_VICRU_BASE)
203#define RV1126B_VICLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1126B_VICRU_BASE)
204#define RV1126B_VISOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1126B_VICRU_BASE)
205#define RV1126B_VEPUCLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1126B_VEPUCRU_BASE)
206#define RV1126B_VEPUCLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1126B_VEPUCRU_BASE)
207#define RV1126B_VEPUSOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1126B_VEPUCRU_BASE)
208#define RV1126B_NPUCLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1126B_NPUCRU_BASE)
209#define RV1126B_NPUCLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1126B_NPUCRU_BASE)
210#define RV1126B_NPUSOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1126B_NPUCRU_BASE)
211#define RV1126B_VDOCLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1126B_VDOCRU_BASE)
212#define RV1126B_VDOCLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1126B_VDOCRU_BASE)
213#define RV1126B_VDOSOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1126B_VDOCRU_BASE)
214#define RV1126B_VCPCLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1126B_VCPCRU_BASE)
215#define RV1126B_VCPCLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1126B_VCPCRU_BASE)
216#define RV1126B_VCPSOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1126B_VCPCRU_BASE)
217
218#define RK2928_PLL_CON(x) ((x) * 0x4)
219#define RK2928_MODE_CON 0x40
220#define RK2928_CLKSEL_CON(x) ((x) * 0x4 + 0x44)
221#define RK2928_CLKGATE_CON(x) ((x) * 0x4 + 0xd0)
222#define RK2928_GLB_SRST_FST 0x100
223#define RK2928_GLB_SRST_SND 0x104
224#define RK2928_SOFTRST_CON(x) ((x) * 0x4 + 0x110)
225#define RK2928_MISC_CON 0x134
226
227#define RK3036_SDMMC_CON0 0x144
228#define RK3036_SDMMC_CON1 0x148
229#define RK3036_SDIO_CON0 0x14c
230#define RK3036_SDIO_CON1 0x150
231#define RK3036_EMMC_CON0 0x154
232#define RK3036_EMMC_CON1 0x158
233
234#define RK3228_GLB_SRST_FST 0x1f0
235#define RK3228_GLB_SRST_SND 0x1f4
236#define RK3228_SDMMC_CON0 0x1c0
237#define RK3228_SDMMC_CON1 0x1c4
238#define RK3228_SDIO_CON0 0x1c8
239#define RK3228_SDIO_CON1 0x1cc
240#define RK3228_EMMC_CON0 0x1d8
241#define RK3228_EMMC_CON1 0x1dc
242
243#define RK3288_PLL_CON(x) RK2928_PLL_CON(x)
244#define RK3288_MODE_CON 0x50
245#define RK3288_CLKSEL_CON(x) ((x) * 0x4 + 0x60)
246#define RK3288_CLKGATE_CON(x) ((x) * 0x4 + 0x160)
247#define RK3288_GLB_SRST_FST 0x1b0
248#define RK3288_GLB_SRST_SND 0x1b4
249#define RK3288_SOFTRST_CON(x) ((x) * 0x4 + 0x1b8)
250#define RK3288_MISC_CON 0x1e8
251#define RK3288_SDMMC_CON0 0x200
252#define RK3288_SDMMC_CON1 0x204
253#define RK3288_SDIO0_CON0 0x208
254#define RK3288_SDIO0_CON1 0x20c
255#define RK3288_SDIO1_CON0 0x210
256#define RK3288_SDIO1_CON1 0x214
257#define RK3288_EMMC_CON0 0x218
258#define RK3288_EMMC_CON1 0x21c
259
260#define RK3308_PLL_CON(x) RK2928_PLL_CON(x)
261#define RK3308_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
262#define RK3308_CLKGATE_CON(x) ((x) * 0x4 + 0x300)
263#define RK3308_GLB_SRST_FST 0xb8
264#define RK3308_SOFTRST_CON(x) ((x) * 0x4 + 0x400)
265#define RK3308_MODE_CON 0xa0
266#define RK3308_SDMMC_CON0 0x480
267#define RK3308_SDMMC_CON1 0x484
268#define RK3308_SDIO_CON0 0x488
269#define RK3308_SDIO_CON1 0x48c
270#define RK3308_EMMC_CON0 0x490
271#define RK3308_EMMC_CON1 0x494
272
273#define RK3328_PLL_CON(x) RK2928_PLL_CON(x)
274#define RK3328_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
275#define RK3328_CLKGATE_CON(x) ((x) * 0x4 + 0x200)
276#define RK3328_GRFCLKSEL_CON(x) ((x) * 0x4 + 0x100)
277#define RK3328_GLB_SRST_FST 0x9c
278#define RK3328_GLB_SRST_SND 0x98
279#define RK3328_SOFTRST_CON(x) ((x) * 0x4 + 0x300)
280#define RK3328_MODE_CON 0x80
281#define RK3328_MISC_CON 0x84
282#define RK3328_SDMMC_CON0 0x380
283#define RK3328_SDMMC_CON1 0x384
284#define RK3328_SDIO_CON0 0x388
285#define RK3328_SDIO_CON1 0x38c
286#define RK3328_EMMC_CON0 0x390
287#define RK3328_EMMC_CON1 0x394
288#define RK3328_SDMMC_EXT_CON0 0x398
289#define RK3328_SDMMC_EXT_CON1 0x39C
290
291#define RK3368_PLL_CON(x) RK2928_PLL_CON(x)
292#define RK3368_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
293#define RK3368_CLKGATE_CON(x) ((x) * 0x4 + 0x200)
294#define RK3368_GLB_SRST_FST 0x280
295#define RK3368_GLB_SRST_SND 0x284
296#define RK3368_SOFTRST_CON(x) ((x) * 0x4 + 0x300)
297#define RK3368_MISC_CON 0x380
298#define RK3368_SDMMC_CON0 0x400
299#define RK3368_SDMMC_CON1 0x404
300#define RK3368_SDIO0_CON0 0x408
301#define RK3368_SDIO0_CON1 0x40c
302#define RK3368_SDIO1_CON0 0x410
303#define RK3368_SDIO1_CON1 0x414
304#define RK3368_EMMC_CON0 0x418
305#define RK3368_EMMC_CON1 0x41c
306
307#define RK3399_PLL_CON(x) RK2928_PLL_CON(x)
308#define RK3399_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
309#define RK3399_CLKGATE_CON(x) ((x) * 0x4 + 0x300)
310#define RK3399_SOFTRST_CON(x) ((x) * 0x4 + 0x400)
311#define RK3399_GLB_SRST_FST 0x500
312#define RK3399_GLB_SRST_SND 0x504
313#define RK3399_GLB_CNT_TH 0x508
314#define RK3399_MISC_CON 0x50c
315#define RK3399_RST_CON 0x510
316#define RK3399_RST_ST 0x514
317#define RK3399_SDMMC_CON0 0x580
318#define RK3399_SDMMC_CON1 0x584
319#define RK3399_SDIO_CON0 0x588
320#define RK3399_SDIO_CON1 0x58c
321
322#define RK3399_PMU_PLL_CON(x) RK2928_PLL_CON(x)
323#define RK3399_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x80)
324#define RK3399_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x100)
325#define RK3399_PMU_SOFTRST_CON(x) ((x) * 0x4 + 0x110)
326
327#define RK3506_PMU_CRU_BASE 0x10000
328#define RK3506_PLL_CON(x) ((x) * 0x4 + RK3506_PMU_CRU_BASE)
329#define RK3506_CLKSEL_CON(x) ((x) * 0x4 + 0x300)
330#define RK3506_CLKGATE_CON(x) ((x) * 0x4 + 0x800)
331#define RK3506_SOFTRST_CON(x) ((x) * 0x4 + 0xa00)
332#define RK3506_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RK3506_PMU_CRU_BASE)
333#define RK3506_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x800 + RK3506_PMU_CRU_BASE)
334#define RK3506_MODE_CON 0x280
335#define RK3506_GLB_CNT_TH 0xc00
336#define RK3506_GLB_SRST_FST 0xc08
337#define RK3506_GLB_SRST_SND 0xc0c
338
339#define RK3528_PMU_CRU_BASE 0x10000
340#define RK3528_PCIE_CRU_BASE 0x20000
341#define RK3528_DDRPHY_CRU_BASE 0x28000
342#define RK3528_PLL_CON(x) RK2928_PLL_CON(x)
343#define RK3528_PCIE_PLL_CON(x) ((x) * 0x4 + RK3528_PCIE_CRU_BASE)
344#define RK3528_DDRPHY_PLL_CON(x) ((x) * 0x4 + RK3528_DDRPHY_CRU_BASE)
345#define RK3528_MODE_CON 0x280
346#define RK3528_CLKSEL_CON(x) ((x) * 0x4 + 0x300)
347#define RK3528_CLKGATE_CON(x) ((x) * 0x4 + 0x800)
348#define RK3528_SOFTRST_CON(x) ((x) * 0x4 + 0xa00)
349#define RK3528_SDMMC_CON(x) ((x) * 0x4 + 0x24)
350#define RK3528_SDIO0_CON(x) ((x) * 0x4 + 0x4)
351#define RK3528_SDIO1_CON(x) ((x) * 0x4 + 0xc)
352#define RK3528_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RK3528_PMU_CRU_BASE)
353#define RK3528_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x800 + RK3528_PMU_CRU_BASE)
354#define RK3528_PCIE_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RK3528_PCIE_CRU_BASE)
355#define RK3528_PCIE_CLKGATE_CON(x) ((x) * 0x4 + 0x800 + RK3528_PCIE_CRU_BASE)
356#define RK3528_DDRPHY_CLKGATE_CON(x) ((x) * 0x4 + 0x800 + RK3528_DDRPHY_CRU_BASE)
357#define RK3528_DDRPHY_MODE_CON (0x280 + RK3528_DDRPHY_CRU_BASE)
358#define RK3528_GLB_CNT_TH 0xc00
359#define RK3528_GLB_SRST_FST 0xc08
360#define RK3528_GLB_SRST_SND 0xc0c
361
362#define RK3562_PMU0_CRU_BASE 0x10000
363#define RK3562_PMU1_CRU_BASE 0x18000
364#define RK3562_DDR_CRU_BASE 0x20000
365#define RK3562_SUBDDR_CRU_BASE 0x28000
366#define RK3562_PERI_CRU_BASE 0x30000
367
368#define RK3562_PLL_CON(x) RK2928_PLL_CON(x)
369#define RK3562_PMU1_PLL_CON(x) ((x) * 0x4 + RK3562_PMU1_CRU_BASE + 0x40)
370#define RK3562_SUBDDR_PLL_CON(x) ((x) * 0x4 + RK3562_SUBDDR_CRU_BASE + 0x20)
371#define RK3562_MODE_CON 0x600
372#define RK3562_PMU1_MODE_CON (RK3562_PMU1_CRU_BASE + 0x380)
373#define RK3562_SUBDDR_MODE_CON (RK3562_SUBDDR_CRU_BASE + 0x380)
374#define RK3562_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
375#define RK3562_CLKGATE_CON(x) ((x) * 0x4 + 0x300)
376#define RK3562_SOFTRST_CON(x) ((x) * 0x4 + 0x400)
377#define RK3562_DDR_CLKSEL_CON(x) ((x) * 0x4 + RK3562_DDR_CRU_BASE + 0x100)
378#define RK3562_DDR_CLKGATE_CON(x) ((x) * 0x4 + RK3562_DDR_CRU_BASE + 0x180)
379#define RK3562_DDR_SOFTRST_CON(x) ((x) * 0x4 + RK3562_DDR_CRU_BASE + 0x200)
380#define RK3562_SUBDDR_CLKSEL_CON(x) ((x) * 0x4 + RK3562_SUBDDR_CRU_BASE + 0x100)
381#define RK3562_SUBDDR_CLKGATE_CON(x) ((x) * 0x4 + RK3562_SUBDDR_CRU_BASE + 0x180)
382#define RK3562_SUBDDR_SOFTRST_CON(x) ((x) * 0x4 + RK3562_SUBDDR_CRU_BASE + 0x200)
383#define RK3562_PERI_CLKSEL_CON(x) ((x) * 0x4 + RK3562_PERI_CRU_BASE + 0x100)
384#define RK3562_PERI_CLKGATE_CON(x) ((x) * 0x4 + RK3562_PERI_CRU_BASE + 0x300)
385#define RK3562_PERI_SOFTRST_CON(x) ((x) * 0x4 + RK3562_PERI_CRU_BASE + 0x400)
386#define RK3562_PMU0_CLKSEL_CON(x) ((x) * 0x4 + RK3562_PMU0_CRU_BASE + 0x100)
387#define RK3562_PMU0_CLKGATE_CON(x) ((x) * 0x4 + RK3562_PMU0_CRU_BASE + 0x180)
388#define RK3562_PMU0_SOFTRST_CON(x) ((x) * 0x4 + RK3562_PMU0_CRU_BASE + 0x200)
389#define RK3562_PMU1_CLKSEL_CON(x) ((x) * 0x4 + RK3562_PMU1_CRU_BASE + 0x100)
390#define RK3562_PMU1_CLKGATE_CON(x) ((x) * 0x4 + RK3562_PMU1_CRU_BASE + 0x180)
391#define RK3562_PMU1_SOFTRST_CON(x) ((x) * 0x4 + RK3562_PMU1_CRU_BASE + 0x200)
392#define RK3562_GLB_SRST_FST 0x614
393#define RK3562_GLB_SRST_SND 0x618
394#define RK3562_GLB_RST_CON 0x61c
395#define RK3562_GLB_RST_ST 0x620
396#define RK3562_SDMMC0_CON0 0x624
397#define RK3562_SDMMC0_CON1 0x628
398#define RK3562_SDMMC1_CON0 0x62c
399#define RK3562_SDMMC1_CON1 0x630
400
401#define RK3568_PLL_CON(x) RK2928_PLL_CON(x)
402#define RK3568_MODE_CON0 0xc0
403#define RK3568_MISC_CON0 0xc4
404#define RK3568_MISC_CON1 0xc8
405#define RK3568_MISC_CON2 0xcc
406#define RK3568_GLB_CNT_TH 0xd0
407#define RK3568_GLB_SRST_FST 0xd4
408#define RK3568_GLB_SRST_SND 0xd8
409#define RK3568_GLB_RST_CON 0xdc
410#define RK3568_GLB_RST_ST 0xe0
411#define RK3568_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
412#define RK3568_CLKGATE_CON(x) ((x) * 0x4 + 0x300)
413#define RK3568_SOFTRST_CON(x) ((x) * 0x4 + 0x400)
414#define RK3568_SDMMC0_CON0 0x580
415#define RK3568_SDMMC0_CON1 0x584
416#define RK3568_SDMMC1_CON0 0x588
417#define RK3568_SDMMC1_CON1 0x58c
418#define RK3568_SDMMC2_CON0 0x590
419#define RK3568_SDMMC2_CON1 0x594
420#define RK3568_EMMC_CON0 0x598
421#define RK3568_EMMC_CON1 0x59c
422
423#define RK3568_PMU_PLL_CON(x) RK2928_PLL_CON(x)
424#define RK3568_PMU_MODE_CON0 0x80
425#define RK3568_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
426#define RK3568_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x180)
427#define RK3568_PMU_SOFTRST_CON(x) ((x) * 0x4 + 0x200)
428
429#define RK3576_PHP_CRU_BASE 0x8000
430#define RK3576_SECURE_NS_CRU_BASE 0x10000
431#define RK3576_PMU_CRU_BASE 0x20000
432#define RK3576_BIGCORE_CRU_BASE 0x38000
433#define RK3576_LITCORE_CRU_BASE 0x40000
434#define RK3576_CCI_CRU_BASE 0x48000
435
436#define RK3576_PLL_CON(x) RK2928_PLL_CON(x)
437#define RK3576_MODE_CON0 0x280
438#define RK3576_BPLL_MODE_CON0 (RK3576_BIGCORE_CRU_BASE + 0x280)
439#define RK3576_LPLL_MODE_CON0 (RK3576_LITCORE_CRU_BASE + 0x280)
440#define RK3576_PPLL_MODE_CON0 (RK3576_PHP_CRU_BASE + 0x280)
441#define RK3576_CLKSEL_CON(x) ((x) * 0x4 + 0x300)
442#define RK3576_CLKGATE_CON(x) ((x) * 0x4 + 0x800)
443#define RK3576_SOFTRST_CON(x) ((x) * 0x4 + 0xa00)
444#define RK3576_GLB_CNT_TH 0xc00
445#define RK3576_GLB_SRST_FST 0xc08
446#define RK3576_GLB_SRST_SND 0xc0c
447#define RK3576_GLB_RST_CON 0xc10
448#define RK3576_GLB_RST_ST 0xc04
449#define RK3576_SDIO_CON0 0xC24
450#define RK3576_SDIO_CON1 0xC28
451#define RK3576_SDMMC_CON0 0xC30
452#define RK3576_SDMMC_CON1 0xC34
453
454#define RK3576_PHP_CLKSEL_CON(x) ((x) * 0x4 + RK3576_PHP_CRU_BASE + 0x300)
455#define RK3576_PHP_CLKGATE_CON(x) ((x) * 0x4 + RK3576_PHP_CRU_BASE + 0x800)
456#define RK3576_PHP_SOFTRST_CON(x) ((x) * 0x4 + RK3576_PHP_CRU_BASE + 0xa00)
457
458#define RK3576_PMU_PLL_CON(x) ((x) * 0x4 + RK3576_PHP_CRU_BASE)
459#define RK3576_PMU_CLKSEL_CON(x) ((x) * 0x4 + RK3576_PMU_CRU_BASE + 0x300)
460#define RK3576_PMU_CLKGATE_CON(x) ((x) * 0x4 + RK3576_PMU_CRU_BASE + 0x800)
461#define RK3576_PMU_SOFTRST_CON(x) ((x) * 0x4 + RK3576_PMU_CRU_BASE + 0xa00)
462
463#define RK3576_SECURE_NS_CLKSEL_CON(x) ((x) * 0x4 + RK3576_SECURE_NS_CRU_BASE + 0x300)
464#define RK3576_SECURE_NS_CLKGATE_CON(x) ((x) * 0x4 + RK3576_SECURE_NS_CRU_BASE + 0x800)
465#define RK3576_SECURE_NS_SOFTRST_CON(x) ((x) * 0x4 + RK3576_SECURE_NS_CRU_BASE + 0xa00)
466
467#define RK3576_CCI_CLKSEL_CON(x) ((x) * 0x4 + RK3576_CCI_CRU_BASE + 0x300)
468#define RK3576_CCI_CLKGATE_CON(x) ((x) * 0x4 + RK3576_CCI_CRU_BASE + 0x800)
469#define RK3576_CCI_SOFTRST_CON(x) ((x) * 0x4 + RK3576_CCI_CRU_BASE + 0xa00)
470
471#define RK3576_BPLL_CON(x) ((x) * 0x4 + RK3576_BIGCORE_CRU_BASE)
472#define RK3576_BIGCORE_CLKSEL_CON(x) ((x) * 0x4 + RK3576_BIGCORE_CRU_BASE + 0x300)
473#define RK3576_BIGCORE_CLKGATE_CON(x) ((x) * 0x4 + RK3576_BIGCORE_CRU_BASE + 0x800)
474#define RK3576_BIGCORE_SOFTRST_CON(x) ((x) * 0x4 + RK3576_BIGCORE_CRU_BASE + 0xa00)
475#define RK3576_LPLL_CON(x) ((x) * 0x4 + RK3576_CCI_CRU_BASE)
476#define RK3576_LITCORE_CLKSEL_CON(x) ((x) * 0x4 + RK3576_LITCORE_CRU_BASE + 0x300)
477#define RK3576_LITCORE_CLKGATE_CON(x) ((x) * 0x4 + RK3576_LITCORE_CRU_BASE + 0x800)
478#define RK3576_LITCORE_SOFTRST_CON(x) ((x) * 0x4 + RK3576_LITCORE_CRU_BASE + 0xa00)
479#define RK3576_NON_SECURE_GATING_CON00 0xc48
480
481#define RK3588_PHP_CRU_BASE 0x8000
482#define RK3588_PMU_CRU_BASE 0x30000
483#define RK3588_BIGCORE0_CRU_BASE 0x50000
484#define RK3588_BIGCORE1_CRU_BASE 0x52000
485#define RK3588_DSU_CRU_BASE 0x58000
486
487#define RK3588_PLL_CON(x) RK2928_PLL_CON(x)
488#define RK3588_MODE_CON0 0x280
489#define RK3588_B0_PLL_MODE_CON0 (RK3588_BIGCORE0_CRU_BASE + 0x280)
490#define RK3588_B1_PLL_MODE_CON0 (RK3588_BIGCORE1_CRU_BASE + 0x280)
491#define RK3588_LPLL_MODE_CON0 (RK3588_DSU_CRU_BASE + 0x280)
492#define RK3588_CLKSEL_CON(x) ((x) * 0x4 + 0x300)
493#define RK3588_CLKGATE_CON(x) ((x) * 0x4 + 0x800)
494#define RK3588_SOFTRST_CON(x) ((x) * 0x4 + 0xa00)
495#define RK3588_GLB_CNT_TH 0xc00
496#define RK3588_GLB_SRST_FST 0xc08
497#define RK3588_GLB_SRST_SND 0xc0c
498#define RK3588_GLB_RST_CON 0xc10
499#define RK3588_GLB_RST_ST 0xc04
500#define RK3588_SDIO_CON0 0xC24
501#define RK3588_SDIO_CON1 0xC28
502#define RK3588_SDMMC_CON0 0xC30
503#define RK3588_SDMMC_CON1 0xC34
504
505#define RK3588_PHP_CLKGATE_CON(x) ((x) * 0x4 + RK3588_PHP_CRU_BASE + 0x800)
506#define RK3588_PHP_SOFTRST_CON(x) ((x) * 0x4 + RK3588_PHP_CRU_BASE + 0xa00)
507
508#define RK3588_PMU_PLL_CON(x) ((x) * 0x4 + RK3588_PHP_CRU_BASE)
509#define RK3588_PMU_CLKSEL_CON(x) ((x) * 0x4 + RK3588_PMU_CRU_BASE + 0x300)
510#define RK3588_PMU_CLKGATE_CON(x) ((x) * 0x4 + RK3588_PMU_CRU_BASE + 0x800)
511#define RK3588_PMU_SOFTRST_CON(x) ((x) * 0x4 + RK3588_PMU_CRU_BASE + 0xa00)
512
513#define RK3588_B0_PLL_CON(x) ((x) * 0x4 + RK3588_BIGCORE0_CRU_BASE)
514#define RK3588_BIGCORE0_CLKSEL_CON(x) ((x) * 0x4 + RK3588_BIGCORE0_CRU_BASE + 0x300)
515#define RK3588_BIGCORE0_CLKGATE_CON(x) ((x) * 0x4 + RK3588_BIGCORE0_CRU_BASE + 0x800)
516#define RK3588_BIGCORE0_SOFTRST_CON(x) ((x) * 0x4 + RK3588_BIGCORE0_CRU_BASE + 0xa00)
517#define RK3588_B1_PLL_CON(x) ((x) * 0x4 + RK3588_BIGCORE1_CRU_BASE)
518#define RK3588_BIGCORE1_CLKSEL_CON(x) ((x) * 0x4 + RK3588_BIGCORE1_CRU_BASE + 0x300)
519#define RK3588_BIGCORE1_CLKGATE_CON(x) ((x) * 0x4 + RK3588_BIGCORE1_CRU_BASE + 0x800)
520#define RK3588_BIGCORE1_SOFTRST_CON(x) ((x) * 0x4 + RK3588_BIGCORE1_CRU_BASE + 0xa00)
521#define RK3588_LPLL_CON(x) ((x) * 0x4 + RK3588_DSU_CRU_BASE)
522#define RK3588_DSU_CLKSEL_CON(x) ((x) * 0x4 + RK3588_DSU_CRU_BASE + 0x300)
523#define RK3588_DSU_CLKGATE_CON(x) ((x) * 0x4 + RK3588_DSU_CRU_BASE + 0x800)
524#define RK3588_DSU_SOFTRST_CON(x) ((x) * 0x4 + RK3588_DSU_CRU_BASE + 0xa00)
525
526enum rockchip_pll_type {
527 pll_rk3036,
528 pll_rk3066,
529 pll_rk3328,
530 pll_rk3399,
531 pll_rk3588,
532 pll_rk3588_core,
533 pll_rk3588_ddr,
534};
535
536#define RK3036_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1, \
537 _postdiv2, _dsmpd, _frac) \
538{ \
539 .rate = _rate##U, \
540 .fbdiv = _fbdiv, \
541 .postdiv1 = _postdiv1, \
542 .refdiv = _refdiv, \
543 .postdiv2 = _postdiv2, \
544 .dsmpd = _dsmpd, \
545 .frac = _frac, \
546}
547
548#define RK3066_PLL_RATE(_rate, _nr, _nf, _no) \
549{ \
550 .rate = _rate##U, \
551 .nr = _nr, \
552 .nf = _nf, \
553 .no = _no, \
554 .nb = ((_nf) < 2) ? 1 : (_nf) >> 1, \
555}
556
557#define RK3066_PLL_RATE_NB(_rate, _nr, _nf, _no, _nb) \
558{ \
559 .rate = _rate##U, \
560 .nr = _nr, \
561 .nf = _nf, \
562 .no = _no, \
563 .nb = _nb, \
564}
565
566#define RK3588_PLL_RATE(_rate, _p, _m, _s, _k) \
567{ \
568 .rate = _rate##U, \
569 .p = _p, \
570 .m = _m, \
571 .s = _s, \
572 .k = _k, \
573}
574
575enum rockchip_grf_type {
576 grf_type_sys = 0,
577 grf_type_pmu0,
578 grf_type_pmu1,
579 grf_type_ioc,
580 grf_type_vo,
581 grf_type_vpu,
582};
583
584/* ceil(sqrt(enums in rockchip_grf_type - 1)) */
585#define GRF_HASH_ORDER 2
586
587/**
588 * struct rockchip_aux_grf - entry for the aux_grf_table hashtable
589 * @grf: pointer to the grf this entry references
590 * @type: what type of GRF this is
591 * @node: hlist node
592 */
593struct rockchip_aux_grf {
594 struct regmap *grf;
595 enum rockchip_grf_type type;
596 struct hlist_node node;
597};
598
599/**
600 * struct rockchip_clk_provider - information about clock provider
601 * @reg_base: virtual address for the register base.
602 * @clk_data: holds clock related data like clk* and number of clocks.
603 * @cru_node: device-node of the clock-provider
604 * @grf: regmap of the general-register-files syscon
605 * @aux_grf_table: hashtable of auxiliary GRF regmaps, indexed by grf_type
606 * @lock: maintains exclusion between callbacks for a given clock-provider.
607 */
608struct rockchip_clk_provider {
609 void __iomem *reg_base;
610 struct clk_onecell_data clk_data;
611 struct device_node *cru_node;
612 struct regmap *grf;
613 DECLARE_HASHTABLE(aux_grf_table, GRF_HASH_ORDER);
614 spinlock_t lock;
615};
616
617struct rockchip_pll_rate_table {
618 unsigned long rate;
619 union {
620 struct {
621 /* for RK3066 */
622 unsigned int nr;
623 unsigned int nf;
624 unsigned int no;
625 unsigned int nb;
626 };
627 struct {
628 /* for RK3036/RK3399 */
629 unsigned int fbdiv;
630 unsigned int postdiv1;
631 unsigned int refdiv;
632 unsigned int postdiv2;
633 unsigned int dsmpd;
634 unsigned int frac;
635 };
636 struct {
637 /* for RK3588 */
638 unsigned int m;
639 unsigned int p;
640 unsigned int s;
641 unsigned int k;
642 };
643 };
644};
645
646/**
647 * struct rockchip_pll_clock - information about pll clock
648 * @id: platform specific id of the clock.
649 * @name: name of this pll clock.
650 * @parent_names: name of the parent clock.
651 * @num_parents: number of parents
652 * @flags: optional flags for basic clock.
653 * @con_offset: offset of the register for configuring the PLL.
654 * @mode_offset: offset of the register for configuring the PLL-mode.
655 * @mode_shift: offset inside the mode-register for the mode of this pll.
656 * @lock_shift: offset inside the lock register for the lock status.
657 * @type: Type of PLL to be registered.
658 * @pll_flags: hardware-specific flags
659 * @rate_table: Table of usable pll rates
660 *
661 * Flags:
662 * ROCKCHIP_PLL_SYNC_RATE - check rate parameters to match against the
663 * rate_table parameters and adjust them if necessary.
664 * ROCKCHIP_PLL_FIXED_MODE - the pll operates in normal mode only
665 */
666struct rockchip_pll_clock {
667 unsigned int id;
668 const char *name;
669 const char *const *parent_names;
670 u8 num_parents;
671 unsigned long flags;
672 int con_offset;
673 int mode_offset;
674 int mode_shift;
675 int lock_shift;
676 enum rockchip_pll_type type;
677 u8 pll_flags;
678 struct rockchip_pll_rate_table *rate_table;
679};
680
681#define ROCKCHIP_PLL_SYNC_RATE BIT(0)
682#define ROCKCHIP_PLL_FIXED_MODE BIT(1)
683
684#define PLL(_type, _id, _name, _pnames, _flags, _con, _mode, _mshift, \
685 _lshift, _pflags, _rtable) \
686 { \
687 .id = _id, \
688 .type = _type, \
689 .name = _name, \
690 .parent_names = _pnames, \
691 .num_parents = ARRAY_SIZE(_pnames), \
692 .flags = CLK_GET_RATE_NOCACHE | _flags, \
693 .con_offset = _con, \
694 .mode_offset = _mode, \
695 .mode_shift = _mshift, \
696 .lock_shift = _lshift, \
697 .pll_flags = _pflags, \
698 .rate_table = _rtable, \
699 }
700
701struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx,
702 enum rockchip_pll_type pll_type,
703 const char *name, const char *const *parent_names,
704 u8 num_parents, int con_offset, int grf_lock_offset,
705 int lock_shift, int mode_offset, int mode_shift,
706 struct rockchip_pll_rate_table *rate_table,
707 unsigned long flags, u8 clk_pll_flags);
708
709struct rockchip_cpuclk_clksel {
710 int reg;
711 u32 val;
712};
713
714#define ROCKCHIP_CPUCLK_NUM_DIVIDERS 6
715#define ROCKCHIP_CPUCLK_MAX_CORES 4
716struct rockchip_cpuclk_rate_table {
717 unsigned long prate;
718 struct rockchip_cpuclk_clksel divs[ROCKCHIP_CPUCLK_NUM_DIVIDERS];
719 struct rockchip_cpuclk_clksel pre_muxs[ROCKCHIP_CPUCLK_NUM_DIVIDERS];
720 struct rockchip_cpuclk_clksel post_muxs[ROCKCHIP_CPUCLK_NUM_DIVIDERS];
721};
722
723/**
724 * struct rockchip_cpuclk_reg_data - register offsets and masks of the cpuclock
725 * @core_reg[]: register offset of the cores setting register
726 * @div_core_shift[]: cores divider offset used to divide the pll value
727 * @div_core_mask[]: cores divider mask
728 * @num_cores: number of cpu cores
729 * @mux_core_reg: register offset of the cores select parent
730 * @mux_core_alt: mux value to select alternate parent
731 * @mux_core_main: mux value to select main parent of core
732 * @mux_core_shift: offset of the core multiplexer
733 * @mux_core_mask: core multiplexer mask
734 */
735struct rockchip_cpuclk_reg_data {
736 int core_reg[ROCKCHIP_CPUCLK_MAX_CORES];
737 u8 div_core_shift[ROCKCHIP_CPUCLK_MAX_CORES];
738 u32 div_core_mask[ROCKCHIP_CPUCLK_MAX_CORES];
739 int num_cores;
740 int mux_core_reg;
741 u8 mux_core_alt;
742 u8 mux_core_main;
743 u8 mux_core_shift;
744 u32 mux_core_mask;
745};
746
747struct clk *rockchip_clk_register_cpuclk(const char *name,
748 const char *const *parent_names, u8 num_parents,
749 const struct rockchip_cpuclk_reg_data *reg_data,
750 const struct rockchip_cpuclk_rate_table *rates,
751 int nrates, void __iomem *reg_base, spinlock_t *lock);
752
753struct clk *rockchip_clk_register_cpuclk_multi_pll(const char *name,
754 const char *const *parent_names,
755 u8 num_parents, void __iomem *base,
756 int muxdiv_offset, u8 mux_shift,
757 u8 mux_width, u8 mux_flags,
758 int div_offset, u8 div_shift,
759 u8 div_width, u8 div_flags,
760 unsigned long flags, spinlock_t *lock,
761 const struct rockchip_cpuclk_rate_table *rates,
762 int nrates);
763
764struct clk *rockchip_clk_register_mmc(const char *name,
765 const char *const *parent_names, u8 num_parents,
766 void __iomem *reg,
767 struct regmap *grf, int grf_reg,
768 int shift);
769
770/*
771 * DDRCLK flags, including method of setting the rate
772 * ROCKCHIP_DDRCLK_SIP: use SIP call to bl31 to change ddrclk rate.
773 */
774#define ROCKCHIP_DDRCLK_SIP BIT(0)
775
776struct clk *rockchip_clk_register_ddrclk(const char *name, int flags,
777 const char *const *parent_names,
778 u8 num_parents, int mux_offset,
779 int mux_shift, int mux_width,
780 int div_shift, int div_width,
781 int ddr_flags, void __iomem *reg_base,
782 spinlock_t *lock);
783
784#define ROCKCHIP_INVERTER_HIWORD_MASK BIT(0)
785
786struct clk *rockchip_clk_register_inverter(const char *name,
787 const char *const *parent_names, u8 num_parents,
788 void __iomem *reg, int shift, int flags,
789 spinlock_t *lock);
790
791struct clk *rockchip_clk_register_muxgrf(const char *name,
792 const char *const *parent_names, u8 num_parents,
793 int flags, struct regmap *grf, int reg,
794 int shift, int width, int mux_flags);
795
796struct clk *rockchip_clk_register_gate_grf(const char *name,
797 const char *parent_name, unsigned long flags,
798 struct regmap *regmap, unsigned int reg,
799 unsigned int shift, u8 gate_flags);
800
801#define PNAME(x) static const char *const x[] __initconst
802
803enum rockchip_clk_branch_type {
804 branch_composite,
805 branch_mux,
806 branch_grf_mux,
807 branch_divider,
808 branch_fraction_divider,
809 branch_gate,
810 branch_grf_gate,
811 branch_linked_gate,
812 branch_mmc,
813 branch_grf_mmc,
814 branch_inverter,
815 branch_factor,
816 branch_ddrclk,
817 branch_half_divider,
818};
819
820struct rockchip_clk_branch {
821 unsigned int id;
822 enum rockchip_clk_branch_type branch_type;
823 const char *name;
824 const char *const *parent_names;
825 u8 num_parents;
826 unsigned long flags;
827 int muxdiv_offset;
828 u8 mux_shift;
829 u8 mux_width;
830 u8 mux_flags;
831 u32 *mux_table;
832 int div_offset;
833 u8 div_shift;
834 u8 div_width;
835 u8 div_flags;
836 struct clk_div_table *div_table;
837 int gate_offset;
838 u8 gate_shift;
839 u8 gate_flags;
840 unsigned int linked_clk_id;
841 enum rockchip_grf_type grf_type;
842 struct rockchip_clk_branch *child;
843};
844
845#define COMPOSITE(_id, cname, pnames, f, mo, ms, mw, mf, ds, dw,\
846 df, go, gs, gf) \
847 { \
848 .id = _id, \
849 .branch_type = branch_composite, \
850 .name = cname, \
851 .parent_names = pnames, \
852 .num_parents = ARRAY_SIZE(pnames), \
853 .flags = f, \
854 .muxdiv_offset = mo, \
855 .mux_shift = ms, \
856 .mux_width = mw, \
857 .mux_flags = mf, \
858 .div_shift = ds, \
859 .div_width = dw, \
860 .div_flags = df, \
861 .gate_offset = go, \
862 .gate_shift = gs, \
863 .gate_flags = gf, \
864 }
865
866#define COMPOSITE_DIV_OFFSET(_id, cname, pnames, f, mo, ms, mw, \
867 mf, do, ds, dw, df, go, gs, gf) \
868 { \
869 .id = _id, \
870 .branch_type = branch_composite, \
871 .name = cname, \
872 .parent_names = pnames, \
873 .num_parents = ARRAY_SIZE(pnames), \
874 .flags = f, \
875 .muxdiv_offset = mo, \
876 .mux_shift = ms, \
877 .mux_width = mw, \
878 .mux_flags = mf, \
879 .div_offset = do, \
880 .div_shift = ds, \
881 .div_width = dw, \
882 .div_flags = df, \
883 .gate_offset = go, \
884 .gate_shift = gs, \
885 .gate_flags = gf, \
886 }
887
888#define COMPOSITE_NOMUX(_id, cname, pname, f, mo, ds, dw, df, \
889 go, gs, gf) \
890 { \
891 .id = _id, \
892 .branch_type = branch_composite, \
893 .name = cname, \
894 .parent_names = (const char *[]){ pname }, \
895 .num_parents = 1, \
896 .flags = f, \
897 .muxdiv_offset = mo, \
898 .div_shift = ds, \
899 .div_width = dw, \
900 .div_flags = df, \
901 .gate_offset = go, \
902 .gate_shift = gs, \
903 .gate_flags = gf, \
904 }
905
906#define COMPOSITE_NOMUX_DIVTBL(_id, cname, pname, f, mo, ds, dw,\
907 df, dt, go, gs, gf) \
908 { \
909 .id = _id, \
910 .branch_type = branch_composite, \
911 .name = cname, \
912 .parent_names = (const char *[]){ pname }, \
913 .num_parents = 1, \
914 .flags = f, \
915 .muxdiv_offset = mo, \
916 .div_shift = ds, \
917 .div_width = dw, \
918 .div_flags = df, \
919 .div_table = dt, \
920 .gate_offset = go, \
921 .gate_shift = gs, \
922 .gate_flags = gf, \
923 }
924
925#define COMPOSITE_NODIV(_id, cname, pnames, f, mo, ms, mw, mf, \
926 go, gs, gf) \
927 { \
928 .id = _id, \
929 .branch_type = branch_composite, \
930 .name = cname, \
931 .parent_names = pnames, \
932 .num_parents = ARRAY_SIZE(pnames), \
933 .flags = f, \
934 .muxdiv_offset = mo, \
935 .mux_shift = ms, \
936 .mux_width = mw, \
937 .mux_flags = mf, \
938 .gate_offset = go, \
939 .gate_shift = gs, \
940 .gate_flags = gf, \
941 }
942
943#define COMPOSITE_NOGATE(_id, cname, pnames, f, mo, ms, mw, mf, \
944 ds, dw, df) \
945 { \
946 .id = _id, \
947 .branch_type = branch_composite, \
948 .name = cname, \
949 .parent_names = pnames, \
950 .num_parents = ARRAY_SIZE(pnames), \
951 .flags = f, \
952 .muxdiv_offset = mo, \
953 .mux_shift = ms, \
954 .mux_width = mw, \
955 .mux_flags = mf, \
956 .div_shift = ds, \
957 .div_width = dw, \
958 .div_flags = df, \
959 .gate_offset = -1, \
960 }
961
962#define COMPOSITE_NOGATE_DIVTBL(_id, cname, pnames, f, mo, ms, \
963 mw, mf, ds, dw, df, dt) \
964 { \
965 .id = _id, \
966 .branch_type = branch_composite, \
967 .name = cname, \
968 .parent_names = pnames, \
969 .num_parents = ARRAY_SIZE(pnames), \
970 .flags = f, \
971 .muxdiv_offset = mo, \
972 .mux_shift = ms, \
973 .mux_width = mw, \
974 .mux_flags = mf, \
975 .div_shift = ds, \
976 .div_width = dw, \
977 .div_flags = df, \
978 .div_table = dt, \
979 .gate_offset = -1, \
980 }
981
982#define COMPOSITE_FRAC(_id, cname, pname, f, mo, df, go, gs, gf)\
983 { \
984 .id = _id, \
985 .branch_type = branch_fraction_divider, \
986 .name = cname, \
987 .parent_names = (const char *[]){ pname }, \
988 .num_parents = 1, \
989 .flags = f, \
990 .muxdiv_offset = mo, \
991 .div_shift = 16, \
992 .div_width = 16, \
993 .div_flags = df, \
994 .gate_offset = go, \
995 .gate_shift = gs, \
996 .gate_flags = gf, \
997 }
998
999#define COMPOSITE_FRACMUX(_id, cname, pname, f, mo, df, go, gs, gf, ch) \
1000 { \
1001 .id = _id, \
1002 .branch_type = branch_fraction_divider, \
1003 .name = cname, \
1004 .parent_names = (const char *[]){ pname }, \
1005 .num_parents = 1, \
1006 .flags = f, \
1007 .muxdiv_offset = mo, \
1008 .div_shift = 16, \
1009 .div_width = 16, \
1010 .div_flags = df, \
1011 .gate_offset = go, \
1012 .gate_shift = gs, \
1013 .gate_flags = gf, \
1014 .child = ch, \
1015 }
1016
1017#define COMPOSITE_FRACMUX_NOGATE(_id, cname, pname, f, mo, df, ch) \
1018 { \
1019 .id = _id, \
1020 .branch_type = branch_fraction_divider, \
1021 .name = cname, \
1022 .parent_names = (const char *[]){ pname }, \
1023 .num_parents = 1, \
1024 .flags = f, \
1025 .muxdiv_offset = mo, \
1026 .div_shift = 16, \
1027 .div_width = 16, \
1028 .div_flags = df, \
1029 .gate_offset = -1, \
1030 .child = ch, \
1031 }
1032
1033#define COMPOSITE_DDRCLK(_id, cname, pnames, f, mo, ms, mw, \
1034 ds, dw, df) \
1035 { \
1036 .id = _id, \
1037 .branch_type = branch_ddrclk, \
1038 .name = cname, \
1039 .parent_names = pnames, \
1040 .num_parents = ARRAY_SIZE(pnames), \
1041 .flags = f, \
1042 .muxdiv_offset = mo, \
1043 .mux_shift = ms, \
1044 .mux_width = mw, \
1045 .div_shift = ds, \
1046 .div_width = dw, \
1047 .div_flags = df, \
1048 .gate_offset = -1, \
1049 }
1050
1051#define MUX(_id, cname, pnames, f, o, s, w, mf) \
1052 { \
1053 .id = _id, \
1054 .branch_type = branch_mux, \
1055 .name = cname, \
1056 .parent_names = pnames, \
1057 .num_parents = ARRAY_SIZE(pnames), \
1058 .flags = f, \
1059 .muxdiv_offset = o, \
1060 .mux_shift = s, \
1061 .mux_width = w, \
1062 .mux_flags = mf, \
1063 .gate_offset = -1, \
1064 }
1065
1066#define MUXTBL(_id, cname, pnames, f, o, s, w, mf, mt) \
1067 { \
1068 .id = _id, \
1069 .branch_type = branch_mux, \
1070 .name = cname, \
1071 .parent_names = pnames, \
1072 .num_parents = ARRAY_SIZE(pnames), \
1073 .flags = f, \
1074 .muxdiv_offset = o, \
1075 .mux_shift = s, \
1076 .mux_width = w, \
1077 .mux_flags = mf, \
1078 .gate_offset = -1, \
1079 .mux_table = mt, \
1080 }
1081
1082#define MUXGRF(_id, cname, pnames, f, o, s, w, mf, gt) \
1083 { \
1084 .id = _id, \
1085 .branch_type = branch_grf_mux, \
1086 .name = cname, \
1087 .parent_names = pnames, \
1088 .num_parents = ARRAY_SIZE(pnames), \
1089 .flags = f, \
1090 .muxdiv_offset = o, \
1091 .mux_shift = s, \
1092 .mux_width = w, \
1093 .mux_flags = mf, \
1094 .gate_offset = -1, \
1095 .grf_type = gt, \
1096 }
1097
1098#define DIV(_id, cname, pname, f, o, s, w, df) \
1099 { \
1100 .id = _id, \
1101 .branch_type = branch_divider, \
1102 .name = cname, \
1103 .parent_names = (const char *[]){ pname }, \
1104 .num_parents = 1, \
1105 .flags = f, \
1106 .muxdiv_offset = o, \
1107 .div_shift = s, \
1108 .div_width = w, \
1109 .div_flags = df, \
1110 .gate_offset = -1, \
1111 }
1112
1113#define DIVTBL(_id, cname, pname, f, o, s, w, df, dt) \
1114 { \
1115 .id = _id, \
1116 .branch_type = branch_divider, \
1117 .name = cname, \
1118 .parent_names = (const char *[]){ pname }, \
1119 .num_parents = 1, \
1120 .flags = f, \
1121 .muxdiv_offset = o, \
1122 .div_shift = s, \
1123 .div_width = w, \
1124 .div_flags = df, \
1125 .div_table = dt, \
1126 }
1127
1128#define GATE(_id, cname, pname, f, o, b, gf) \
1129 { \
1130 .id = _id, \
1131 .branch_type = branch_gate, \
1132 .name = cname, \
1133 .parent_names = (const char *[]){ pname }, \
1134 .num_parents = 1, \
1135 .flags = f, \
1136 .gate_offset = o, \
1137 .gate_shift = b, \
1138 .gate_flags = gf, \
1139 }
1140
1141#define GATE_GRF(_id, cname, pname, f, o, b, gf, gt) \
1142 { \
1143 .id = _id, \
1144 .branch_type = branch_grf_gate, \
1145 .name = cname, \
1146 .parent_names = (const char *[]){ pname }, \
1147 .num_parents = 1, \
1148 .flags = f, \
1149 .gate_offset = o, \
1150 .gate_shift = b, \
1151 .gate_flags = gf, \
1152 .grf_type = gt, \
1153 }
1154
1155#define GATE_LINK(_id, cname, pname, linkedclk, f, o, b, gf) \
1156 { \
1157 .id = _id, \
1158 .branch_type = branch_linked_gate, \
1159 .name = cname, \
1160 .parent_names = (const char *[]){ pname }, \
1161 .linked_clk_id = linkedclk, \
1162 .num_parents = 1, \
1163 .flags = f, \
1164 .gate_offset = o, \
1165 .gate_shift = b, \
1166 .gate_flags = gf, \
1167 }
1168
1169#define MMC(_id, cname, pname, offset, shift) \
1170 { \
1171 .id = _id, \
1172 .branch_type = branch_mmc, \
1173 .name = cname, \
1174 .parent_names = (const char *[]){ pname }, \
1175 .num_parents = 1, \
1176 .muxdiv_offset = offset, \
1177 .div_shift = shift, \
1178 }
1179
1180#define MMC_GRF(_id, cname, pname, offset, shift, grftype) \
1181 { \
1182 .id = _id, \
1183 .branch_type = branch_grf_mmc, \
1184 .name = cname, \
1185 .parent_names = (const char *[]){ pname }, \
1186 .num_parents = 1, \
1187 .muxdiv_offset = offset, \
1188 .div_shift = shift, \
1189 .grf_type = grftype, \
1190 }
1191
1192#define INVERTER(_id, cname, pname, io, is, if) \
1193 { \
1194 .id = _id, \
1195 .branch_type = branch_inverter, \
1196 .name = cname, \
1197 .parent_names = (const char *[]){ pname }, \
1198 .num_parents = 1, \
1199 .muxdiv_offset = io, \
1200 .div_shift = is, \
1201 .div_flags = if, \
1202 }
1203
1204#define FACTOR(_id, cname, pname, f, fm, fd) \
1205 { \
1206 .id = _id, \
1207 .branch_type = branch_factor, \
1208 .name = cname, \
1209 .parent_names = (const char *[]){ pname }, \
1210 .num_parents = 1, \
1211 .flags = f, \
1212 .div_shift = fm, \
1213 .div_width = fd, \
1214 }
1215
1216#define FACTOR_GATE(_id, cname, pname, f, fm, fd, go, gb, gf) \
1217 { \
1218 .id = _id, \
1219 .branch_type = branch_factor, \
1220 .name = cname, \
1221 .parent_names = (const char *[]){ pname }, \
1222 .num_parents = 1, \
1223 .flags = f, \
1224 .div_shift = fm, \
1225 .div_width = fd, \
1226 .gate_offset = go, \
1227 .gate_shift = gb, \
1228 .gate_flags = gf, \
1229 }
1230
1231#define COMPOSITE_HALFDIV(_id, cname, pnames, f, mo, ms, mw, mf, ds, dw,\
1232 df, go, gs, gf) \
1233 { \
1234 .id = _id, \
1235 .branch_type = branch_half_divider, \
1236 .name = cname, \
1237 .parent_names = pnames, \
1238 .num_parents = ARRAY_SIZE(pnames), \
1239 .flags = f, \
1240 .muxdiv_offset = mo, \
1241 .mux_shift = ms, \
1242 .mux_width = mw, \
1243 .mux_flags = mf, \
1244 .div_shift = ds, \
1245 .div_width = dw, \
1246 .div_flags = df, \
1247 .gate_offset = go, \
1248 .gate_shift = gs, \
1249 .gate_flags = gf, \
1250 }
1251
1252#define COMPOSITE_NOGATE_HALFDIV(_id, cname, pnames, f, mo, ms, mw, mf, \
1253 ds, dw, df) \
1254 { \
1255 .id = _id, \
1256 .branch_type = branch_half_divider, \
1257 .name = cname, \
1258 .parent_names = pnames, \
1259 .num_parents = ARRAY_SIZE(pnames), \
1260 .flags = f, \
1261 .muxdiv_offset = mo, \
1262 .mux_shift = ms, \
1263 .mux_width = mw, \
1264 .mux_flags = mf, \
1265 .div_shift = ds, \
1266 .div_width = dw, \
1267 .div_flags = df, \
1268 .gate_offset = -1, \
1269 }
1270
1271#define COMPOSITE_NOMUX_HALFDIV(_id, cname, pname, f, mo, ds, dw, df, \
1272 go, gs, gf) \
1273 { \
1274 .id = _id, \
1275 .branch_type = branch_half_divider, \
1276 .name = cname, \
1277 .parent_names = (const char *[]){ pname }, \
1278 .num_parents = 1, \
1279 .flags = f, \
1280 .muxdiv_offset = mo, \
1281 .div_shift = ds, \
1282 .div_width = dw, \
1283 .div_flags = df, \
1284 .gate_offset = go, \
1285 .gate_shift = gs, \
1286 .gate_flags = gf, \
1287 }
1288
1289#define DIV_HALF(_id, cname, pname, f, o, s, w, df) \
1290 { \
1291 .id = _id, \
1292 .branch_type = branch_half_divider, \
1293 .name = cname, \
1294 .parent_names = (const char *[]){ pname }, \
1295 .num_parents = 1, \
1296 .flags = f, \
1297 .muxdiv_offset = o, \
1298 .div_shift = s, \
1299 .div_width = w, \
1300 .div_flags = df, \
1301 .gate_offset = -1, \
1302 }
1303
1304/* SGRF clocks are only accessible from secure mode, so not controllable */
1305#define SGRF_GATE(_id, cname, pname) \
1306 FACTOR(_id, cname, pname, 0, 1, 1)
1307
1308static inline struct clk *rockchip_clk_get_lookup(struct rockchip_clk_provider *ctx,
1309 unsigned int id)
1310{
1311 return ctx->clk_data.clks[id];
1312}
1313
1314static inline void rockchip_clk_set_lookup(struct rockchip_clk_provider *ctx,
1315 struct clk *clk, unsigned int id)
1316{
1317 ctx->clk_data.clks[id] = clk;
1318}
1319
1320struct rockchip_gate_link_platdata {
1321 struct rockchip_clk_provider *ctx;
1322 struct rockchip_clk_branch *clkbr;
1323};
1324
1325struct rockchip_clk_provider *rockchip_clk_init(struct device_node *np,
1326 void __iomem *base, unsigned long nr_clks);
1327struct rockchip_clk_provider *rockchip_clk_init_early(struct device_node *np,
1328 void __iomem *base, unsigned long nr_clks);
1329void rockchip_clk_finalize(struct rockchip_clk_provider *ctx);
1330void rockchip_clk_of_add_provider(struct device_node *np,
1331 struct rockchip_clk_provider *ctx);
1332unsigned long rockchip_clk_find_max_clk_id(struct rockchip_clk_branch *list,
1333 unsigned int nr_clk);
1334void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx,
1335 struct rockchip_clk_branch *list,
1336 unsigned int nr_clk);
1337void rockchip_clk_register_late_branches(struct device *dev,
1338 struct rockchip_clk_provider *ctx,
1339 struct rockchip_clk_branch *list,
1340 unsigned int nr_clk);
1341void rockchip_clk_register_plls(struct rockchip_clk_provider *ctx,
1342 struct rockchip_pll_clock *pll_list,
1343 unsigned int nr_pll, int grf_lock_offset);
1344void rockchip_clk_register_armclk(struct rockchip_clk_provider *ctx,
1345 unsigned int lookup_id, const char *name,
1346 const char *const *parent_names, u8 num_parents,
1347 const struct rockchip_cpuclk_reg_data *reg_data,
1348 const struct rockchip_cpuclk_rate_table *rates,
1349 int nrates);
1350void rockchip_clk_register_armclk_multi_pll(struct rockchip_clk_provider *ctx,
1351 struct rockchip_clk_branch *list,
1352 const struct rockchip_cpuclk_rate_table *rates,
1353 int nrates);
1354void rockchip_clk_protect_critical(const char *const clocks[], int nclocks);
1355void rockchip_register_restart_notifier(struct rockchip_clk_provider *ctx,
1356 unsigned int reg, void (*cb)(void));
1357
1358#define ROCKCHIP_SOFTRST_HIWORD_MASK BIT(0)
1359
1360struct clk *rockchip_clk_register_halfdiv(const char *name,
1361 const char *const *parent_names,
1362 u8 num_parents, void __iomem *base,
1363 int muxdiv_offset, u8 mux_shift,
1364 u8 mux_width, u8 mux_flags,
1365 u8 div_shift, u8 div_width,
1366 u8 div_flags, int gate_offset,
1367 u8 gate_shift, u8 gate_flags,
1368 unsigned long flags,
1369 spinlock_t *lock);
1370
1371#ifdef CONFIG_RESET_CONTROLLER
1372void rockchip_register_softrst_lut(struct device_node *np,
1373 const int *lookup_table,
1374 unsigned int num_regs,
1375 void __iomem *base, u8 flags);
1376#else
1377static inline void rockchip_register_softrst_lut(struct device_node *np,
1378 const int *lookup_table,
1379 unsigned int num_regs,
1380 void __iomem *base, u8 flags)
1381{
1382}
1383#endif
1384
1385static inline void rockchip_register_softrst(struct device_node *np,
1386 unsigned int num_regs,
1387 void __iomem *base, u8 flags)
1388{
1389 return rockchip_register_softrst_lut(np, NULL, num_regs, base, flags);
1390}
1391
1392void rv1126b_rst_init(struct device_node *np, void __iomem *reg_base);
1393void rk3506_rst_init(struct device_node *np, void __iomem *reg_base);
1394void rk3528_rst_init(struct device_node *np, void __iomem *reg_base);
1395void rk3562_rst_init(struct device_node *np, void __iomem *reg_base);
1396void rk3576_rst_init(struct device_node *np, void __iomem *reg_base);
1397void rk3588_rst_init(struct device_node *np, void __iomem *reg_base);
1398
1399#endif