Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2025 Samsung Electronics Co., Ltd.
4 * https://www.samsung.com
5 * Copyright (c) 2025 Axis Communications AB.
6 * https://www.axis.com
7 *
8 * Common Clock Framework support for ARTPEC-9 SoC.
9 */
10
11#include <linux/clk-provider.h>
12#include <linux/platform_device.h>
13#include <dt-bindings/clock/axis,artpec9-clk.h>
14
15#include "clk.h"
16#include "clk-exynos-arm64.h"
17
18/* NOTE: Must be equal to the last clock ID increased by one */
19#define CMU_CMU_NR_CLK (CLK_DOUT_CMU_VIO_AUDIO + 1)
20#define CMU_BUS_NR_CLK (CLK_MOUT_BUS_ACLK_USER + 1)
21#define CMU_CORE_NR_CLK (CLK_MOUT_CORE_ACLK_USER + 1)
22#define CMU_CPUCL_NR_CLK (CLK_GOUT_CPUCL_CSSYS_IPCLKPORT_PCLKDBG + 1)
23#define CMU_FSYS0_NR_CLK (CLK_GOUT_FSYS0_PWM_IPCLKPORT_I_PCLK_S0 + 1)
24#define CMU_FSYS1_NR_CLK (CLK_GOUT_FSYS1_XHB_USB_IPCLKPORT_CLK + 1)
25#define CMU_IMEM_NR_CLK (CLK_GOUT_IMEM_PCLK_TMU0_APBIF + 1)
26#define CMU_PERI_NR_CLK (CLK_GOUT_PERI_UART2_SCLK_UART + 1)
27
28/* Register Offset definitions for CMU_CMU (0x12c00000) */
29#define PLL_LOCKTIME_PLL_AUDIO 0x0000
30#define PLL_LOCKTIME_PLL_SHARED0 0x0004
31#define PLL_LOCKTIME_PLL_SHARED1 0x0008
32#define PLL_CON0_PLL_AUDIO 0x0100
33#define PLL_CON0_PLL_SHARED0 0x0120
34#define PLL_CON0_PLL_SHARED1 0x0140
35#define CLK_CON_MUX_CLKCMU_BUS 0x1000
36#define CLK_CON_MUX_CLKCMU_CDC_CORE 0x1004
37#define CLK_CON_MUX_CLKCMU_CORE_MAIN 0x1008
38#define CLK_CON_MUX_CLKCMU_CPUCL_SWITCH 0x100c
39#define CLK_CON_MUX_CLKCMU_VIO_AUDIO 0x1010
40#define CLK_CON_MUX_CLKCMU_DLP_CORE 0x1014
41#define CLK_CON_MUX_CLKCMU_FSYS0_BUS 0x1018
42#define CLK_CON_MUX_CLKCMU_FSYS0_IP 0x101c
43#define CLK_CON_MUX_CLKCMU_FSYS1_BUS 0x1020
44#define CLK_CON_MUX_CLKCMU_FSYS1_SCAN0 0x1024
45#define CLK_CON_MUX_CLKCMU_FSYS1_SCAN1 0x1028
46#define CLK_CON_MUX_CLKCMU_GPU_2D 0x102c
47#define CLK_CON_MUX_CLKCMU_GPU_3D 0x1030
48#define CLK_CON_MUX_CLKCMU_IMEM_ACLK 0x1034
49#define CLK_CON_MUX_CLKCMU_IMEM_CA5 0x1038
50#define CLK_CON_MUX_CLKCMU_IMEM_JPEG 0x103c
51#define CLK_CON_MUX_CLKCMU_IMEM_SSS 0x1040
52#define CLK_CON_MUX_CLKCMU_IPA_CORE 0x1044
53#define CLK_CON_MUX_CLKCMU_MIF_BUSP 0x1048
54#define CLK_CON_MUX_CLKCMU_MIF_SWITCH 0x104c
55#define CLK_CON_MUX_CLKCMU_PERI_DISP 0x1050
56#define CLK_CON_MUX_CLKCMU_PERI_IP 0x1054
57#define CLK_CON_MUX_CLKCMU_RSP_CORE 0x1058
58#define CLK_CON_MUX_CLKCMU_TRFM 0x105c
59#define CLK_CON_MUX_CLKCMU_VIO_CORE 0x1060
60#define CLK_CON_MUX_CLKCMU_VIO_CORE_L 0x1064
61#define CLK_CON_MUX_CLKCMU_VIP0 0x1068
62#define CLK_CON_MUX_CLKCMU_VIP1 0x106c
63#define CLK_CON_MUX_CLKCMU_VPP_CORE 0x1070
64#define CLK_CON_DIV_CLKCMU_ADD 0x1800
65#define CLK_CON_DIV_CLKCMU_BUS 0x1804
66#define CLK_CON_DIV_CLKCMU_CDC_CORE 0x1808
67#define CLK_CON_DIV_CLKCMU_CORE_MAIN 0x180c
68#define CLK_CON_DIV_CLKCMU_CPUCL_SWITCH 0x1810
69#define CLK_CON_DIV_CLKCMU_DLP_CORE 0x1814
70#define CLK_CON_DIV_CLKCMU_FSYS0_BUS 0x1818
71#define CLK_CON_DIV_CLKCMU_FSYS0_IP 0x181c
72#define CLK_CON_DIV_CLKCMU_FSYS1_BUS 0x1820
73#define CLK_CON_DIV_CLKCMU_FSYS1_SCAN0 0x1824
74#define CLK_CON_DIV_CLKCMU_FSYS1_SCAN1 0x1828
75#define CLK_CON_DIV_CLKCMU_GPU_2D 0x182c
76#define CLK_CON_DIV_CLKCMU_GPU_3D 0x1830
77#define CLK_CON_DIV_CLKCMU_IMEM_ACLK 0x1834
78#define CLK_CON_DIV_CLKCMU_IMEM_CA5 0x1838
79#define CLK_CON_DIV_CLKCMU_IMEM_JPEG 0x183c
80#define CLK_CON_DIV_CLKCMU_IMEM_SSS 0x1840
81#define CLK_CON_DIV_CLKCMU_IPA_CORE 0x1844
82#define CLK_CON_DIV_CLKCMU_LCPU 0x1848
83#define CLK_CON_DIV_CLKCMU_MIF_BUSP 0x184c
84#define CLK_CON_DIV_CLKCMU_MIF_SWITCH 0x1850
85#define CLK_CON_DIV_CLKCMU_PERI_DISP 0x1854
86#define CLK_CON_DIV_CLKCMU_PERI_IP 0x1858
87#define CLK_CON_DIV_CLKCMU_RSP_CORE 0x185c
88#define CLK_CON_DIV_CLKCMU_TRFM 0x1860
89#define CLK_CON_DIV_CLKCMU_VIO_AUDIO 0x1864
90#define CLK_CON_DIV_CLKCMU_VIO_CORE 0x1868
91#define CLK_CON_DIV_CLKCMU_VIO_CORE_L 0x186c
92#define CLK_CON_DIV_CLKCMU_VIP0 0x1870
93#define CLK_CON_DIV_CLKCMU_VIP1 0x1874
94#define CLK_CON_DIV_CLKCMU_VPP_CORE 0x1878
95#define CLK_CON_DIV_PLL_SHARED0_DIV2 0x187c
96#define CLK_CON_DIV_PLL_SHARED0_DIV3 0x1880
97#define CLK_CON_DIV_PLL_SHARED0_DIV4 0x1884
98#define CLK_CON_DIV_PLL_SHARED1_DIV2 0x1888
99#define CLK_CON_DIV_PLL_SHARED1_DIV3 0x188c
100#define CLK_CON_DIV_PLL_SHARED1_DIV4 0x1890
101
102static const unsigned long cmu_cmu_clk_regs[] __initconst = {
103 PLL_LOCKTIME_PLL_AUDIO,
104 PLL_LOCKTIME_PLL_SHARED0,
105 PLL_LOCKTIME_PLL_SHARED1,
106 PLL_CON0_PLL_AUDIO,
107 PLL_CON0_PLL_SHARED0,
108 PLL_CON0_PLL_SHARED1,
109 CLK_CON_MUX_CLKCMU_BUS,
110 CLK_CON_MUX_CLKCMU_CDC_CORE,
111 CLK_CON_MUX_CLKCMU_CORE_MAIN,
112 CLK_CON_MUX_CLKCMU_CPUCL_SWITCH,
113 CLK_CON_MUX_CLKCMU_DLP_CORE,
114 CLK_CON_MUX_CLKCMU_FSYS0_BUS,
115 CLK_CON_MUX_CLKCMU_FSYS0_IP,
116 CLK_CON_MUX_CLKCMU_FSYS1_BUS,
117 CLK_CON_MUX_CLKCMU_FSYS1_SCAN0,
118 CLK_CON_MUX_CLKCMU_FSYS1_SCAN1,
119 CLK_CON_MUX_CLKCMU_GPU_2D,
120 CLK_CON_MUX_CLKCMU_GPU_3D,
121 CLK_CON_MUX_CLKCMU_IMEM_ACLK,
122 CLK_CON_MUX_CLKCMU_IMEM_CA5,
123 CLK_CON_MUX_CLKCMU_IMEM_JPEG,
124 CLK_CON_MUX_CLKCMU_IMEM_SSS,
125 CLK_CON_MUX_CLKCMU_IPA_CORE,
126 CLK_CON_MUX_CLKCMU_MIF_BUSP,
127 CLK_CON_MUX_CLKCMU_MIF_SWITCH,
128 CLK_CON_MUX_CLKCMU_PERI_DISP,
129 CLK_CON_MUX_CLKCMU_PERI_IP,
130 CLK_CON_MUX_CLKCMU_RSP_CORE,
131 CLK_CON_MUX_CLKCMU_TRFM,
132 CLK_CON_MUX_CLKCMU_VIO_CORE,
133 CLK_CON_MUX_CLKCMU_VIO_CORE_L,
134 CLK_CON_MUX_CLKCMU_VIP0,
135 CLK_CON_MUX_CLKCMU_VIP1,
136 CLK_CON_MUX_CLKCMU_VPP_CORE,
137 CLK_CON_DIV_CLKCMU_ADD,
138 CLK_CON_DIV_CLKCMU_BUS,
139 CLK_CON_DIV_CLKCMU_CDC_CORE,
140 CLK_CON_DIV_CLKCMU_CORE_MAIN,
141 CLK_CON_DIV_CLKCMU_CPUCL_SWITCH,
142 CLK_CON_DIV_CLKCMU_VIO_AUDIO,
143 CLK_CON_DIV_CLKCMU_DLP_CORE,
144 CLK_CON_DIV_CLKCMU_FSYS0_BUS,
145 CLK_CON_DIV_CLKCMU_FSYS0_IP,
146 CLK_CON_DIV_CLKCMU_FSYS1_BUS,
147 CLK_CON_DIV_CLKCMU_FSYS1_SCAN0,
148 CLK_CON_DIV_CLKCMU_FSYS1_SCAN1,
149 CLK_CON_DIV_CLKCMU_GPU_2D,
150 CLK_CON_DIV_CLKCMU_GPU_3D,
151 CLK_CON_DIV_CLKCMU_IMEM_ACLK,
152 CLK_CON_DIV_CLKCMU_IMEM_CA5,
153 CLK_CON_DIV_CLKCMU_IMEM_JPEG,
154 CLK_CON_DIV_CLKCMU_IMEM_SSS,
155 CLK_CON_DIV_CLKCMU_IPA_CORE,
156 CLK_CON_DIV_CLKCMU_LCPU,
157 CLK_CON_DIV_CLKCMU_MIF_BUSP,
158 CLK_CON_DIV_CLKCMU_MIF_SWITCH,
159 CLK_CON_DIV_CLKCMU_PERI_DISP,
160 CLK_CON_DIV_CLKCMU_PERI_IP,
161 CLK_CON_DIV_CLKCMU_RSP_CORE,
162 CLK_CON_DIV_CLKCMU_TRFM,
163 CLK_CON_DIV_CLKCMU_VIO_AUDIO,
164 CLK_CON_DIV_CLKCMU_VIO_CORE,
165 CLK_CON_DIV_CLKCMU_VIO_CORE_L,
166 CLK_CON_DIV_CLKCMU_VIP0,
167 CLK_CON_DIV_CLKCMU_VIP1,
168 CLK_CON_DIV_CLKCMU_VPP_CORE,
169 CLK_CON_DIV_PLL_SHARED0_DIV2,
170 CLK_CON_DIV_PLL_SHARED0_DIV3,
171 CLK_CON_DIV_PLL_SHARED0_DIV4,
172 CLK_CON_DIV_PLL_SHARED1_DIV2,
173 CLK_CON_DIV_PLL_SHARED1_DIV3,
174 CLK_CON_DIV_PLL_SHARED1_DIV4,
175};
176
177static const struct samsung_pll_rate_table artpec9_pll_audio_rates[] __initconst = {
178 PLL_A9FRACO_RATE(25 * MHZ, 589824000U, 94, 1, 3, 6238440),
179};
180
181static const struct samsung_pll_clock cmu_cmu_pll_clks[] __initconst = {
182 PLL(pll_a9fracm, CLK_FOUT_SHARED0_PLL, "fout_pll_shared0", "fin_pll",
183 PLL_LOCKTIME_PLL_SHARED0, PLL_CON0_PLL_SHARED0, NULL),
184 PLL(pll_a9fracm, CLK_FOUT_SHARED1_PLL, "fout_pll_shared1", "fin_pll",
185 PLL_LOCKTIME_PLL_SHARED1, PLL_CON0_PLL_SHARED1, NULL),
186 PLL(pll_a9fraco, CLK_FOUT_AUDIO_PLL, "fout_pll_audio", "fin_pll",
187 PLL_LOCKTIME_PLL_AUDIO, PLL_CON0_PLL_AUDIO, artpec9_pll_audio_rates),
188};
189
190PNAME(mout_clkcmu_bus_bus_p) = { "dout_pll_shared0_div2", "dout_pll_shared1_div2",
191 "dout_pll_shared1_div3", "dout_pll_shared1_div4" };
192PNAME(mout_clkcmu_cdc_core_p) = { "dout_pll_shared0_div2", "dout_pll_shared1_div3",
193 "dout_pll_shared1_div2", "mout_clk_pll_fsys1" };
194PNAME(mout_clkcmu_core_main_p) = { "dout_pll_shared0_div2", "dout_pll_shared1_div2",
195 "dout_pll_shared1_div3", "dout_pll_shared1_div4" };
196PNAME(mout_clkcmu_cpucl_switch_p) = { "dout_pll_shared0_div2", "dout_pll_shared1_div2",
197 "dout_pll_shared0_div3", "dout_pll_shared1_div3" };
198PNAME(mout_clkcmu_dlp_core_p) = { "dout_pll_shared1_div3", "dout_pll_shared0_div2",
199 "dout_pll_shared1_div2", "mout_clk_pll_fsys1" };
200PNAME(mout_clkcmu_fsys0_bus_p) = { "dout_pll_shared1_div3", "dout_pll_shared0_div2",
201 "dout_pll_shared1_div4", "dout_pll_shared1_div2" };
202PNAME(mout_clkcmu_fsys0_ip_p) = { "dout_pll_shared0_div2", "dout_pll_shared1_div3",
203 "dout_pll_shared1_div2", "dout_pll_shared0_div3" };
204PNAME(mout_clkcmu_fsys1_bus_p) = { "dout_pll_shared1_div3", "dout_pll_shared0_div2",
205 "dout_pll_shared1_div2", "dout_pll_shared0_div4" };
206PNAME(mout_clkcmu_fsys1_scan0_p) = { "dout_pll_shared0_div2", "dout_pll_shared1_div4" };
207PNAME(mout_clkcmu_fsys1_scan1_p) = { "dout_pll_shared1_div3", "dout_pll_shared1_div4" };
208PNAME(mout_clkcmu_gpu_3d_p) = { "dout_pll_shared1_div3", "dout_pll_shared0_div2",
209 "dout_pll_shared1_div2", "mout_clk_pll_fsys1" };
210PNAME(mout_clkcmu_gpu_2d_p) = { "dout_pll_shared1_div3", "dout_pll_shared0_div2",
211 "dout_pll_shared1_div2", "mout_clk_pll_fsys1" };
212PNAME(mout_clkcmu_imem_aclk_p) = { "dout_pll_shared1_div3", "dout_pll_shared0_div2",
213 "dout_pll_shared1_div4", "dout_pll_shared1_div2" };
214PNAME(mout_clkcmu_imem_ca5_p) = { "dout_pll_shared0_div2", "dout_pll_shared1_div2",
215 "dout_pll_shared1_div3", "mout_clk_pll_shared1" };
216PNAME(mout_clkcmu_imem_jpeg_p) = { "dout_pll_shared0_div2", "dout_pll_shared0_div3",
217 "dout_pll_shared1_div2", "dout_pll_shared1_div3" };
218PNAME(mout_clkcmu_imem_sss_p) = { "dout_pll_shared0_div2", "dout_pll_shared1_div2" };
219PNAME(mout_clkcmu_ipa_core_p) = { "dout_pll_shared1_div3", "dout_pll_shared0_div2",
220 "dout_pll_shared1_div2", "mout_clk_pll_fsys1" };
221PNAME(mout_clkcmu_mif_switch_p) = { "fout_pll_shared1", "mout_clkcmu_pll_shared0",
222 "dout_pll_shared0_div2", "dout_pll_shared0_div3" };
223PNAME(mout_clkcmu_mif_busp_p) = { "dout_pll_shared1_div3", "dout_pll_shared1_div4",
224 "dout_pll_shared0_div4", "dout_pll_shared0_div2" };
225PNAME(mout_clkcmu_peri_disp_p) = { "dout_pll_shared1_div3", "dout_pll_shared0_div2",
226 "dout_pll_shared1_div4", "dout_pll_shared1_div2" };
227PNAME(mout_clkcmu_peri_ip_p) = { "fout_pll_fsys1", "dout_pll_shared1_2",
228 "dout_pll_shared1_div4", "dout_pll_shared0_div2" };
229PNAME(mout_clkcmu_rsp_core_p) = { "dout_pll_shared1_div3", "dout_pll_shared0_div2",
230 "dout_pll_shared1_div2", "mout_clk_pll_fsys1" };
231PNAME(mout_clkcmu_trfm_p) = { "dout_pll_shared1_div3", "dout_pll_shared0_div2",
232 "dout_pll_shared1_div2", "mout_clk_pll_fsys1" };
233PNAME(mout_clkcmu_vio_core_l_p) = { "dout_pll_shared0_div2", "dout_pll_shared1_div3",
234 "dout_pll_shared1_div2", "mout_clk_pll_fsys1" };
235PNAME(mout_clkcmu_vio_core_p) = { "fout_pll_fsys1", "dout_pll_shared0_div2",
236 "dout_pll_shared1_div3", "dout_pll_shared1_div2" };
237PNAME(mout_clkcmu_vio_audio_p) = { "fout_pll_audio", "mout_clkcmu_pll_audio" };
238PNAME(mout_clkcmu_vip0_p) = { "dout_pll_shared1_div3", "dout_pll_shared0_div2",
239 "dout_pll_shared1_div2", "mout_clk_pll_fsys1" };
240PNAME(mout_clkcmu_vip1_p) = { "dout_pll_shared1_div3", "dout_pll_shared0_div2",
241 "dout_pll_shared1_div2", "mout_clk_pll_fsys1" };
242PNAME(mout_clkcmu_vpp_core_p) = { "dout_pll_shared1_div3", "dout_pll_shared0_div2",
243 "dout_pll_shared1_div2", "mout_clk_pll_fsys1" };
244PNAME(mout_clkcmu_pll_shared0_p) = { "fin_pll", "fout_pll_shared0" };
245PNAME(mout_clkcmu_pll_shared1_p) = { "fin_pll", "fout_pll_shared1" };
246PNAME(mout_clkcmu_pll_audio_p) = { "fin_pll", "fout_pll_audio" };
247
248static const struct samsung_mux_clock cmu_cmu_mux_clks[] __initconst = {
249 MUX(0, "mout_clkcmu_pll_shared0", mout_clkcmu_pll_shared0_p, PLL_CON0_PLL_SHARED0, 4, 1),
250 MUX(0, "mout_clkcmu_pll_shared1", mout_clkcmu_pll_shared1_p, PLL_CON0_PLL_SHARED1, 4, 1),
251 MUX(0, "mout_clkcmu_pll_audio", mout_clkcmu_pll_audio_p, PLL_CON0_PLL_AUDIO, 4, 1),
252 MUX(0, "mout_clkcmu_bus_bus", mout_clkcmu_bus_bus_p, CLK_CON_MUX_CLKCMU_BUS, 0, 2),
253 nMUX(0, "mout_clkcmu_cdc_core", mout_clkcmu_cdc_core_p, CLK_CON_MUX_CLKCMU_CDC_CORE, 0, 2),
254 MUX(0, "mout_clkcmu_core_main", mout_clkcmu_core_main_p,
255 CLK_CON_MUX_CLKCMU_CORE_MAIN, 0, 2),
256 MUX(0, "mout_clkcmu_cpucl_switch", mout_clkcmu_cpucl_switch_p,
257 CLK_CON_MUX_CLKCMU_CPUCL_SWITCH, 0, 2),
258 nMUX(0, "mout_clkcmu_dlp_core", mout_clkcmu_dlp_core_p, CLK_CON_MUX_CLKCMU_DLP_CORE, 0, 2),
259 MUX(0, "mout_clkcmu_fsys0_bus", mout_clkcmu_fsys0_bus_p,
260 CLK_CON_MUX_CLKCMU_FSYS0_BUS, 0, 2),
261 MUX(0, "mout_clkcmu_fsys0_ip", mout_clkcmu_fsys0_ip_p, CLK_CON_MUX_CLKCMU_FSYS0_IP, 0, 2),
262 MUX(0, "mout_clkcmu_fsys1_bus", mout_clkcmu_fsys1_bus_p,
263 CLK_CON_MUX_CLKCMU_FSYS1_BUS, 0, 2),
264 MUX(0, "mout_clkcmu_fsys1_scan0", mout_clkcmu_fsys1_scan0_p,
265 CLK_CON_MUX_CLKCMU_FSYS1_SCAN0, 0, 1),
266 MUX(0, "mout_clkcmu_fsys1_scan1", mout_clkcmu_fsys1_scan1_p,
267 CLK_CON_MUX_CLKCMU_FSYS1_SCAN1, 0, 1),
268 MUX(0, "mout_clkcmu_gpu_2d", mout_clkcmu_gpu_2d_p, CLK_CON_MUX_CLKCMU_GPU_2D, 0, 2),
269 MUX(0, "mout_clkcmu_gpu_3d", mout_clkcmu_gpu_3d_p, CLK_CON_MUX_CLKCMU_GPU_3D, 0, 2),
270 MUX(0, "mout_clkcmu_imem_aclk", mout_clkcmu_imem_aclk_p,
271 CLK_CON_MUX_CLKCMU_IMEM_ACLK, 0, 2),
272 MUX(0, "mout_clkcmu_imem_ca5", mout_clkcmu_imem_ca5_p, CLK_CON_MUX_CLKCMU_IMEM_CA5, 0, 2),
273 MUX(0, "mout_clkcmu_imem_jpeg", mout_clkcmu_imem_jpeg_p,
274 CLK_CON_MUX_CLKCMU_IMEM_JPEG, 0, 2),
275 MUX(0, "mout_clkcmu_imem_sss", mout_clkcmu_imem_sss_p, CLK_CON_MUX_CLKCMU_IMEM_SSS, 0, 1),
276 MUX(0, "mout_clkcmu_ipa_core", mout_clkcmu_ipa_core_p, CLK_CON_MUX_CLKCMU_IPA_CORE, 0, 2),
277 MUX(0, "mout_clkcmu_mif_busp", mout_clkcmu_mif_busp_p, CLK_CON_MUX_CLKCMU_MIF_BUSP, 0, 2),
278 MUX(0, "mout_clkcmu_mif_switch", mout_clkcmu_mif_switch_p,
279 CLK_CON_MUX_CLKCMU_MIF_SWITCH, 0, 2),
280 MUX(0, "mout_clkcmu_peri_disp", mout_clkcmu_peri_disp_p,
281 CLK_CON_MUX_CLKCMU_PERI_DISP, 0, 2),
282 MUX(0, "mout_clkcmu_peri_ip", mout_clkcmu_peri_ip_p, CLK_CON_MUX_CLKCMU_PERI_IP, 0, 2),
283 MUX(0, "mout_clkcmu_rsp_core", mout_clkcmu_rsp_core_p, CLK_CON_MUX_CLKCMU_RSP_CORE, 0, 2),
284 MUX(0, "mout_clkcmu_trfm", mout_clkcmu_trfm_p, CLK_CON_MUX_CLKCMU_TRFM, 0, 2),
285 MUX(0, "mout_clkcmu_vio_core", mout_clkcmu_vio_core_p, CLK_CON_MUX_CLKCMU_VIO_CORE, 0, 2),
286 MUX(0, "mout_clkcmu_vio_core_l", mout_clkcmu_vio_core_l_p,
287 CLK_CON_MUX_CLKCMU_VIO_CORE_L, 0, 2),
288 MUX(0, "mout_clkcmu_vio_audio", mout_clkcmu_vio_audio_p,
289 CLK_CON_MUX_CLKCMU_VIO_AUDIO, 0, 1),
290 MUX(0, "mout_clkcmu_vip0", mout_clkcmu_vip0_p, CLK_CON_MUX_CLKCMU_VIP0, 0, 2),
291 MUX(0, "mout_clkcmu_vip1", mout_clkcmu_vip1_p, CLK_CON_MUX_CLKCMU_VIP1, 0, 2),
292 MUX(0, "mout_clkcmu_vpp_core", mout_clkcmu_vpp_core_p, CLK_CON_MUX_CLKCMU_VPP_CORE, 0, 2),
293};
294
295static const struct samsung_div_clock cmu_cmu_div_clks[] __initconst = {
296 DIV(CLK_DOUT_CMU_ADD, "dout_clkcmu_add", "gate_clkcmu_add", CLK_CON_DIV_CLKCMU_ADD, 0, 8),
297 DIV(CLK_DOUT_CMU_BUS, "dout_clkcmu_bus",
298 "gate_clkcmu_bus_bus", CLK_CON_DIV_CLKCMU_BUS, 0, 4),
299 DIV_F(CLK_DOUT_CMU_CDC_CORE, "dout_clkcmu_cdc_core",
300 "gate_clkcmu_cdc_core", CLK_CON_DIV_CLKCMU_CDC_CORE, 0, 4, CLK_SET_RATE_PARENT, 0),
301 DIV(CLK_DOUT_CMU_CORE_MAIN, "dout_clkcmu_core_main",
302 "gate_clkcmu_core_main", CLK_CON_DIV_CLKCMU_CORE_MAIN, 0, 4),
303 DIV(CLK_DOUT_CMU_CPUCL_SWITCH, "dout_clkcmu_cpucl_switch",
304 "gate_clkcmu_cpucl_switch", CLK_CON_DIV_CLKCMU_CPUCL_SWITCH, 0, 3),
305 DIV_F(CLK_DOUT_CMU_DLP_CORE, "dout_clkcmu_dlp_core",
306 "gate_clkcmu_dlp_core", CLK_CON_DIV_CLKCMU_DLP_CORE, 0, 4, CLK_SET_RATE_PARENT, 0),
307 DIV(CLK_DOUT_CMU_FSYS0_BUS, "dout_clkcmu_fsys0_bus",
308 "gate_clkcmu_fsys0_bus", CLK_CON_DIV_CLKCMU_FSYS0_BUS, 0, 4),
309 DIV(CLK_DOUT_CMU_FSYS0_IP, "dout_clkcmu_fsys0_ip",
310 "gate_clkcmu_fsys0_ip", CLK_CON_DIV_CLKCMU_FSYS0_IP, 0, 9),
311 DIV(CLK_DOUT_CMU_FSYS1_BUS, "dout_clkcmu_fsys1_bus",
312 "gate_clkcmu_fsys1_bus", CLK_CON_DIV_CLKCMU_FSYS1_BUS, 0, 4),
313 DIV(CLK_DOUT_CMU_FSYS1_SCAN0, "dout_clkcmu_fsys1_scan0",
314 "gate_clkcmu_fsys1_scan0", CLK_CON_DIV_CLKCMU_FSYS1_SCAN0, 0, 4),
315 DIV(CLK_DOUT_CMU_FSYS1_SCAN1, "dout_clkcmu_fsys1_scan1",
316 "gate_clkcmu_fsys1_scan1", CLK_CON_DIV_CLKCMU_FSYS1_SCAN1, 0, 4),
317 DIV(CLK_DOUT_CMU_GPU_2D, "dout_clkcmu_gpu_2d",
318 "gate_clkcmu_gpu_2d", CLK_CON_DIV_CLKCMU_GPU_2D, 0, 4),
319 DIV(CLK_DOUT_CMU_GPU_3D, "dout_clkcmu_gpu_3d",
320 "gate_clkcmu_gpu_3d", CLK_CON_DIV_CLKCMU_GPU_3D, 0, 4),
321 DIV(CLK_DOUT_CMU_IMEM_ACLK, "dout_clkcmu_imem_aclk",
322 "gate_clkcmu_imem_aclk", CLK_CON_DIV_CLKCMU_IMEM_ACLK, 0, 4),
323 DIV(CLK_DOUT_CMU_IMEM_CA5, "dout_clkcmu_imem_ca5",
324 "gate_clkcmu_imem_ca5", CLK_CON_DIV_CLKCMU_IMEM_CA5, 0, 4),
325 DIV(CLK_DOUT_CMU_IMEM_JPEG, "dout_clkcmu_imem_jpeg",
326 "gate_clkcmu_imem_jpeg", CLK_CON_DIV_CLKCMU_IMEM_JPEG, 0, 4),
327 DIV(CLK_DOUT_CMU_IMEM_SSS, "dout_clkcmu_imem_sss",
328 "gate_clkcmu_imem_sss", CLK_CON_DIV_CLKCMU_IMEM_SSS, 0, 4),
329 DIV(CLK_DOUT_CMU_IPA_CORE, "dout_clkcmu_ipa_core",
330 "gate_clkcmu_ipa_core", CLK_CON_DIV_CLKCMU_IPA_CORE, 0, 4),
331 DIV(CLK_DOUT_CMU_LCPU, "dout_clkcmu_lcpu",
332 "gate_clkcmu_lcpu", CLK_CON_DIV_CLKCMU_LCPU, 0, 4),
333 DIV(CLK_DOUT_CMU_MIF_BUSP, "dout_clkcmu_mif_busp",
334 "gate_clkcmu_mif_busp", CLK_CON_DIV_CLKCMU_MIF_BUSP, 0, 3),
335 DIV(CLK_DOUT_CMU_MIF_SWITCH, "dout_clkcmu_mif_switch",
336 "gate_clkcmu_mif_switch", CLK_CON_DIV_CLKCMU_MIF_SWITCH, 0, 4),
337 DIV(CLK_DOUT_CMU_PERI_DISP, "dout_clkcmu_peri_disp",
338 "gate_clkcmu_peri_disp", CLK_CON_DIV_CLKCMU_PERI_DISP, 0, 4),
339 DIV(CLK_DOUT_CMU_PERI_IP, "dout_clkcmu_peri_ip",
340 "gate_clkcmu_peri_ip", CLK_CON_DIV_CLKCMU_PERI_IP, 0, 4),
341 DIV(CLK_DOUT_CMU_RSP_CORE, "dout_clkcmu_rsp_core",
342 "gate_clkcmu_rsp_core", CLK_CON_DIV_CLKCMU_RSP_CORE, 0, 4),
343 DIV(CLK_DOUT_CMU_TRFM, "dout_clkcmu_trfm",
344 "gate_clkcmu_trfm", CLK_CON_DIV_CLKCMU_TRFM, 0, 4),
345 DIV(CLK_DOUT_CMU_VIO_CORE, "dout_clkcmu_vio_core",
346 "gate_clkcmu_vio_core", CLK_CON_DIV_CLKCMU_VIO_CORE, 0, 4),
347 DIV(CLK_DOUT_CMU_VIO_CORE_L, "dout_clkcmu_vio_core_l",
348 "gate_clkcmu_vio_core_l", CLK_CON_DIV_CLKCMU_VIO_CORE_L, 0, 4),
349 DIV(CLK_DOUT_CMU_VIO_AUDIO, "dout_clkcmu_vio_audio",
350 "gate_clkcmu_vio_audio", CLK_CON_DIV_CLKCMU_VIO_AUDIO, 0, 4),
351 DIV(CLK_DOUT_CMU_VIP0, "dout_clkcmu_vip0",
352 "gate_clkcmu_vip0", CLK_CON_DIV_CLKCMU_VIP0, 0, 4),
353 DIV(CLK_DOUT_CMU_VIP1, "dout_clkcmu_vip1",
354 "gate_clkcmu_vip1", CLK_CON_DIV_CLKCMU_VIP1, 0, 4),
355 DIV(CLK_DOUT_CMU_VPP_CORE, "dout_clkcmu_vpp_core",
356 "gate_clkcmu_vpp_core", CLK_CON_DIV_CLKCMU_VPP_CORE, 0, 4),
357 DIV(CLK_DOUT_SHARED0_DIV2, "dout_pll_shared0_div2",
358 "mout_clkcmu_pll_shared0", CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1),
359 DIV(CLK_DOUT_SHARED0_DIV3, "dout_pll_shared0_div3",
360 "mout_clkcmu_pll_shared0", CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2),
361 DIV(CLK_DOUT_SHARED0_DIV4, "dout_pll_shared0_div4",
362 "dout_pll_shared0_div2", CLK_CON_DIV_PLL_SHARED0_DIV4, 0, 1),
363 DIV(CLK_DOUT_SHARED1_DIV2, "dout_pll_shared1_div2",
364 "mout_clkcmu_pll_shared1", CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1),
365 DIV(CLK_DOUT_SHARED1_DIV3, "dout_pll_shared1_div3",
366 "mout_clkcmu_pll_shared1", CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2),
367 DIV(CLK_DOUT_SHARED1_DIV4, "dout_pll_shared1_div4",
368 "dout_pll_shared1_div2", CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1),
369};
370
371static const struct samsung_cmu_info cmu_cmu_info __initconst = {
372 .pll_clks = cmu_cmu_pll_clks,
373 .nr_pll_clks = ARRAY_SIZE(cmu_cmu_pll_clks),
374 .mux_clks = cmu_cmu_mux_clks,
375 .nr_mux_clks = ARRAY_SIZE(cmu_cmu_mux_clks),
376 .div_clks = cmu_cmu_div_clks,
377 .nr_div_clks = ARRAY_SIZE(cmu_cmu_div_clks),
378 .nr_clk_ids = CMU_CMU_NR_CLK,
379 .clk_regs = cmu_cmu_clk_regs,
380 .nr_clk_regs = ARRAY_SIZE(cmu_cmu_clk_regs),
381};
382
383/* Register Offset definitions for CMU_BUS (0x13410000) */
384#define PLL_CON0_MUX_CLK_BUS_ACLK_USER 0x0100
385
386static const unsigned long cmu_bus_clk_regs[] __initconst = {
387 PLL_CON0_MUX_CLK_BUS_ACLK_USER,
388};
389
390PNAME(mout_clk_bus_aclk_user_p) = {"fin_pll", "dout_clkcmu_bus_bus",};
391
392static const struct samsung_mux_clock cmu_bus_mux_clks[] __initconst = {
393 MUX(CLK_MOUT_BUS_ACLK_USER, "mout_clk_bus_aclk_user", mout_clk_bus_aclk_user_p,
394 PLL_CON0_MUX_CLK_BUS_ACLK_USER, 4, 1),
395};
396
397static const struct samsung_cmu_info cmu_bus_info __initconst = {
398 .mux_clks = cmu_bus_mux_clks,
399 .nr_mux_clks = ARRAY_SIZE(cmu_bus_mux_clks),
400 .nr_clk_ids = CMU_BUS_NR_CLK,
401 .clk_regs = cmu_bus_clk_regs,
402 .nr_clk_regs = ARRAY_SIZE(cmu_bus_clk_regs),
403};
404
405/* Register Offset definitions for CMU_CORE (0x12c10000) */
406#define PLL_CON0_MUX_CLK_CORE_ACLK_USER 0x0100
407
408static const unsigned long cmu_core_clk_regs[] __initconst = {
409 PLL_CON0_MUX_CLK_CORE_ACLK_USER,
410};
411
412PNAME(mout_clk_core_aclk_user_p) = {"fin_pll", "dout_clkcmu_core_main",};
413
414static const struct samsung_mux_clock cmu_core_mux_clks[] __initconst = {
415 MUX(CLK_MOUT_CORE_ACLK_USER, "mout_clk_core_aclk_user", mout_clk_core_aclk_user_p,
416 PLL_CON0_MUX_CLK_CORE_ACLK_USER, 4, 1),
417};
418
419static const struct samsung_cmu_info cmu_core_info __initconst = {
420 .mux_clks = cmu_core_mux_clks,
421 .nr_mux_clks = ARRAY_SIZE(cmu_core_mux_clks),
422 .nr_clk_ids = CMU_CORE_NR_CLK,
423 .clk_regs = cmu_core_clk_regs,
424 .nr_clk_regs = ARRAY_SIZE(cmu_core_clk_regs),
425};
426
427/* Register Offset definitions for CMU_CPUCL (0x12810000) */
428#define PLL_LOCKTIME_PLL0_CPUCL 0x0000
429#define PLL_LOCKTIME_PLL1_CPUCL 0x0008
430#define PLL_CON0_MUX_CLKCMU_CPUCL_SWITCH_SCU_USER 0x0100
431#define PLL_CON0_MUX_CLKCMU_CPUCL_SWITCH_USER 0x0120
432#define PLL_CON0_PLL0_CPUCL 0x0140
433#define PLL_CON0_PLL1_CPUCL 0x0160
434#define CLK_CON_MUX_CLK_CPUCL_PLL 0x1000
435#define CLK_CON_MUX_CLK_CPUCL_PLL_SCU 0x1004
436#define CLK_CON_DIV_CLK_CPUCL_CLUSTER_PERIPHCLK 0x1800
437#define CLK_CON_DIV_CLK_CPUCL_CLUSTER_GICCLK 0x1804
438#define CLK_CON_DIV_CLK_CPUCL_CLUSTER_PCLK 0x1808
439#define CLK_CON_DIV_CLK_CPUCL_CMUREF 0x180c
440#define CLK_CON_DIV_CLK_CPUCL_CPU 0x1810
441#define CLK_CON_DIV_CLK_CPUCL_CLUSTER_ATCLK 0x1818
442#define CLK_CON_DIV_CLK_CPUCL_CLUSTER_SCU 0x181c
443#define CLK_CON_DIV_CLK_CPUCL_DBG 0x1820
444#define CLK_CON_GAT_CLK_CLUSTER_CPU 0x2008
445#define CLK_CON_GAT_CLK_CPUCL_SHORTSTOP 0x200c
446#define CSSYS_IPCLKPORT_ATCLK 0x2070
447#define CSSYS_IPCLKPORT_PCLKDBG 0x2074
448#define DMYQCH_CON_CSSYS_QCH 0x3000
449#define DMYQCH_CON_CLUSTER_QCH_CORECLK0 0x3104
450#define DMYQCH_CON_CLUSTER_QCH_CORECLK1 0x3108
451#define DMYQCH_CON_CLUSTER_QCH_CORECLK2 0x310c
452#define DMYQCH_CON_CLUSTER_QCH_CORECLK3 0x3110
453#define DMYQCH_CON_CLUSTER_QCH_CORECLK4 0x3114
454#define DMYQCH_CON_CLUSTER_QCH_CORECLK5 0x3118
455#define DMYQCH_CON_CLUSTER_QCH_PERIPHCLK 0x311c
456
457static const unsigned long cmu_cpucl_clk_regs[] __initconst = {
458 PLL_LOCKTIME_PLL0_CPUCL,
459 PLL_LOCKTIME_PLL1_CPUCL,
460 PLL_CON0_MUX_CLKCMU_CPUCL_SWITCH_SCU_USER,
461 PLL_CON0_MUX_CLKCMU_CPUCL_SWITCH_USER,
462 PLL_CON0_PLL0_CPUCL,
463 PLL_CON0_PLL1_CPUCL,
464 CLK_CON_MUX_CLK_CPUCL_PLL,
465 CLK_CON_MUX_CLK_CPUCL_PLL_SCU,
466 CLK_CON_DIV_CLK_CPUCL_CLUSTER_PERIPHCLK,
467 CLK_CON_DIV_CLK_CPUCL_CLUSTER_GICCLK,
468 CLK_CON_DIV_CLK_CPUCL_CLUSTER_PCLK,
469 CLK_CON_DIV_CLK_CPUCL_CMUREF,
470 CLK_CON_DIV_CLK_CPUCL_CPU,
471 CLK_CON_DIV_CLK_CPUCL_CLUSTER_ATCLK,
472 CLK_CON_DIV_CLK_CPUCL_CLUSTER_SCU,
473 CLK_CON_DIV_CLK_CPUCL_DBG,
474 CLK_CON_GAT_CLK_CLUSTER_CPU,
475 CLK_CON_GAT_CLK_CPUCL_SHORTSTOP,
476 CSSYS_IPCLKPORT_ATCLK,
477 CSSYS_IPCLKPORT_PCLKDBG,
478 DMYQCH_CON_CSSYS_QCH,
479 DMYQCH_CON_CLUSTER_QCH_CORECLK0,
480 DMYQCH_CON_CLUSTER_QCH_CORECLK1,
481 DMYQCH_CON_CLUSTER_QCH_CORECLK2,
482 DMYQCH_CON_CLUSTER_QCH_CORECLK3,
483 DMYQCH_CON_CLUSTER_QCH_CORECLK4,
484 DMYQCH_CON_CLUSTER_QCH_CORECLK5,
485 DMYQCH_CON_CLUSTER_QCH_PERIPHCLK,
486};
487
488/* rate_table must be in descending order */
489static const struct samsung_pll_rate_table artpec9_pll_cpucl_rates[] __initconst = {
490 PLL_35XX_RATE(25 * MHZ, 1400000000U, 56, 1, 0),
491 PLL_35XX_RATE(25 * MHZ, 1100000000U, 44, 1, 0),
492 PLL_35XX_RATE(25 * MHZ, 850000000U, 34, 1, 0),
493};
494
495static const struct samsung_pll_clock cmu_cpucl_pll_clks[] __initconst = {
496 PLL(pll_a9fracm, CLK_FOUT_CPUCL_PLL0, "fout_pll0_cpucl", "fin_pll",
497 PLL_LOCKTIME_PLL0_CPUCL, PLL_CON0_PLL0_CPUCL, artpec9_pll_cpucl_rates),
498 PLL(pll_a9fracm, CLK_FOUT_CPUCL_PLL1, "fout_pll1_cpucl", "fin_pll",
499 PLL_LOCKTIME_PLL1_CPUCL, PLL_CON0_PLL1_CPUCL, artpec9_pll_cpucl_rates),
500};
501
502PNAME(mout_clkcmu_cpucl_switch_scu_user_p) = { "fin_pll", "dout_clkcmu_cpucl_switch" };
503PNAME(mout_clkcmu_cpucl_switch_user_p) = { "fin_pll", "dout_clkcmu_cpucl_switch" };
504PNAME(mout_pll0_cpucl_p) = { "fin_pll", "fout_pll0_cpucl" };
505PNAME(mout_clk_cpucl_pll0_p) = { "mout_pll0_cpucl", "mout_clkcmu_cpucl_switch_user" };
506PNAME(mout_pll1_cpucl_p) = { "fin_pll", "fout_pll1_cpucl" };
507PNAME(mout_clk_cpucl_pll_scu_p) = { "mout_pll1_cpucl", "mout_clkcmu_cpucl_switch_scu_user" };
508
509static const struct samsung_mux_clock cmu_cpucl_mux_clks[] __initconst = {
510 MUX_F(0, "mout_pll0_cpucl", mout_pll0_cpucl_p,
511 PLL_CON0_PLL0_CPUCL, 4, 1, CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0),
512 MUX_F(0, "mout_pll1_cpucl", mout_pll1_cpucl_p,
513 PLL_CON0_PLL1_CPUCL, 4, 1, CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0),
514 MUX(CLK_MOUT_CPUCL_SWITCH_SCU_USER, "mout_clkcmu_cpucl_switch_scu_user",
515 mout_clkcmu_cpucl_switch_scu_user_p, PLL_CON0_MUX_CLKCMU_CPUCL_SWITCH_SCU_USER, 4, 1),
516 MUX(CLK_MOUT_CPUCL_SWITCH_USER, "mout_clkcmu_cpucl_switch_user",
517 mout_clkcmu_cpucl_switch_user_p, PLL_CON0_MUX_CLKCMU_CPUCL_SWITCH_USER, 4, 1),
518 MUX_F(CLK_MOUT_CPUCL_PLL0, "mout_clk_cpucl_pll0",
519 mout_clk_cpucl_pll0_p, CLK_CON_MUX_CLK_CPUCL_PLL, 0, 1, CLK_SET_RATE_PARENT, 0),
520 MUX_F(CLK_MOUT_CPUCL_PLL_SCU, "mout_clk_cpucl_pll_scu", mout_clk_cpucl_pll_scu_p,
521 CLK_CON_MUX_CLK_CPUCL_PLL_SCU, 0, 1, CLK_SET_RATE_PARENT, 0),
522};
523
524static const struct samsung_fixed_factor_clock cpucl_ffactor_clks[] __initconst = {
525 FFACTOR(CLK_DOUT_CPUCL_CPU, "dout_clk_cpucl_cpu",
526 "mout_clk_cpucl_pll0", 1, 1, CLK_SET_RATE_PARENT),
527};
528
529static const struct samsung_div_clock cmu_cpucl_div_clks[] __initconst = {
530 DIV(CLK_DOUT_CPUCL_CLUSTER_PERIPHCLK, "dout_clk_cluster_periphclk",
531 "clk_con_gat_clk_cluster_cpu", CLK_CON_DIV_CLK_CPUCL_CLUSTER_PERIPHCLK, 0, 4),
532 DIV(CLK_DOUT_CPUCL_CLUSTER_GICCLK, "dout_clk_cluster_gicclk",
533 "clk_con_gat_clk_cluster_cpu", CLK_CON_DIV_CLK_CPUCL_CLUSTER_GICCLK, 0, 4),
534 DIV(CLK_DOUT_CPUCL_CLUSTER_PCLK, "dout_clk_cluster_pclk",
535 "clk_con_gat_clk_cluster_cpu", CLK_CON_DIV_CLK_CPUCL_CLUSTER_PCLK, 0, 4),
536 DIV(CLK_DOUT_CPUCL_CMUREF, "dout_clk_cpucl_cmuref",
537 "dout_clk_cpucl_cpu", CLK_CON_DIV_CLK_CPUCL_CMUREF, 0, 3),
538 DIV(CLK_DOUT_CPUCL_CLUSTER_ATCLK, "dout_clk_cluster_atclk",
539 "clk_con_gat_clk_cluster_cpu", CLK_CON_DIV_CLK_CPUCL_CLUSTER_ATCLK, 0, 4),
540 DIV_F(CLK_DOUT_CPUCL_CLUSTER_SCU, "dout_clk_cluster_scu", "mout_clk_cpucl_pll_scu",
541 CLK_CON_DIV_CLK_CPUCL_CLUSTER_SCU, 0, 4, CLK_SET_RATE_PARENT, 0),
542 DIV(CLK_DOUT_CPUCL_DBG, "dout_clk_cpucl_dbg",
543 "dout_clk_cpucl_cpu", CLK_CON_DIV_CLK_CPUCL_DBG, 0, 4),
544};
545
546static const struct samsung_gate_clock cmu_cpucl_gate_clks[] __initconst = {
547 GATE(CLK_GOUT_CPUCL_CLUSTER_CPU, "clk_con_gat_clk_cluster_cpu",
548 "clk_con_gat_clk_cpucl_shortstop", CLK_CON_GAT_CLK_CLUSTER_CPU, 21,
549 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
550 GATE(CLK_GOUT_CPUCL_SHORTSTOP, "clk_con_gat_clk_cpucl_shortstop", "dout_clk_cpucl_cpu",
551 CLK_CON_GAT_CLK_CPUCL_SHORTSTOP, 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
552 GATE(CLK_GOUT_CPUCL_CSSYS_IPCLKPORT_ATCLK, "cssys_ipclkport_atclk", "dout_clk_cpucl_dbg",
553 CSSYS_IPCLKPORT_ATCLK, 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
554 GATE(CLK_GOUT_CPUCL_CSSYS_IPCLKPORT_PCLKDBG, "cssys_ipclkport_pclkdbg",
555 "dout_clk_cpucl_dbg", CSSYS_IPCLKPORT_PCLKDBG, 21,
556 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
557};
558
559static const struct samsung_cmu_info cmu_cpucl_info __initconst = {
560 .pll_clks = cmu_cpucl_pll_clks,
561 .nr_pll_clks = ARRAY_SIZE(cmu_cpucl_pll_clks),
562 .fixed_factor_clks = cpucl_ffactor_clks,
563 .nr_fixed_factor_clks = ARRAY_SIZE(cpucl_ffactor_clks),
564 .mux_clks = cmu_cpucl_mux_clks,
565 .nr_mux_clks = ARRAY_SIZE(cmu_cpucl_mux_clks),
566 .div_clks = cmu_cpucl_div_clks,
567 .nr_div_clks = ARRAY_SIZE(cmu_cpucl_div_clks),
568 .gate_clks = cmu_cpucl_gate_clks,
569 .nr_gate_clks = ARRAY_SIZE(cmu_cpucl_gate_clks),
570 .nr_clk_ids = CMU_CPUCL_NR_CLK,
571 .clk_regs = cmu_cpucl_clk_regs,
572 .nr_clk_regs = ARRAY_SIZE(cmu_cpucl_clk_regs),
573};
574
575/* Register Offset definitions for CMU_FSYS0 (0x14410000) */
576#define PLL_CON0_MUX_CLK_FSYS0_BUS_USER 0x0100
577#define PLL_CON0_MUX_CLK_FSYS0_IP_USER 0x0120
578#define PLL_CON0_MUX_CLK_FSYS0_MAIN_USER 0x0140
579#define CLK_CON_DIV_CLK_FSYS0_125 0x1800
580#define CLK_CON_DIV_CLK_FSYS0_ADC 0x1804
581#define CLK_CON_DIV_CLK_FSYS0_BUS_300 0x1808
582#define CLK_CON_DIV_CLK_FSYS0_EQOS0 0x1814
583#define CLK_CON_DIV_CLK_FSYS0_EQOS1 0x1818
584#define CLK_CON_DIV_CLK_FSYS0_EQOS_250 0x181C
585#define CLK_CON_DIV_CLK_FSYS0_MMC_CARD0 0x1820
586#define CLK_CON_DIV_CLK_FSYS0_MMC_CARD1 0x1824
587#define CLK_CON_DIV_CLK_FSYS0_MMC_CARD2 0x1828
588#define CLK_CON_DIV_CLK_FSYS0_QSPI 0x182c
589#define CLK_CON_DIV_CLK_FSYS0_SFMC_NAND 0x1830
590#define CLK_CON_FSYS0_I2C0_IPCLKPORT_I_PCLK 0x2040
591#define CLK_CON_FSYS0_I2C1_IPCLKPORT_I_PCLK 0x2044
592#define CLK_CON_MMC0_IPCLKPORT_I_ACLK 0x2078
593#define CLK_CON_MMC1_IPCLKPORT_I_ACLK 0x2080
594#define CLK_CON_MMC2_IPCLKPORT_I_ACLK 0x2088
595#define CLK_CON_PWM_IPCLKPORT_I_PCLK_S0 0x2090
596#define CLK_CON_DMYQCH_CON_ADC_WRAP_QCH 0x3000
597#define CLK_CON_DMYQCH_CON_EQOS_TOP0_QCH 0x3004
598#define CLK_CON_DMYQCH_CON_EQOS_TOP1_QCH 0x3008
599#define CLK_CON_DMYQCH_CON_FSYS0_I3C0_QCH 0x3010
600#define CLK_CON_DMYQCH_CON_FSYS0_I3C1_QCH 0x3014
601#define CLK_CON_DMYQCH_CON_MMC0_QCH 0x3018
602#define CLK_CON_DMYQCH_CON_MMC1_QCH 0x301c
603#define CLK_CON_DMYQCH_CON_MMC2_QCH 0x3020
604#define CLK_CON_DMYQCH_CON_QSPI_QCH 0x3024
605#define CLK_CON_DMYQCH_CON_SFMC_QCH 0x3028
606
607static const unsigned long cmu_fsys0_clk_regs[] __initconst = {
608 PLL_CON0_MUX_CLK_FSYS0_BUS_USER,
609 PLL_CON0_MUX_CLK_FSYS0_IP_USER,
610 PLL_CON0_MUX_CLK_FSYS0_MAIN_USER,
611 CLK_CON_DIV_CLK_FSYS0_125,
612 CLK_CON_DIV_CLK_FSYS0_ADC,
613 CLK_CON_DIV_CLK_FSYS0_BUS_300,
614 CLK_CON_DIV_CLK_FSYS0_EQOS0,
615 CLK_CON_DIV_CLK_FSYS0_EQOS1,
616 CLK_CON_DIV_CLK_FSYS0_EQOS_250,
617 CLK_CON_DIV_CLK_FSYS0_MMC_CARD0,
618 CLK_CON_DIV_CLK_FSYS0_MMC_CARD1,
619 CLK_CON_DIV_CLK_FSYS0_MMC_CARD2,
620 CLK_CON_DIV_CLK_FSYS0_QSPI,
621 CLK_CON_DIV_CLK_FSYS0_SFMC_NAND,
622 CLK_CON_FSYS0_I2C0_IPCLKPORT_I_PCLK,
623 CLK_CON_FSYS0_I2C1_IPCLKPORT_I_PCLK,
624 CLK_CON_MMC0_IPCLKPORT_I_ACLK,
625 CLK_CON_MMC1_IPCLKPORT_I_ACLK,
626 CLK_CON_MMC2_IPCLKPORT_I_ACLK,
627 CLK_CON_PWM_IPCLKPORT_I_PCLK_S0,
628 CLK_CON_DMYQCH_CON_ADC_WRAP_QCH,
629 CLK_CON_DMYQCH_CON_EQOS_TOP0_QCH,
630 CLK_CON_DMYQCH_CON_EQOS_TOP1_QCH,
631 CLK_CON_DMYQCH_CON_FSYS0_I3C0_QCH,
632 CLK_CON_DMYQCH_CON_FSYS0_I3C1_QCH,
633 CLK_CON_DMYQCH_CON_MMC0_QCH,
634 CLK_CON_DMYQCH_CON_MMC1_QCH,
635 CLK_CON_DMYQCH_CON_MMC2_QCH,
636 CLK_CON_DMYQCH_CON_QSPI_QCH,
637 CLK_CON_DMYQCH_CON_SFMC_QCH,
638};
639
640PNAME(mout_fsys0_bus_user_p) = { "fin_pll", "dout_clkcmu_fsys0_bus" };
641PNAME(mout_fsys0_ip_user_p) = { "fin_pll", "dout_clkcmu_fsys0_ip" };
642PNAME(mout_fsys0_main_user_p) = { "fin_pll", "fout_pll_fsys1" };
643
644static const struct samsung_mux_clock cmu_fsys0_mux_clks[] __initconst = {
645 MUX(CLK_MOUT_FSYS0_BUS_USER, "mout_fsys0_bus_user",
646 mout_fsys0_bus_user_p, PLL_CON0_MUX_CLK_FSYS0_BUS_USER, 4, 1),
647 MUX(CLK_MOUT_FSYS0_IP_USER, "mout_fsys0_ip_user",
648 mout_fsys0_ip_user_p, PLL_CON0_MUX_CLK_FSYS0_IP_USER, 4, 1),
649 MUX(CLK_MOUT_FSYS0_MAIN_USER, "mout_fsys0_main_user",
650 mout_fsys0_main_user_p, PLL_CON0_MUX_CLK_FSYS0_MAIN_USER, 4, 1),
651};
652
653static const struct samsung_div_clock cmu_fsys0_div_clks[] __initconst = {
654 DIV(CLK_DOUT_FSYS0_125, "dout_fsys0_125", "mout_fsys0_main_user",
655 CLK_CON_DIV_CLK_FSYS0_125, 0, 5),
656 DIV(CLK_DOUT_FSYS0_ADC, "dout_fsys0_adc", "mout_fsys0_main_user",
657 CLK_CON_DIV_CLK_FSYS0_ADC, 0, 7),
658 DIV(CLK_DOUT_FSYS0_BUS_300, "dout_fsys0_bus_300", "mout_fsys0_bus_user",
659 CLK_CON_DIV_CLK_FSYS0_BUS_300, 0, 4),
660 DIV(CLK_DOUT_FSYS0_EQOS0, "dout_fsys0_eqos0", "dout_fsys0_eqos_250",
661 CLK_CON_DIV_CLK_FSYS0_EQOS0, 0, 7),
662 DIV(CLK_DOUT_FSYS0_EQOS1, "dout_fsys0_eqos1", "dout_fsys0_eqos_250",
663 CLK_CON_DIV_CLK_FSYS0_EQOS1, 0, 7),
664 DIV(0, "dout_fsys0_eqos_250", "mout_fsys0_main_user",
665 CLK_CON_DIV_CLK_FSYS0_EQOS_250, 0, 4),
666 DIV(CLK_DOUT_FSYS0_MMC_CARD0, "dout_fsys0_mmc_card0", "mout_fsys0_ip_user",
667 CLK_CON_DIV_CLK_FSYS0_MMC_CARD0, 0, 10),
668 DIV(CLK_DOUT_FSYS0_MMC_CARD1, "dout_fsys0_mmc_card1", "mout_fsys0_ip_user",
669 CLK_CON_DIV_CLK_FSYS0_MMC_CARD1, 0, 10),
670 DIV(CLK_DOUT_FSYS0_MMC_CARD2, "dout_fsys0_mmc_card2", "mout_fsys0_ip_user",
671 CLK_CON_DIV_CLK_FSYS0_MMC_CARD2, 0, 10),
672 DIV(CLK_DOUT_FSYS0_QSPI, "dout_fsys0_qspi", "mout_fsys0_ip_user",
673 CLK_CON_DIV_CLK_FSYS0_QSPI, 0, 4),
674 DIV(CLK_DOUT_FSYS0_SFMC_NAND, "dout_fsys0_sfmc_nand", "mout_fsys0_ip_user",
675 CLK_CON_DIV_CLK_FSYS0_SFMC_NAND, 0, 4),
676};
677
678static const struct samsung_gate_clock cmu_fsys0_gate_clks[] __initconst = {
679 GATE(0, "adc_wrap_ipclkport_clk", "dout_fsys0_adc",
680 CLK_CON_DMYQCH_CON_ADC_WRAP_QCH, 1, CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
681 GATE(CLK_GOUT_FSYS0_EQOS_TOP0_IPCLKPORT_ACLK_I, "eqos_top0_ipclkport_aclk_i",
682 "dout_fsys0_bus_300", CLK_CON_DMYQCH_CON_EQOS_TOP0_QCH, 1, CLK_SET_RATE_PARENT, 0),
683 GATE(CLK_GOUT_FSYS0_EQOS_TOP0_IPCLKPORT_CLK_CSR_I, "eqos_top0_ipclkport_clk_csr_i",
684 "dout_fsys0_bus_300", CLK_CON_DMYQCH_CON_EQOS_TOP0_QCH, 1, CLK_SET_RATE_PARENT, 0),
685 GATE(CLK_GOUT_FSYS0_EQOS_TOP0_IPCLKPORT_I_RGMII_PHASE_CLK_250,
686 "eqos_top0_ipclkport_i_rgmii_phase_clk_250",
687 "dout_fsys0_eqos_250", CLK_CON_DMYQCH_CON_EQOS_TOP0_QCH, 1, CLK_SET_RATE_PARENT, 0),
688 GATE(CLK_GOUT_FSYS0_EQOS_TOP0_IPCLKPORT_I_RGMII_TXCLK, "eqos_top0_ipclkport_i_rgmii_txclk",
689 "dout_fsys0_eqos0", CLK_CON_DMYQCH_CON_EQOS_TOP0_QCH, 1, CLK_SET_RATE_PARENT, 0),
690 GATE(CLK_GOUT_FSYS0_EQOS_TOP1_IPCLKPORT_I_RGMII_PHASE_CLK_250,
691 "eqos_top1_ipclkport_i_rgmii_phase_clk_250",
692 "dout_fsys0_eqos_250", CLK_CON_DMYQCH_CON_EQOS_TOP1_QCH, 1, CLK_SET_RATE_PARENT, 0),
693 GATE(CLK_GOUT_FSYS0_EQOS_TOP1_IPCLKPORT_I_RGMII_TXCLK, "eqos_top1_ipclkport_i_rgmii_txclk",
694 "dout_fsys0_eqos1", CLK_CON_DMYQCH_CON_EQOS_TOP1_QCH, 1, CLK_SET_RATE_PARENT, 0),
695 GATE(CLK_GOUT_FSYS0_EQOS_TOP1_IPCLKPORT_ACLK_I, "eqos_top1_ipclkport_aclk_i",
696 "dout_fsys0_bus_300", CLK_CON_DMYQCH_CON_EQOS_TOP1_QCH, 1, CLK_SET_RATE_PARENT, 0),
697 GATE(CLK_GOUT_FSYS0_EQOS_TOP1_IPCLKPORT_CLK_CSR_I, "eqos_top1_ipclkport_clk_csr_i",
698 "dout_fsys0_bus_300", CLK_CON_DMYQCH_CON_EQOS_TOP1_QCH, 1, CLK_SET_RATE_PARENT, 0),
699 GATE(CLK_GOUT_FSYS0_I3C0_IPCLKPORT_I_APB_S_PCLK, "i3c0_ipclkport_i_apb_s_pclk",
700 "dout_fsys0_bus_300", CLK_CON_DMYQCH_CON_FSYS0_I3C0_QCH, 1,
701 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
702 GATE(CLK_GOUT_FSYS0_I3C0_IPCLKPORT_I_CORE_CLK, "i3c0_ipclkport_i_core_clk",
703 "dout_fsys0_125", CLK_CON_DMYQCH_CON_FSYS0_I3C0_QCH, 1, CLK_SET_RATE_PARENT, 0),
704 GATE(CLK_GOUT_FSYS0_I3C0_IPCLKPORT_I_DMA_CLK, "i3c0_ipclkport_i_dma_clk",
705 "dout_fsys0_bus_300", CLK_CON_DMYQCH_CON_FSYS0_I3C0_QCH,
706 1, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
707 GATE(CLK_GOUT_FSYS0_I3C0_IPCLKPORT_I_HDR_TX_CLK, "i3c0_ipclkport_i_hdr_tx_clk",
708 "dout_fsys0_bus_300", CLK_CON_DMYQCH_CON_FSYS0_I3C0_QCH,
709 1, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
710 GATE(CLK_GOUT_FSYS0_I3C1_IPCLKPORT_I_APB_S_PCLK, "i3c1_ipclkport_i_apb_s_pclk",
711 "dout_fsys0_bus_300", CLK_CON_DMYQCH_CON_FSYS0_I3C1_QCH,
712 1, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
713 GATE(CLK_GOUT_FSYS0_I3C1_IPCLKPORT_I_CORE_CLK, "i3c1_ipclkport_i_core_clk",
714 "dout_fsys0_125", CLK_CON_DMYQCH_CON_FSYS0_I3C1_QCH, 1, CLK_SET_RATE_PARENT, 0),
715 GATE(CLK_GOUT_FSYS0_I3C1_IPCLKPORT_I_DMA_CLK, "i3c1_ipclkport_i_dma_clk",
716 "dout_fsys0_bus_300", CLK_CON_DMYQCH_CON_FSYS0_I3C1_QCH,
717 1, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
718 GATE(CLK_GOUT_FSYS0_I3C1_IPCLKPORT_I_HDR_TX_CLK, "i3c1_ipclkport_i_hdr_tx_clk",
719 "dout_fsys0_bus_300", CLK_CON_DMYQCH_CON_FSYS0_I3C1_QCH,
720 1, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
721 GATE(CLK_GOUT_FSYS0_MMC0_IPCLKPORT_SDCLKIN, "mmc0_ipclkport_sdclkin",
722 "dout_fsys0_mmc_card0", CLK_CON_DMYQCH_CON_MMC0_QCH, 1, CLK_SET_RATE_PARENT, 0),
723 GATE(CLK_GOUT_FSYS0_MMC1_IPCLKPORT_SDCLKIN, "mmc1_ipclkport_sdclkin",
724 "dout_fsys0_mmc_card1", CLK_CON_DMYQCH_CON_MMC1_QCH, 1, CLK_SET_RATE_PARENT, 0),
725 GATE(CLK_GOUT_FSYS0_MMC2_IPCLKPORT_SDCLKIN, "mmc2_ipclkport_sdclkin",
726 "dout_fsys0_mmc_card2", CLK_CON_DMYQCH_CON_MMC2_QCH, 1, CLK_SET_RATE_PARENT, 0),
727 GATE(CLK_GOUT_FSYS0_QSPI_IPCLKPORT_HCLK, "qspi_ipclkport_hclk",
728 "dout_fsys0_bus_300", CLK_CON_DMYQCH_CON_QSPI_QCH, 1, CLK_SET_RATE_PARENT, 0),
729 GATE(CLK_GOUT_FSYS0_QSPI_IPCLKPORT_SSI_CLK, "qspi_ipclkport_ssi_clk", "dout_fsys0_qspi",
730 CLK_CON_DMYQCH_CON_QSPI_QCH, 1, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
731 GATE(CLK_GOUT_FSYS0_SFMC_IPCLKPORT_I_ACLK_NAND, "sfmc_ipclkport_i_aclk_nand",
732 "dout_fsys0_sfmc_nand", CLK_CON_DMYQCH_CON_SFMC_QCH, 1, CLK_SET_RATE_PARENT, 0),
733 GATE(CLK_GOUT_FSYS0_I2C0_IPCLKPORT_I_PCLK, "i2c0_ipclkport_i_pclk", "dout_fsys0_bus_300",
734 CLK_CON_FSYS0_I2C0_IPCLKPORT_I_PCLK, 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
735 GATE(CLK_GOUT_FSYS0_I2C1_IPCLKPORT_I_PCLK, "i2c1_ipclkport_i_pclk", "dout_fsys0_bus_300",
736 CLK_CON_FSYS0_I2C1_IPCLKPORT_I_PCLK, 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
737 GATE(CLK_GOUT_FSYS0_MMC0_IPCLKPORT_I_ACLK, "mmc0_ipclkport_i_aclk", "dout_fsys0_bus_300",
738 CLK_CON_MMC0_IPCLKPORT_I_ACLK, 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
739 GATE(CLK_GOUT_FSYS0_MMC1_IPCLKPORT_I_ACLK, "mmc1_ipclkport_i_aclk", "dout_fsys0_bus_300",
740 CLK_CON_MMC1_IPCLKPORT_I_ACLK, 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
741 GATE(CLK_GOUT_FSYS0_MMC2_IPCLKPORT_I_ACLK, "mmc2_ipclkport_i_aclk", "dout_fsys0_bus_300",
742 CLK_CON_MMC2_IPCLKPORT_I_ACLK, 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
743 GATE(CLK_GOUT_FSYS0_PWM_IPCLKPORT_I_PCLK_S0, "pwm_ipclkport_i_pclk", "dout_fsys0_bus_300",
744 CLK_CON_PWM_IPCLKPORT_I_PCLK_S0, 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
745};
746
747static const struct samsung_cmu_info cmu_fsys0_info __initconst = {
748 .mux_clks = cmu_fsys0_mux_clks,
749 .nr_mux_clks = ARRAY_SIZE(cmu_fsys0_mux_clks),
750 .div_clks = cmu_fsys0_div_clks,
751 .nr_div_clks = ARRAY_SIZE(cmu_fsys0_div_clks),
752 .gate_clks = cmu_fsys0_gate_clks,
753 .nr_gate_clks = ARRAY_SIZE(cmu_fsys0_gate_clks),
754 .nr_clk_ids = CMU_FSYS0_NR_CLK,
755 .clk_regs = cmu_fsys0_clk_regs,
756 .nr_clk_regs = ARRAY_SIZE(cmu_fsys0_clk_regs),
757};
758
759/* Register Offset definitions for CMU_FSYS1 (0x14c10000) */
760#define PLL_LOCKTIME_PLL_FSYS1 0x0000
761#define PLL_CON0_MUX_CLK_FSYS1_BUS_USER 0x0100
762#define PLL_CON0_MUX_CLK_FSYS1_SCAN0_USER 0x0120
763#define PLL_CON0_MUX_CLK_FSYS1_SCAN1_USER 0x0140
764#define PLL_CON0_PLL_FSYS1 0x0160
765#define CLK_CON_DIV_CLK_FSYS1_200 0x1808
766#define CLK_CON_DIV_CLK_FSYS1_BUS_300 0x1810
767#define CLK_CON_DIV_CLK_FSYS1_OTP_MEM 0x1814
768#define CLK_CON_DIV_CLK_FSYS1_PCIE_PHY_REFCLK_SYSPLL 0x1818
769#define CLK_CON_FSYS1_UART0_IPCLKPORT_I_PCLK 0x202c
770#define CLK_CON_FSYS1_UART0_IPCLKPORT_I_SCLK_UART 0x2030
771#define CLK_CON_PCIE_TOP_IPCLKPORT_PCIE_PHY_APB2CR_PCLK_300 0x205c
772#define CLK_CON_PCIE_TOP_IPCLKPORT_PCIE_SUB_CON_X1_DBI_ACLK_SOC 0x2068
773#define CLK_CON_PCIE_TOP_IPCLKPORT_PCIE_SUB_CON_X1_MSTR_ACLK_SOC 0x206c
774#define CLK_CON_PCIE_TOP_IPCLKPORT_PCIE_SUB_CON_X1_SLV_ACLK_SOC 0x2070
775#define CLK_CON_PCIE_TOP_IPCLKPORT_PCIE_SUB_CON_X2_DBI_ACLK_SOC 0x2078
776#define CLK_CON_PCIE_TOP_IPCLKPORT_PCIE_SUB_CON_X2_MSTR_ACLK_SOC 0x2080
777#define CLK_CON_PCIE_TOP_IPCLKPORT_PCIE_SUB_CON_X2_SLV_ACLK_SOC 0x2084
778#define CLK_CON_USB20DRD_IPCLKPORT_ACLK_PHYCTRL_20 0x209c
779#define CLK_CON_USB20DRD_IPCLKPORT_BUS_CLK_EARLY 0x20a0
780#define CLK_CON_XHB_AHBBR_FSYS1_IPCLKPORT_CLK 0x20a8
781#define CLK_CON_XHB_USB_IPCLKPORT_CLK 0x20ac
782#define CLK_CON_DMYQCH_CON_TZ400_QCH 0x3004
783#define CLK_CON_DMYQCH_CON_PCIE_TOP_QCH_PHY_100 0x309c
784#define CLK_CON_QCH_CON_MMU_FSYS1_QCH_U_TBU_0_0 0x3050
785#define CLK_CON_QCH_CON_MMU_FSYS1_QCH_U_TBU_1_0 0x3058
786
787static const unsigned long cmu_fsys1_clk_regs[] __initconst = {
788 PLL_LOCKTIME_PLL_FSYS1,
789 PLL_CON0_MUX_CLK_FSYS1_BUS_USER,
790 PLL_CON0_MUX_CLK_FSYS1_SCAN0_USER,
791 PLL_CON0_MUX_CLK_FSYS1_SCAN1_USER,
792 PLL_CON0_PLL_FSYS1,
793 CLK_CON_DIV_CLK_FSYS1_200,
794 CLK_CON_DIV_CLK_FSYS1_BUS_300,
795 CLK_CON_DIV_CLK_FSYS1_OTP_MEM,
796 CLK_CON_DIV_CLK_FSYS1_PCIE_PHY_REFCLK_SYSPLL,
797 CLK_CON_FSYS1_UART0_IPCLKPORT_I_PCLK,
798 CLK_CON_FSYS1_UART0_IPCLKPORT_I_SCLK_UART,
799 CLK_CON_PCIE_TOP_IPCLKPORT_PCIE_PHY_APB2CR_PCLK_300,
800 CLK_CON_PCIE_TOP_IPCLKPORT_PCIE_SUB_CON_X1_DBI_ACLK_SOC,
801 CLK_CON_PCIE_TOP_IPCLKPORT_PCIE_SUB_CON_X1_MSTR_ACLK_SOC,
802 CLK_CON_PCIE_TOP_IPCLKPORT_PCIE_SUB_CON_X1_SLV_ACLK_SOC,
803 CLK_CON_PCIE_TOP_IPCLKPORT_PCIE_SUB_CON_X2_DBI_ACLK_SOC,
804 CLK_CON_PCIE_TOP_IPCLKPORT_PCIE_SUB_CON_X2_MSTR_ACLK_SOC,
805 CLK_CON_PCIE_TOP_IPCLKPORT_PCIE_SUB_CON_X2_SLV_ACLK_SOC,
806 CLK_CON_USB20DRD_IPCLKPORT_ACLK_PHYCTRL_20,
807 CLK_CON_USB20DRD_IPCLKPORT_BUS_CLK_EARLY,
808 CLK_CON_XHB_AHBBR_FSYS1_IPCLKPORT_CLK,
809 CLK_CON_XHB_USB_IPCLKPORT_CLK,
810 CLK_CON_DMYQCH_CON_TZ400_QCH,
811 CLK_CON_DMYQCH_CON_PCIE_TOP_QCH_PHY_100,
812 CLK_CON_QCH_CON_MMU_FSYS1_QCH_U_TBU_0_0,
813 CLK_CON_QCH_CON_MMU_FSYS1_QCH_U_TBU_1_0
814};
815
816static const struct samsung_pll_rate_table artpec9_pll_fsys1_rates[] __initconst = {
817 PLL_35XX_RATE(25 * MHZ, 2000000000U, 80, 1, 0),
818};
819
820static const struct samsung_pll_clock cmu_fsys1_pll_clks[] __initconst = {
821 PLL(pll_a9fracm, CLK_FOUT_FSYS1_PLL, "fout_pll_fsys1", "fin_pll",
822 PLL_LOCKTIME_PLL_FSYS1, PLL_CON0_PLL_FSYS1, artpec9_pll_fsys1_rates),
823};
824
825PNAME(mout_fsys1_scan0_user_p) = { "fin_pll", "dout_clkcmu_fsys1_scan0" };
826PNAME(mout_fsys1_scan1_user_p) = { "fin_pll", "dout_clkcmu_fsys1_scan1" };
827PNAME(mout_fsys1_bus_user_p) = { "fin_pll", "dout_clkcmu_fsys1_bus" };
828PNAME(mout_fsys_pll_fsys_p) = { "fin_pll", "fout_pll_fsys1" };
829
830static const struct samsung_mux_clock cmu_fsys1_mux_clks[] __initconst = {
831 MUX(0, "mout_clk_pll_fsys1", mout_fsys_pll_fsys_p, PLL_CON0_PLL_FSYS1, 4, 1),
832 MUX(CLK_MOUT_FSYS1_SCAN0_USER, "mout_fsys1_scan0_user",
833 mout_fsys1_scan0_user_p, PLL_CON0_MUX_CLK_FSYS1_SCAN0_USER, 4, 1),
834 MUX(CLK_MOUT_FSYS1_SCAN1_USER, "mout_fsys1_scan1_user",
835 mout_fsys1_scan1_user_p, PLL_CON0_MUX_CLK_FSYS1_SCAN1_USER, 4, 1),
836 MUX(CLK_MOUT_FSYS1_BUS_USER, "mout_fsys1_bus_user",
837 mout_fsys1_bus_user_p, PLL_CON0_MUX_CLK_FSYS1_BUS_USER, 4, 1),
838};
839
840static const struct samsung_div_clock cmu_fsys1_div_clks[] __initconst = {
841 DIV(CLK_DOUT_FSYS1_200, "dout_fsys1_200", "mout_clk_pll_fsys1",
842 CLK_CON_DIV_CLK_FSYS1_200, 0, 4),
843 DIV(CLK_DOUT_FSYS1_BUS_300, "dout_fsys1_bus_300", "mout_fsys1_bus_user",
844 CLK_CON_DIV_CLK_FSYS1_BUS_300, 0, 4),
845 DIV(CLK_DOUT_FSYS1_OTP_MEM, "dout_fsys1_otp_mem", "fin_pll",
846 CLK_CON_DIV_CLK_FSYS1_OTP_MEM, 0, 4),
847 DIV(CLK_DOUT_FSYS1_PCIE_PHY_REFCLK_SYSPLL, "dout_fsys1_pcie_phy_refclk_syspll",
848 "mout_clk_pll_fsys1", CLK_CON_DIV_CLK_FSYS1_PCIE_PHY_REFCLK_SYSPLL, 0, 5),
849};
850
851static const struct samsung_gate_clock cmu_fsys1_gate_clks[] __initconst = {
852 GATE(CLK_GOUT_FSYS1_IPCLKPORT_PCIE_PHY_APB2CR_PCLK_100,
853 "pcie_top_ipclkport_pcie_phy_apb2cr_pclk_100", "dout_fsys1_pcie_phy_refclk_syspll",
854 CLK_CON_DMYQCH_CON_PCIE_TOP_QCH_PHY_100, 1, CLK_SET_RATE_PARENT, 0),
855 GATE(0, "tzc400_ipclkport_aclk0", "mout_fsys1_bus_user",
856 CLK_CON_DMYQCH_CON_TZ400_QCH, 1, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
857 GATE(0, "tzc400_ipclkport_aclk1", "mout_fsys1_bus_user",
858 CLK_CON_DMYQCH_CON_TZ400_QCH, 1, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
859 GATE(0, "tzc400_ipclkport_pclk", "dout_fsys1_bus_300",
860 CLK_CON_DMYQCH_CON_TZ400_QCH, 1, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
861 GATE(CLK_GOUT_FSYS1_UART0_PCLK, "uart", "dout_fsys1_bus_300",
862 CLK_CON_FSYS1_UART0_IPCLKPORT_I_PCLK, 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
863 GATE(CLK_GOUT_FSYS1_UART0_SCLK_UART, "clk_uart_baud0", "dout_fsys1_200",
864 CLK_CON_FSYS1_UART0_IPCLKPORT_I_SCLK_UART, 21,
865 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
866 GATE(CLK_GOUT_FSYS1_IPCLKPORT_PCIE_PHY_APB2CR_PCLK_300,
867 "pcie_top_ipclkport_pcie_phy_apb2cr_pclk_300", "dout_fsys1_bus_300",
868 CLK_CON_PCIE_TOP_IPCLKPORT_PCIE_PHY_APB2CR_PCLK_300, 21,
869 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
870 GATE(CLK_GOUT_FSYS1_IPCLKPORT_PCIE_SUB_CON_X1_DBI_ACLK_SOC,
871 "pcie_top_ipclkport_pcie_sub_con_x1_dbi_aclk_soc", "dout_fsys1_bus_300",
872 CLK_CON_PCIE_TOP_IPCLKPORT_PCIE_SUB_CON_X1_DBI_ACLK_SOC,
873 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
874 GATE(CLK_GOUT_FSYS1_IPCLKPORT_PCIE_SUB_CON_X1_MSTR_ACLK_SOC,
875 "pcie_top_ipclkport_pcie_sub_con_x1_mstr_aclk_soc", "mout_fsys1_bus_user",
876 CLK_CON_PCIE_TOP_IPCLKPORT_PCIE_SUB_CON_X1_MSTR_ACLK_SOC,
877 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
878 GATE(CLK_GOUT_FSYS1_IPCLKPORT_PCIE_SUB_CON_X1_SLV_ACLK_SOC,
879 "pcie_top_ipclkport_pcie_sub_con_x1_slv_aclk_soc", "mout_fsys1_bus_user",
880 CLK_CON_PCIE_TOP_IPCLKPORT_PCIE_SUB_CON_X1_SLV_ACLK_SOC,
881 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
882 GATE(CLK_GOUT_FSYS1_IPCLKPORT_PCIE_SUB_CON_X2_DBI_ACLK_SOC,
883 "pcie_top_ipclkport_pcie_sub_con_x2_dbi_aclk_soc", "dout_fsys1_bus_300",
884 CLK_CON_PCIE_TOP_IPCLKPORT_PCIE_SUB_CON_X2_DBI_ACLK_SOC,
885 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
886 GATE(CLK_GOUT_FSYS1_IPCLKPORT_PCIE_SUB_CON_X2_MSTR_ACLK_SOC,
887 "pcie_top_ipclkport_pcie_sub_con_x2_mstr_aclk_soc", "mout_fsys1_bus_user",
888 CLK_CON_PCIE_TOP_IPCLKPORT_PCIE_SUB_CON_X2_MSTR_ACLK_SOC,
889 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
890 GATE(CLK_GOUT_FSYS1_IPCLKPORT_PCIE_SUB_CON_X2_SLV_ACLK_SOC,
891 "pcie_top_ipclkport_pcie_sub_con_x2_slv_aclk_soc", "mout_fsys1_bus_user",
892 CLK_CON_PCIE_TOP_IPCLKPORT_PCIE_SUB_CON_X2_SLV_ACLK_SOC,
893 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
894 GATE(CLK_GOUT_FSYS1_USB20DRD_IPCLKPORT_ACLK_PHYCTRL_20,
895 "usb20drd_ipclkport_aclk_phyctrl_20", "dout_fsys1_bus_300",
896 CLK_CON_USB20DRD_IPCLKPORT_ACLK_PHYCTRL_20,
897 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
898 GATE(CLK_GOUT_FSYS1_USB20DRD_IPCLKPORT_BUS_CLK_EARLY, "usb20drd_ipclkport_bus_clk_early",
899 "dout_fsys1_bus_300", CLK_CON_USB20DRD_IPCLKPORT_BUS_CLK_EARLY,
900 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
901 GATE(CLK_GOUT_FSYS1_XHB_AHBBR_FSYS1_IPCLKPORT_CLK, "xhb_ahbbr_fsys1_ipclkport_clk",
902 "dout_fsys1_bus_300", CLK_CON_XHB_AHBBR_FSYS1_IPCLKPORT_CLK,
903 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
904 GATE(CLK_GOUT_FSYS1_XHB_USB_IPCLKPORT_CLK, "xhb_usb_ipclkport_clk", "dout_fsys1_bus_300",
905 CLK_CON_XHB_USB_IPCLKPORT_CLK, 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
906 GATE(0, "qch_con_mmu_fsys1_qch_u_tbu_0_0", "mout_fsys1_bus_user",
907 CLK_CON_QCH_CON_MMU_FSYS1_QCH_U_TBU_0_0, 1, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
908 GATE(0, "qch_con_mmu_fsys1_qch_u_tbu_1_0", "mout_fsys1_bus_user",
909 CLK_CON_QCH_CON_MMU_FSYS1_QCH_U_TBU_1_0, 1, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
910};
911
912static const struct samsung_cmu_info cmu_fsys1_info __initconst = {
913 .pll_clks = cmu_fsys1_pll_clks,
914 .nr_pll_clks = ARRAY_SIZE(cmu_fsys1_pll_clks),
915 .mux_clks = cmu_fsys1_mux_clks,
916 .nr_mux_clks = ARRAY_SIZE(cmu_fsys1_mux_clks),
917 .div_clks = cmu_fsys1_div_clks,
918 .nr_div_clks = ARRAY_SIZE(cmu_fsys1_div_clks),
919 .gate_clks = cmu_fsys1_gate_clks,
920 .nr_gate_clks = ARRAY_SIZE(cmu_fsys1_gate_clks),
921 .nr_clk_ids = CMU_FSYS1_NR_CLK,
922 .clk_regs = cmu_fsys1_clk_regs,
923 .nr_clk_regs = ARRAY_SIZE(cmu_fsys1_clk_regs),
924};
925
926/* Register Offset definitions for CMU_IMEM (0x10010000) */
927#define PLL_CON0_MUX_CLK_IMEM_ACLK_USER 0x0100
928#define PLL_CON0_MUX_CLK_IMEM_CA5_USER 0x0120
929#define PLL_CON0_MUX_CLK_IMEM_JPEG_USER 0x0140
930#define PLL_CON0_MUX_CLK_IMEM_SSS_USER 0x0160
931#define CLK_CON_MCT0_IPCLKPORT_PCLK 0x20b4
932#define CLK_CON_MCT1_IPCLKPORT_PCLK 0x20b8
933#define CLK_CON_MCT2_IPCLKPORT_PCLK 0x20bc
934#define CLK_CON_MCT3_IPCLKPORT_PCLK 0x20c0
935#define CLK_CON_TMU_APB_IPCLKPORT_PCLK 0x20d4
936#define CLK_CON_DMYQCH_CON_CA5_0_QCH 0x3008
937#define CLK_CON_DMYQCH_CON_CA5_1_QCH 0x3018
938#define CLK_CON_DMYQCH_CON_INTMEM_QCH 0x3020
939#define CLK_CON_QCH_CON_GIC_CA55_QCHANNEL_SLAVE_0 0x306c
940#define CLK_CON_QCH_CON_GIC_CA5_0_QCH 0x3078
941#define CLK_CON_QCH_CON_GIC_CA5_1_QCH 0x307c
942#define CLK_CON_QCH_CON_MMU_IMEM_QCH_U_TBU_0_0 0x30ac
943#define CLK_CON_QCH_CON_MMU_IMEM_QCH_U_TBU_1_0 0x30b4
944
945static const unsigned long cmu_imem_clk_regs[] __initconst = {
946 PLL_CON0_MUX_CLK_IMEM_ACLK_USER,
947 PLL_CON0_MUX_CLK_IMEM_CA5_USER,
948 PLL_CON0_MUX_CLK_IMEM_JPEG_USER,
949 PLL_CON0_MUX_CLK_IMEM_SSS_USER,
950 CLK_CON_MCT0_IPCLKPORT_PCLK,
951 CLK_CON_MCT1_IPCLKPORT_PCLK,
952 CLK_CON_MCT2_IPCLKPORT_PCLK,
953 CLK_CON_MCT3_IPCLKPORT_PCLK,
954 CLK_CON_TMU_APB_IPCLKPORT_PCLK,
955 CLK_CON_DMYQCH_CON_CA5_0_QCH,
956 CLK_CON_DMYQCH_CON_CA5_1_QCH,
957 CLK_CON_DMYQCH_CON_INTMEM_QCH,
958 CLK_CON_QCH_CON_GIC_CA55_QCHANNEL_SLAVE_0,
959 CLK_CON_QCH_CON_GIC_CA5_0_QCH,
960 CLK_CON_QCH_CON_GIC_CA5_1_QCH,
961 CLK_CON_QCH_CON_MMU_IMEM_QCH_U_TBU_0_0,
962 CLK_CON_QCH_CON_MMU_IMEM_QCH_U_TBU_1_0
963};
964
965PNAME(mout_imem_aclk_user_p) = { "fin_pll", "dout_clkcmu_imem_aclk" };
966PNAME(mout_imem_ca5_user_p) = { "fin_pll", "dout_clkcmu_imem_ca5" };
967PNAME(mout_imem_jpeg_user_p) = { "fin_pll", "dout_clkcmu_imem_jpeg" };
968PNAME(mout_imem_sss_user_p) = { "fin_pll", "dout_clkcmu_imem_sss" };
969
970static const struct samsung_mux_clock cmu_imem_mux_clks[] __initconst = {
971 MUX(CLK_MOUT_IMEM_ACLK_USER, "mout_clk_imem_aclk_user",
972 mout_imem_aclk_user_p, PLL_CON0_MUX_CLK_IMEM_ACLK_USER, 4, 1),
973 MUX(CLK_MOUT_IMEM_CA5_USER, "mout_clk_imem_ca5_user",
974 mout_imem_ca5_user_p, PLL_CON0_MUX_CLK_IMEM_CA5_USER, 4, 1),
975 MUX(CLK_MOUT_IMEM_SSS_USER, "mout_clk_imem_sss_user",
976 mout_imem_sss_user_p, PLL_CON0_MUX_CLK_IMEM_SSS_USER, 4, 1),
977 MUX(CLK_MOUT_IMEM_JPEG_USER, "mout_clk_imem_jpeg_user",
978 mout_imem_jpeg_user_p, PLL_CON0_MUX_CLK_IMEM_JPEG_USER, 4, 1),
979};
980
981static const struct samsung_fixed_factor_clock imem_ffactor_clks[] __initconst = {
982 FFACTOR(CLK_DOUT_IMEM_PCLK, "dout_clk_imem_pclk", "mout_clk_imem_aclk_user", 1, 2, 0),
983};
984
985static const struct samsung_gate_clock cmu_imem_gate_clks[] __initconst = {
986 GATE(CLK_GOUT_IMEM_CA5_0_IPCLKPORT_ATCLK, "ca5_0_ipclkport_atclk",
987 "mout_clk_imem_ca5_user", CLK_CON_DMYQCH_CON_CA5_0_QCH, 1, CLK_SET_RATE_PARENT, 0),
988 GATE(CLK_GOUT_IMEM_CA5_0_IPCLKPORT_CLKIN, "ca5_0_ipclkport_clkin",
989 "mout_clk_imem_ca5_user", CLK_CON_DMYQCH_CON_CA5_0_QCH, 1, CLK_SET_RATE_PARENT, 0),
990 GATE(CLK_GOUT_IMEM_CA5_0_IPCLKPORT_PCLK_DBG, "ca5_0_ipclkport_pclk_dbg",
991 "mout_clk_imem_ca5_user", CLK_CON_DMYQCH_CON_CA5_0_QCH, 1, CLK_SET_RATE_PARENT, 0),
992 GATE(CLK_GOUT_IMEM_CA5_1_IPCLKPORT_ATCLK, "ca5_1_ipclkport_atclk",
993 "mout_clk_imem_ca5_user", CLK_CON_DMYQCH_CON_CA5_1_QCH, 1, CLK_SET_RATE_PARENT, 0),
994 GATE(CLK_GOUT_IMEM_CA5_1_IPCLKPORT_CLKIN, "ca5_1_ipclkport_clkin",
995 "mout_clk_imem_ca5_user", CLK_CON_DMYQCH_CON_CA5_1_QCH, 1, CLK_SET_RATE_PARENT, 0),
996 GATE(CLK_GOUT_IMEM_CA5_1_IPCLKPORT_PCLK_DBG, "ca5_1_ipclkport_pclk_dbg",
997 "mout_clk_imem_ca5_user", CLK_CON_DMYQCH_CON_CA5_1_QCH, 1, CLK_SET_RATE_PARENT, 0),
998 GATE(0, "intmem_ipclkport_aclk", "mout_clk_imem_aclk_user",
999 CLK_CON_DMYQCH_CON_INTMEM_QCH, 1, CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
1000 GATE(CLK_GOUT_IMEM_MCT0_PCLK, "mct0", "dout_clk_imem_pclk",
1001 CLK_CON_MCT0_IPCLKPORT_PCLK, 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
1002 GATE(CLK_GOUT_IMEM_MCT1_PCLK, "mct1", "dout_clk_imem_pclk",
1003 CLK_CON_MCT1_IPCLKPORT_PCLK, 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
1004 GATE(CLK_GOUT_IMEM_MCT2_PCLK, "mct2", "dout_clk_imem_pclk",
1005 CLK_CON_MCT2_IPCLKPORT_PCLK, 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
1006 GATE(CLK_GOUT_IMEM_MCT3_PCLK, "mct3", "dout_clk_imem_pclk",
1007 CLK_CON_MCT3_IPCLKPORT_PCLK, 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
1008 GATE(CLK_GOUT_IMEM_PCLK_TMU0_APBIF, "tmu_apb_ipclkport_pclk", "dout_clk_imem_pclk",
1009 CLK_CON_TMU_APB_IPCLKPORT_PCLK, 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
1010 GATE(0, "qch_con_gic_ca55_qchannel_slave_0", "dout_clk_imem_pclk",
1011 CLK_CON_QCH_CON_GIC_CA55_QCHANNEL_SLAVE_0, 1,
1012 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
1013 GATE(0, "qch_con_gic_ca5_0_qch", "dout_clk_imem_pclk",
1014 CLK_CON_QCH_CON_GIC_CA5_0_QCH, 1, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
1015 GATE(0, "qch_con_gic_ca5_1_qch", "dout_clk_imem_pclk",
1016 CLK_CON_QCH_CON_GIC_CA5_1_QCH, 1, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
1017 GATE(0, "qch_con_mmu_imem_qch_u_tbu_0_0", "mout_clk_imem_ca5_user",
1018 CLK_CON_QCH_CON_MMU_IMEM_QCH_U_TBU_0_0, 1, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
1019 GATE(0, "qch_con_mmu_imem_qch_u_tbu_1_0", "mout_clk_imem_ca5_user",
1020 CLK_CON_QCH_CON_MMU_IMEM_QCH_U_TBU_1_0, 1, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
1021};
1022
1023static const struct samsung_cmu_info cmu_imem_info __initconst = {
1024 .fixed_factor_clks = imem_ffactor_clks,
1025 .nr_fixed_factor_clks = ARRAY_SIZE(imem_ffactor_clks),
1026 .mux_clks = cmu_imem_mux_clks,
1027 .nr_mux_clks = ARRAY_SIZE(cmu_imem_mux_clks),
1028 .gate_clks = cmu_imem_gate_clks,
1029 .nr_gate_clks = ARRAY_SIZE(cmu_imem_gate_clks),
1030 .nr_clk_ids = CMU_IMEM_NR_CLK,
1031 .clk_regs = cmu_imem_clk_regs,
1032 .nr_clk_regs = ARRAY_SIZE(cmu_imem_clk_regs),
1033};
1034
1035static void __init artpec9_cmu_imem_init(struct device_node *np)
1036{
1037 exynos_arm64_register_cmu(NULL, np, &cmu_imem_info);
1038}
1039
1040CLK_OF_DECLARE(artpec9_cmu_imem, "axis,artpec9-cmu-imem", artpec9_cmu_imem_init);
1041
1042/* Register Offset definitions for CMU_PERI (0x14010000) */
1043#define PLL_CON0_MUX_CLK_PERI_DISP_USER 0x0100
1044#define PLL_CON0_MUX_CLK_PERI_IP_USER 0x0120
1045#define CLK_CON_DIV_CLK_PERI_125 0x1800
1046#define CLK_CON_DIV_CLK_PERI_PCLK 0x180c
1047#define CLK_CON_DIV_CLK_PERI_SPI 0x1810
1048#define CLK_CON_DIV_CLK_PERI_UART1 0x1814
1049#define CLK_CON_DIV_CLK_PERI_UART2 0x1818
1050#define CLK_CON_APB_ASYNC_DSIM_IPCLKPORT_PCLKS 0x2000
1051#define CLK_CON_PERI_I2C2_IPCLKPORT_I_PCLK 0x202c
1052#define CLK_CON_PERI_I2C3_IPCLKPORT_I_PCLK 0x2030
1053#define CLK_CON_PERI_SPI0_IPCLKPORT_I_PCLK 0x2054
1054#define CLK_CON_PERI_SPI0_IPCLKPORT_I_SCLK_SPI 0x2058
1055#define CLK_CON_PERI_UART1_IPCLKPORT_I_PCLK 0x205c
1056#define CLK_CON_PERI_UART1_IPCLKPORT_I_SCLK_UART 0x2060
1057#define CLK_CON_PERI_UART2_IPCLKPORT_I_PCLK 0x2064
1058#define CLK_CON_PERI_UART2_IPCLKPORT_I_SCLK_UART 0x2068
1059#define CLK_CON_DMYQCH_CON_DMA4DSIM_QCH 0x3000
1060#define CLK_CON_DMYQCH_CON_PERI_I3C2_QCH 0x3004
1061#define CLK_CON_DMYQCH_CON_PERI_I3C3_QCH 0x3008
1062
1063static const unsigned long cmu_peri_clk_regs[] __initconst = {
1064 PLL_CON0_MUX_CLK_PERI_DISP_USER,
1065 PLL_CON0_MUX_CLK_PERI_IP_USER,
1066 CLK_CON_DIV_CLK_PERI_125,
1067 CLK_CON_DIV_CLK_PERI_PCLK,
1068 CLK_CON_DIV_CLK_PERI_SPI,
1069 CLK_CON_DIV_CLK_PERI_UART1,
1070 CLK_CON_DIV_CLK_PERI_UART2,
1071 CLK_CON_APB_ASYNC_DSIM_IPCLKPORT_PCLKS,
1072 CLK_CON_PERI_I2C2_IPCLKPORT_I_PCLK,
1073 CLK_CON_PERI_I2C3_IPCLKPORT_I_PCLK,
1074 CLK_CON_PERI_SPI0_IPCLKPORT_I_PCLK,
1075 CLK_CON_PERI_SPI0_IPCLKPORT_I_SCLK_SPI,
1076 CLK_CON_PERI_UART1_IPCLKPORT_I_PCLK,
1077 CLK_CON_PERI_UART1_IPCLKPORT_I_SCLK_UART,
1078 CLK_CON_PERI_UART2_IPCLKPORT_I_PCLK,
1079 CLK_CON_PERI_UART2_IPCLKPORT_I_SCLK_UART,
1080 CLK_CON_DMYQCH_CON_DMA4DSIM_QCH,
1081 CLK_CON_DMYQCH_CON_PERI_I3C2_QCH,
1082 CLK_CON_DMYQCH_CON_PERI_I3C3_QCH,
1083};
1084
1085PNAME(mout_peri_ip_user_p) = { "fin_pll", "dout_clkcmu_peri_ip" };
1086PNAME(mout_peri_disp_user_p) = { "fin_pll", "dout_clkcmu_peri_disp" };
1087
1088static const struct samsung_mux_clock cmu_peri_mux_clks[] __initconst = {
1089 MUX(CLK_MOUT_PERI_IP_USER, "mout_peri_ip_user", mout_peri_ip_user_p,
1090 PLL_CON0_MUX_CLK_PERI_IP_USER, 4, 1),
1091 MUX(CLK_MOUT_PERI_DISP_USER, "mout_peri_disp_user", mout_peri_disp_user_p,
1092 PLL_CON0_MUX_CLK_PERI_DISP_USER, 4, 1),
1093};
1094
1095static const struct samsung_div_clock cmu_peri_div_clks[] __initconst = {
1096 DIV(CLK_DOUT_PERI_125, "dout_peri_125", "mout_peri_ip_user",
1097 CLK_CON_DIV_CLK_PERI_125, 0, 4),
1098 DIV(CLK_DOUT_PERI_PCLK, "dout_peri_pclk", "mout_peri_ip_user",
1099 CLK_CON_DIV_CLK_PERI_PCLK, 0, 4),
1100 DIV(CLK_DOUT_PERI_SPI, "dout_peri_spi", "mout_peri_ip_user",
1101 CLK_CON_DIV_CLK_PERI_SPI, 0, 13),
1102 DIV(CLK_DOUT_PERI_UART1, "dout_peri_uart1", "mout_peri_ip_user",
1103 CLK_CON_DIV_CLK_PERI_UART1, 0, 10),
1104 DIV(CLK_DOUT_PERI_UART2, "dout_peri_uart2", "mout_peri_ip_user",
1105 CLK_CON_DIV_CLK_PERI_UART2, 0, 10),
1106};
1107
1108static const struct samsung_gate_clock cmu_peri_gate_clks[] __initconst = {
1109 GATE(CLK_GOUT_PERI_DMA4DSIM_IPCLKPORT_CLK_APB_CLK, "dma4dsim_ipclkport_clk_apb_clk",
1110 "dout_peri_pclk", CLK_CON_DMYQCH_CON_DMA4DSIM_QCH, 1, CLK_SET_RATE_PARENT, 0),
1111 GATE(CLK_GOUT_PERI_DMA4DSIM_IPCLKPORT_CLK_AXI_CLK, "dma4dsim_ipclkport_clk_axi_clk",
1112 "mout_peri_disp_user", CLK_CON_DMYQCH_CON_DMA4DSIM_QCH, 1, CLK_SET_RATE_PARENT, 0),
1113 GATE(CLK_GOUT_PERI_I3C2_IPCLKPORT_I_APB_S_PCLK, "peri_i3c2_ipclkport_i_apb_s_pclk",
1114 "dout_peri_pclk", CLK_CON_DMYQCH_CON_PERI_I3C2_QCH, 1,
1115 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
1116 GATE(CLK_GOUT_PERI_I3C2_IPCLKPORT_I_CORE_CLK, "peri_i3c2_ipclkport_i_core_clk",
1117 "dout_peri_125", CLK_CON_DMYQCH_CON_PERI_I3C2_QCH, 1, CLK_SET_RATE_PARENT, 0),
1118 GATE(CLK_GOUT_PERI_I3C2_IPCLKPORT_I_DMA_CLK, "peri_i3c2_ipclkport_i_dma_clk",
1119 "dout_peri_pclk", CLK_CON_DMYQCH_CON_PERI_I3C2_QCH, 1,
1120 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
1121 GATE(CLK_GOUT_PERI_I3C2_IPCLKPORT_I_HDR_TX_CLK, "peri_i3c2_ipclkport_i_hdr_tx_clk",
1122 "dout_peri_pclk", CLK_CON_DMYQCH_CON_PERI_I3C2_QCH, 1,
1123 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
1124 GATE(CLK_GOUT_PERI_I3C3_IPCLKPORT_I_APB_S_PCLK, "peri_i3c3_ipclkport_i_apb_s_pclk",
1125 "dout_peri_pclk", CLK_CON_DMYQCH_CON_PERI_I3C3_QCH, 1,
1126 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
1127 GATE(CLK_GOUT_PERI_I3C3_IPCLKPORT_I_CORE_CLK, "peri_i3c3_ipclkport_i_core_clk",
1128 "dout_peri_125", CLK_CON_DMYQCH_CON_PERI_I3C3_QCH, 1, CLK_SET_RATE_PARENT, 0),
1129 GATE(CLK_GOUT_PERI_I3C3_IPCLKPORT_I_DMA_CLK, "peri_i3c3_ipclkport_i_dma_clk",
1130 "dout_peri_pclk", CLK_CON_DMYQCH_CON_PERI_I3C3_QCH, 1,
1131 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
1132 GATE(CLK_GOUT_PERI_I3C3_IPCLKPORT_I_HDR_TX_CLK, "peri_i3c3_ipclkport_i_hdr_tx_clk",
1133 "dout_peri_pclk", CLK_CON_DMYQCH_CON_PERI_I3C3_QCH, 1,
1134 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
1135 GATE(CLK_GOUT_PERI_APB_ASYNC_DSIM_IPCLKPORT_PCLKS, "apb_async_dsim_ipclkport_pclks",
1136 "dout_peri_pclk", CLK_CON_APB_ASYNC_DSIM_IPCLKPORT_PCLKS, 21,
1137 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
1138 GATE(CLK_GOUT_PERI_I2C2_IPCLKPORT_I_PCLK, "peri_i2c2_ipclkport_i_pclk",
1139 "dout_peri_pclk", CLK_CON_PERI_I2C2_IPCLKPORT_I_PCLK, 21,
1140 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
1141 GATE(CLK_GOUT_PERI_I2C3_IPCLKPORT_I_PCLK, "peri_i2c3_ipclkport_i_pclk",
1142 "dout_peri_pclk", CLK_CON_PERI_I2C3_IPCLKPORT_I_PCLK, 21,
1143 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
1144 GATE(CLK_GOUT_PERI_SPI0_PCLK, "peri_spi0_ipclkport_i_pclk",
1145 "dout_peri_pclk", CLK_CON_PERI_SPI0_IPCLKPORT_I_PCLK, 21,
1146 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
1147 GATE(CLK_GOUT_PERI_SPI0_SCLK_SPI, "peri_spi0_ipclkport_i_sclk_spi",
1148 "dout_peri_spi", CLK_CON_PERI_SPI0_IPCLKPORT_I_SCLK_SPI, 21,
1149 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
1150 GATE(CLK_GOUT_PERI_UART1_PCLK, "uart1", "dout_peri_pclk",
1151 CLK_CON_PERI_UART1_IPCLKPORT_I_PCLK, 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
1152 GATE(CLK_GOUT_PERI_UART1_SCLK_UART, "clk_uart_baud1", "dout_peri_uart1",
1153 CLK_CON_PERI_UART1_IPCLKPORT_I_SCLK_UART, 21,
1154 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
1155 GATE(CLK_GOUT_PERI_UART2_PCLK, "uart2", "dout_peri_pclk",
1156 CLK_CON_PERI_UART2_IPCLKPORT_I_PCLK, 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
1157 GATE(CLK_GOUT_PERI_UART2_SCLK_UART, "clk_uart_baud2", "dout_peri_uart2",
1158 CLK_CON_PERI_UART2_IPCLKPORT_I_SCLK_UART,
1159 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
1160};
1161
1162static const struct samsung_cmu_info cmu_peri_info __initconst = {
1163 .mux_clks = cmu_peri_mux_clks,
1164 .nr_mux_clks = ARRAY_SIZE(cmu_peri_mux_clks),
1165 .div_clks = cmu_peri_div_clks,
1166 .nr_div_clks = ARRAY_SIZE(cmu_peri_div_clks),
1167 .gate_clks = cmu_peri_gate_clks,
1168 .nr_gate_clks = ARRAY_SIZE(cmu_peri_gate_clks),
1169 .nr_clk_ids = CMU_PERI_NR_CLK,
1170 .clk_regs = cmu_peri_clk_regs,
1171 .nr_clk_regs = ARRAY_SIZE(cmu_peri_clk_regs),
1172};
1173
1174static int __init artpec9_cmu_probe(struct platform_device *pdev)
1175{
1176 const struct samsung_cmu_info *info;
1177 struct device *dev = &pdev->dev;
1178
1179 info = of_device_get_match_data(dev);
1180 exynos_arm64_register_cmu(dev, dev->of_node, info);
1181
1182 return 0;
1183}
1184
1185static const struct of_device_id artpec9_cmu_of_match[] = {
1186 {
1187 .compatible = "axis,artpec9-cmu-cmu",
1188 .data = &cmu_cmu_info,
1189 }, {
1190 .compatible = "axis,artpec9-cmu-bus",
1191 .data = &cmu_bus_info,
1192 }, {
1193 .compatible = "axis,artpec9-cmu-core",
1194 .data = &cmu_core_info,
1195 }, {
1196 .compatible = "axis,artpec9-cmu-cpucl",
1197 .data = &cmu_cpucl_info,
1198 }, {
1199 .compatible = "axis,artpec9-cmu-fsys0",
1200 .data = &cmu_fsys0_info,
1201 }, {
1202 .compatible = "axis,artpec9-cmu-fsys1",
1203 .data = &cmu_fsys1_info,
1204 }, {
1205 .compatible = "axis,artpec9-cmu-peri",
1206 .data = &cmu_peri_info,
1207 }, {
1208 },
1209};
1210
1211static struct platform_driver artpec9_cmu_driver __refdata = {
1212 .driver = {
1213 .name = "artpec9-cmu",
1214 .of_match_table = artpec9_cmu_of_match,
1215 .suppress_bind_attrs = true,
1216 },
1217 .probe = artpec9_cmu_probe,
1218};
1219
1220static int __init artpec9_cmu_init(void)
1221{
1222 return platform_driver_register(&artpec9_cmu_driver);
1223}
1224core_initcall(artpec9_cmu_init);