Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
4 *
5 * Common Clock Framework support for all PLL's in Samsung platforms
6*/
7
8#ifndef __SAMSUNG_CLK_CPU_H
9#define __SAMSUNG_CLK_CPU_H
10
11/* The CPU clock registers have DIV1 configuration register */
12#define CLK_CPU_HAS_DIV1 BIT(0)
13/* When ALT parent is active, debug clocks need safe divider values */
14#define CLK_CPU_NEEDS_DEBUG_ALT_DIV BIT(1)
15
16/**
17 * enum exynos_cpuclk_layout - CPU clock registers layout compatibility
18 * @CPUCLK_LAYOUT_E4210: Exynos4210 compatible layout
19 * @CPUCLK_LAYOUT_E5433: Exynos5433 compatible layout
20 * @CPUCLK_LAYOUT_E850_CL0: Exynos850 cluster 0 compatible layout
21 * @CPUCLK_LAYOUT_E850_CL1: Exynos850 cluster 1 compatible layout
22 */
23enum exynos_cpuclk_layout {
24 CPUCLK_LAYOUT_E4210,
25 CPUCLK_LAYOUT_E5433,
26 CPUCLK_LAYOUT_E850_CL0,
27 CPUCLK_LAYOUT_E850_CL1,
28};
29
30/**
31 * struct exynos_cpuclk_cfg_data - config data to setup cpu clocks
32 * @prate: frequency of the primary parent clock (in KHz)
33 * @div0: value to be programmed in the div_cpu0 register
34 * @div1: value to be programmed in the div_cpu1 register
35 *
36 * This structure holds the divider configuration data for dividers in the CPU
37 * clock domain. The parent frequency at which these divider values are valid is
38 * specified in @prate. The @prate is the frequency of the primary parent clock.
39 * For CPU clock domains that do not have a DIV1 register, the @div1 member
40 * value is not used.
41 */
42struct exynos_cpuclk_cfg_data {
43 unsigned long prate;
44 unsigned long div0;
45 unsigned long div1;
46};
47
48#endif /* __SAMSUNG_CLK_CPU_H */