Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
4 */
5
6#include <linux/io.h>
7#include <linux/delay.h>
8#include <linux/clk-provider.h>
9#include <linux/clkdev.h>
10#include <linux/init.h>
11#include <linux/of.h>
12#include <linux/of_address.h>
13#include <linux/platform_device.h>
14#include <linux/clk/tegra.h>
15
16#include <soc/tegra/pmc.h>
17
18#include <dt-bindings/clock/tegra30-car.h>
19
20#include "clk.h"
21#include "clk-id.h"
22
23#define OSC_CTRL 0x50
24#define OSC_CTRL_OSC_FREQ_MASK (0xF<<28)
25#define OSC_CTRL_OSC_FREQ_13MHZ (0X0<<28)
26#define OSC_CTRL_OSC_FREQ_19_2MHZ (0X4<<28)
27#define OSC_CTRL_OSC_FREQ_12MHZ (0X8<<28)
28#define OSC_CTRL_OSC_FREQ_26MHZ (0XC<<28)
29#define OSC_CTRL_OSC_FREQ_16_8MHZ (0X1<<28)
30#define OSC_CTRL_OSC_FREQ_38_4MHZ (0X5<<28)
31#define OSC_CTRL_OSC_FREQ_48MHZ (0X9<<28)
32#define OSC_CTRL_MASK (0x3f2 | OSC_CTRL_OSC_FREQ_MASK)
33
34#define OSC_CTRL_PLL_REF_DIV_MASK (3<<26)
35#define OSC_CTRL_PLL_REF_DIV_1 (0<<26)
36#define OSC_CTRL_PLL_REF_DIV_2 (1<<26)
37#define OSC_CTRL_PLL_REF_DIV_4 (2<<26)
38
39#define OSC_FREQ_DET 0x58
40#define OSC_FREQ_DET_TRIG BIT(31)
41
42#define OSC_FREQ_DET_STATUS 0x5c
43#define OSC_FREQ_DET_BUSY BIT(31)
44#define OSC_FREQ_DET_CNT_MASK 0xffff
45
46#define CCLKG_BURST_POLICY 0x368
47#define SUPER_CCLKG_DIVIDER 0x36c
48#define CCLKLP_BURST_POLICY 0x370
49#define SUPER_CCLKLP_DIVIDER 0x374
50#define SCLK_BURST_POLICY 0x028
51#define SUPER_SCLK_DIVIDER 0x02c
52
53#define SYSTEM_CLK_RATE 0x030
54
55#define TEGRA30_CLK_PERIPH_BANKS 5
56#define TEGRA30_CLK_CLK_MAX 311
57
58#define PLLC_BASE 0x80
59#define PLLC_MISC 0x8c
60#define PLLM_BASE 0x90
61#define PLLM_MISC 0x9c
62#define PLLP_BASE 0xa0
63#define PLLP_MISC 0xac
64#define PLLX_BASE 0xe0
65#define PLLX_MISC 0xe4
66#define PLLD_BASE 0xd0
67#define PLLD_MISC 0xdc
68#define PLLD2_BASE 0x4b8
69#define PLLD2_MISC 0x4bc
70#define PLLE_BASE 0xe8
71#define PLLE_MISC 0xec
72#define PLLA_BASE 0xb0
73#define PLLA_MISC 0xbc
74#define PLLU_BASE 0xc0
75#define PLLU_MISC 0xcc
76
77#define PLL_MISC_LOCK_ENABLE 18
78#define PLLDU_MISC_LOCK_ENABLE 22
79#define PLLE_MISC_LOCK_ENABLE 9
80
81#define PLL_BASE_LOCK BIT(27)
82#define PLLE_MISC_LOCK BIT(11)
83
84#define PLLE_AUX 0x48c
85#define PLLC_OUT 0x84
86#define PLLM_OUT 0x94
87#define PLLP_OUTA 0xa4
88#define PLLP_OUTB 0xa8
89#define PLLA_OUT 0xb4
90
91#define AUDIO_SYNC_CLK_I2S0 0x4a0
92#define AUDIO_SYNC_CLK_I2S1 0x4a4
93#define AUDIO_SYNC_CLK_I2S2 0x4a8
94#define AUDIO_SYNC_CLK_I2S3 0x4ac
95#define AUDIO_SYNC_CLK_I2S4 0x4b0
96#define AUDIO_SYNC_CLK_SPDIF 0x4b4
97
98#define CLK_SOURCE_SPDIF_OUT 0x108
99#define CLK_SOURCE_PWM 0x110
100#define CLK_SOURCE_D_AUDIO 0x3d0
101#define CLK_SOURCE_DAM0 0x3d8
102#define CLK_SOURCE_DAM1 0x3dc
103#define CLK_SOURCE_DAM2 0x3e0
104#define CLK_SOURCE_3D2 0x3b0
105#define CLK_SOURCE_2D 0x15c
106#define CLK_SOURCE_HDMI 0x18c
107#define CLK_SOURCE_DSIB 0xd0
108#define CLK_SOURCE_SE 0x42c
109#define CLK_SOURCE_EMC 0x19c
110
111#define AUDIO_SYNC_DOUBLER 0x49c
112
113/* Tegra CPU clock and reset control regs */
114#define TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX 0x4c
115#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET 0x340
116#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR 0x344
117#define TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR 0x34c
118#define TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS 0x470
119
120#define CPU_CLOCK(cpu) (0x1 << (8 + cpu))
121#define CPU_RESET(cpu) (0x1111ul << (cpu))
122
123#define CLK_RESET_CCLK_BURST 0x20
124#define CLK_RESET_CCLK_DIVIDER 0x24
125#define CLK_RESET_PLLX_BASE 0xe0
126#define CLK_RESET_PLLX_MISC 0xe4
127
128#define CLK_RESET_SOURCE_CSITE 0x1d4
129
130#define CLK_RESET_CCLK_BURST_POLICY_SHIFT 28
131#define CLK_RESET_CCLK_RUN_POLICY_SHIFT 4
132#define CLK_RESET_CCLK_IDLE_POLICY_SHIFT 0
133#define CLK_RESET_CCLK_IDLE_POLICY 1
134#define CLK_RESET_CCLK_RUN_POLICY 2
135#define CLK_RESET_CCLK_BURST_POLICY_PLLX 8
136
137/* PLLM override registers */
138#define PMC_PLLM_WB0_OVERRIDE 0x1dc
139
140#ifdef CONFIG_PM_SLEEP
141static struct cpu_clk_suspend_context {
142 u32 pllx_misc;
143 u32 pllx_base;
144
145 u32 cpu_burst;
146 u32 clk_csite_src;
147 u32 cclk_divider;
148} tegra30_cpu_clk_sctx;
149#endif
150
151static void __iomem *clk_base;
152static void __iomem *pmc_base;
153static unsigned long input_freq;
154
155static DEFINE_SPINLOCK(cml_lock);
156static DEFINE_SPINLOCK(pll_d_lock);
157static DEFINE_SPINLOCK(pll_d2_lock);
158
159#define TEGRA_INIT_DATA_MUX(_name, _parents, _offset, \
160 _clk_num, _gate_flags, _clk_id) \
161 TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \
162 30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, \
163 _clk_num, _gate_flags, _clk_id)
164
165#define TEGRA_INIT_DATA_MUX8(_name, _parents, _offset, \
166 _clk_num, _gate_flags, _clk_id) \
167 TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \
168 29, 3, 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, \
169 _clk_num, _gate_flags, _clk_id)
170
171#define TEGRA_INIT_DATA_INT(_name, _parents, _offset, \
172 _clk_num, _gate_flags, _clk_id) \
173 TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \
174 30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_INT | \
175 TEGRA_DIVIDER_ROUND_UP, _clk_num, \
176 _gate_flags, _clk_id)
177
178#define TEGRA_INIT_DATA_NODIV(_name, _parents, _offset, \
179 _mux_shift, _mux_width, _clk_num, \
180 _gate_flags, _clk_id) \
181 TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \
182 _mux_shift, _mux_width, 0, 0, 0, 0, 0,\
183 _clk_num, _gate_flags, \
184 _clk_id)
185
186static struct clk **clks;
187
188static struct tegra_clk_pll_freq_table pll_c_freq_table[] = {
189 { 12000000, 1040000000, 520, 6, 1, 8 },
190 { 13000000, 1040000000, 480, 6, 1, 8 },
191 { 16800000, 1040000000, 495, 8, 1, 8 }, /* actual: 1039.5 MHz */
192 { 19200000, 1040000000, 325, 6, 1, 6 },
193 { 26000000, 1040000000, 520, 13, 1, 8 },
194 { 12000000, 832000000, 416, 6, 1, 8 },
195 { 13000000, 832000000, 832, 13, 1, 8 },
196 { 16800000, 832000000, 396, 8, 1, 8 }, /* actual: 831.6 MHz */
197 { 19200000, 832000000, 260, 6, 1, 8 },
198 { 26000000, 832000000, 416, 13, 1, 8 },
199 { 12000000, 624000000, 624, 12, 1, 8 },
200 { 13000000, 624000000, 624, 13, 1, 8 },
201 { 16800000, 600000000, 520, 14, 1, 8 },
202 { 19200000, 624000000, 520, 16, 1, 8 },
203 { 26000000, 624000000, 624, 26, 1, 8 },
204 { 12000000, 600000000, 600, 12, 1, 8 },
205 { 13000000, 600000000, 600, 13, 1, 8 },
206 { 16800000, 600000000, 500, 14, 1, 8 },
207 { 19200000, 600000000, 375, 12, 1, 6 },
208 { 26000000, 600000000, 600, 26, 1, 8 },
209 { 12000000, 520000000, 520, 12, 1, 8 },
210 { 13000000, 520000000, 520, 13, 1, 8 },
211 { 16800000, 520000000, 495, 16, 1, 8 }, /* actual: 519.75 MHz */
212 { 19200000, 520000000, 325, 12, 1, 6 },
213 { 26000000, 520000000, 520, 26, 1, 8 },
214 { 12000000, 416000000, 416, 12, 1, 8 },
215 { 13000000, 416000000, 416, 13, 1, 8 },
216 { 16800000, 416000000, 396, 16, 1, 8 }, /* actual: 415.8 MHz */
217 { 19200000, 416000000, 260, 12, 1, 6 },
218 { 26000000, 416000000, 416, 26, 1, 8 },
219 { 0, 0, 0, 0, 0, 0 },
220};
221
222static struct tegra_clk_pll_freq_table pll_m_freq_table[] = {
223 { 12000000, 666000000, 666, 12, 1, 8 },
224 { 13000000, 666000000, 666, 13, 1, 8 },
225 { 16800000, 666000000, 555, 14, 1, 8 },
226 { 19200000, 666000000, 555, 16, 1, 8 },
227 { 26000000, 666000000, 666, 26, 1, 8 },
228 { 12000000, 600000000, 600, 12, 1, 8 },
229 { 13000000, 600000000, 600, 13, 1, 8 },
230 { 16800000, 600000000, 500, 14, 1, 8 },
231 { 19200000, 600000000, 375, 12, 1, 6 },
232 { 26000000, 600000000, 600, 26, 1, 8 },
233 { 0, 0, 0, 0, 0, 0 },
234};
235
236static struct tegra_clk_pll_freq_table pll_p_freq_table[] = {
237 { 12000000, 216000000, 432, 12, 2, 8 },
238 { 13000000, 216000000, 432, 13, 2, 8 },
239 { 16800000, 216000000, 360, 14, 2, 8 },
240 { 19200000, 216000000, 360, 16, 2, 8 },
241 { 26000000, 216000000, 432, 26, 2, 8 },
242 { 0, 0, 0, 0, 0, 0 },
243};
244
245static struct tegra_clk_pll_freq_table pll_a_freq_table[] = {
246 { 9600000, 564480000, 294, 5, 1, 4 },
247 { 9600000, 552960000, 288, 5, 1, 4 },
248 { 9600000, 24000000, 5, 2, 1, 1 },
249 { 28800000, 56448000, 49, 25, 1, 1 },
250 { 28800000, 73728000, 64, 25, 1, 1 },
251 { 28800000, 24000000, 5, 6, 1, 1 },
252 { 0, 0, 0, 0, 0, 0 },
253};
254
255static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
256 { 12000000, 216000000, 216, 12, 1, 4 },
257 { 13000000, 216000000, 216, 13, 1, 4 },
258 { 16800000, 216000000, 180, 14, 1, 4 },
259 { 19200000, 216000000, 180, 16, 1, 4 },
260 { 26000000, 216000000, 216, 26, 1, 4 },
261 { 12000000, 594000000, 594, 12, 1, 8 },
262 { 13000000, 594000000, 594, 13, 1, 8 },
263 { 16800000, 594000000, 495, 14, 1, 8 },
264 { 19200000, 594000000, 495, 16, 1, 8 },
265 { 26000000, 594000000, 594, 26, 1, 8 },
266 { 12000000, 1000000000, 1000, 12, 1, 12 },
267 { 13000000, 1000000000, 1000, 13, 1, 12 },
268 { 19200000, 1000000000, 625, 12, 1, 8 },
269 { 26000000, 1000000000, 1000, 26, 1, 12 },
270 { 0, 0, 0, 0, 0, 0 },
271};
272
273static const struct pdiv_map pllu_p[] = {
274 { .pdiv = 1, .hw_val = 1 },
275 { .pdiv = 2, .hw_val = 0 },
276 { .pdiv = 0, .hw_val = 0 },
277};
278
279static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
280 { 12000000, 480000000, 960, 12, 2, 12 },
281 { 13000000, 480000000, 960, 13, 2, 12 },
282 { 16800000, 480000000, 400, 7, 2, 5 },
283 { 19200000, 480000000, 200, 4, 2, 3 },
284 { 26000000, 480000000, 960, 26, 2, 12 },
285 { 0, 0, 0, 0, 0, 0 },
286};
287
288static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
289 /* 1.7 GHz */
290 { 12000000, 1700000000, 850, 6, 1, 8 },
291 { 13000000, 1700000000, 915, 7, 1, 8 }, /* actual: 1699.2 MHz */
292 { 16800000, 1700000000, 708, 7, 1, 8 }, /* actual: 1699.2 MHz */
293 { 19200000, 1700000000, 885, 10, 1, 8 }, /* actual: 1699.2 MHz */
294 { 26000000, 1700000000, 850, 13, 1, 8 },
295 /* 1.6 GHz */
296 { 12000000, 1600000000, 800, 6, 1, 8 },
297 { 13000000, 1600000000, 738, 6, 1, 8 }, /* actual: 1599.0 MHz */
298 { 16800000, 1600000000, 857, 9, 1, 8 }, /* actual: 1599.7 MHz */
299 { 19200000, 1600000000, 500, 6, 1, 8 },
300 { 26000000, 1600000000, 800, 13, 1, 8 },
301 /* 1.5 GHz */
302 { 12000000, 1500000000, 750, 6, 1, 8 },
303 { 13000000, 1500000000, 923, 8, 1, 8 }, /* actual: 1499.8 MHz */
304 { 16800000, 1500000000, 625, 7, 1, 8 },
305 { 19200000, 1500000000, 625, 8, 1, 8 },
306 { 26000000, 1500000000, 750, 13, 1, 8 },
307 /* 1.4 GHz */
308 { 12000000, 1400000000, 700, 6, 1, 8 },
309 { 13000000, 1400000000, 969, 9, 1, 8 }, /* actual: 1399.7 MHz */
310 { 16800000, 1400000000, 1000, 12, 1, 8 },
311 { 19200000, 1400000000, 875, 12, 1, 8 },
312 { 26000000, 1400000000, 700, 13, 1, 8 },
313 /* 1.3 GHz */
314 { 12000000, 1300000000, 975, 9, 1, 8 },
315 { 13000000, 1300000000, 1000, 10, 1, 8 },
316 { 16800000, 1300000000, 928, 12, 1, 8 }, /* actual: 1299.2 MHz */
317 { 19200000, 1300000000, 812, 12, 1, 8 }, /* actual: 1299.2 MHz */
318 { 26000000, 1300000000, 650, 13, 1, 8 },
319 /* 1.2 GHz */
320 { 12000000, 1200000000, 1000, 10, 1, 8 },
321 { 13000000, 1200000000, 923, 10, 1, 8 }, /* actual: 1199.9 MHz */
322 { 16800000, 1200000000, 1000, 14, 1, 8 },
323 { 19200000, 1200000000, 1000, 16, 1, 8 },
324 { 26000000, 1200000000, 600, 13, 1, 8 },
325 /* 1.1 GHz */
326 { 12000000, 1100000000, 825, 9, 1, 8 },
327 { 13000000, 1100000000, 846, 10, 1, 8 }, /* actual: 1099.8 MHz */
328 { 16800000, 1100000000, 982, 15, 1, 8 }, /* actual: 1099.8 MHz */
329 { 19200000, 1100000000, 859, 15, 1, 8 }, /* actual: 1099.5 MHz */
330 { 26000000, 1100000000, 550, 13, 1, 8 },
331 /* 1 GHz */
332 { 12000000, 1000000000, 1000, 12, 1, 8 },
333 { 13000000, 1000000000, 1000, 13, 1, 8 },
334 { 16800000, 1000000000, 833, 14, 1, 8 }, /* actual: 999.6 MHz */
335 { 19200000, 1000000000, 625, 12, 1, 8 },
336 { 26000000, 1000000000, 1000, 26, 1, 8 },
337 { 0, 0, 0, 0, 0, 0 },
338};
339
340static const struct pdiv_map plle_p[] = {
341 { .pdiv = 18, .hw_val = 18 },
342 { .pdiv = 24, .hw_val = 24 },
343 { .pdiv = 0, .hw_val = 0 },
344};
345
346static struct tegra_clk_pll_freq_table pll_e_freq_table[] = {
347 /* PLLE special case: use cpcon field to store cml divider value */
348 { 12000000, 100000000, 150, 1, 18, 11 },
349 { 216000000, 100000000, 200, 18, 24, 13 },
350 { 0, 0, 0, 0, 0, 0 },
351};
352
353/* PLL parameters */
354static struct tegra_clk_pll_params pll_c_params __ro_after_init = {
355 .input_min = 2000000,
356 .input_max = 31000000,
357 .cf_min = 1000000,
358 .cf_max = 6000000,
359 .vco_min = 20000000,
360 .vco_max = 1400000000,
361 .base_reg = PLLC_BASE,
362 .misc_reg = PLLC_MISC,
363 .lock_mask = PLL_BASE_LOCK,
364 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
365 .lock_delay = 300,
366 .freq_table = pll_c_freq_table,
367 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK |
368 TEGRA_PLL_HAS_LOCK_ENABLE,
369};
370
371static struct div_nmp pllm_nmp = {
372 .divn_shift = 8,
373 .divn_width = 10,
374 .override_divn_shift = 5,
375 .divm_shift = 0,
376 .divm_width = 5,
377 .override_divm_shift = 0,
378 .divp_shift = 20,
379 .divp_width = 3,
380 .override_divp_shift = 15,
381};
382
383static struct tegra_clk_pll_params pll_m_params __ro_after_init = {
384 .input_min = 2000000,
385 .input_max = 31000000,
386 .cf_min = 1000000,
387 .cf_max = 6000000,
388 .vco_min = 20000000,
389 .vco_max = 1200000000,
390 .base_reg = PLLM_BASE,
391 .misc_reg = PLLM_MISC,
392 .lock_mask = PLL_BASE_LOCK,
393 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
394 .lock_delay = 300,
395 .div_nmp = &pllm_nmp,
396 .pmc_divnm_reg = PMC_PLLM_WB0_OVERRIDE,
397 .pmc_divp_reg = PMC_PLLM_WB0_OVERRIDE,
398 .freq_table = pll_m_freq_table,
399 .flags = TEGRA_PLLM | TEGRA_PLL_HAS_CPCON |
400 TEGRA_PLL_SET_DCCON | TEGRA_PLL_USE_LOCK |
401 TEGRA_PLL_HAS_LOCK_ENABLE | TEGRA_PLL_FIXED,
402};
403
404static struct tegra_clk_pll_params pll_p_params __ro_after_init = {
405 .input_min = 2000000,
406 .input_max = 31000000,
407 .cf_min = 1000000,
408 .cf_max = 6000000,
409 .vco_min = 20000000,
410 .vco_max = 1400000000,
411 .base_reg = PLLP_BASE,
412 .misc_reg = PLLP_MISC,
413 .lock_mask = PLL_BASE_LOCK,
414 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
415 .lock_delay = 300,
416 .freq_table = pll_p_freq_table,
417 .flags = TEGRA_PLL_FIXED | TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK |
418 TEGRA_PLL_HAS_LOCK_ENABLE,
419 .fixed_rate = 408000000,
420};
421
422static struct tegra_clk_pll_params pll_a_params = {
423 .input_min = 2000000,
424 .input_max = 31000000,
425 .cf_min = 1000000,
426 .cf_max = 6000000,
427 .vco_min = 20000000,
428 .vco_max = 1400000000,
429 .base_reg = PLLA_BASE,
430 .misc_reg = PLLA_MISC,
431 .lock_mask = PLL_BASE_LOCK,
432 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
433 .lock_delay = 300,
434 .freq_table = pll_a_freq_table,
435 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK |
436 TEGRA_PLL_HAS_LOCK_ENABLE,
437};
438
439static struct tegra_clk_pll_params pll_d_params __ro_after_init = {
440 .input_min = 2000000,
441 .input_max = 40000000,
442 .cf_min = 1000000,
443 .cf_max = 6000000,
444 .vco_min = 40000000,
445 .vco_max = 1000000000,
446 .base_reg = PLLD_BASE,
447 .misc_reg = PLLD_MISC,
448 .lock_mask = PLL_BASE_LOCK,
449 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
450 .lock_delay = 1000,
451 .freq_table = pll_d_freq_table,
452 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
453 TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
454};
455
456static struct tegra_clk_pll_params pll_d2_params __ro_after_init = {
457 .input_min = 2000000,
458 .input_max = 40000000,
459 .cf_min = 1000000,
460 .cf_max = 6000000,
461 .vco_min = 40000000,
462 .vco_max = 1000000000,
463 .base_reg = PLLD2_BASE,
464 .misc_reg = PLLD2_MISC,
465 .lock_mask = PLL_BASE_LOCK,
466 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
467 .lock_delay = 1000,
468 .freq_table = pll_d_freq_table,
469 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
470 TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
471};
472
473static struct tegra_clk_pll_params pll_u_params __ro_after_init = {
474 .input_min = 2000000,
475 .input_max = 40000000,
476 .cf_min = 1000000,
477 .cf_max = 6000000,
478 .vco_min = 48000000,
479 .vco_max = 960000000,
480 .base_reg = PLLU_BASE,
481 .misc_reg = PLLU_MISC,
482 .lock_mask = PLL_BASE_LOCK,
483 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
484 .lock_delay = 1000,
485 .pdiv_tohw = pllu_p,
486 .freq_table = pll_u_freq_table,
487 .flags = TEGRA_PLLU | TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
488 TEGRA_PLL_HAS_LOCK_ENABLE,
489};
490
491static struct tegra_clk_pll_params pll_x_params __ro_after_init = {
492 .input_min = 2000000,
493 .input_max = 31000000,
494 .cf_min = 1000000,
495 .cf_max = 6000000,
496 .vco_min = 20000000,
497 .vco_max = 1700000000,
498 .base_reg = PLLX_BASE,
499 .misc_reg = PLLX_MISC,
500 .lock_mask = PLL_BASE_LOCK,
501 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
502 .lock_delay = 300,
503 .freq_table = pll_x_freq_table,
504 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_DCCON |
505 TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
506 .pre_rate_change = tegra_cclk_pre_pllx_rate_change,
507 .post_rate_change = tegra_cclk_post_pllx_rate_change,
508};
509
510static struct tegra_clk_pll_params pll_e_params __ro_after_init = {
511 .input_min = 12000000,
512 .input_max = 216000000,
513 .cf_min = 12000000,
514 .cf_max = 12000000,
515 .vco_min = 1200000000,
516 .vco_max = 2400000000U,
517 .base_reg = PLLE_BASE,
518 .misc_reg = PLLE_MISC,
519 .lock_mask = PLLE_MISC_LOCK,
520 .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE,
521 .lock_delay = 300,
522 .pdiv_tohw = plle_p,
523 .freq_table = pll_e_freq_table,
524 .flags = TEGRA_PLLE_CONFIGURE | TEGRA_PLL_FIXED |
525 TEGRA_PLL_HAS_LOCK_ENABLE | TEGRA_PLL_LOCK_MISC,
526 .fixed_rate = 100000000,
527};
528
529static unsigned long tegra30_input_freq[] = {
530 [ 0] = 13000000,
531 [ 1] = 16800000,
532 [ 4] = 19200000,
533 [ 5] = 38400000,
534 [ 8] = 12000000,
535 [ 9] = 48000000,
536 [12] = 26000000,
537};
538
539static struct tegra_devclk devclks[] = {
540 { .con_id = "pll_c", .dt_id = TEGRA30_CLK_PLL_C },
541 { .con_id = "pll_c_out1", .dt_id = TEGRA30_CLK_PLL_C_OUT1 },
542 { .con_id = "pll_p", .dt_id = TEGRA30_CLK_PLL_P },
543 { .con_id = "pll_p_out1", .dt_id = TEGRA30_CLK_PLL_P_OUT1 },
544 { .con_id = "pll_p_out2", .dt_id = TEGRA30_CLK_PLL_P_OUT2 },
545 { .con_id = "pll_p_out3", .dt_id = TEGRA30_CLK_PLL_P_OUT3 },
546 { .con_id = "pll_p_out4", .dt_id = TEGRA30_CLK_PLL_P_OUT4 },
547 { .con_id = "pll_m", .dt_id = TEGRA30_CLK_PLL_M },
548 { .con_id = "pll_m_out1", .dt_id = TEGRA30_CLK_PLL_M_OUT1 },
549 { .con_id = "pll_x", .dt_id = TEGRA30_CLK_PLL_X },
550 { .con_id = "pll_x_out0", .dt_id = TEGRA30_CLK_PLL_X_OUT0 },
551 { .con_id = "pll_u", .dt_id = TEGRA30_CLK_PLL_U },
552 { .con_id = "pll_d", .dt_id = TEGRA30_CLK_PLL_D },
553 { .con_id = "pll_d_out0", .dt_id = TEGRA30_CLK_PLL_D_OUT0 },
554 { .con_id = "pll_d2", .dt_id = TEGRA30_CLK_PLL_D2 },
555 { .con_id = "pll_d2_out0", .dt_id = TEGRA30_CLK_PLL_D2_OUT0 },
556 { .con_id = "pll_a", .dt_id = TEGRA30_CLK_PLL_A },
557 { .con_id = "pll_a_out0", .dt_id = TEGRA30_CLK_PLL_A_OUT0 },
558 { .con_id = "pll_e", .dt_id = TEGRA30_CLK_PLL_E },
559 { .con_id = "spdif_in_sync", .dt_id = TEGRA30_CLK_SPDIF_IN_SYNC },
560 { .con_id = "i2s0_sync", .dt_id = TEGRA30_CLK_I2S0_SYNC },
561 { .con_id = "i2s1_sync", .dt_id = TEGRA30_CLK_I2S1_SYNC },
562 { .con_id = "i2s2_sync", .dt_id = TEGRA30_CLK_I2S2_SYNC },
563 { .con_id = "i2s3_sync", .dt_id = TEGRA30_CLK_I2S3_SYNC },
564 { .con_id = "i2s4_sync", .dt_id = TEGRA30_CLK_I2S4_SYNC },
565 { .con_id = "vimclk_sync", .dt_id = TEGRA30_CLK_VIMCLK_SYNC },
566 { .con_id = "audio0", .dt_id = TEGRA30_CLK_AUDIO0 },
567 { .con_id = "audio1", .dt_id = TEGRA30_CLK_AUDIO1 },
568 { .con_id = "audio2", .dt_id = TEGRA30_CLK_AUDIO2 },
569 { .con_id = "audio3", .dt_id = TEGRA30_CLK_AUDIO3 },
570 { .con_id = "audio4", .dt_id = TEGRA30_CLK_AUDIO4 },
571 { .con_id = "spdif", .dt_id = TEGRA30_CLK_SPDIF },
572 { .con_id = "audio0_2x", .dt_id = TEGRA30_CLK_AUDIO0_2X },
573 { .con_id = "audio1_2x", .dt_id = TEGRA30_CLK_AUDIO1_2X },
574 { .con_id = "audio2_2x", .dt_id = TEGRA30_CLK_AUDIO2_2X },
575 { .con_id = "audio3_2x", .dt_id = TEGRA30_CLK_AUDIO3_2X },
576 { .con_id = "audio4_2x", .dt_id = TEGRA30_CLK_AUDIO4_2X },
577 { .con_id = "spdif_2x", .dt_id = TEGRA30_CLK_SPDIF_2X },
578 { .con_id = "extern1", .dt_id = TEGRA30_CLK_EXTERN1 },
579 { .con_id = "extern2", .dt_id = TEGRA30_CLK_EXTERN2 },
580 { .con_id = "extern3", .dt_id = TEGRA30_CLK_EXTERN3 },
581 { .con_id = "cclk_g", .dt_id = TEGRA30_CLK_CCLK_G },
582 { .con_id = "cclk_lp", .dt_id = TEGRA30_CLK_CCLK_LP },
583 { .con_id = "sclk", .dt_id = TEGRA30_CLK_SCLK },
584 { .con_id = "hclk", .dt_id = TEGRA30_CLK_HCLK },
585 { .con_id = "pclk", .dt_id = TEGRA30_CLK_PCLK },
586 { .con_id = "twd", .dt_id = TEGRA30_CLK_TWD },
587 { .con_id = "emc", .dt_id = TEGRA30_CLK_EMC },
588 { .con_id = "clk_32k", .dt_id = TEGRA30_CLK_CLK_32K },
589 { .con_id = "osc", .dt_id = TEGRA30_CLK_OSC },
590 { .con_id = "osc_div2", .dt_id = TEGRA30_CLK_OSC_DIV2 },
591 { .con_id = "osc_div4", .dt_id = TEGRA30_CLK_OSC_DIV4 },
592 { .con_id = "cml0", .dt_id = TEGRA30_CLK_CML0 },
593 { .con_id = "cml1", .dt_id = TEGRA30_CLK_CML1 },
594 { .con_id = "clk_m", .dt_id = TEGRA30_CLK_CLK_M },
595 { .con_id = "pll_ref", .dt_id = TEGRA30_CLK_PLL_REF },
596 { .con_id = "csus", .dev_id = "tengra_camera", .dt_id = TEGRA30_CLK_CSUS },
597 { .con_id = "vcp", .dev_id = "tegra-avp", .dt_id = TEGRA30_CLK_VCP },
598 { .con_id = "bsea", .dev_id = "tegra-avp", .dt_id = TEGRA30_CLK_BSEA },
599 { .con_id = "bsev", .dev_id = "tegra-aes", .dt_id = TEGRA30_CLK_BSEV },
600 { .con_id = "dsia", .dev_id = "tegradc.0", .dt_id = TEGRA30_CLK_DSIA },
601 { .con_id = "csi", .dev_id = "tegra_camera", .dt_id = TEGRA30_CLK_CSI },
602 { .con_id = "isp", .dev_id = "tegra_camera", .dt_id = TEGRA30_CLK_ISP },
603 { .con_id = "pcie", .dev_id = "tegra-pcie", .dt_id = TEGRA30_CLK_PCIE },
604 { .con_id = "afi", .dev_id = "tegra-pcie", .dt_id = TEGRA30_CLK_AFI },
605 { .con_id = "fuse", .dt_id = TEGRA30_CLK_FUSE },
606 { .con_id = "fuse_burn", .dev_id = "fuse-tegra", .dt_id = TEGRA30_CLK_FUSE_BURN },
607 { .con_id = "apbif", .dev_id = "tegra30-ahub", .dt_id = TEGRA30_CLK_APBIF },
608 { .con_id = "hda2hdmi", .dev_id = "tegra30-hda", .dt_id = TEGRA30_CLK_HDA2HDMI },
609 { .dev_id = "tegra-apbdma", .dt_id = TEGRA30_CLK_APBDMA },
610 { .dev_id = "rtc-tegra", .dt_id = TEGRA30_CLK_RTC },
611 { .dev_id = "timer", .dt_id = TEGRA30_CLK_TIMER },
612 { .dev_id = "tegra-kbc", .dt_id = TEGRA30_CLK_KBC },
613 { .dev_id = "fsl-tegra-udc", .dt_id = TEGRA30_CLK_USBD },
614 { .dev_id = "tegra-ehci.1", .dt_id = TEGRA30_CLK_USB2 },
615 { .dev_id = "tegra-ehci.2", .dt_id = TEGRA30_CLK_USB2 },
616 { .dev_id = "kfuse-tegra", .dt_id = TEGRA30_CLK_KFUSE },
617 { .dev_id = "tegra_sata_cold", .dt_id = TEGRA30_CLK_SATA_COLD },
618 { .dev_id = "dtv", .dt_id = TEGRA30_CLK_DTV },
619 { .dev_id = "tegra30-i2s.0", .dt_id = TEGRA30_CLK_I2S0 },
620 { .dev_id = "tegra30-i2s.1", .dt_id = TEGRA30_CLK_I2S1 },
621 { .dev_id = "tegra30-i2s.2", .dt_id = TEGRA30_CLK_I2S2 },
622 { .dev_id = "tegra30-i2s.3", .dt_id = TEGRA30_CLK_I2S3 },
623 { .dev_id = "tegra30-i2s.4", .dt_id = TEGRA30_CLK_I2S4 },
624 { .con_id = "spdif_out", .dev_id = "tegra30-spdif", .dt_id = TEGRA30_CLK_SPDIF_OUT },
625 { .con_id = "spdif_in", .dev_id = "tegra30-spdif", .dt_id = TEGRA30_CLK_SPDIF_IN },
626 { .con_id = "d_audio", .dev_id = "tegra30-ahub", .dt_id = TEGRA30_CLK_D_AUDIO },
627 { .dev_id = "tegra30-dam.0", .dt_id = TEGRA30_CLK_DAM0 },
628 { .dev_id = "tegra30-dam.1", .dt_id = TEGRA30_CLK_DAM1 },
629 { .dev_id = "tegra30-dam.2", .dt_id = TEGRA30_CLK_DAM2 },
630 { .con_id = "hda", .dev_id = "tegra30-hda", .dt_id = TEGRA30_CLK_HDA },
631 { .con_id = "hda2codec_2x", .dev_id = "tegra30-hda", .dt_id = TEGRA30_CLK_HDA2CODEC_2X },
632 { .dev_id = "spi_tegra.0", .dt_id = TEGRA30_CLK_SBC1 },
633 { .dev_id = "spi_tegra.1", .dt_id = TEGRA30_CLK_SBC2 },
634 { .dev_id = "spi_tegra.2", .dt_id = TEGRA30_CLK_SBC3 },
635 { .dev_id = "spi_tegra.3", .dt_id = TEGRA30_CLK_SBC4 },
636 { .dev_id = "spi_tegra.4", .dt_id = TEGRA30_CLK_SBC5 },
637 { .dev_id = "spi_tegra.5", .dt_id = TEGRA30_CLK_SBC6 },
638 { .dev_id = "tegra_sata_oob", .dt_id = TEGRA30_CLK_SATA_OOB },
639 { .dev_id = "tegra_sata", .dt_id = TEGRA30_CLK_SATA },
640 { .dev_id = "tegra_nand", .dt_id = TEGRA30_CLK_NDFLASH },
641 { .dev_id = "tegra_nand_speed", .dt_id = TEGRA30_CLK_NDSPEED },
642 { .dev_id = "vfir", .dt_id = TEGRA30_CLK_VFIR },
643 { .dev_id = "csite", .dt_id = TEGRA30_CLK_CSITE },
644 { .dev_id = "la", .dt_id = TEGRA30_CLK_LA },
645 { .dev_id = "tegra_w1", .dt_id = TEGRA30_CLK_OWR },
646 { .dev_id = "mipi", .dt_id = TEGRA30_CLK_MIPI },
647 { .dev_id = "tegra-tsensor", .dt_id = TEGRA30_CLK_TSENSOR },
648 { .dev_id = "i2cslow", .dt_id = TEGRA30_CLK_I2CSLOW },
649 { .dev_id = "vde", .dt_id = TEGRA30_CLK_VDE },
650 { .con_id = "vi", .dev_id = "tegra_camera", .dt_id = TEGRA30_CLK_VI },
651 { .dev_id = "epp", .dt_id = TEGRA30_CLK_EPP },
652 { .dev_id = "mpe", .dt_id = TEGRA30_CLK_MPE },
653 { .dev_id = "host1x", .dt_id = TEGRA30_CLK_HOST1X },
654 { .dev_id = "3d", .dt_id = TEGRA30_CLK_GR3D },
655 { .dev_id = "3d2", .dt_id = TEGRA30_CLK_GR3D2 },
656 { .dev_id = "2d", .dt_id = TEGRA30_CLK_GR2D },
657 { .dev_id = "se", .dt_id = TEGRA30_CLK_SE },
658 { .dev_id = "mselect", .dt_id = TEGRA30_CLK_MSELECT },
659 { .dev_id = "tegra-nor", .dt_id = TEGRA30_CLK_NOR },
660 { .dev_id = "sdhci-tegra.0", .dt_id = TEGRA30_CLK_SDMMC1 },
661 { .dev_id = "sdhci-tegra.1", .dt_id = TEGRA30_CLK_SDMMC2 },
662 { .dev_id = "sdhci-tegra.2", .dt_id = TEGRA30_CLK_SDMMC3 },
663 { .dev_id = "sdhci-tegra.3", .dt_id = TEGRA30_CLK_SDMMC4 },
664 { .dev_id = "cve", .dt_id = TEGRA30_CLK_CVE },
665 { .dev_id = "tvo", .dt_id = TEGRA30_CLK_TVO },
666 { .dev_id = "tvdac", .dt_id = TEGRA30_CLK_TVDAC },
667 { .dev_id = "actmon", .dt_id = TEGRA30_CLK_ACTMON },
668 { .con_id = "vi_sensor", .dev_id = "tegra_camera", .dt_id = TEGRA30_CLK_VI_SENSOR },
669 { .con_id = "div-clk", .dev_id = "tegra-i2c.0", .dt_id = TEGRA30_CLK_I2C1 },
670 { .con_id = "div-clk", .dev_id = "tegra-i2c.1", .dt_id = TEGRA30_CLK_I2C2 },
671 { .con_id = "div-clk", .dev_id = "tegra-i2c.2", .dt_id = TEGRA30_CLK_I2C3 },
672 { .con_id = "div-clk", .dev_id = "tegra-i2c.3", .dt_id = TEGRA30_CLK_I2C4 },
673 { .con_id = "div-clk", .dev_id = "tegra-i2c.4", .dt_id = TEGRA30_CLK_I2C5 },
674 { .dev_id = "tegra_uart.0", .dt_id = TEGRA30_CLK_UARTA },
675 { .dev_id = "tegra_uart.1", .dt_id = TEGRA30_CLK_UARTB },
676 { .dev_id = "tegra_uart.2", .dt_id = TEGRA30_CLK_UARTC },
677 { .dev_id = "tegra_uart.3", .dt_id = TEGRA30_CLK_UARTD },
678 { .dev_id = "tegra_uart.4", .dt_id = TEGRA30_CLK_UARTE },
679 { .dev_id = "hdmi", .dt_id = TEGRA30_CLK_HDMI },
680 { .dev_id = "extern1", .dt_id = TEGRA30_CLK_EXTERN1 },
681 { .dev_id = "extern2", .dt_id = TEGRA30_CLK_EXTERN2 },
682 { .dev_id = "extern3", .dt_id = TEGRA30_CLK_EXTERN3 },
683 { .dev_id = "pwm", .dt_id = TEGRA30_CLK_PWM },
684 { .dev_id = "tegradc.0", .dt_id = TEGRA30_CLK_DISP1 },
685 { .dev_id = "tegradc.1", .dt_id = TEGRA30_CLK_DISP2 },
686 { .dev_id = "tegradc.1", .dt_id = TEGRA30_CLK_DSIB },
687};
688
689static struct tegra_clk tegra30_clks[tegra_clk_max] __initdata = {
690 [tegra_clk_clk_32k] = { .dt_id = TEGRA30_CLK_CLK_32K, .present = true },
691 [tegra_clk_clk_m] = { .dt_id = TEGRA30_CLK_CLK_M, .present = true },
692 [tegra_clk_osc] = { .dt_id = TEGRA30_CLK_OSC, .present = true },
693 [tegra_clk_osc_div2] = { .dt_id = TEGRA30_CLK_OSC_DIV2, .present = true },
694 [tegra_clk_osc_div4] = { .dt_id = TEGRA30_CLK_OSC_DIV4, .present = true },
695 [tegra_clk_pll_ref] = { .dt_id = TEGRA30_CLK_PLL_REF, .present = true },
696 [tegra_clk_spdif_in_sync] = { .dt_id = TEGRA30_CLK_SPDIF_IN_SYNC, .present = true },
697 [tegra_clk_i2s0_sync] = { .dt_id = TEGRA30_CLK_I2S0_SYNC, .present = true },
698 [tegra_clk_i2s1_sync] = { .dt_id = TEGRA30_CLK_I2S1_SYNC, .present = true },
699 [tegra_clk_i2s2_sync] = { .dt_id = TEGRA30_CLK_I2S2_SYNC, .present = true },
700 [tegra_clk_i2s3_sync] = { .dt_id = TEGRA30_CLK_I2S3_SYNC, .present = true },
701 [tegra_clk_i2s4_sync] = { .dt_id = TEGRA30_CLK_I2S4_SYNC, .present = true },
702 [tegra_clk_vimclk_sync] = { .dt_id = TEGRA30_CLK_VIMCLK_SYNC, .present = true },
703 [tegra_clk_audio0] = { .dt_id = TEGRA30_CLK_AUDIO0, .present = true },
704 [tegra_clk_audio1] = { .dt_id = TEGRA30_CLK_AUDIO1, .present = true },
705 [tegra_clk_audio2] = { .dt_id = TEGRA30_CLK_AUDIO2, .present = true },
706 [tegra_clk_audio3] = { .dt_id = TEGRA30_CLK_AUDIO3, .present = true },
707 [tegra_clk_audio4] = { .dt_id = TEGRA30_CLK_AUDIO4, .present = true },
708 [tegra_clk_spdif] = { .dt_id = TEGRA30_CLK_SPDIF, .present = true },
709 [tegra_clk_audio0_mux] = { .dt_id = TEGRA30_CLK_AUDIO0_MUX, .present = true },
710 [tegra_clk_audio1_mux] = { .dt_id = TEGRA30_CLK_AUDIO1_MUX, .present = true },
711 [tegra_clk_audio2_mux] = { .dt_id = TEGRA30_CLK_AUDIO2_MUX, .present = true },
712 [tegra_clk_audio3_mux] = { .dt_id = TEGRA30_CLK_AUDIO3_MUX, .present = true },
713 [tegra_clk_audio4_mux] = { .dt_id = TEGRA30_CLK_AUDIO4_MUX, .present = true },
714 [tegra_clk_spdif_mux] = { .dt_id = TEGRA30_CLK_SPDIF_MUX, .present = true },
715 [tegra_clk_audio0_2x] = { .dt_id = TEGRA30_CLK_AUDIO0_2X, .present = true },
716 [tegra_clk_audio1_2x] = { .dt_id = TEGRA30_CLK_AUDIO1_2X, .present = true },
717 [tegra_clk_audio2_2x] = { .dt_id = TEGRA30_CLK_AUDIO2_2X, .present = true },
718 [tegra_clk_audio3_2x] = { .dt_id = TEGRA30_CLK_AUDIO3_2X, .present = true },
719 [tegra_clk_audio4_2x] = { .dt_id = TEGRA30_CLK_AUDIO4_2X, .present = true },
720 [tegra_clk_spdif_2x] = { .dt_id = TEGRA30_CLK_SPDIF_2X, .present = true },
721 [tegra_clk_hclk] = { .dt_id = TEGRA30_CLK_HCLK, .present = true },
722 [tegra_clk_pclk] = { .dt_id = TEGRA30_CLK_PCLK, .present = true },
723 [tegra_clk_i2s0] = { .dt_id = TEGRA30_CLK_I2S0, .present = true },
724 [tegra_clk_i2s1] = { .dt_id = TEGRA30_CLK_I2S1, .present = true },
725 [tegra_clk_i2s2] = { .dt_id = TEGRA30_CLK_I2S2, .present = true },
726 [tegra_clk_i2s3] = { .dt_id = TEGRA30_CLK_I2S3, .present = true },
727 [tegra_clk_i2s4] = { .dt_id = TEGRA30_CLK_I2S4, .present = true },
728 [tegra_clk_spdif_in] = { .dt_id = TEGRA30_CLK_SPDIF_IN, .present = true },
729 [tegra_clk_hda] = { .dt_id = TEGRA30_CLK_HDA, .present = true },
730 [tegra_clk_hda2codec_2x] = { .dt_id = TEGRA30_CLK_HDA2CODEC_2X, .present = true },
731 [tegra_clk_sbc1] = { .dt_id = TEGRA30_CLK_SBC1, .present = true },
732 [tegra_clk_sbc2] = { .dt_id = TEGRA30_CLK_SBC2, .present = true },
733 [tegra_clk_sbc3] = { .dt_id = TEGRA30_CLK_SBC3, .present = true },
734 [tegra_clk_sbc4] = { .dt_id = TEGRA30_CLK_SBC4, .present = true },
735 [tegra_clk_sbc5] = { .dt_id = TEGRA30_CLK_SBC5, .present = true },
736 [tegra_clk_sbc6] = { .dt_id = TEGRA30_CLK_SBC6, .present = true },
737 [tegra_clk_ndflash] = { .dt_id = TEGRA30_CLK_NDFLASH, .present = true },
738 [tegra_clk_ndspeed] = { .dt_id = TEGRA30_CLK_NDSPEED, .present = true },
739 [tegra_clk_vfir] = { .dt_id = TEGRA30_CLK_VFIR, .present = true },
740 [tegra_clk_la] = { .dt_id = TEGRA30_CLK_LA, .present = true },
741 [tegra_clk_csite] = { .dt_id = TEGRA30_CLK_CSITE, .present = true },
742 [tegra_clk_owr] = { .dt_id = TEGRA30_CLK_OWR, .present = true },
743 [tegra_clk_mipi] = { .dt_id = TEGRA30_CLK_MIPI, .present = true },
744 [tegra_clk_tsensor] = { .dt_id = TEGRA30_CLK_TSENSOR, .present = true },
745 [tegra_clk_i2cslow] = { .dt_id = TEGRA30_CLK_I2CSLOW, .present = true },
746 [tegra_clk_vde] = { .dt_id = TEGRA30_CLK_VDE, .present = true },
747 [tegra_clk_vi] = { .dt_id = TEGRA30_CLK_VI, .present = true },
748 [tegra_clk_epp] = { .dt_id = TEGRA30_CLK_EPP, .present = true },
749 [tegra_clk_mpe] = { .dt_id = TEGRA30_CLK_MPE, .present = true },
750 [tegra_clk_host1x] = { .dt_id = TEGRA30_CLK_HOST1X, .present = true },
751 [tegra_clk_gr2d] = { .dt_id = TEGRA30_CLK_GR2D, .present = true },
752 [tegra_clk_gr3d] = { .dt_id = TEGRA30_CLK_GR3D, .present = true },
753 [tegra_clk_mselect] = { .dt_id = TEGRA30_CLK_MSELECT, .present = true },
754 [tegra_clk_nor] = { .dt_id = TEGRA30_CLK_NOR, .present = true },
755 [tegra_clk_sdmmc1] = { .dt_id = TEGRA30_CLK_SDMMC1, .present = true },
756 [tegra_clk_sdmmc2] = { .dt_id = TEGRA30_CLK_SDMMC2, .present = true },
757 [tegra_clk_sdmmc3] = { .dt_id = TEGRA30_CLK_SDMMC3, .present = true },
758 [tegra_clk_sdmmc4] = { .dt_id = TEGRA30_CLK_SDMMC4, .present = true },
759 [tegra_clk_cve] = { .dt_id = TEGRA30_CLK_CVE, .present = true },
760 [tegra_clk_tvo] = { .dt_id = TEGRA30_CLK_TVO, .present = true },
761 [tegra_clk_tvdac] = { .dt_id = TEGRA30_CLK_TVDAC, .present = true },
762 [tegra_clk_actmon] = { .dt_id = TEGRA30_CLK_ACTMON, .present = true },
763 [tegra_clk_vi_sensor] = { .dt_id = TEGRA30_CLK_VI_SENSOR, .present = true },
764 [tegra_clk_i2c1] = { .dt_id = TEGRA30_CLK_I2C1, .present = true },
765 [tegra_clk_i2c2] = { .dt_id = TEGRA30_CLK_I2C2, .present = true },
766 [tegra_clk_i2c3] = { .dt_id = TEGRA30_CLK_I2C3, .present = true },
767 [tegra_clk_i2c4] = { .dt_id = TEGRA30_CLK_I2C4, .present = true },
768 [tegra_clk_i2c5] = { .dt_id = TEGRA30_CLK_I2C5, .present = true },
769 [tegra_clk_uarta] = { .dt_id = TEGRA30_CLK_UARTA, .present = true },
770 [tegra_clk_uartb] = { .dt_id = TEGRA30_CLK_UARTB, .present = true },
771 [tegra_clk_uartc] = { .dt_id = TEGRA30_CLK_UARTC, .present = true },
772 [tegra_clk_uartd] = { .dt_id = TEGRA30_CLK_UARTD, .present = true },
773 [tegra_clk_uarte] = { .dt_id = TEGRA30_CLK_UARTE, .present = true },
774 [tegra_clk_extern1] = { .dt_id = TEGRA30_CLK_EXTERN1, .present = true },
775 [tegra_clk_extern2] = { .dt_id = TEGRA30_CLK_EXTERN2, .present = true },
776 [tegra_clk_extern3] = { .dt_id = TEGRA30_CLK_EXTERN3, .present = true },
777 [tegra_clk_disp1] = { .dt_id = TEGRA30_CLK_DISP1, .present = true },
778 [tegra_clk_disp2] = { .dt_id = TEGRA30_CLK_DISP2, .present = true },
779 [tegra_clk_ahbdma] = { .dt_id = TEGRA30_CLK_AHBDMA, .present = true },
780 [tegra_clk_apbdma] = { .dt_id = TEGRA30_CLK_APBDMA, .present = true },
781 [tegra_clk_rtc] = { .dt_id = TEGRA30_CLK_RTC, .present = true },
782 [tegra_clk_timer] = { .dt_id = TEGRA30_CLK_TIMER, .present = true },
783 [tegra_clk_kbc] = { .dt_id = TEGRA30_CLK_KBC, .present = true },
784 [tegra_clk_vcp] = { .dt_id = TEGRA30_CLK_VCP, .present = true },
785 [tegra_clk_bsea] = { .dt_id = TEGRA30_CLK_BSEA, .present = true },
786 [tegra_clk_bsev] = { .dt_id = TEGRA30_CLK_BSEV, .present = true },
787 [tegra_clk_usbd] = { .dt_id = TEGRA30_CLK_USBD, .present = true },
788 [tegra_clk_usb2] = { .dt_id = TEGRA30_CLK_USB2, .present = true },
789 [tegra_clk_usb3] = { .dt_id = TEGRA30_CLK_USB3, .present = true },
790 [tegra_clk_csi] = { .dt_id = TEGRA30_CLK_CSI, .present = true },
791 [tegra_clk_isp] = { .dt_id = TEGRA30_CLK_ISP, .present = true },
792 [tegra_clk_kfuse] = { .dt_id = TEGRA30_CLK_KFUSE, .present = true },
793 [tegra_clk_fuse] = { .dt_id = TEGRA30_CLK_FUSE, .present = true },
794 [tegra_clk_fuse_burn] = { .dt_id = TEGRA30_CLK_FUSE_BURN, .present = true },
795 [tegra_clk_apbif] = { .dt_id = TEGRA30_CLK_APBIF, .present = true },
796 [tegra_clk_hda2hdmi] = { .dt_id = TEGRA30_CLK_HDA2HDMI, .present = true },
797 [tegra_clk_sata_cold] = { .dt_id = TEGRA30_CLK_SATA_COLD, .present = true },
798 [tegra_clk_sata_oob] = { .dt_id = TEGRA30_CLK_SATA_OOB, .present = true },
799 [tegra_clk_sata] = { .dt_id = TEGRA30_CLK_SATA, .present = true },
800 [tegra_clk_dtv] = { .dt_id = TEGRA30_CLK_DTV, .present = true },
801 [tegra_clk_pll_p] = { .dt_id = TEGRA30_CLK_PLL_P, .present = true },
802 [tegra_clk_pll_p_out1] = { .dt_id = TEGRA30_CLK_PLL_P_OUT1, .present = true },
803 [tegra_clk_pll_p_out2] = { .dt_id = TEGRA30_CLK_PLL_P_OUT2, .present = true },
804 [tegra_clk_pll_p_out3] = { .dt_id = TEGRA30_CLK_PLL_P_OUT3, .present = true },
805 [tegra_clk_pll_p_out4] = { .dt_id = TEGRA30_CLK_PLL_P_OUT4, .present = true },
806 [tegra_clk_pll_a] = { .dt_id = TEGRA30_CLK_PLL_A, .present = true },
807 [tegra_clk_pll_a_out0] = { .dt_id = TEGRA30_CLK_PLL_A_OUT0, .present = true },
808 [tegra_clk_cec] = { .dt_id = TEGRA30_CLK_CEC, .present = true },
809 [tegra_clk_emc] = { .dt_id = TEGRA30_CLK_EMC, .present = false },
810};
811
812static const char *pll_e_parents[] = { "pll_ref", "pll_p" };
813
814static void __init tegra30_pll_init(void)
815{
816 struct clk *clk;
817
818 /* PLLC_OUT1 */
819 clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c",
820 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
821 8, 8, 1, NULL);
822 clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div",
823 clk_base + PLLC_OUT, 1, 0, CLK_SET_RATE_PARENT,
824 0, NULL);
825 clks[TEGRA30_CLK_PLL_C_OUT1] = clk;
826
827 /* PLLM_OUT1 */
828 clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m",
829 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
830 8, 8, 1, NULL);
831 clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div",
832 clk_base + PLLM_OUT, 1, 0,
833 CLK_SET_RATE_PARENT, 0, NULL);
834 clks[TEGRA30_CLK_PLL_M_OUT1] = clk;
835
836 /* PLLX */
837 clk = tegra_clk_register_pll("pll_x", "pll_ref", clk_base, pmc_base, 0,
838 &pll_x_params, NULL);
839 clks[TEGRA30_CLK_PLL_X] = clk;
840
841 /* PLLX_OUT0 */
842 clk = clk_register_fixed_factor(NULL, "pll_x_out0", "pll_x",
843 CLK_SET_RATE_PARENT, 1, 2);
844 clks[TEGRA30_CLK_PLL_X_OUT0] = clk;
845
846 /* PLLU */
847 clk = tegra_clk_register_pllu("pll_u", "pll_ref", clk_base, 0,
848 &pll_u_params, NULL);
849 clks[TEGRA30_CLK_PLL_U] = clk;
850
851 /* PLLD */
852 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc_base, 0,
853 &pll_d_params, &pll_d_lock);
854 clks[TEGRA30_CLK_PLL_D] = clk;
855
856 /* PLLD_OUT0 */
857 clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d",
858 CLK_SET_RATE_PARENT, 1, 2);
859 clks[TEGRA30_CLK_PLL_D_OUT0] = clk;
860
861 /* PLLD2 */
862 clk = tegra_clk_register_pll("pll_d2", "pll_ref", clk_base, pmc_base, 0,
863 &pll_d2_params, &pll_d2_lock);
864 clks[TEGRA30_CLK_PLL_D2] = clk;
865
866 /* PLLD2_OUT0 */
867 clk = clk_register_fixed_factor(NULL, "pll_d2_out0", "pll_d2",
868 CLK_SET_RATE_PARENT, 1, 2);
869 clks[TEGRA30_CLK_PLL_D2_OUT0] = clk;
870
871 /* PLLE */
872 clk = clk_register_mux(NULL, "pll_e_mux", pll_e_parents,
873 ARRAY_SIZE(pll_e_parents),
874 CLK_SET_RATE_NO_REPARENT,
875 clk_base + PLLE_AUX, 2, 1, 0, NULL);
876}
877
878static const char *cclk_g_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
879 "pll_p_cclkg", "pll_p_out4_cclkg",
880 "pll_p_out3_cclkg", "unused", "pll_x" };
881static const char *cclk_lp_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
882 "pll_p_cclklp", "pll_p_out4_cclklp",
883 "pll_p_out3_cclklp", "unused", "pll_x",
884 "pll_x_out0" };
885static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4",
886 "pll_p_out3", "pll_p_out2", "unused",
887 "clk_32k", "pll_m_out1" };
888
889static void __init tegra30_super_clk_init(void)
890{
891 struct clk *clk;
892
893 /*
894 * Clock input to cclk_g divided from pll_p using
895 * U71 divider of cclk_g.
896 */
897 clk = tegra_clk_register_divider("pll_p_cclkg", "pll_p",
898 clk_base + SUPER_CCLKG_DIVIDER, 0,
899 TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
900 clk_register_clkdev(clk, "pll_p_cclkg", NULL);
901
902 /*
903 * Clock input to cclk_g divided from pll_p_out3 using
904 * U71 divider of cclk_g.
905 */
906 clk = tegra_clk_register_divider("pll_p_out3_cclkg", "pll_p_out3",
907 clk_base + SUPER_CCLKG_DIVIDER, 0,
908 TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
909 clk_register_clkdev(clk, "pll_p_out3_cclkg", NULL);
910
911 /*
912 * Clock input to cclk_g divided from pll_p_out4 using
913 * U71 divider of cclk_g.
914 */
915 clk = tegra_clk_register_divider("pll_p_out4_cclkg", "pll_p_out4",
916 clk_base + SUPER_CCLKG_DIVIDER, 0,
917 TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
918 clk_register_clkdev(clk, "pll_p_out4_cclkg", NULL);
919
920 /* CCLKG */
921 clk = tegra_clk_register_super_cclk("cclk_g", cclk_g_parents,
922 ARRAY_SIZE(cclk_g_parents),
923 CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
924 clk_base + CCLKG_BURST_POLICY,
925 0, NULL);
926 clks[TEGRA30_CLK_CCLK_G] = clk;
927
928 /*
929 * Clock input to cclk_lp divided from pll_p using
930 * U71 divider of cclk_lp.
931 */
932 clk = tegra_clk_register_divider("pll_p_cclklp", "pll_p",
933 clk_base + SUPER_CCLKLP_DIVIDER, 0,
934 TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
935 clk_register_clkdev(clk, "pll_p_cclklp", NULL);
936
937 /*
938 * Clock input to cclk_lp divided from pll_p_out3 using
939 * U71 divider of cclk_lp.
940 */
941 clk = tegra_clk_register_divider("pll_p_out3_cclklp", "pll_p_out3",
942 clk_base + SUPER_CCLKLP_DIVIDER, 0,
943 TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
944 clk_register_clkdev(clk, "pll_p_out3_cclklp", NULL);
945
946 /*
947 * Clock input to cclk_lp divided from pll_p_out4 using
948 * U71 divider of cclk_lp.
949 */
950 clk = tegra_clk_register_divider("pll_p_out4_cclklp", "pll_p_out4",
951 clk_base + SUPER_CCLKLP_DIVIDER, 0,
952 TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
953 clk_register_clkdev(clk, "pll_p_out4_cclklp", NULL);
954
955 /* CCLKLP */
956 clk = tegra_clk_register_super_mux("cclk_lp", cclk_lp_parents,
957 ARRAY_SIZE(cclk_lp_parents),
958 CLK_SET_RATE_PARENT,
959 clk_base + CCLKLP_BURST_POLICY,
960 TEGRA_DIVIDER_2, 4, 8, 9,
961 NULL);
962 clks[TEGRA30_CLK_CCLK_LP] = clk;
963
964 /* twd */
965 clk = clk_register_fixed_factor(NULL, "twd", "cclk_g",
966 CLK_SET_RATE_PARENT, 1, 2);
967 clks[TEGRA30_CLK_TWD] = clk;
968
969 tegra_super_clk_gen4_init(clk_base, pmc_base, tegra30_clks, NULL);
970}
971
972static const char *mux_pllacp_clkm[] = { "pll_a_out0", "unused", "pll_p",
973 "clk_m" };
974static const char *mux_pllpcm_clkm[] = { "pll_p", "pll_c", "pll_m", "clk_m" };
975static const char *spdif_out_parents[] = { "pll_a_out0", "spdif_2x", "pll_p",
976 "clk_m" };
977static const char *mux_pllmcpa[] = { "pll_m", "pll_c", "pll_p", "pll_a_out0" };
978static const char *mux_pllpmdacd2_clkm[] = { "pll_p", "pll_m", "pll_d_out0",
979 "pll_a_out0", "pll_c",
980 "pll_d2_out0", "clk_m" };
981static const char *mux_plld_out0_plld2_out0[] = { "pll_d_out0",
982 "pll_d2_out0" };
983static const char *pwm_parents[] = { "pll_p", "pll_c", "clk_32k", "clk_m" };
984
985static struct tegra_periph_init_data tegra_periph_clk_list[] = {
986 TEGRA_INIT_DATA_MUX("spdif_out", spdif_out_parents, CLK_SOURCE_SPDIF_OUT, 10, TEGRA_PERIPH_ON_APB, TEGRA30_CLK_SPDIF_OUT),
987 TEGRA_INIT_DATA_MUX("d_audio", mux_pllacp_clkm, CLK_SOURCE_D_AUDIO, 106, 0, TEGRA30_CLK_D_AUDIO),
988 TEGRA_INIT_DATA_MUX("dam0", mux_pllacp_clkm, CLK_SOURCE_DAM0, 108, 0, TEGRA30_CLK_DAM0),
989 TEGRA_INIT_DATA_MUX("dam1", mux_pllacp_clkm, CLK_SOURCE_DAM1, 109, 0, TEGRA30_CLK_DAM1),
990 TEGRA_INIT_DATA_MUX("dam2", mux_pllacp_clkm, CLK_SOURCE_DAM2, 110, 0, TEGRA30_CLK_DAM2),
991 TEGRA_INIT_DATA_INT("3d2", mux_pllmcpa, CLK_SOURCE_3D2, 98, 0, TEGRA30_CLK_GR3D2),
992 TEGRA_INIT_DATA_INT("se", mux_pllpcm_clkm, CLK_SOURCE_SE, 127, 0, TEGRA30_CLK_SE),
993 TEGRA_INIT_DATA_MUX8("hdmi", mux_pllpmdacd2_clkm, CLK_SOURCE_HDMI, 51, 0, TEGRA30_CLK_HDMI),
994 TEGRA_INIT_DATA("pwm", NULL, NULL, pwm_parents, CLK_SOURCE_PWM, 28, 2, 0, 0, 8, 1, 0, 17, TEGRA_PERIPH_ON_APB, TEGRA30_CLK_PWM),
995};
996
997static struct tegra_periph_init_data tegra_periph_nodiv_clk_list[] = {
998 TEGRA_INIT_DATA_NODIV("dsib", mux_plld_out0_plld2_out0, CLK_SOURCE_DSIB, 25, 1, 82, 0, TEGRA30_CLK_DSIB),
999};
1000
1001static void __init tegra30_periph_clk_init(void)
1002{
1003 struct tegra_periph_init_data *data;
1004 struct clk *clk;
1005 unsigned int i;
1006
1007 /* dsia */
1008 clk = tegra_clk_register_periph_gate("dsia", "pll_d_out0", 0, clk_base,
1009 0, 48, periph_clk_enb_refcnt);
1010 clks[TEGRA30_CLK_DSIA] = clk;
1011
1012 /* csia_pad */
1013 clk = clk_register_gate(NULL, "csia_pad", "pll_d", CLK_SET_RATE_PARENT,
1014 clk_base + PLLD_BASE, 26, 0, &pll_d_lock);
1015 clks[TEGRA30_CLK_CSIA_PAD] = clk;
1016
1017 /* csib_pad */
1018 clk = clk_register_gate(NULL, "csib_pad", "pll_d2", CLK_SET_RATE_PARENT,
1019 clk_base + PLLD2_BASE, 26, 0, &pll_d2_lock);
1020 clks[TEGRA30_CLK_CSIB_PAD] = clk;
1021
1022 /* csus */
1023 clk = tegra_clk_register_periph_gate("csus", "vi_sensor", 0,
1024 clk_base, 0, TEGRA30_CLK_CSUS,
1025 periph_clk_enb_refcnt);
1026 clks[TEGRA30_CLK_CSUS] = clk;
1027
1028 /* pcie */
1029 clk = tegra_clk_register_periph_gate("pcie", "clk_m", 0, clk_base, 0,
1030 70, periph_clk_enb_refcnt);
1031 clks[TEGRA30_CLK_PCIE] = clk;
1032
1033 /* afi */
1034 clk = tegra_clk_register_periph_gate("afi", "clk_m", 0, clk_base, 0, 72,
1035 periph_clk_enb_refcnt);
1036 clks[TEGRA30_CLK_AFI] = clk;
1037
1038 /* emc */
1039 clk = tegra20_clk_register_emc(clk_base + CLK_SOURCE_EMC, true);
1040
1041 clks[TEGRA30_CLK_EMC] = clk;
1042
1043 clk = tegra_clk_register_mc("mc", "emc", clk_base + CLK_SOURCE_EMC,
1044 NULL);
1045 clks[TEGRA30_CLK_MC] = clk;
1046
1047 /* cml0 */
1048 clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX,
1049 0, 0, &cml_lock);
1050 clks[TEGRA30_CLK_CML0] = clk;
1051
1052 /* cml1 */
1053 clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX,
1054 1, 0, &cml_lock);
1055 clks[TEGRA30_CLK_CML1] = clk;
1056
1057 for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) {
1058 data = &tegra_periph_clk_list[i];
1059 clk = tegra_clk_register_periph_data(clk_base, data);
1060 clks[data->clk_id] = clk;
1061 }
1062
1063 for (i = 0; i < ARRAY_SIZE(tegra_periph_nodiv_clk_list); i++) {
1064 data = &tegra_periph_nodiv_clk_list[i];
1065 clk = tegra_clk_register_periph_nodiv(data->name,
1066 data->p.parent_names,
1067 data->num_parents, &data->periph,
1068 clk_base, data->offset);
1069 clks[data->clk_id] = clk;
1070 }
1071
1072 tegra_periph_clk_init(clk_base, pmc_base, tegra30_clks, &pll_p_params);
1073}
1074
1075/* Tegra30 CPU clock and reset control functions */
1076static void tegra30_wait_cpu_in_reset(u32 cpu)
1077{
1078 unsigned int reg;
1079
1080 do {
1081 reg = readl(clk_base +
1082 TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);
1083 cpu_relax();
1084 } while (!(reg & (1 << cpu))); /* check CPU been reset or not */
1085
1086 return;
1087}
1088
1089static void tegra30_put_cpu_in_reset(u32 cpu)
1090{
1091 writel(CPU_RESET(cpu),
1092 clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);
1093 dmb();
1094}
1095
1096static void tegra30_cpu_out_of_reset(u32 cpu)
1097{
1098 writel(CPU_RESET(cpu),
1099 clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR);
1100 wmb();
1101}
1102
1103static void tegra30_enable_cpu_clock(u32 cpu)
1104{
1105 writel(CPU_CLOCK(cpu),
1106 clk_base + TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
1107 readl(clk_base + TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
1108}
1109
1110static void tegra30_disable_cpu_clock(u32 cpu)
1111{
1112 unsigned int reg;
1113
1114 reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
1115 writel(reg | CPU_CLOCK(cpu),
1116 clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
1117}
1118
1119#ifdef CONFIG_PM_SLEEP
1120static bool tegra30_cpu_rail_off_ready(void)
1121{
1122 unsigned int cpu_rst_status;
1123 int cpu_pwr_status;
1124
1125 cpu_rst_status = readl(clk_base +
1126 TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);
1127 cpu_pwr_status = tegra_pmc_cpu_is_powered(1) ||
1128 tegra_pmc_cpu_is_powered(2) ||
1129 tegra_pmc_cpu_is_powered(3);
1130
1131 if (((cpu_rst_status & 0xE) != 0xE) || cpu_pwr_status)
1132 return false;
1133
1134 return true;
1135}
1136
1137static void tegra30_cpu_clock_suspend(void)
1138{
1139 /* switch coresite to clk_m, save off original source */
1140 tegra30_cpu_clk_sctx.clk_csite_src =
1141 readl(clk_base + CLK_RESET_SOURCE_CSITE);
1142 writel(3 << 30, clk_base + CLK_RESET_SOURCE_CSITE);
1143
1144 tegra30_cpu_clk_sctx.cpu_burst =
1145 readl(clk_base + CLK_RESET_CCLK_BURST);
1146 tegra30_cpu_clk_sctx.pllx_base =
1147 readl(clk_base + CLK_RESET_PLLX_BASE);
1148 tegra30_cpu_clk_sctx.pllx_misc =
1149 readl(clk_base + CLK_RESET_PLLX_MISC);
1150 tegra30_cpu_clk_sctx.cclk_divider =
1151 readl(clk_base + CLK_RESET_CCLK_DIVIDER);
1152}
1153
1154static void tegra30_cpu_clock_resume(void)
1155{
1156 unsigned int reg, policy;
1157 u32 misc, base;
1158
1159 /* Is CPU complex already running on PLLX? */
1160 reg = readl(clk_base + CLK_RESET_CCLK_BURST);
1161 policy = (reg >> CLK_RESET_CCLK_BURST_POLICY_SHIFT) & 0xF;
1162
1163 if (policy == CLK_RESET_CCLK_IDLE_POLICY)
1164 reg = (reg >> CLK_RESET_CCLK_IDLE_POLICY_SHIFT) & 0xF;
1165 else if (policy == CLK_RESET_CCLK_RUN_POLICY)
1166 reg = (reg >> CLK_RESET_CCLK_RUN_POLICY_SHIFT) & 0xF;
1167 else
1168 BUG();
1169
1170 if (reg != CLK_RESET_CCLK_BURST_POLICY_PLLX) {
1171 misc = readl_relaxed(clk_base + CLK_RESET_PLLX_MISC);
1172 base = readl_relaxed(clk_base + CLK_RESET_PLLX_BASE);
1173
1174 if (misc != tegra30_cpu_clk_sctx.pllx_misc ||
1175 base != tegra30_cpu_clk_sctx.pllx_base) {
1176 /* restore PLLX settings if CPU is on different PLL */
1177 writel(tegra30_cpu_clk_sctx.pllx_misc,
1178 clk_base + CLK_RESET_PLLX_MISC);
1179 writel(tegra30_cpu_clk_sctx.pllx_base,
1180 clk_base + CLK_RESET_PLLX_BASE);
1181
1182 /* wait for PLL stabilization if PLLX was enabled */
1183 if (tegra30_cpu_clk_sctx.pllx_base & (1 << 30))
1184 udelay(300);
1185 }
1186 }
1187
1188 /*
1189 * Restore original burst policy setting for calls resulting from CPU
1190 * LP2 in idle or system suspend.
1191 */
1192 writel(tegra30_cpu_clk_sctx.cclk_divider,
1193 clk_base + CLK_RESET_CCLK_DIVIDER);
1194 writel(tegra30_cpu_clk_sctx.cpu_burst,
1195 clk_base + CLK_RESET_CCLK_BURST);
1196
1197 writel(tegra30_cpu_clk_sctx.clk_csite_src,
1198 clk_base + CLK_RESET_SOURCE_CSITE);
1199}
1200#endif
1201
1202static struct tegra_cpu_car_ops tegra30_cpu_car_ops = {
1203 .wait_for_reset = tegra30_wait_cpu_in_reset,
1204 .put_in_reset = tegra30_put_cpu_in_reset,
1205 .out_of_reset = tegra30_cpu_out_of_reset,
1206 .enable_clock = tegra30_enable_cpu_clock,
1207 .disable_clock = tegra30_disable_cpu_clock,
1208#ifdef CONFIG_PM_SLEEP
1209 .rail_off_ready = tegra30_cpu_rail_off_ready,
1210 .suspend = tegra30_cpu_clock_suspend,
1211 .resume = tegra30_cpu_clock_resume,
1212#endif
1213};
1214
1215static struct tegra_clk_init_table init_table[] = {
1216 { TEGRA30_CLK_UARTA, TEGRA30_CLK_PLL_P, 408000000, 0 },
1217 { TEGRA30_CLK_UARTB, TEGRA30_CLK_PLL_P, 408000000, 0 },
1218 { TEGRA30_CLK_UARTC, TEGRA30_CLK_PLL_P, 408000000, 0 },
1219 { TEGRA30_CLK_UARTD, TEGRA30_CLK_PLL_P, 408000000, 0 },
1220 { TEGRA30_CLK_UARTE, TEGRA30_CLK_PLL_P, 408000000, 0 },
1221 { TEGRA30_CLK_PLL_A, TEGRA30_CLK_CLK_MAX, 564480000, 0 },
1222 { TEGRA30_CLK_PLL_A_OUT0, TEGRA30_CLK_CLK_MAX, 11289600, 0 },
1223 { TEGRA30_CLK_I2S0, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 },
1224 { TEGRA30_CLK_I2S1, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 },
1225 { TEGRA30_CLK_I2S2, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 },
1226 { TEGRA30_CLK_I2S3, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 },
1227 { TEGRA30_CLK_I2S4, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 },
1228 { TEGRA30_CLK_SDMMC1, TEGRA30_CLK_PLL_P, 48000000, 0 },
1229 { TEGRA30_CLK_SDMMC2, TEGRA30_CLK_PLL_P, 48000000, 0 },
1230 { TEGRA30_CLK_SDMMC3, TEGRA30_CLK_PLL_P, 48000000, 0 },
1231 { TEGRA30_CLK_CSITE, TEGRA30_CLK_CLK_MAX, 0, 1 },
1232 { TEGRA30_CLK_MSELECT, TEGRA30_CLK_CLK_MAX, 0, 1 },
1233 { TEGRA30_CLK_SBC1, TEGRA30_CLK_PLL_P, 100000000, 0 },
1234 { TEGRA30_CLK_SBC2, TEGRA30_CLK_PLL_P, 100000000, 0 },
1235 { TEGRA30_CLK_SBC3, TEGRA30_CLK_PLL_P, 100000000, 0 },
1236 { TEGRA30_CLK_SBC4, TEGRA30_CLK_PLL_P, 100000000, 0 },
1237 { TEGRA30_CLK_SBC5, TEGRA30_CLK_PLL_P, 100000000, 0 },
1238 { TEGRA30_CLK_SBC6, TEGRA30_CLK_PLL_P, 100000000, 0 },
1239 { TEGRA30_CLK_PLL_C, TEGRA30_CLK_CLK_MAX, 600000000, 0 },
1240 { TEGRA30_CLK_HOST1X, TEGRA30_CLK_PLL_C, 150000000, 0 },
1241 { TEGRA30_CLK_TWD, TEGRA30_CLK_CLK_MAX, 0, 1 },
1242 { TEGRA30_CLK_GR2D, TEGRA30_CLK_PLL_C, 300000000, 0 },
1243 { TEGRA30_CLK_GR3D, TEGRA30_CLK_PLL_C, 300000000, 0 },
1244 { TEGRA30_CLK_GR3D2, TEGRA30_CLK_PLL_C, 300000000, 0 },
1245 { TEGRA30_CLK_PLL_U, TEGRA30_CLK_CLK_MAX, 480000000, 0 },
1246 { TEGRA30_CLK_VDE, TEGRA30_CLK_PLL_C, 300000000, 0 },
1247 { TEGRA30_CLK_SPDIF_IN_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 },
1248 { TEGRA30_CLK_I2S0_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 },
1249 { TEGRA30_CLK_I2S1_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 },
1250 { TEGRA30_CLK_I2S2_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 },
1251 { TEGRA30_CLK_I2S3_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 },
1252 { TEGRA30_CLK_I2S4_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 },
1253 { TEGRA30_CLK_VIMCLK_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 },
1254 { TEGRA30_CLK_HDA, TEGRA30_CLK_PLL_P, 102000000, 0 },
1255 { TEGRA30_CLK_HDA2CODEC_2X, TEGRA30_CLK_PLL_P, 48000000, 0 },
1256 { TEGRA30_CLK_PWM, TEGRA30_CLK_PLL_P, 48000000, 0 },
1257 /* must be the last entry */
1258 { TEGRA30_CLK_CLK_MAX, TEGRA30_CLK_CLK_MAX, 0, 0 },
1259};
1260
1261/*
1262 * Some clocks may be used by different drivers depending on the board
1263 * configuration. List those here to register them twice in the clock lookup
1264 * table under two names.
1265 */
1266static struct tegra_clk_duplicate tegra_clk_duplicates[] = {
1267 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_USBD, "utmip-pad", NULL),
1268 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_USBD, "tegra-ehci.0", NULL),
1269 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_USBD, "tegra-otg", NULL),
1270 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_BSEV, "tegra-avp", "bsev"),
1271 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_BSEV, "nvavp", "bsev"),
1272 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_VDE, "tegra-aes", "vde"),
1273 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_BSEA, "tegra-aes", "bsea"),
1274 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_BSEA, "nvavp", "bsea"),
1275 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_CML1, "tegra_sata_cml", NULL),
1276 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_CML0, "tegra_pcie", "cml"),
1277 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_VCP, "nvavp", "vcp"),
1278 /* must be the last entry */
1279 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_CLK_MAX, NULL, NULL),
1280};
1281
1282static const struct of_device_id pmc_match[] __initconst = {
1283 { .compatible = "nvidia,tegra30-pmc" },
1284 { },
1285};
1286
1287static struct tegra_audio_clk_info tegra30_audio_plls[] = {
1288 { "pll_a", &pll_a_params, tegra_clk_pll_a, "pll_p_out1" },
1289};
1290
1291static bool tegra30_car_initialized;
1292
1293static struct clk *tegra30_clk_src_onecell_get(struct of_phandle_args *clkspec,
1294 void *data)
1295{
1296 struct clk_hw *hw;
1297 struct clk *clk;
1298
1299 /*
1300 * Timer clocks are needed early, the rest of the clocks shouldn't be
1301 * available to device drivers until clock tree is fully initialized.
1302 */
1303 if (clkspec->args[0] != TEGRA30_CLK_RTC &&
1304 clkspec->args[0] != TEGRA30_CLK_TWD &&
1305 clkspec->args[0] != TEGRA30_CLK_TIMER &&
1306 !tegra30_car_initialized)
1307 return ERR_PTR(-EPROBE_DEFER);
1308
1309 clk = of_clk_src_onecell_get(clkspec, data);
1310 if (IS_ERR(clk))
1311 return clk;
1312
1313 hw = __clk_get_hw(clk);
1314
1315 if (clkspec->args[0] == TEGRA30_CLK_EMC) {
1316 if (!tegra20_clk_emc_driver_available(hw))
1317 return ERR_PTR(-EPROBE_DEFER);
1318 }
1319
1320 return clk;
1321}
1322
1323static void __init tegra30_clock_init(struct device_node *np)
1324{
1325 struct device_node *node;
1326
1327 clk_base = of_iomap(np, 0);
1328 if (!clk_base) {
1329 pr_err("ioremap tegra30 CAR failed\n");
1330 return;
1331 }
1332
1333 node = of_find_matching_node(NULL, pmc_match);
1334 if (!node) {
1335 pr_err("Failed to find pmc node\n");
1336 BUG();
1337 }
1338
1339 pmc_base = of_iomap(node, 0);
1340 of_node_put(node);
1341 if (!pmc_base) {
1342 pr_err("Can't map pmc registers\n");
1343 BUG();
1344 }
1345
1346 clks = tegra_clk_init(clk_base, TEGRA30_CLK_CLK_MAX,
1347 TEGRA30_CLK_PERIPH_BANKS);
1348 if (!clks)
1349 return;
1350
1351 if (tegra_osc_clk_init(clk_base, tegra30_clks, tegra30_input_freq,
1352 ARRAY_SIZE(tegra30_input_freq), 1, &input_freq,
1353 NULL) < 0)
1354 return;
1355
1356 tegra_fixed_clk_init(tegra30_clks);
1357 tegra30_pll_init();
1358 tegra30_super_clk_init();
1359 tegra30_periph_clk_init();
1360 tegra_audio_clk_init(clk_base, pmc_base, tegra30_clks,
1361 tegra30_audio_plls,
1362 ARRAY_SIZE(tegra30_audio_plls), 24000000);
1363
1364 tegra_init_dup_clks(tegra_clk_duplicates, clks, TEGRA30_CLK_CLK_MAX);
1365
1366 tegra_add_of_provider(np, tegra30_clk_src_onecell_get);
1367
1368 tegra_cpu_car_ops = &tegra30_cpu_car_ops;
1369}
1370CLK_OF_DECLARE_DRIVER(tegra30, "nvidia,tegra30-car", tegra30_clock_init);
1371
1372/*
1373 * Clocks that use runtime PM can't be created at the tegra30_clock_init
1374 * time because drivers' base isn't initialized yet, and thus platform
1375 * devices can't be created for the clocks. Hence we need to split the
1376 * registration of the clocks into two phases. The first phase registers
1377 * essential clocks which don't require RPM and are actually used during
1378 * early boot. The second phase registers clocks which use RPM and this
1379 * is done when device drivers' core API is ready.
1380 */
1381static int tegra30_car_probe(struct platform_device *pdev)
1382{
1383 struct clk *clk;
1384
1385 /* PLLC */
1386 clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, pmc_base, 0,
1387 &pll_c_params, NULL);
1388 clks[TEGRA30_CLK_PLL_C] = clk;
1389
1390 /* PLLE */
1391 clk = tegra_clk_register_plle("pll_e", "pll_e_mux", clk_base, pmc_base,
1392 CLK_GET_RATE_NOCACHE, &pll_e_params, NULL);
1393 clks[TEGRA30_CLK_PLL_E] = clk;
1394
1395 /* PLLM */
1396 clk = tegra_clk_register_pll("pll_m", "pll_ref", clk_base, pmc_base,
1397 CLK_SET_RATE_GATE, &pll_m_params, NULL);
1398 clks[TEGRA30_CLK_PLL_M] = clk;
1399
1400 /* SCLK */
1401 clk = tegra_clk_register_super_mux("sclk", sclk_parents,
1402 ARRAY_SIZE(sclk_parents),
1403 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
1404 clk_base + SCLK_BURST_POLICY,
1405 0, 4, 0, 0, NULL);
1406 clks[TEGRA30_CLK_SCLK] = clk;
1407
1408 tegra_register_devclks(devclks, ARRAY_SIZE(devclks));
1409 tegra_init_from_table(init_table, clks, TEGRA30_CLK_CLK_MAX);
1410 tegra30_car_initialized = true;
1411
1412 return 0;
1413}
1414
1415static const struct of_device_id tegra30_car_match[] = {
1416 { .compatible = "nvidia,tegra30-car" },
1417 { }
1418};
1419
1420static struct platform_driver tegra30_car_driver = {
1421 .driver = {
1422 .name = "tegra30-car",
1423 .of_match_table = tegra30_car_match,
1424 .suppress_bind_attrs = true,
1425 },
1426 .probe = tegra30_car_probe,
1427};
1428
1429/*
1430 * Clock driver must be registered before memory controller driver,
1431 * which doesn't support deferred probing for today and is registered
1432 * from arch init-level.
1433 */
1434static int tegra30_car_init(void)
1435{
1436 return platform_driver_register(&tegra30_car_driver);
1437}
1438postcore_initcall(tegra30_car_init);