Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
4 */
5
6/*
7 * In Certain QCOM SoCs like apq8096 and msm8996 that have KRYO processors,
8 * the CPU frequency subset and voltage value of each OPP varies
9 * based on the silicon variant in use. Qualcomm Process Voltage Scaling Tables
10 * defines the voltage and frequency value based on the msm-id in SMEM
11 * and speedbin blown in the efuse combination.
12 * The qcom-cpufreq-nvmem driver reads the msm-id and efuse value from the SoC
13 * to provide the OPP framework with required information.
14 * This is used to determine the voltage and frequency value for each OPP of
15 * operating-points-v2 table when it is parsed by the OPP framework.
16 */
17
18#include <linux/cpu.h>
19#include <linux/err.h>
20#include <linux/init.h>
21#include <linux/kernel.h>
22#include <linux/module.h>
23#include <linux/nvmem-consumer.h>
24#include <linux/of.h>
25#include <linux/platform_device.h>
26#include <linux/pm.h>
27#include <linux/pm_domain.h>
28#include <linux/pm_opp.h>
29#include <linux/pm_runtime.h>
30#include <linux/slab.h>
31#include <linux/soc/qcom/smem.h>
32
33#include <dt-bindings/arm/qcom,ids.h>
34
35enum ipq806x_versions {
36 IPQ8062_VERSION = 0,
37 IPQ8064_VERSION,
38 IPQ8065_VERSION,
39};
40
41#define IPQ6000_VERSION BIT(2)
42
43enum ipq8074_versions {
44 IPQ8074_HAWKEYE_VERSION = 0,
45 IPQ8074_ACORN_VERSION,
46};
47
48struct qcom_cpufreq_drv;
49
50struct qcom_cpufreq_match_data {
51 int (*get_version)(struct device *cpu_dev,
52 struct nvmem_cell *speedbin_nvmem,
53 char **pvs_name,
54 struct qcom_cpufreq_drv *drv);
55 const char **pd_names;
56 unsigned int num_pd_names;
57};
58
59struct qcom_cpufreq_drv_cpu {
60 int opp_token;
61 struct dev_pm_domain_list *pd_list;
62};
63
64struct qcom_cpufreq_drv {
65 u32 versions;
66 const struct qcom_cpufreq_match_data *data;
67 struct qcom_cpufreq_drv_cpu cpus[];
68};
69
70static struct platform_device *cpufreq_dt_pdev, *cpufreq_pdev;
71
72static int qcom_cpufreq_simple_get_version(struct device *cpu_dev,
73 struct nvmem_cell *speedbin_nvmem,
74 char **pvs_name,
75 struct qcom_cpufreq_drv *drv)
76{
77 u8 *speedbin;
78
79 *pvs_name = NULL;
80 speedbin = nvmem_cell_read(speedbin_nvmem, NULL);
81 if (IS_ERR(speedbin))
82 return PTR_ERR(speedbin);
83
84 dev_dbg(cpu_dev, "speedbin: %d\n", *speedbin);
85 drv->versions = 1 << *speedbin;
86 kfree(speedbin);
87 return 0;
88}
89
90static void get_krait_bin_format_a(struct device *cpu_dev,
91 int *speed, int *pvs,
92 u8 *buf)
93{
94 u32 pte_efuse;
95
96 pte_efuse = *((u32 *)buf);
97
98 *speed = pte_efuse & 0xf;
99 if (*speed == 0xf)
100 *speed = (pte_efuse >> 4) & 0xf;
101
102 if (*speed == 0xf) {
103 *speed = 0;
104 dev_warn(cpu_dev, "Speed bin: Defaulting to %d\n", *speed);
105 } else {
106 dev_dbg(cpu_dev, "Speed bin: %d\n", *speed);
107 }
108
109 *pvs = (pte_efuse >> 10) & 0x7;
110 if (*pvs == 0x7)
111 *pvs = (pte_efuse >> 13) & 0x7;
112
113 if (*pvs == 0x7) {
114 *pvs = 0;
115 dev_warn(cpu_dev, "PVS bin: Defaulting to %d\n", *pvs);
116 } else {
117 dev_dbg(cpu_dev, "PVS bin: %d\n", *pvs);
118 }
119}
120
121static void get_krait_bin_format_b(struct device *cpu_dev,
122 int *speed, int *pvs, int *pvs_ver,
123 u8 *buf)
124{
125 u32 pte_efuse, redundant_sel;
126
127 pte_efuse = *((u32 *)buf);
128 redundant_sel = (pte_efuse >> 24) & 0x7;
129
130 *pvs_ver = (pte_efuse >> 4) & 0x3;
131
132 switch (redundant_sel) {
133 case 1:
134 *pvs = ((pte_efuse >> 28) & 0x8) | ((pte_efuse >> 6) & 0x7);
135 *speed = (pte_efuse >> 27) & 0xf;
136 break;
137 case 2:
138 *pvs = (pte_efuse >> 27) & 0xf;
139 *speed = pte_efuse & 0x7;
140 break;
141 default:
142 /* 4 bits of PVS are in efuse register bits 31, 8-6. */
143 *pvs = ((pte_efuse >> 28) & 0x8) | ((pte_efuse >> 6) & 0x7);
144 *speed = pte_efuse & 0x7;
145 }
146
147 /* Check SPEED_BIN_BLOW_STATUS */
148 if (pte_efuse & BIT(3)) {
149 dev_dbg(cpu_dev, "Speed bin: %d\n", *speed);
150 } else {
151 dev_warn(cpu_dev, "Speed bin not set. Defaulting to 0!\n");
152 *speed = 0;
153 }
154
155 /* Check PVS_BLOW_STATUS */
156 pte_efuse = *(((u32 *)buf) + 1);
157 pte_efuse &= BIT(21);
158 if (pte_efuse) {
159 dev_dbg(cpu_dev, "PVS bin: %d\n", *pvs);
160 } else {
161 dev_warn(cpu_dev, "PVS bin not set. Defaulting to 0!\n");
162 *pvs = 0;
163 }
164
165 dev_dbg(cpu_dev, "PVS version: %d\n", *pvs_ver);
166}
167
168static int qcom_cpufreq_kryo_name_version(struct device *cpu_dev,
169 struct nvmem_cell *speedbin_nvmem,
170 char **pvs_name,
171 struct qcom_cpufreq_drv *drv)
172{
173 size_t len;
174 u32 msm_id;
175 u8 *speedbin;
176 int ret;
177 *pvs_name = NULL;
178
179 ret = qcom_smem_get_soc_id(&msm_id);
180 if (ret)
181 return ret;
182
183 speedbin = nvmem_cell_read(speedbin_nvmem, &len);
184 if (IS_ERR(speedbin))
185 return PTR_ERR(speedbin);
186
187 switch (msm_id) {
188 case QCOM_ID_MSM8996:
189 case QCOM_ID_APQ8096:
190 case QCOM_ID_IPQ5332:
191 case QCOM_ID_IPQ5322:
192 case QCOM_ID_IPQ5312:
193 case QCOM_ID_IPQ5302:
194 case QCOM_ID_IPQ5300:
195 case QCOM_ID_IPQ5321:
196 case QCOM_ID_IPQ9514:
197 case QCOM_ID_IPQ9550:
198 case QCOM_ID_IPQ9554:
199 case QCOM_ID_IPQ9570:
200 case QCOM_ID_IPQ9574:
201 drv->versions = 1 << (unsigned int)(*speedbin);
202 break;
203 case QCOM_ID_IPQ5424:
204 case QCOM_ID_IPQ5404:
205 drv->versions = (*speedbin == 0x3b) ? BIT(1) : BIT(0);
206 break;
207 case QCOM_ID_MSM8996SG:
208 case QCOM_ID_APQ8096SG:
209 drv->versions = 1 << ((unsigned int)(*speedbin) + 4);
210 break;
211 default:
212 BUG();
213 break;
214 }
215
216 kfree(speedbin);
217 return 0;
218}
219
220static int qcom_cpufreq_krait_name_version(struct device *cpu_dev,
221 struct nvmem_cell *speedbin_nvmem,
222 char **pvs_name,
223 struct qcom_cpufreq_drv *drv)
224{
225 int speed = 0, pvs = 0, pvs_ver = 0;
226 u8 *speedbin;
227 size_t len;
228 int ret = 0;
229
230 speedbin = nvmem_cell_read(speedbin_nvmem, &len);
231
232 if (IS_ERR(speedbin))
233 return PTR_ERR(speedbin);
234
235 switch (len) {
236 case 4:
237 get_krait_bin_format_a(cpu_dev, &speed, &pvs, speedbin);
238 break;
239 case 8:
240 get_krait_bin_format_b(cpu_dev, &speed, &pvs, &pvs_ver,
241 speedbin);
242 break;
243 default:
244 dev_err(cpu_dev, "Unable to read nvmem data. Defaulting to 0!\n");
245 ret = -ENODEV;
246 goto len_error;
247 }
248
249 snprintf(*pvs_name, sizeof("speedXX-pvsXX-vXX"), "speed%d-pvs%d-v%d",
250 speed, pvs, pvs_ver);
251
252 drv->versions = (1 << speed);
253
254len_error:
255 kfree(speedbin);
256 return ret;
257}
258
259static const struct of_device_id qcom_cpufreq_ipq806x_match_list[] __maybe_unused = {
260 { .compatible = "qcom,ipq8062", .data = (const void *)QCOM_ID_IPQ8062 },
261 { .compatible = "qcom,ipq8064", .data = (const void *)QCOM_ID_IPQ8064 },
262 { .compatible = "qcom,ipq8065", .data = (const void *)QCOM_ID_IPQ8065 },
263 { .compatible = "qcom,ipq8066", .data = (const void *)QCOM_ID_IPQ8066 },
264 { .compatible = "qcom,ipq8068", .data = (const void *)QCOM_ID_IPQ8068 },
265 { .compatible = "qcom,ipq8069", .data = (const void *)QCOM_ID_IPQ8069 },
266 { /* sentinel */ }
267};
268
269static int qcom_cpufreq_ipq8064_name_version(struct device *cpu_dev,
270 struct nvmem_cell *speedbin_nvmem,
271 char **pvs_name,
272 struct qcom_cpufreq_drv *drv)
273{
274 int msm_id = -1, ret = 0;
275 int speed = 0, pvs = 0;
276 u8 *speedbin;
277 size_t len;
278
279 speedbin = nvmem_cell_read(speedbin_nvmem, &len);
280 if (IS_ERR(speedbin))
281 return PTR_ERR(speedbin);
282
283 if (len != 4) {
284 dev_err(cpu_dev, "Unable to read nvmem data. Defaulting to 0!\n");
285 ret = -ENODEV;
286 goto exit;
287 }
288
289 get_krait_bin_format_a(cpu_dev, &speed, &pvs, speedbin);
290
291 ret = qcom_smem_get_soc_id(&msm_id);
292 if (ret == -ENODEV) {
293 const struct of_device_id *match;
294
295 /* Fallback to compatible match with no SMEM initialized */
296 match = of_machine_get_match(qcom_cpufreq_ipq806x_match_list);
297 if (!match) {
298 ret = -ENODEV;
299 goto exit;
300 }
301
302 /* We found a matching device, get the msm_id from the data entry */
303 msm_id = (int)(uintptr_t)match->data;
304 ret = 0;
305 } else if (ret) {
306 goto exit;
307 }
308
309 switch (msm_id) {
310 case QCOM_ID_IPQ8062:
311 drv->versions = BIT(IPQ8062_VERSION);
312 break;
313 case QCOM_ID_IPQ8064:
314 case QCOM_ID_IPQ8066:
315 case QCOM_ID_IPQ8068:
316 drv->versions = BIT(IPQ8064_VERSION);
317 break;
318 case QCOM_ID_IPQ8065:
319 case QCOM_ID_IPQ8069:
320 drv->versions = BIT(IPQ8065_VERSION);
321 break;
322 default:
323 dev_err(cpu_dev,
324 "SoC ID %u is not part of IPQ8064 family, limiting to 1.0GHz!\n",
325 msm_id);
326 drv->versions = BIT(IPQ8062_VERSION);
327 break;
328 }
329
330 /* IPQ8064 speed is never fused. Only pvs values are fused. */
331 snprintf(*pvs_name, sizeof("speed0-pvsXX"), "speed0-pvs%d", pvs);
332
333exit:
334 kfree(speedbin);
335 return ret;
336}
337
338static int qcom_cpufreq_ipq6018_name_version(struct device *cpu_dev,
339 struct nvmem_cell *speedbin_nvmem,
340 char **pvs_name,
341 struct qcom_cpufreq_drv *drv)
342{
343 u32 msm_id;
344 int ret;
345 u8 *speedbin;
346 *pvs_name = NULL;
347
348 ret = qcom_smem_get_soc_id(&msm_id);
349 if (ret)
350 return ret;
351
352 speedbin = nvmem_cell_read(speedbin_nvmem, NULL);
353 if (IS_ERR(speedbin))
354 return PTR_ERR(speedbin);
355
356 switch (msm_id) {
357 case QCOM_ID_IPQ6005:
358 case QCOM_ID_IPQ6010:
359 case QCOM_ID_IPQ6018:
360 case QCOM_ID_IPQ6028:
361 /* Fuse Value Freq BIT to set
362 * ---------------------------------
363 * 2’b0 No Limit BIT(0)
364 * 2’b1 1.5 GHz BIT(1)
365 */
366 drv->versions = 1 << (unsigned int)(*speedbin);
367 break;
368 case QCOM_ID_IPQ6000:
369 /*
370 * IPQ6018 family only has one bit to advertise the CPU
371 * speed-bin, but that is not enough for IPQ6000 which
372 * is only rated up to 1.2GHz.
373 * So for IPQ6000 manually set BIT(2) based on SMEM ID.
374 */
375 drv->versions = IPQ6000_VERSION;
376 break;
377 default:
378 dev_err(cpu_dev,
379 "SoC ID %u is not part of IPQ6018 family, limiting to 1.2GHz!\n",
380 msm_id);
381 drv->versions = IPQ6000_VERSION;
382 break;
383 }
384
385 kfree(speedbin);
386 return 0;
387}
388
389static int qcom_cpufreq_ipq8074_name_version(struct device *cpu_dev,
390 struct nvmem_cell *speedbin_nvmem,
391 char **pvs_name,
392 struct qcom_cpufreq_drv *drv)
393{
394 u32 msm_id;
395 int ret;
396 *pvs_name = NULL;
397
398 ret = qcom_smem_get_soc_id(&msm_id);
399 if (ret)
400 return ret;
401
402 switch (msm_id) {
403 case QCOM_ID_IPQ8070A:
404 case QCOM_ID_IPQ8071A:
405 case QCOM_ID_IPQ8172:
406 case QCOM_ID_IPQ8173:
407 case QCOM_ID_IPQ8174:
408 drv->versions = BIT(IPQ8074_ACORN_VERSION);
409 break;
410 case QCOM_ID_IPQ8072A:
411 case QCOM_ID_IPQ8074A:
412 case QCOM_ID_IPQ8076A:
413 case QCOM_ID_IPQ8078A:
414 drv->versions = BIT(IPQ8074_HAWKEYE_VERSION);
415 break;
416 default:
417 dev_err(cpu_dev,
418 "SoC ID %u is not part of IPQ8074 family, limiting to 1.4GHz!\n",
419 msm_id);
420 drv->versions = BIT(IPQ8074_ACORN_VERSION);
421 break;
422 }
423
424 return 0;
425}
426
427static const struct qcom_cpufreq_match_data match_data_kryo = {
428 .get_version = qcom_cpufreq_kryo_name_version,
429};
430
431static const struct qcom_cpufreq_match_data match_data_krait = {
432 .get_version = qcom_cpufreq_krait_name_version,
433};
434
435static const struct qcom_cpufreq_match_data match_data_msm8909 = {
436 .get_version = qcom_cpufreq_simple_get_version,
437 .pd_names = (const char *[]) { "perf" },
438 .num_pd_names = 1,
439};
440
441static const struct qcom_cpufreq_match_data match_data_qcs404 = {
442 .pd_names = (const char *[]) { "cpr" },
443 .num_pd_names = 1,
444};
445
446static const struct qcom_cpufreq_match_data match_data_ipq6018 = {
447 .get_version = qcom_cpufreq_ipq6018_name_version,
448};
449
450static const struct qcom_cpufreq_match_data match_data_ipq8064 = {
451 .get_version = qcom_cpufreq_ipq8064_name_version,
452};
453
454static const struct qcom_cpufreq_match_data match_data_ipq8074 = {
455 .get_version = qcom_cpufreq_ipq8074_name_version,
456};
457
458static void qcom_cpufreq_suspend_pd_devs(struct qcom_cpufreq_drv *drv, unsigned int cpu)
459{
460 struct dev_pm_domain_list *pd_list = drv->cpus[cpu].pd_list;
461 int i;
462
463 if (!pd_list)
464 return;
465
466 for (i = 0; i < pd_list->num_pds; i++)
467 device_set_awake_path(pd_list->pd_devs[i]);
468}
469
470static int qcom_cpufreq_probe(struct platform_device *pdev)
471{
472 struct qcom_cpufreq_drv *drv;
473 struct nvmem_cell *speedbin_nvmem;
474 struct device *cpu_dev;
475 char pvs_name_buffer[] = "speedXX-pvsXX-vXX";
476 char *pvs_name = pvs_name_buffer;
477 unsigned cpu;
478 const struct of_device_id *match;
479 int ret;
480
481 cpu_dev = get_cpu_device(0);
482 if (!cpu_dev)
483 return -ENODEV;
484
485 struct device_node *np __free(device_node) =
486 dev_pm_opp_of_get_opp_desc_node(cpu_dev);
487 if (!np)
488 return -ENOENT;
489
490 ret = of_device_is_compatible(np, "operating-points-v2-kryo-cpu") ||
491 of_device_is_compatible(np, "operating-points-v2-krait-cpu");
492 if (!ret)
493 return -ENOENT;
494
495 drv = devm_kzalloc(&pdev->dev, struct_size(drv, cpus, num_possible_cpus()),
496 GFP_KERNEL);
497 if (!drv)
498 return -ENOMEM;
499
500 match = pdev->dev.platform_data;
501 drv->data = match->data;
502 if (!drv->data)
503 return -ENODEV;
504
505 if (drv->data->get_version) {
506 speedbin_nvmem = of_nvmem_cell_get(np, NULL);
507 if (IS_ERR(speedbin_nvmem))
508 return dev_err_probe(cpu_dev, PTR_ERR(speedbin_nvmem),
509 "Could not get nvmem cell\n");
510
511 ret = drv->data->get_version(cpu_dev,
512 speedbin_nvmem, &pvs_name, drv);
513 if (ret) {
514 nvmem_cell_put(speedbin_nvmem);
515 return ret;
516 }
517 nvmem_cell_put(speedbin_nvmem);
518 }
519
520 for_each_present_cpu(cpu) {
521 struct dev_pm_opp_config config = {
522 .supported_hw = NULL,
523 };
524
525 cpu_dev = get_cpu_device(cpu);
526 if (NULL == cpu_dev) {
527 ret = -ENODEV;
528 goto free_opp;
529 }
530
531 if (drv->data->get_version) {
532 config.supported_hw = &drv->versions;
533 config.supported_hw_count = 1;
534
535 if (pvs_name)
536 config.prop_name = pvs_name;
537 }
538
539 if (config.supported_hw) {
540 drv->cpus[cpu].opp_token = dev_pm_opp_set_config(cpu_dev, &config);
541 if (drv->cpus[cpu].opp_token < 0) {
542 ret = drv->cpus[cpu].opp_token;
543 dev_err(cpu_dev, "Failed to set OPP config\n");
544 goto free_opp;
545 }
546 }
547
548 if (drv->data->pd_names) {
549 struct dev_pm_domain_attach_data attach_data = {
550 .pd_names = drv->data->pd_names,
551 .num_pd_names = drv->data->num_pd_names,
552 .pd_flags = PD_FLAG_DEV_LINK_ON |
553 PD_FLAG_REQUIRED_OPP,
554 };
555
556 ret = dev_pm_domain_attach_list(cpu_dev, &attach_data,
557 &drv->cpus[cpu].pd_list);
558 if (ret < 0)
559 goto free_opp;
560 }
561 }
562
563 cpufreq_dt_pdev = platform_device_register_simple("cpufreq-dt", -1,
564 NULL, 0);
565 if (!IS_ERR(cpufreq_dt_pdev)) {
566 platform_set_drvdata(pdev, drv);
567 return 0;
568 }
569
570 ret = PTR_ERR(cpufreq_dt_pdev);
571 dev_err(cpu_dev, "Failed to register platform device\n");
572
573free_opp:
574 for_each_present_cpu(cpu) {
575 dev_pm_domain_detach_list(drv->cpus[cpu].pd_list);
576 dev_pm_opp_clear_config(drv->cpus[cpu].opp_token);
577 }
578 return ret;
579}
580
581static void qcom_cpufreq_remove(struct platform_device *pdev)
582{
583 struct qcom_cpufreq_drv *drv = platform_get_drvdata(pdev);
584 unsigned int cpu;
585
586 platform_device_unregister(cpufreq_dt_pdev);
587
588 for_each_present_cpu(cpu) {
589 dev_pm_domain_detach_list(drv->cpus[cpu].pd_list);
590 dev_pm_opp_clear_config(drv->cpus[cpu].opp_token);
591 }
592}
593
594static int qcom_cpufreq_suspend(struct device *dev)
595{
596 struct qcom_cpufreq_drv *drv = dev_get_drvdata(dev);
597 unsigned int cpu;
598
599 for_each_present_cpu(cpu)
600 qcom_cpufreq_suspend_pd_devs(drv, cpu);
601
602 return 0;
603}
604
605static DEFINE_SIMPLE_DEV_PM_OPS(qcom_cpufreq_pm_ops, qcom_cpufreq_suspend, NULL);
606
607static struct platform_driver qcom_cpufreq_driver = {
608 .probe = qcom_cpufreq_probe,
609 .remove = qcom_cpufreq_remove,
610 .driver = {
611 .name = "qcom-cpufreq-nvmem",
612 .pm = pm_sleep_ptr(&qcom_cpufreq_pm_ops),
613 },
614};
615
616static const struct of_device_id qcom_cpufreq_match_list[] __initconst __maybe_unused = {
617 { .compatible = "qcom,apq8096", .data = &match_data_kryo },
618 { .compatible = "qcom,msm8909", .data = &match_data_msm8909 },
619 { .compatible = "qcom,msm8996", .data = &match_data_kryo },
620 { .compatible = "qcom,qcs404", .data = &match_data_qcs404 },
621 { .compatible = "qcom,ipq5332", .data = &match_data_kryo },
622 { .compatible = "qcom,ipq5424", .data = &match_data_kryo },
623 { .compatible = "qcom,ipq6018", .data = &match_data_ipq6018 },
624 { .compatible = "qcom,ipq8064", .data = &match_data_ipq8064 },
625 { .compatible = "qcom,ipq8074", .data = &match_data_ipq8074 },
626 { .compatible = "qcom,apq8064", .data = &match_data_krait },
627 { .compatible = "qcom,ipq9574", .data = &match_data_kryo },
628 { .compatible = "qcom,msm8974", .data = &match_data_krait },
629 { .compatible = "qcom,msm8960", .data = &match_data_krait },
630 {},
631};
632MODULE_DEVICE_TABLE(of, qcom_cpufreq_match_list);
633
634/*
635 * Since the driver depends on smem and nvmem drivers, which may
636 * return EPROBE_DEFER, all the real activity is done in the probe,
637 * which may be defered as well. The init here is only registering
638 * the driver and the platform device.
639 */
640static int __init qcom_cpufreq_init(void)
641{
642 const struct of_device_id *match;
643 int ret;
644
645 match = of_machine_get_match(qcom_cpufreq_match_list);
646 if (!match)
647 return -ENODEV;
648
649 ret = platform_driver_register(&qcom_cpufreq_driver);
650 if (unlikely(ret < 0))
651 return ret;
652
653 cpufreq_pdev = platform_device_register_data(NULL, "qcom-cpufreq-nvmem",
654 -1, match, sizeof(*match));
655 ret = PTR_ERR_OR_ZERO(cpufreq_pdev);
656 if (0 == ret)
657 return 0;
658
659 platform_driver_unregister(&qcom_cpufreq_driver);
660 return ret;
661}
662module_init(qcom_cpufreq_init);
663
664static void __exit qcom_cpufreq_exit(void)
665{
666 platform_device_unregister(cpufreq_pdev);
667 platform_driver_unregister(&qcom_cpufreq_driver);
668}
669module_exit(qcom_cpufreq_exit);
670
671MODULE_DESCRIPTION("Qualcomm Technologies, Inc. CPUfreq driver");
672MODULE_LICENSE("GPL v2");