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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * TI CPUFreq/OPP hw-supported driver
4 *
5 * Copyright (C) 2016-2017 Texas Instruments, Inc.
6 * Dave Gerlach <d-gerlach@ti.com>
7 */
8
9#include <linux/cpu.h>
10#include <linux/io.h>
11#include <linux/mfd/syscon.h>
12#include <linux/module.h>
13#include <linux/init.h>
14#include <linux/of.h>
15#include <linux/platform_device.h>
16#include <linux/pm_opp.h>
17#include <linux/regmap.h>
18#include <linux/slab.h>
19#include <linux/sys_soc.h>
20
21#define REVISION_MASK 0xF
22#define REVISION_SHIFT 28
23
24#define AM33XX_800M_ARM_MPU_MAX_FREQ 0x1E2F
25#define AM43XX_600M_ARM_MPU_MAX_FREQ 0xFFA
26
27#define DRA7_EFUSE_HAS_OD_MPU_OPP 11
28#define DRA7_EFUSE_HAS_HIGH_MPU_OPP 15
29#define DRA76_EFUSE_HAS_PLUS_MPU_OPP 18
30#define DRA7_EFUSE_HAS_ALL_MPU_OPP 23
31#define DRA76_EFUSE_HAS_ALL_MPU_OPP 24
32
33#define DRA7_EFUSE_NOM_MPU_OPP BIT(0)
34#define DRA7_EFUSE_OD_MPU_OPP BIT(1)
35#define DRA7_EFUSE_HIGH_MPU_OPP BIT(2)
36#define DRA76_EFUSE_PLUS_MPU_OPP BIT(3)
37
38#define OMAP3_CONTROL_DEVICE_STATUS 0x4800244C
39#define OMAP3_CONTROL_IDCODE 0x4830A204
40#define OMAP34xx_ProdID_SKUID 0x4830A20C
41#define OMAP3_SYSCON_BASE (0x48000000 + 0x2000 + 0x270)
42
43#define AM625_EFUSE_K_MPU_OPP 11
44#define AM625_EFUSE_S_MPU_OPP 19
45#define AM625_EFUSE_T_MPU_OPP 20
46
47#define AM625_SUPPORT_K_MPU_OPP BIT(0)
48#define AM625_SUPPORT_S_MPU_OPP BIT(1)
49#define AM625_SUPPORT_T_MPU_OPP BIT(2)
50
51enum {
52 AM62A7_EFUSE_M_MPU_OPP = 13,
53 AM62A7_EFUSE_N_MPU_OPP,
54 AM62A7_EFUSE_O_MPU_OPP,
55 AM62A7_EFUSE_P_MPU_OPP,
56 AM62A7_EFUSE_Q_MPU_OPP,
57 AM62A7_EFUSE_R_MPU_OPP,
58 AM62A7_EFUSE_S_MPU_OPP,
59 /*
60 * The V, U, and T speed grade numbering is out of order
61 * to align with the AM625 more uniformly. I promise I know
62 * my ABCs ;)
63 */
64 AM62A7_EFUSE_V_MPU_OPP,
65 AM62A7_EFUSE_U_MPU_OPP,
66 AM62A7_EFUSE_T_MPU_OPP,
67};
68
69#define AM62A7_SUPPORT_N_MPU_OPP BIT(0)
70#define AM62A7_SUPPORT_R_MPU_OPP BIT(1)
71#define AM62A7_SUPPORT_V_MPU_OPP BIT(2)
72
73#define AM62L3_EFUSE_E_MPU_OPP 5
74#define AM62L3_EFUSE_O_MPU_OPP 15
75
76#define AM62L3_SUPPORT_E_MPU_OPP BIT(0)
77#define AM62L3_SUPPORT_O_MPU_OPP BIT(1)
78
79#define AM62P5_EFUSE_O_MPU_OPP 15
80#define AM62P5_EFUSE_S_MPU_OPP 19
81#define AM62P5_EFUSE_T_MPU_OPP 20
82#define AM62P5_EFUSE_U_MPU_OPP 21
83#define AM62P5_EFUSE_V_MPU_OPP 22
84
85#define AM62P5_SUPPORT_O_MPU_OPP BIT(0)
86#define AM62P5_SUPPORT_U_MPU_OPP BIT(2)
87
88#define VERSION_COUNT 2
89
90struct ti_cpufreq_data;
91
92struct ti_cpufreq_soc_data {
93 const char * const *reg_names;
94 unsigned long (*efuse_xlate)(struct ti_cpufreq_data *opp_data,
95 unsigned long efuse);
96 unsigned long efuse_fallback;
97 unsigned long efuse_offset;
98 unsigned long efuse_mask;
99 unsigned long efuse_shift;
100 unsigned long rev_offset;
101 bool multi_regulator;
102/* Backward compatibility hack: Might have missing syscon */
103#define TI_QUIRK_SYSCON_MAY_BE_MISSING 0x1
104/* Backward compatibility hack: new syscon size is 1 register wide */
105#define TI_QUIRK_SYSCON_IS_SINGLE_REG 0x2
106 u8 quirks;
107};
108
109struct ti_cpufreq_data {
110 struct device *cpu_dev;
111 struct device_node *opp_node;
112 struct regmap *syscon;
113 const struct ti_cpufreq_soc_data *soc_data;
114};
115
116static unsigned long amx3_efuse_xlate(struct ti_cpufreq_data *opp_data,
117 unsigned long efuse)
118{
119 if (!efuse)
120 efuse = opp_data->soc_data->efuse_fallback;
121 /* AM335x and AM437x use "OPP disable" bits, so invert */
122 return ~efuse;
123}
124
125static unsigned long dra7_efuse_xlate(struct ti_cpufreq_data *opp_data,
126 unsigned long efuse)
127{
128 unsigned long calculated_efuse = DRA7_EFUSE_NOM_MPU_OPP;
129
130 /*
131 * The efuse on dra7 and am57 parts contains a specific
132 * value indicating the highest available OPP.
133 */
134
135 switch (efuse) {
136 case DRA76_EFUSE_HAS_PLUS_MPU_OPP:
137 case DRA76_EFUSE_HAS_ALL_MPU_OPP:
138 calculated_efuse |= DRA76_EFUSE_PLUS_MPU_OPP;
139 fallthrough;
140 case DRA7_EFUSE_HAS_ALL_MPU_OPP:
141 case DRA7_EFUSE_HAS_HIGH_MPU_OPP:
142 calculated_efuse |= DRA7_EFUSE_HIGH_MPU_OPP;
143 fallthrough;
144 case DRA7_EFUSE_HAS_OD_MPU_OPP:
145 calculated_efuse |= DRA7_EFUSE_OD_MPU_OPP;
146 }
147
148 return calculated_efuse;
149}
150
151static unsigned long omap3_efuse_xlate(struct ti_cpufreq_data *opp_data,
152 unsigned long efuse)
153{
154 /* OPP enable bit ("Speed Binned") */
155 return BIT(efuse);
156}
157
158static unsigned long am62p5_efuse_xlate(struct ti_cpufreq_data *opp_data,
159 unsigned long efuse)
160{
161 unsigned long calculated_efuse = AM62P5_SUPPORT_O_MPU_OPP;
162
163 switch (efuse) {
164 case AM62P5_EFUSE_V_MPU_OPP:
165 case AM62P5_EFUSE_U_MPU_OPP:
166 case AM62P5_EFUSE_T_MPU_OPP:
167 case AM62P5_EFUSE_S_MPU_OPP:
168 calculated_efuse |= AM62P5_SUPPORT_U_MPU_OPP;
169 fallthrough;
170 case AM62P5_EFUSE_O_MPU_OPP:
171 calculated_efuse |= AM62P5_SUPPORT_O_MPU_OPP;
172 }
173
174 return calculated_efuse;
175}
176
177static unsigned long am62a7_efuse_xlate(struct ti_cpufreq_data *opp_data,
178 unsigned long efuse)
179{
180 unsigned long calculated_efuse = AM62A7_SUPPORT_N_MPU_OPP;
181
182 switch (efuse) {
183 case AM62A7_EFUSE_V_MPU_OPP:
184 case AM62A7_EFUSE_U_MPU_OPP:
185 case AM62A7_EFUSE_T_MPU_OPP:
186 case AM62A7_EFUSE_S_MPU_OPP:
187 calculated_efuse |= AM62A7_SUPPORT_V_MPU_OPP;
188 fallthrough;
189 case AM62A7_EFUSE_R_MPU_OPP:
190 case AM62A7_EFUSE_Q_MPU_OPP:
191 case AM62A7_EFUSE_P_MPU_OPP:
192 case AM62A7_EFUSE_O_MPU_OPP:
193 calculated_efuse |= AM62A7_SUPPORT_R_MPU_OPP;
194 fallthrough;
195 case AM62A7_EFUSE_N_MPU_OPP:
196 case AM62A7_EFUSE_M_MPU_OPP:
197 calculated_efuse |= AM62A7_SUPPORT_N_MPU_OPP;
198 }
199
200 return calculated_efuse;
201}
202
203static unsigned long am625_efuse_xlate(struct ti_cpufreq_data *opp_data,
204 unsigned long efuse)
205{
206 unsigned long calculated_efuse = AM625_SUPPORT_K_MPU_OPP;
207
208 switch (efuse) {
209 case AM625_EFUSE_T_MPU_OPP:
210 calculated_efuse |= AM625_SUPPORT_T_MPU_OPP;
211 fallthrough;
212 case AM625_EFUSE_S_MPU_OPP:
213 calculated_efuse |= AM625_SUPPORT_S_MPU_OPP;
214 fallthrough;
215 case AM625_EFUSE_K_MPU_OPP:
216 calculated_efuse |= AM625_SUPPORT_K_MPU_OPP;
217 }
218
219 return calculated_efuse;
220}
221
222static unsigned long am62l3_efuse_xlate(struct ti_cpufreq_data *opp_data,
223 unsigned long efuse)
224{
225 unsigned long calculated_efuse = AM62L3_SUPPORT_E_MPU_OPP;
226
227 switch (efuse) {
228 case AM62L3_EFUSE_O_MPU_OPP:
229 calculated_efuse |= AM62L3_SUPPORT_O_MPU_OPP;
230 fallthrough;
231 case AM62L3_EFUSE_E_MPU_OPP:
232 calculated_efuse |= AM62L3_SUPPORT_E_MPU_OPP;
233 }
234
235 return calculated_efuse;
236}
237
238static struct ti_cpufreq_soc_data am3x_soc_data = {
239 .efuse_xlate = amx3_efuse_xlate,
240 .efuse_fallback = AM33XX_800M_ARM_MPU_MAX_FREQ,
241 .efuse_offset = 0x07fc,
242 .efuse_mask = 0x1fff,
243 .rev_offset = 0x600,
244 .multi_regulator = false,
245};
246
247static struct ti_cpufreq_soc_data am4x_soc_data = {
248 .efuse_xlate = amx3_efuse_xlate,
249 .efuse_fallback = AM43XX_600M_ARM_MPU_MAX_FREQ,
250 .efuse_offset = 0x0610,
251 .efuse_mask = 0x3f,
252 .rev_offset = 0x600,
253 .multi_regulator = false,
254};
255
256static struct ti_cpufreq_soc_data dra7_soc_data = {
257 .efuse_xlate = dra7_efuse_xlate,
258 .efuse_offset = 0x020c,
259 .efuse_mask = 0xf80000,
260 .efuse_shift = 19,
261 .rev_offset = 0x204,
262 .multi_regulator = true,
263};
264
265/*
266 * OMAP35x TRM (SPRUF98K):
267 * CONTROL_IDCODE (0x4830 A204) describes Silicon revisions.
268 * Control OMAP Status Register 15:0 (Address 0x4800 244C)
269 * to separate between omap3503, omap3515, omap3525, omap3530
270 * and feature presence.
271 * There are encodings for versions limited to 400/266MHz
272 * but we ignore.
273 * Not clear if this also holds for omap34xx.
274 * some eFuse values e.g. CONTROL_FUSE_OPP1_VDD1
275 * are stored in the SYSCON register range
276 * Register 0x4830A20C [ProdID.SKUID] [0:3]
277 * 0x0 for normal 600/430MHz device.
278 * 0x8 for 720/520MHz device.
279 * Not clear what omap34xx value is.
280 */
281
282static struct ti_cpufreq_soc_data omap34xx_soc_data = {
283 .efuse_xlate = omap3_efuse_xlate,
284 .efuse_offset = OMAP34xx_ProdID_SKUID - OMAP3_SYSCON_BASE,
285 .efuse_shift = 3,
286 .efuse_mask = BIT(3),
287 .rev_offset = OMAP3_CONTROL_IDCODE - OMAP3_SYSCON_BASE,
288 .multi_regulator = false,
289 .quirks = TI_QUIRK_SYSCON_MAY_BE_MISSING,
290};
291
292/*
293 * AM/DM37x TRM (SPRUGN4M)
294 * CONTROL_IDCODE (0x4830 A204) describes Silicon revisions.
295 * Control Device Status Register 15:0 (Address 0x4800 244C)
296 * to separate between am3703, am3715, dm3725, dm3730
297 * and feature presence.
298 * Speed Binned = Bit 9
299 * 0 800/600 MHz
300 * 1 1000/800 MHz
301 * some eFuse values e.g. CONTROL_FUSE_OPP 1G_VDD1
302 * are stored in the SYSCON register range.
303 * There is no 0x4830A20C [ProdID.SKUID] register (exists but
304 * seems to always read as 0).
305 */
306
307static const char * const omap3_reg_names[] = {"cpu0", "vbb", NULL};
308
309static struct ti_cpufreq_soc_data omap36xx_soc_data = {
310 .reg_names = omap3_reg_names,
311 .efuse_xlate = omap3_efuse_xlate,
312 .efuse_offset = OMAP3_CONTROL_DEVICE_STATUS - OMAP3_SYSCON_BASE,
313 .efuse_shift = 9,
314 .efuse_mask = BIT(9),
315 .rev_offset = OMAP3_CONTROL_IDCODE - OMAP3_SYSCON_BASE,
316 .multi_regulator = true,
317 .quirks = TI_QUIRK_SYSCON_MAY_BE_MISSING,
318};
319
320/*
321 * AM3517 is quite similar to AM/DM37x except that it has no
322 * high speed grade eFuse and no abb ldo
323 */
324
325static struct ti_cpufreq_soc_data am3517_soc_data = {
326 .efuse_xlate = omap3_efuse_xlate,
327 .efuse_offset = OMAP3_CONTROL_DEVICE_STATUS - OMAP3_SYSCON_BASE,
328 .efuse_shift = 0,
329 .efuse_mask = 0,
330 .rev_offset = OMAP3_CONTROL_IDCODE - OMAP3_SYSCON_BASE,
331 .multi_regulator = false,
332 .quirks = TI_QUIRK_SYSCON_MAY_BE_MISSING,
333};
334
335static const struct soc_device_attribute k3_cpufreq_soc[] = {
336 { .family = "AM62X", },
337 { .family = "AM62AX", },
338 { .family = "AM62DX", },
339 { .family = "AM62LX", },
340 { .family = "AM62PX", },
341 { /* sentinel */ }
342};
343
344static struct ti_cpufreq_soc_data am625_soc_data = {
345 .efuse_xlate = am625_efuse_xlate,
346 .efuse_offset = 0x0018,
347 .efuse_mask = 0x07c0,
348 .efuse_shift = 0x6,
349 .multi_regulator = false,
350 .quirks = TI_QUIRK_SYSCON_IS_SINGLE_REG,
351};
352
353static struct ti_cpufreq_soc_data am62a7_soc_data = {
354 .efuse_xlate = am62a7_efuse_xlate,
355 .efuse_offset = 0x0,
356 .efuse_mask = 0x07c0,
357 .efuse_shift = 0x6,
358 .multi_regulator = false,
359};
360
361static struct ti_cpufreq_soc_data am62l3_soc_data = {
362 .efuse_xlate = am62l3_efuse_xlate,
363 .efuse_offset = 0x0,
364 .efuse_mask = 0x07c0,
365 .efuse_shift = 0x6,
366 .multi_regulator = false,
367};
368
369static struct ti_cpufreq_soc_data am62p5_soc_data = {
370 .efuse_xlate = am62p5_efuse_xlate,
371 .efuse_offset = 0x0,
372 .efuse_mask = 0x07c0,
373 .efuse_shift = 0x6,
374 .multi_regulator = false,
375};
376
377/**
378 * ti_cpufreq_get_efuse() - Parse and return efuse value present on SoC
379 * @opp_data: pointer to ti_cpufreq_data context
380 * @efuse_value: Set to the value parsed from efuse
381 *
382 * Returns error code if efuse not read properly.
383 */
384static int ti_cpufreq_get_efuse(struct ti_cpufreq_data *opp_data,
385 u32 *efuse_value)
386{
387 struct device *dev = opp_data->cpu_dev;
388 u32 efuse;
389 int ret;
390
391 ret = regmap_read(opp_data->syscon, opp_data->soc_data->efuse_offset,
392 &efuse);
393
394 if (opp_data->soc_data->quirks & TI_QUIRK_SYSCON_IS_SINGLE_REG && ret == -EIO)
395 ret = regmap_read(opp_data->syscon, 0x0, &efuse);
396
397 if (opp_data->soc_data->quirks & TI_QUIRK_SYSCON_MAY_BE_MISSING && ret == -EIO) {
398 /* not a syscon register! */
399 void __iomem *regs = ioremap(OMAP3_SYSCON_BASE +
400 opp_data->soc_data->efuse_offset, 4);
401
402 if (!regs)
403 return -ENOMEM;
404 efuse = readl(regs);
405 iounmap(regs);
406 }
407 else if (ret) {
408 dev_err(dev,
409 "Failed to read the efuse value from syscon: %d\n",
410 ret);
411 return ret;
412 }
413
414 efuse = (efuse & opp_data->soc_data->efuse_mask);
415 efuse >>= opp_data->soc_data->efuse_shift;
416
417 *efuse_value = opp_data->soc_data->efuse_xlate(opp_data, efuse);
418
419 return 0;
420}
421
422/**
423 * ti_cpufreq_get_rev() - Parse and return rev value present on SoC
424 * @opp_data: pointer to ti_cpufreq_data context
425 * @revision_value: Set to the value parsed from revision register
426 *
427 * Returns error code if revision not read properly.
428 */
429static int ti_cpufreq_get_rev(struct ti_cpufreq_data *opp_data,
430 u32 *revision_value)
431{
432 struct device *dev = opp_data->cpu_dev;
433 u32 revision;
434 int ret;
435 if (soc_device_match(k3_cpufreq_soc)) {
436 /*
437 * Since the SR is 1.0, hard code the revision_value as
438 * 0x1 here. This way we avoid re using the same register
439 * that is giving us required information inside socinfo
440 * anyway.
441 */
442 *revision_value = 0x1;
443 goto done;
444 }
445
446 ret = regmap_read(opp_data->syscon, opp_data->soc_data->rev_offset,
447 &revision);
448 if (opp_data->soc_data->quirks & TI_QUIRK_SYSCON_MAY_BE_MISSING && ret == -EIO) {
449 /* not a syscon register! */
450 void __iomem *regs = ioremap(OMAP3_SYSCON_BASE +
451 opp_data->soc_data->rev_offset, 4);
452
453 if (!regs)
454 return -ENOMEM;
455 revision = readl(regs);
456 iounmap(regs);
457 }
458 else if (ret) {
459 dev_err(dev,
460 "Failed to read the revision number from syscon: %d\n",
461 ret);
462 return ret;
463 }
464
465 *revision_value = BIT((revision >> REVISION_SHIFT) & REVISION_MASK);
466
467done:
468 return 0;
469}
470
471static int ti_cpufreq_setup_syscon_register(struct ti_cpufreq_data *opp_data)
472{
473 struct device *dev = opp_data->cpu_dev;
474 struct device_node *np = opp_data->opp_node;
475
476 opp_data->syscon = syscon_regmap_lookup_by_phandle(np,
477 "syscon");
478 if (IS_ERR(opp_data->syscon)) {
479 dev_err(dev,
480 "\"syscon\" is missing, cannot use OPPv2 table.\n");
481 return PTR_ERR(opp_data->syscon);
482 }
483
484 return 0;
485}
486
487static const struct of_device_id ti_cpufreq_of_match[] __maybe_unused = {
488 { .compatible = "ti,am33xx", .data = &am3x_soc_data, },
489 { .compatible = "ti,am3517", .data = &am3517_soc_data, },
490 { .compatible = "ti,am43", .data = &am4x_soc_data, },
491 { .compatible = "ti,dra7", .data = &dra7_soc_data },
492 { .compatible = "ti,omap34xx", .data = &omap34xx_soc_data, },
493 { .compatible = "ti,omap36xx", .data = &omap36xx_soc_data, },
494 { .compatible = "ti,am625", .data = &am625_soc_data, },
495 { .compatible = "ti,am62a7", .data = &am62a7_soc_data, },
496 { .compatible = "ti,am62d2", .data = &am62a7_soc_data, },
497 { .compatible = "ti,am62l3", .data = &am62l3_soc_data, },
498 { .compatible = "ti,am62p5", .data = &am62p5_soc_data, },
499 /* legacy */
500 { .compatible = "ti,omap3430", .data = &omap34xx_soc_data, },
501 { .compatible = "ti,omap3630", .data = &omap36xx_soc_data, },
502 {},
503};
504
505static int ti_cpufreq_probe(struct platform_device *pdev)
506{
507 u32 version[VERSION_COUNT];
508 const struct of_device_id *match;
509 struct ti_cpufreq_data *opp_data;
510 const char * const default_reg_names[] = {"vdd", "vbb", NULL};
511 int ret;
512 struct dev_pm_opp_config config = {
513 .supported_hw = version,
514 .supported_hw_count = ARRAY_SIZE(version),
515 };
516
517 match = dev_get_platdata(&pdev->dev);
518 if (!match)
519 return -ENODEV;
520
521 opp_data = devm_kzalloc(&pdev->dev, sizeof(*opp_data), GFP_KERNEL);
522 if (!opp_data)
523 return -ENOMEM;
524
525 opp_data->soc_data = match->data;
526
527 opp_data->cpu_dev = get_cpu_device(0);
528 if (!opp_data->cpu_dev) {
529 pr_err("%s: Failed to get device for CPU0\n", __func__);
530 return -ENODEV;
531 }
532
533 opp_data->opp_node = dev_pm_opp_of_get_opp_desc_node(opp_data->cpu_dev);
534 if (!opp_data->opp_node) {
535 dev_info(opp_data->cpu_dev,
536 "OPP-v2 not supported, cpufreq-dt will attempt to use legacy tables.\n");
537 goto register_cpufreq_dt;
538 }
539
540 ret = ti_cpufreq_setup_syscon_register(opp_data);
541 if (ret)
542 goto fail_put_node;
543
544 /*
545 * OPPs determine whether or not they are supported based on
546 * two metrics:
547 * 0 - SoC Revision
548 * 1 - eFuse value
549 */
550 ret = ti_cpufreq_get_rev(opp_data, &version[0]);
551 if (ret)
552 goto fail_put_node;
553
554 ret = ti_cpufreq_get_efuse(opp_data, &version[1]);
555 if (ret)
556 goto fail_put_node;
557
558 if (opp_data->soc_data->multi_regulator) {
559 if (opp_data->soc_data->reg_names)
560 config.regulator_names = opp_data->soc_data->reg_names;
561 else
562 config.regulator_names = default_reg_names;
563 }
564
565 ret = dev_pm_opp_set_config(opp_data->cpu_dev, &config);
566 if (ret < 0) {
567 dev_err_probe(opp_data->cpu_dev, ret, "Failed to set OPP config\n");
568 goto fail_put_node;
569 }
570
571 of_node_put(opp_data->opp_node);
572
573register_cpufreq_dt:
574 platform_device_register_simple("cpufreq-dt", -1, NULL, 0);
575
576 return 0;
577
578fail_put_node:
579 of_node_put(opp_data->opp_node);
580
581 return ret;
582}
583
584static int __init ti_cpufreq_init(void)
585{
586 const struct of_device_id *match;
587
588 /* Check to ensure we are on a compatible platform */
589 match = of_machine_get_match(ti_cpufreq_of_match);
590 if (match)
591 platform_device_register_data(NULL, "ti-cpufreq", -1, match,
592 sizeof(*match));
593
594 return 0;
595}
596module_init(ti_cpufreq_init);
597
598static struct platform_driver ti_cpufreq_driver = {
599 .probe = ti_cpufreq_probe,
600 .driver = {
601 .name = "ti-cpufreq",
602 },
603};
604builtin_platform_driver(ti_cpufreq_driver);
605
606MODULE_DESCRIPTION("TI CPUFreq/OPP hw-supported driver");
607MODULE_AUTHOR("Dave Gerlach <d-gerlach@ti.com>");
608MODULE_LICENSE("GPL v2");