Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Generic EP93xx GPIO handling
4 *
5 * Copyright (c) 2008 Ryan Mallon
6 * Copyright (c) 2011 H Hartley Sweeten <hsweeten@visionengravers.com>
7 *
8 * Based on code originally from:
9 * linux/arch/arm/mach-ep93xx/core.c
10 */
11
12#include <linux/bitops.h>
13#include <linux/gpio/driver.h>
14#include <linux/gpio/generic.h>
15#include <linux/init.h>
16#include <linux/interrupt.h>
17#include <linux/io.h>
18#include <linux/irq.h>
19#include <linux/module.h>
20#include <linux/platform_device.h>
21#include <linux/seq_file.h>
22#include <linux/slab.h>
23
24struct ep93xx_gpio_irq_chip {
25 void __iomem *base;
26 u8 int_unmasked;
27 u8 int_enabled;
28 u8 int_type1;
29 u8 int_type2;
30 u8 int_debounce;
31};
32
33struct ep93xx_gpio_chip {
34 void __iomem *base;
35 struct gpio_generic_chip chip;
36 struct ep93xx_gpio_irq_chip *eic;
37};
38
39static struct ep93xx_gpio_chip *to_ep93xx_gpio_chip(struct gpio_chip *gc)
40{
41 return container_of(to_gpio_generic_chip(gc), struct ep93xx_gpio_chip, chip);
42}
43
44static struct ep93xx_gpio_irq_chip *to_ep93xx_gpio_irq_chip(struct gpio_chip *gc)
45{
46 struct ep93xx_gpio_chip *egc = to_ep93xx_gpio_chip(gc);
47
48 return egc->eic;
49}
50
51/*************************************************************************
52 * Interrupt handling for EP93xx on-chip GPIOs
53 *************************************************************************/
54#define EP93XX_INT_TYPE1_OFFSET 0x00
55#define EP93XX_INT_TYPE2_OFFSET 0x04
56#define EP93XX_INT_EOI_OFFSET 0x08
57#define EP93XX_INT_EN_OFFSET 0x0c
58#define EP93XX_INT_STATUS_OFFSET 0x10
59#define EP93XX_INT_RAW_STATUS_OFFSET 0x14
60#define EP93XX_INT_DEBOUNCE_OFFSET 0x18
61
62static void ep93xx_gpio_update_int_params(struct ep93xx_gpio_irq_chip *eic)
63{
64 writeb_relaxed(0, eic->base + EP93XX_INT_EN_OFFSET);
65
66 writeb_relaxed(eic->int_type2,
67 eic->base + EP93XX_INT_TYPE2_OFFSET);
68
69 writeb_relaxed(eic->int_type1,
70 eic->base + EP93XX_INT_TYPE1_OFFSET);
71
72 writeb_relaxed(eic->int_unmasked & eic->int_enabled,
73 eic->base + EP93XX_INT_EN_OFFSET);
74}
75
76static void ep93xx_gpio_int_debounce(struct gpio_chip *gc,
77 unsigned int offset, bool enable)
78{
79 struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);
80 int port_mask = BIT(offset);
81
82 if (enable)
83 eic->int_debounce |= port_mask;
84 else
85 eic->int_debounce &= ~port_mask;
86
87 writeb(eic->int_debounce, eic->base + EP93XX_INT_DEBOUNCE_OFFSET);
88}
89
90static u32 ep93xx_gpio_ab_irq_handler(struct gpio_chip *gc)
91{
92 struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);
93 unsigned long stat;
94 int offset;
95
96 stat = readb(eic->base + EP93XX_INT_STATUS_OFFSET);
97 for_each_set_bit(offset, &stat, 8)
98 generic_handle_domain_irq(gc->irq.domain, offset);
99
100 return stat;
101}
102
103static irqreturn_t ep93xx_ab_irq_handler(int irq, void *dev_id)
104{
105 return IRQ_RETVAL(ep93xx_gpio_ab_irq_handler(dev_id));
106}
107
108static void ep93xx_gpio_f_irq_handler(struct irq_desc *desc)
109{
110 struct irq_chip *irqchip = irq_desc_get_chip(desc);
111 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
112 struct gpio_irq_chip *gic = &gc->irq;
113 unsigned int parent = irq_desc_get_irq(desc);
114 unsigned int i;
115
116 chained_irq_enter(irqchip, desc);
117 for (i = 0; i < gic->num_parents; i++)
118 if (gic->parents[i] == parent)
119 break;
120
121 if (i < gic->num_parents)
122 generic_handle_domain_irq(gc->irq.domain, i);
123
124 chained_irq_exit(irqchip, desc);
125}
126
127static void ep93xx_gpio_irq_ack(struct irq_data *d)
128{
129 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
130 struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);
131 int port_mask = BIT(irqd_to_hwirq(d));
132
133 if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) {
134 eic->int_type2 ^= port_mask; /* switch edge direction */
135 ep93xx_gpio_update_int_params(eic);
136 }
137
138 writeb(port_mask, eic->base + EP93XX_INT_EOI_OFFSET);
139}
140
141static void ep93xx_gpio_irq_mask_ack(struct irq_data *d)
142{
143 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
144 struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);
145 irq_hw_number_t hwirq = irqd_to_hwirq(d);
146 int port_mask = BIT(hwirq);
147
148 if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH)
149 eic->int_type2 ^= port_mask; /* switch edge direction */
150
151 eic->int_unmasked &= ~port_mask;
152 ep93xx_gpio_update_int_params(eic);
153
154 writeb(port_mask, eic->base + EP93XX_INT_EOI_OFFSET);
155 gpiochip_disable_irq(gc, hwirq);
156}
157
158static void ep93xx_gpio_irq_mask(struct irq_data *d)
159{
160 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
161 struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);
162 irq_hw_number_t hwirq = irqd_to_hwirq(d);
163
164 eic->int_unmasked &= ~BIT(hwirq);
165 ep93xx_gpio_update_int_params(eic);
166 gpiochip_disable_irq(gc, hwirq);
167}
168
169static void ep93xx_gpio_irq_unmask(struct irq_data *d)
170{
171 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
172 struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);
173 irq_hw_number_t hwirq = irqd_to_hwirq(d);
174
175 gpiochip_enable_irq(gc, hwirq);
176 eic->int_unmasked |= BIT(hwirq);
177 ep93xx_gpio_update_int_params(eic);
178}
179
180/*
181 * gpio_int_type1 controls whether the interrupt is level (0) or
182 * edge (1) triggered, while gpio_int_type2 controls whether it
183 * triggers on low/falling (0) or high/rising (1).
184 */
185static int ep93xx_gpio_irq_type(struct irq_data *d, unsigned int type)
186{
187 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
188 struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);
189 irq_hw_number_t hwirq = irqd_to_hwirq(d);
190 int port_mask = BIT(hwirq);
191 irq_flow_handler_t handler;
192
193 gc->direction_input(gc, hwirq);
194
195 switch (type) {
196 case IRQ_TYPE_EDGE_RISING:
197 eic->int_type1 |= port_mask;
198 eic->int_type2 |= port_mask;
199 handler = handle_edge_irq;
200 break;
201 case IRQ_TYPE_EDGE_FALLING:
202 eic->int_type1 |= port_mask;
203 eic->int_type2 &= ~port_mask;
204 handler = handle_edge_irq;
205 break;
206 case IRQ_TYPE_LEVEL_HIGH:
207 eic->int_type1 &= ~port_mask;
208 eic->int_type2 |= port_mask;
209 handler = handle_level_irq;
210 break;
211 case IRQ_TYPE_LEVEL_LOW:
212 eic->int_type1 &= ~port_mask;
213 eic->int_type2 &= ~port_mask;
214 handler = handle_level_irq;
215 break;
216 case IRQ_TYPE_EDGE_BOTH:
217 eic->int_type1 |= port_mask;
218 /* set initial polarity based on current input level */
219 if (gc->get(gc, hwirq))
220 eic->int_type2 &= ~port_mask; /* falling */
221 else
222 eic->int_type2 |= port_mask; /* rising */
223 handler = handle_edge_irq;
224 break;
225 default:
226 return -EINVAL;
227 }
228
229 irq_set_handler_locked(d, handler);
230
231 eic->int_enabled |= port_mask;
232
233 ep93xx_gpio_update_int_params(eic);
234
235 return 0;
236}
237
238static int ep93xx_gpio_set_config(struct gpio_chip *gc, unsigned offset,
239 unsigned long config)
240{
241 u32 debounce;
242
243 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
244 return -ENOTSUPP;
245
246 debounce = pinconf_to_config_argument(config);
247 ep93xx_gpio_int_debounce(gc, offset, debounce ? true : false);
248
249 return 0;
250}
251
252static void ep93xx_irq_print_chip(struct irq_data *data, struct seq_file *p)
253{
254 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
255
256 seq_puts(p, dev_name(gc->parent));
257}
258
259static const struct irq_chip gpio_eic_irq_chip = {
260 .name = "ep93xx-gpio-eic",
261 .irq_ack = ep93xx_gpio_irq_ack,
262 .irq_mask = ep93xx_gpio_irq_mask,
263 .irq_unmask = ep93xx_gpio_irq_unmask,
264 .irq_mask_ack = ep93xx_gpio_irq_mask_ack,
265 .irq_set_type = ep93xx_gpio_irq_type,
266 .irq_print_chip = ep93xx_irq_print_chip,
267 .flags = IRQCHIP_IMMUTABLE,
268 GPIOCHIP_IRQ_RESOURCE_HELPERS,
269};
270
271static int ep93xx_setup_irqs(struct platform_device *pdev,
272 struct ep93xx_gpio_chip *egc)
273{
274 struct gpio_chip *gc = &egc->chip.gc;
275 struct device *dev = &pdev->dev;
276 struct gpio_irq_chip *girq = &gc->irq;
277 int ret, irq, i;
278 void __iomem *intr;
279
280 intr = devm_platform_ioremap_resource_byname(pdev, "intr");
281 if (IS_ERR(intr))
282 return PTR_ERR(intr);
283
284 gc->set_config = ep93xx_gpio_set_config;
285 egc->eic = devm_kzalloc(dev, sizeof(*egc->eic), GFP_KERNEL);
286 if (!egc->eic)
287 return -ENOMEM;
288
289 egc->eic->base = intr;
290 gpio_irq_chip_set_chip(girq, &gpio_eic_irq_chip);
291 girq->num_parents = platform_irq_count(pdev);
292 if (girq->num_parents == 0)
293 return -EINVAL;
294
295 girq->parents = devm_kcalloc(dev, girq->num_parents, sizeof(*girq->parents),
296 GFP_KERNEL);
297 if (!girq->parents)
298 return -ENOMEM;
299
300 if (girq->num_parents == 1) { /* A/B irqchips */
301 irq = platform_get_irq(pdev, 0);
302 if (irq < 0)
303 return irq;
304
305 ret = devm_request_irq(dev, irq, ep93xx_ab_irq_handler,
306 IRQF_SHARED, gc->label, gc);
307 if (ret)
308 return dev_err_probe(dev, ret, "requesting IRQ: %d\n", irq);
309
310 girq->parents[0] = irq;
311 } else { /* F irqchip */
312 girq->parent_handler = ep93xx_gpio_f_irq_handler;
313
314 for (i = 0; i < girq->num_parents; i++) {
315 irq = platform_get_irq_optional(pdev, i);
316 if (irq < 0)
317 continue;
318
319 girq->parents[i] = irq;
320 }
321
322 girq->map = girq->parents;
323 }
324
325 girq->default_type = IRQ_TYPE_NONE;
326 /* TODO: replace with handle_bad_irq() once we are fully hierarchical */
327 girq->handler = handle_simple_irq;
328
329 return 0;
330}
331
332static int ep93xx_gpio_probe(struct platform_device *pdev)
333{
334 struct gpio_generic_chip_config config;
335 struct ep93xx_gpio_chip *egc;
336 struct gpio_chip *gc;
337 void __iomem *data;
338 void __iomem *dir;
339 int ret;
340
341 egc = devm_kzalloc(&pdev->dev, sizeof(*egc), GFP_KERNEL);
342 if (!egc)
343 return -ENOMEM;
344
345 data = devm_platform_ioremap_resource_byname(pdev, "data");
346 if (IS_ERR(data))
347 return PTR_ERR(data);
348
349 dir = devm_platform_ioremap_resource_byname(pdev, "dir");
350 if (IS_ERR(dir))
351 return PTR_ERR(dir);
352
353 gc = &egc->chip.gc;
354
355 config = (struct gpio_generic_chip_config) {
356 .dev = &pdev->dev,
357 .sz = 1,
358 .dat = data,
359 .dirout = dir,
360 };
361
362 ret = gpio_generic_chip_init(&egc->chip, &config);
363 if (ret)
364 return dev_err_probe(&pdev->dev, ret, "unable to init generic GPIO\n");
365
366 gc->label = dev_name(&pdev->dev);
367 if (platform_irq_count(pdev) > 0) {
368 dev_dbg(&pdev->dev, "setting up irqs for %s\n", dev_name(&pdev->dev));
369 ret = ep93xx_setup_irqs(pdev, egc);
370 if (ret)
371 dev_err_probe(&pdev->dev, ret, "setup irqs failed");
372 }
373
374 return devm_gpiochip_add_data(&pdev->dev, gc, egc);
375}
376
377static const struct of_device_id ep93xx_gpio_match[] = {
378 { .compatible = "cirrus,ep9301-gpio" },
379 { /* sentinel */ }
380};
381
382static struct platform_driver ep93xx_gpio_driver = {
383 .driver = {
384 .name = "gpio-ep93xx",
385 .of_match_table = ep93xx_gpio_match,
386 },
387 .probe = ep93xx_gpio_probe,
388};
389
390static int __init ep93xx_gpio_init(void)
391{
392 return platform_driver_register(&ep93xx_gpio_driver);
393}
394postcore_initcall(ep93xx_gpio_init);
395
396MODULE_AUTHOR("Ryan Mallon <ryan@bluewatersys.com> "
397 "H Hartley Sweeten <hsweeten@visionengravers.com>");
398MODULE_DESCRIPTION("EP93XX GPIO driver");
399MODULE_LICENSE("GPL");