Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * MAXIM MAX77620 GPIO driver
4 *
5 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
6 */
7
8#include <linux/gpio/driver.h>
9#include <linux/interrupt.h>
10#include <linux/mfd/max77620.h>
11#include <linux/module.h>
12#include <linux/platform_device.h>
13#include <linux/regmap.h>
14
15#define GPIO_REG_ADDR(offset) (MAX77620_REG_GPIO0 + offset)
16
17struct max77620_gpio {
18 struct gpio_chip gpio_chip;
19 struct regmap *rmap;
20 struct device *dev;
21 struct mutex buslock; /* irq_bus_lock */
22 unsigned int irq_type[MAX77620_GPIO_NR];
23 bool irq_enabled[MAX77620_GPIO_NR];
24};
25
26static irqreturn_t max77620_gpio_irqhandler(int irq, void *data)
27{
28 struct max77620_gpio *gpio = data;
29 unsigned int value, offset;
30 unsigned long pending;
31 int err;
32
33 err = regmap_read(gpio->rmap, MAX77620_REG_IRQ_LVL2_GPIO, &value);
34 if (err < 0) {
35 dev_err(gpio->dev, "REG_IRQ_LVL2_GPIO read failed: %d\n", err);
36 return IRQ_NONE;
37 }
38
39 pending = value;
40
41 for_each_set_bit(offset, &pending, MAX77620_GPIO_NR) {
42 unsigned int virq;
43
44 virq = irq_find_mapping(gpio->gpio_chip.irq.domain, offset);
45 handle_nested_irq(virq);
46 }
47
48 return IRQ_HANDLED;
49}
50
51static void max77620_gpio_irq_mask(struct irq_data *data)
52{
53 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
54 struct max77620_gpio *gpio = gpiochip_get_data(chip);
55
56 gpio->irq_enabled[data->hwirq] = false;
57 gpiochip_disable_irq(chip, data->hwirq);
58}
59
60static void max77620_gpio_irq_unmask(struct irq_data *data)
61{
62 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
63 struct max77620_gpio *gpio = gpiochip_get_data(chip);
64
65 gpiochip_enable_irq(chip, data->hwirq);
66 gpio->irq_enabled[data->hwirq] = true;
67}
68
69static int max77620_gpio_set_irq_type(struct irq_data *data, unsigned int type)
70{
71 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
72 struct max77620_gpio *gpio = gpiochip_get_data(chip);
73 unsigned int irq_type;
74
75 switch (type) {
76 case IRQ_TYPE_EDGE_RISING:
77 irq_type = MAX77620_CNFG_GPIO_INT_RISING;
78 break;
79
80 case IRQ_TYPE_EDGE_FALLING:
81 irq_type = MAX77620_CNFG_GPIO_INT_FALLING;
82 break;
83
84 case IRQ_TYPE_EDGE_BOTH:
85 irq_type = MAX77620_CNFG_GPIO_INT_RISING |
86 MAX77620_CNFG_GPIO_INT_FALLING;
87 break;
88
89 default:
90 return -EINVAL;
91 }
92
93 gpio->irq_type[data->hwirq] = irq_type;
94
95 return 0;
96}
97
98static void max77620_gpio_bus_lock(struct irq_data *data)
99{
100 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
101 struct max77620_gpio *gpio = gpiochip_get_data(chip);
102
103 mutex_lock(&gpio->buslock);
104}
105
106static void max77620_gpio_bus_sync_unlock(struct irq_data *data)
107{
108 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
109 struct max77620_gpio *gpio = gpiochip_get_data(chip);
110 unsigned int value, offset = data->hwirq;
111 int err;
112
113 value = gpio->irq_enabled[offset] ? gpio->irq_type[offset] : 0;
114
115 err = regmap_update_bits(gpio->rmap, GPIO_REG_ADDR(offset),
116 MAX77620_CNFG_GPIO_INT_MASK, value);
117 if (err < 0)
118 dev_err(chip->parent, "failed to update interrupt mask: %d\n",
119 err);
120
121 mutex_unlock(&gpio->buslock);
122}
123
124static const struct irq_chip max77620_gpio_irqchip = {
125 .name = "max77620-gpio",
126 .irq_mask = max77620_gpio_irq_mask,
127 .irq_unmask = max77620_gpio_irq_unmask,
128 .irq_set_type = max77620_gpio_set_irq_type,
129 .irq_bus_lock = max77620_gpio_bus_lock,
130 .irq_bus_sync_unlock = max77620_gpio_bus_sync_unlock,
131 .flags = IRQCHIP_IMMUTABLE | IRQCHIP_MASK_ON_SUSPEND,
132 GPIOCHIP_IRQ_RESOURCE_HELPERS,
133};
134
135static int max77620_gpio_get_dir(struct gpio_chip *gc, unsigned int offset)
136{
137 struct max77620_gpio *mgpio = gpiochip_get_data(gc);
138 unsigned int val;
139 int ret;
140
141 ret = regmap_read(mgpio->rmap, GPIO_REG_ADDR(offset), &val);
142 if (ret < 0) {
143 dev_err(mgpio->dev, "CNFG_GPIOx read failed: %d\n", ret);
144 return ret;
145 }
146
147 if (val & MAX77620_CNFG_GPIO_DIR_MASK)
148 return GPIO_LINE_DIRECTION_IN;
149 else
150 return GPIO_LINE_DIRECTION_OUT;
151}
152
153static int max77620_gpio_dir_input(struct gpio_chip *gc, unsigned int offset)
154{
155 struct max77620_gpio *mgpio = gpiochip_get_data(gc);
156 int ret;
157
158 ret = regmap_update_bits(mgpio->rmap, GPIO_REG_ADDR(offset),
159 MAX77620_CNFG_GPIO_DIR_MASK,
160 MAX77620_CNFG_GPIO_DIR_INPUT);
161 if (ret < 0)
162 dev_err(mgpio->dev, "CNFG_GPIOx dir update failed: %d\n", ret);
163
164 return ret;
165}
166
167static int max77620_gpio_get(struct gpio_chip *gc, unsigned int offset)
168{
169 struct max77620_gpio *mgpio = gpiochip_get_data(gc);
170 unsigned int val;
171 int ret;
172
173 ret = regmap_read(mgpio->rmap, GPIO_REG_ADDR(offset), &val);
174 if (ret < 0) {
175 dev_err(mgpio->dev, "CNFG_GPIOx read failed: %d\n", ret);
176 return ret;
177 }
178
179 if (val & MAX77620_CNFG_GPIO_DIR_MASK)
180 return !!(val & MAX77620_CNFG_GPIO_INPUT_VAL_MASK);
181 else
182 return !!(val & MAX77620_CNFG_GPIO_OUTPUT_VAL_MASK);
183}
184
185static int max77620_gpio_dir_output(struct gpio_chip *gc, unsigned int offset,
186 int value)
187{
188 struct max77620_gpio *mgpio = gpiochip_get_data(gc);
189 u8 val;
190 int ret;
191
192 val = (value) ? MAX77620_CNFG_GPIO_OUTPUT_VAL_HIGH :
193 MAX77620_CNFG_GPIO_OUTPUT_VAL_LOW;
194
195 ret = regmap_update_bits(mgpio->rmap, GPIO_REG_ADDR(offset),
196 MAX77620_CNFG_GPIO_OUTPUT_VAL_MASK, val);
197 if (ret < 0) {
198 dev_err(mgpio->dev, "CNFG_GPIOx val update failed: %d\n", ret);
199 return ret;
200 }
201
202 ret = regmap_update_bits(mgpio->rmap, GPIO_REG_ADDR(offset),
203 MAX77620_CNFG_GPIO_DIR_MASK,
204 MAX77620_CNFG_GPIO_DIR_OUTPUT);
205 if (ret < 0)
206 dev_err(mgpio->dev, "CNFG_GPIOx dir update failed: %d\n", ret);
207
208 return ret;
209}
210
211static int max77620_gpio_set_debounce(struct max77620_gpio *mgpio,
212 unsigned int offset,
213 unsigned int debounce)
214{
215 u8 val;
216 int ret;
217
218 switch (debounce) {
219 case 0:
220 val = MAX77620_CNFG_GPIO_DBNC_None;
221 break;
222 case 1 ... 8000:
223 val = MAX77620_CNFG_GPIO_DBNC_8ms;
224 break;
225 case 8001 ... 16000:
226 val = MAX77620_CNFG_GPIO_DBNC_16ms;
227 break;
228 case 16001 ... 32000:
229 val = MAX77620_CNFG_GPIO_DBNC_32ms;
230 break;
231 default:
232 dev_err(mgpio->dev, "Illegal value %u\n", debounce);
233 return -EINVAL;
234 }
235
236 ret = regmap_update_bits(mgpio->rmap, GPIO_REG_ADDR(offset),
237 MAX77620_CNFG_GPIO_DBNC_MASK, val);
238 if (ret < 0)
239 dev_err(mgpio->dev, "CNFG_GPIOx_DBNC update failed: %d\n", ret);
240
241 return ret;
242}
243
244static int max77620_gpio_set(struct gpio_chip *gc, unsigned int offset,
245 int value)
246{
247 struct max77620_gpio *mgpio = gpiochip_get_data(gc);
248 u8 val;
249
250 val = (value) ? MAX77620_CNFG_GPIO_OUTPUT_VAL_HIGH :
251 MAX77620_CNFG_GPIO_OUTPUT_VAL_LOW;
252
253 return regmap_update_bits(mgpio->rmap, GPIO_REG_ADDR(offset),
254 MAX77620_CNFG_GPIO_OUTPUT_VAL_MASK, val);
255}
256
257static int max77620_gpio_set_config(struct gpio_chip *gc, unsigned int offset,
258 unsigned long config)
259{
260 struct max77620_gpio *mgpio = gpiochip_get_data(gc);
261
262 switch (pinconf_to_config_param(config)) {
263 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
264 return regmap_update_bits(mgpio->rmap, GPIO_REG_ADDR(offset),
265 MAX77620_CNFG_GPIO_DRV_MASK,
266 MAX77620_CNFG_GPIO_DRV_OPENDRAIN);
267 case PIN_CONFIG_DRIVE_PUSH_PULL:
268 return regmap_update_bits(mgpio->rmap, GPIO_REG_ADDR(offset),
269 MAX77620_CNFG_GPIO_DRV_MASK,
270 MAX77620_CNFG_GPIO_DRV_PUSHPULL);
271 case PIN_CONFIG_INPUT_DEBOUNCE:
272 return max77620_gpio_set_debounce(mgpio, offset,
273 pinconf_to_config_argument(config));
274 default:
275 break;
276 }
277
278 return -ENOTSUPP;
279}
280
281static int max77620_gpio_irq_init_hw(struct gpio_chip *gc)
282{
283 struct max77620_gpio *gpio = gpiochip_get_data(gc);
284 unsigned int i;
285 int err;
286
287 /*
288 * GPIO interrupts may be left ON after bootloader, hence let's
289 * pre-initialize hardware to the expected state by disabling all
290 * the interrupts.
291 */
292 for (i = 0; i < MAX77620_GPIO_NR; i++) {
293 err = regmap_update_bits(gpio->rmap, GPIO_REG_ADDR(i),
294 MAX77620_CNFG_GPIO_INT_MASK, 0);
295 if (err < 0) {
296 dev_err(gpio->dev,
297 "failed to disable interrupt: %d\n", err);
298 return err;
299 }
300 }
301
302 return 0;
303}
304
305static int max77620_gpio_probe(struct platform_device *pdev)
306{
307 struct max77620_chip *chip = dev_get_drvdata(pdev->dev.parent);
308 struct max77620_gpio *mgpio;
309 struct gpio_irq_chip *girq;
310 unsigned int gpio_irq;
311 int ret;
312
313 ret = platform_get_irq(pdev, 0);
314 if (ret < 0)
315 return ret;
316
317 gpio_irq = ret;
318
319 mgpio = devm_kzalloc(&pdev->dev, sizeof(*mgpio), GFP_KERNEL);
320 if (!mgpio)
321 return -ENOMEM;
322
323 mutex_init(&mgpio->buslock);
324 mgpio->rmap = chip->rmap;
325 mgpio->dev = &pdev->dev;
326
327 mgpio->gpio_chip.label = pdev->name;
328 mgpio->gpio_chip.parent = pdev->dev.parent;
329 mgpio->gpio_chip.get_direction = max77620_gpio_get_dir;
330 mgpio->gpio_chip.direction_input = max77620_gpio_dir_input;
331 mgpio->gpio_chip.get = max77620_gpio_get;
332 mgpio->gpio_chip.direction_output = max77620_gpio_dir_output;
333 mgpio->gpio_chip.set = max77620_gpio_set;
334 mgpio->gpio_chip.set_config = max77620_gpio_set_config;
335 mgpio->gpio_chip.ngpio = MAX77620_GPIO_NR;
336 mgpio->gpio_chip.can_sleep = 1;
337 mgpio->gpio_chip.base = -1;
338
339 girq = &mgpio->gpio_chip.irq;
340 gpio_irq_chip_set_chip(girq, &max77620_gpio_irqchip);
341 /* This will let us handle the parent IRQ in the driver */
342 girq->parent_handler = NULL;
343 girq->num_parents = 0;
344 girq->parents = NULL;
345 girq->default_type = IRQ_TYPE_NONE;
346 girq->handler = handle_edge_irq;
347 girq->init_hw = max77620_gpio_irq_init_hw;
348 girq->threaded = true;
349
350 ret = devm_gpiochip_add_data(&pdev->dev, &mgpio->gpio_chip, mgpio);
351 if (ret < 0) {
352 dev_err(&pdev->dev, "gpio_init: Failed to add max77620_gpio\n");
353 return ret;
354 }
355
356 ret = devm_request_threaded_irq(&pdev->dev, gpio_irq, NULL,
357 max77620_gpio_irqhandler, IRQF_ONESHOT,
358 "max77620-gpio", mgpio);
359 if (ret < 0) {
360 dev_err(&pdev->dev, "failed to request IRQ: %d\n", ret);
361 return ret;
362 }
363
364 return 0;
365}
366
367static const struct platform_device_id max77620_gpio_devtype[] = {
368 { .name = "max77620-gpio", },
369 { .name = "max20024-gpio", },
370 {},
371};
372MODULE_DEVICE_TABLE(platform, max77620_gpio_devtype);
373
374static struct platform_driver max77620_gpio_driver = {
375 .driver.name = "max77620-gpio",
376 .probe = max77620_gpio_probe,
377 .id_table = max77620_gpio_devtype,
378};
379
380module_platform_driver(max77620_gpio_driver);
381
382MODULE_DESCRIPTION("GPIO interface for MAX77620 and MAX20024 PMIC");
383MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
384MODULE_AUTHOR("Chaitanya Bandi <bandik@nvidia.com>");
385MODULE_LICENSE("GPL v2");