Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2016-2026 NVIDIA Corporation
4 *
5 * Author: Thierry Reding <treding@nvidia.com>
6 * Dipen Patel <dpatel@nvidia.com>
7 */
8
9#include <linux/gpio/driver.h>
10#include <linux/hte.h>
11#include <linux/interrupt.h>
12#include <linux/irq.h>
13#include <linux/module.h>
14#include <linux/of.h>
15#include <linux/platform_device.h>
16#include <linux/property.h>
17#include <linux/seq_file.h>
18
19#include <dt-bindings/gpio/tegra186-gpio.h>
20#include <dt-bindings/gpio/tegra194-gpio.h>
21#include <dt-bindings/gpio/tegra234-gpio.h>
22#include <dt-bindings/gpio/tegra241-gpio.h>
23#include <dt-bindings/gpio/tegra256-gpio.h>
24#include <dt-bindings/gpio/nvidia,tegra264-gpio.h>
25
26/* security registers */
27#define TEGRA186_GPIO_CTL_SCR 0x0c
28#define TEGRA186_GPIO_CTL_SCR_SEC_WEN BIT(28)
29#define TEGRA186_GPIO_CTL_SCR_SEC_REN BIT(27)
30
31#define TEGRA186_GPIO_INT_ROUTE_MAPPING(p, x) (0x14 + (p) * 0x20 + (x) * 4)
32
33#define TEGRA186_GPIO_VM 0x00
34#define TEGRA186_GPIO_VM_RW_MASK 0x03
35#define TEGRA186_GPIO_SCR 0x04
36#define TEGRA186_GPIO_SCR_PIN_SIZE 0x08
37#define TEGRA186_GPIO_SCR_PORT_SIZE 0x40
38#define TEGRA186_GPIO_SCR_SEC_WEN BIT(28)
39#define TEGRA186_GPIO_SCR_SEC_REN BIT(27)
40#define TEGRA186_GPIO_SCR_SEC_G1W BIT(9)
41#define TEGRA186_GPIO_SCR_SEC_G1R BIT(1)
42
43/* control registers */
44#define TEGRA186_GPIO_ENABLE_CONFIG 0x00
45#define TEGRA186_GPIO_ENABLE_CONFIG_ENABLE BIT(0)
46#define TEGRA186_GPIO_ENABLE_CONFIG_OUT BIT(1)
47#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_NONE (0x0 << 2)
48#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL (0x1 << 2)
49#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE (0x2 << 2)
50#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE (0x3 << 2)
51#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_MASK (0x3 << 2)
52#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL BIT(4)
53#define TEGRA186_GPIO_ENABLE_CONFIG_DEBOUNCE BIT(5)
54#define TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT BIT(6)
55#define TEGRA186_GPIO_ENABLE_CONFIG_TIMESTAMP_FUNC BIT(7)
56
57#define TEGRA186_GPIO_DEBOUNCE_CONTROL 0x04
58#define TEGRA186_GPIO_DEBOUNCE_CONTROL_THRESHOLD(x) ((x) & 0xff)
59
60#define TEGRA186_GPIO_INPUT 0x08
61#define TEGRA186_GPIO_INPUT_HIGH BIT(0)
62
63#define TEGRA186_GPIO_OUTPUT_CONTROL 0x0c
64#define TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED BIT(0)
65
66#define TEGRA186_GPIO_OUTPUT_VALUE 0x10
67#define TEGRA186_GPIO_OUTPUT_VALUE_HIGH BIT(0)
68
69#define TEGRA186_GPIO_INTERRUPT_CLEAR 0x14
70
71#define TEGRA186_GPIO_INTERRUPT_STATUS(x) (0x100 + (x) * 4)
72
73/* Tegra410 GPIOs implemented by the COMPUTE GPIO controller */
74#define TEGRA410_COMPUTE_GPIO_PORT_A 0
75#define TEGRA410_COMPUTE_GPIO_PORT_B 1
76#define TEGRA410_COMPUTE_GPIO_PORT_C 2
77#define TEGRA410_COMPUTE_GPIO_PORT_D 3
78#define TEGRA410_COMPUTE_GPIO_PORT_E 4
79
80/* Tegra410 GPIOs implemented by the SYSTEM GPIO controller */
81#define TEGRA410_SYSTEM_GPIO_PORT_A 0
82#define TEGRA410_SYSTEM_GPIO_PORT_B 1
83#define TEGRA410_SYSTEM_GPIO_PORT_C 2
84#define TEGRA410_SYSTEM_GPIO_PORT_D 3
85#define TEGRA410_SYSTEM_GPIO_PORT_E 4
86#define TEGRA410_SYSTEM_GPIO_PORT_I 5
87#define TEGRA410_SYSTEM_GPIO_PORT_J 6
88#define TEGRA410_SYSTEM_GPIO_PORT_K 7
89#define TEGRA410_SYSTEM_GPIO_PORT_L 8
90#define TEGRA410_SYSTEM_GPIO_PORT_M 9
91#define TEGRA410_SYSTEM_GPIO_PORT_N 10
92#define TEGRA410_SYSTEM_GPIO_PORT_P 11
93#define TEGRA410_SYSTEM_GPIO_PORT_Q 12
94#define TEGRA410_SYSTEM_GPIO_PORT_R 13
95#define TEGRA410_SYSTEM_GPIO_PORT_V 14
96
97struct tegra_gpio_port {
98 const char *name;
99 unsigned int bank;
100 unsigned int port;
101 unsigned int pins;
102};
103
104struct tegra186_pin_range {
105 unsigned int offset;
106 const char *group;
107};
108
109struct tegra_gpio_soc {
110 const struct tegra_gpio_port *ports;
111 unsigned int num_ports;
112 const char *name;
113 const char *prefix;
114 unsigned int instance;
115
116 unsigned int num_irqs_per_bank;
117
118 const struct tegra186_pin_range *pin_ranges;
119 unsigned int num_pin_ranges;
120 const char *pinmux;
121 bool has_gte;
122 bool has_vm_support;
123};
124
125struct tegra_gpio {
126 struct gpio_chip gpio;
127 unsigned int num_irq;
128
129 const struct tegra_gpio_soc *soc;
130 unsigned int num_irqs_per_bank;
131 unsigned int num_banks;
132
133 void __iomem *secure;
134 void __iomem *base;
135
136 unsigned int irq[] __counted_by(num_irq);
137};
138
139static const struct tegra_gpio_port *
140tegra186_gpio_get_port(struct tegra_gpio *gpio, unsigned int *pin)
141{
142 unsigned int start = 0, i;
143
144 for (i = 0; i < gpio->soc->num_ports; i++) {
145 const struct tegra_gpio_port *port = &gpio->soc->ports[i];
146
147 if (*pin >= start && *pin < start + port->pins) {
148 *pin -= start;
149 return port;
150 }
151
152 start += port->pins;
153 }
154
155 return NULL;
156}
157
158static void __iomem *tegra186_gpio_get_base(struct tegra_gpio *gpio,
159 unsigned int pin)
160{
161 const struct tegra_gpio_port *port;
162 unsigned int offset;
163
164 port = tegra186_gpio_get_port(gpio, &pin);
165 if (!port)
166 return NULL;
167
168 offset = port->bank * 0x1000 + port->port * 0x200;
169
170 return gpio->base + offset + pin * 0x20;
171}
172
173static void __iomem *tegra186_gpio_get_secure_base(struct tegra_gpio *gpio,
174 unsigned int pin)
175{
176 const struct tegra_gpio_port *port;
177 unsigned int offset;
178
179 port = tegra186_gpio_get_port(gpio, &pin);
180 if (!port)
181 return NULL;
182
183 offset = port->bank * 0x1000 + port->port * TEGRA186_GPIO_SCR_PORT_SIZE;
184
185 return gpio->secure + offset + pin * TEGRA186_GPIO_SCR_PIN_SIZE;
186}
187
188static inline bool tegra186_gpio_is_accessible(struct tegra_gpio *gpio, unsigned int pin)
189{
190 void __iomem *secure;
191 u32 value;
192
193 secure = tegra186_gpio_get_secure_base(gpio, pin);
194
195 if (gpio->soc->has_vm_support) {
196 value = readl(secure + TEGRA186_GPIO_VM);
197 if ((value & TEGRA186_GPIO_VM_RW_MASK) != TEGRA186_GPIO_VM_RW_MASK)
198 return false;
199 }
200
201 value = __raw_readl(secure + TEGRA186_GPIO_SCR);
202
203 /*
204 * When SCR_SEC_[R|W]EN is unset, then we have full read/write access to all the
205 * registers for given GPIO pin.
206 * When SCR_SEC[R|W]EN is set, then there is need to further check the accompanying
207 * SCR_SEC_G1[R|W] bit to determine read/write access to all the registers for given
208 * GPIO pin.
209 */
210
211 if (((value & TEGRA186_GPIO_SCR_SEC_REN) == 0 ||
212 ((value & TEGRA186_GPIO_SCR_SEC_REN) && (value & TEGRA186_GPIO_SCR_SEC_G1R))) &&
213 ((value & TEGRA186_GPIO_SCR_SEC_WEN) == 0 ||
214 ((value & TEGRA186_GPIO_SCR_SEC_WEN) && (value & TEGRA186_GPIO_SCR_SEC_G1W))))
215 return true;
216
217 return false;
218}
219
220static int tegra186_init_valid_mask(struct gpio_chip *chip,
221 unsigned long *valid_mask, unsigned int ngpios)
222{
223 struct tegra_gpio *gpio = gpiochip_get_data(chip);
224 unsigned int j;
225
226 for (j = 0; j < ngpios; j++) {
227 if (!tegra186_gpio_is_accessible(gpio, j))
228 clear_bit(j, valid_mask);
229 }
230 return 0;
231}
232
233static int tegra186_gpio_set(struct gpio_chip *chip, unsigned int offset,
234 int level)
235{
236 struct tegra_gpio *gpio = gpiochip_get_data(chip);
237 void __iomem *base;
238 u32 value;
239
240 base = tegra186_gpio_get_base(gpio, offset);
241 if (WARN_ON(base == NULL))
242 return -ENODEV;
243
244 value = readl(base + TEGRA186_GPIO_OUTPUT_VALUE);
245 if (level == 0)
246 value &= ~TEGRA186_GPIO_OUTPUT_VALUE_HIGH;
247 else
248 value |= TEGRA186_GPIO_OUTPUT_VALUE_HIGH;
249
250 writel(value, base + TEGRA186_GPIO_OUTPUT_VALUE);
251
252 return 0;
253}
254
255static int tegra186_gpio_get_direction(struct gpio_chip *chip,
256 unsigned int offset)
257{
258 struct tegra_gpio *gpio = gpiochip_get_data(chip);
259 void __iomem *base;
260 u32 value;
261
262 base = tegra186_gpio_get_base(gpio, offset);
263 if (WARN_ON(base == NULL))
264 return -ENODEV;
265
266 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
267 if (value & TEGRA186_GPIO_ENABLE_CONFIG_OUT)
268 return GPIO_LINE_DIRECTION_OUT;
269
270 return GPIO_LINE_DIRECTION_IN;
271}
272
273static int tegra186_gpio_direction_input(struct gpio_chip *chip,
274 unsigned int offset)
275{
276 struct tegra_gpio *gpio = gpiochip_get_data(chip);
277 void __iomem *base;
278 u32 value;
279
280 base = tegra186_gpio_get_base(gpio, offset);
281 if (WARN_ON(base == NULL))
282 return -ENODEV;
283
284 value = readl(base + TEGRA186_GPIO_OUTPUT_CONTROL);
285 value |= TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED;
286 writel(value, base + TEGRA186_GPIO_OUTPUT_CONTROL);
287
288 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
289 value |= TEGRA186_GPIO_ENABLE_CONFIG_ENABLE;
290 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_OUT;
291 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
292
293 return 0;
294}
295
296static int tegra186_gpio_direction_output(struct gpio_chip *chip,
297 unsigned int offset, int level)
298{
299 struct tegra_gpio *gpio = gpiochip_get_data(chip);
300 void __iomem *base;
301 u32 value;
302 int ret;
303
304 /* configure output level first */
305 ret = tegra186_gpio_set(chip, offset, level);
306 if (ret)
307 return ret;
308
309 base = tegra186_gpio_get_base(gpio, offset);
310 if (WARN_ON(base == NULL))
311 return -EINVAL;
312
313 /* set the direction */
314 value = readl(base + TEGRA186_GPIO_OUTPUT_CONTROL);
315 value &= ~TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED;
316 writel(value, base + TEGRA186_GPIO_OUTPUT_CONTROL);
317
318 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
319 value |= TEGRA186_GPIO_ENABLE_CONFIG_ENABLE;
320 value |= TEGRA186_GPIO_ENABLE_CONFIG_OUT;
321 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
322
323 return 0;
324}
325
326#define HTE_BOTH_EDGES (HTE_RISING_EDGE_TS | HTE_FALLING_EDGE_TS)
327
328static int tegra186_gpio_en_hw_ts(struct gpio_chip *gc, u32 offset,
329 unsigned long flags)
330{
331 struct tegra_gpio *gpio;
332 void __iomem *base;
333 int value;
334
335 if (!gc)
336 return -EINVAL;
337
338 gpio = gpiochip_get_data(gc);
339 if (!gpio)
340 return -ENODEV;
341
342 base = tegra186_gpio_get_base(gpio, offset);
343 if (WARN_ON(base == NULL))
344 return -EINVAL;
345
346 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
347 value |= TEGRA186_GPIO_ENABLE_CONFIG_TIMESTAMP_FUNC;
348
349 if (flags == HTE_BOTH_EDGES) {
350 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE;
351 } else if (flags == HTE_RISING_EDGE_TS) {
352 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE;
353 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL;
354 } else if (flags == HTE_FALLING_EDGE_TS) {
355 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE;
356 }
357
358 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
359
360 return 0;
361}
362
363static int tegra186_gpio_dis_hw_ts(struct gpio_chip *gc, u32 offset,
364 unsigned long flags)
365{
366 struct tegra_gpio *gpio;
367 void __iomem *base;
368 int value;
369
370 if (!gc)
371 return -EINVAL;
372
373 gpio = gpiochip_get_data(gc);
374 if (!gpio)
375 return -ENODEV;
376
377 base = tegra186_gpio_get_base(gpio, offset);
378 if (WARN_ON(base == NULL))
379 return -EINVAL;
380
381 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
382 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TIMESTAMP_FUNC;
383 if (flags == HTE_BOTH_EDGES) {
384 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE;
385 } else if (flags == HTE_RISING_EDGE_TS) {
386 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE;
387 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL;
388 } else if (flags == HTE_FALLING_EDGE_TS) {
389 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE;
390 }
391 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
392
393 return 0;
394}
395
396static int tegra186_gpio_get(struct gpio_chip *chip, unsigned int offset)
397{
398 struct tegra_gpio *gpio = gpiochip_get_data(chip);
399 void __iomem *base;
400 u32 value;
401
402 base = tegra186_gpio_get_base(gpio, offset);
403 if (WARN_ON(base == NULL))
404 return -ENODEV;
405
406 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
407 if (value & TEGRA186_GPIO_ENABLE_CONFIG_OUT)
408 value = readl(base + TEGRA186_GPIO_OUTPUT_VALUE);
409 else
410 value = readl(base + TEGRA186_GPIO_INPUT);
411
412 return value & BIT(0);
413}
414
415static int tegra186_gpio_set_config(struct gpio_chip *chip,
416 unsigned int offset,
417 unsigned long config)
418{
419 struct tegra_gpio *gpio = gpiochip_get_data(chip);
420 u32 debounce, value;
421 void __iomem *base;
422
423 base = tegra186_gpio_get_base(gpio, offset);
424 if (base == NULL)
425 return -ENXIO;
426
427 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
428 return -ENOTSUPP;
429
430 debounce = pinconf_to_config_argument(config);
431
432 /*
433 * The Tegra186 GPIO controller supports a maximum of 255 ms debounce
434 * time.
435 */
436 if (debounce > 255000)
437 return -EINVAL;
438
439 debounce = DIV_ROUND_UP(debounce, USEC_PER_MSEC);
440
441 value = TEGRA186_GPIO_DEBOUNCE_CONTROL_THRESHOLD(debounce);
442 writel(value, base + TEGRA186_GPIO_DEBOUNCE_CONTROL);
443
444 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
445 value |= TEGRA186_GPIO_ENABLE_CONFIG_DEBOUNCE;
446 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
447
448 return 0;
449}
450
451static int tegra186_gpio_add_pin_ranges(struct gpio_chip *chip)
452{
453 struct tegra_gpio *gpio = gpiochip_get_data(chip);
454 struct pinctrl_dev *pctldev;
455 struct device_node *np;
456 unsigned int i, j;
457 int err;
458
459 if (!gpio->soc->pinmux || gpio->soc->num_pin_ranges == 0)
460 return 0;
461
462 np = of_find_compatible_node(NULL, NULL, gpio->soc->pinmux);
463 if (!np)
464 return -ENODEV;
465
466 pctldev = of_pinctrl_get(np);
467 of_node_put(np);
468 if (!pctldev)
469 return -EPROBE_DEFER;
470
471 for (i = 0; i < gpio->soc->num_pin_ranges; i++) {
472 unsigned int pin = gpio->soc->pin_ranges[i].offset, port;
473 const char *group = gpio->soc->pin_ranges[i].group;
474
475 port = pin / 8;
476 pin = pin % 8;
477
478 if (port >= gpio->soc->num_ports) {
479 dev_warn(chip->parent, "invalid port %u for %s\n",
480 port, group);
481 continue;
482 }
483
484 for (j = 0; j < port; j++)
485 pin += gpio->soc->ports[j].pins;
486
487 err = gpiochip_add_pingroup_range(chip, pctldev, pin, group);
488 if (err < 0)
489 return err;
490 }
491
492 return 0;
493}
494
495static int tegra186_gpio_of_xlate(struct gpio_chip *chip,
496 const struct of_phandle_args *spec,
497 u32 *flags)
498{
499 struct tegra_gpio *gpio = gpiochip_get_data(chip);
500 unsigned int port, pin, i, offset = 0;
501
502 if (WARN_ON(chip->of_gpio_n_cells < 2))
503 return -EINVAL;
504
505 if (WARN_ON(spec->args_count < chip->of_gpio_n_cells))
506 return -EINVAL;
507
508 port = spec->args[0] / 8;
509 pin = spec->args[0] % 8;
510
511 if (port >= gpio->soc->num_ports) {
512 dev_err(chip->parent, "invalid port number: %u\n", port);
513 return -EINVAL;
514 }
515
516 for (i = 0; i < port; i++)
517 offset += gpio->soc->ports[i].pins;
518
519 if (flags)
520 *flags = spec->args[1];
521
522 return offset + pin;
523}
524
525#define to_tegra_gpio(x) container_of((x), struct tegra_gpio, gpio)
526
527static void tegra186_irq_ack(struct irq_data *data)
528{
529 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
530 struct tegra_gpio *gpio = to_tegra_gpio(gc);
531 void __iomem *base;
532
533 base = tegra186_gpio_get_base(gpio, data->hwirq);
534 if (WARN_ON(base == NULL))
535 return;
536
537 writel(1, base + TEGRA186_GPIO_INTERRUPT_CLEAR);
538}
539
540static void tegra186_irq_mask(struct irq_data *data)
541{
542 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
543 struct tegra_gpio *gpio = to_tegra_gpio(gc);
544 void __iomem *base;
545 u32 value;
546
547 base = tegra186_gpio_get_base(gpio, data->hwirq);
548 if (WARN_ON(base == NULL))
549 return;
550
551 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
552 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT;
553 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
554
555 gpiochip_disable_irq(&gpio->gpio, data->hwirq);
556}
557
558static void tegra186_irq_unmask(struct irq_data *data)
559{
560 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
561 struct tegra_gpio *gpio = to_tegra_gpio(gc);
562 void __iomem *base;
563 u32 value;
564
565 base = tegra186_gpio_get_base(gpio, data->hwirq);
566 if (WARN_ON(base == NULL))
567 return;
568
569 gpiochip_enable_irq(&gpio->gpio, data->hwirq);
570
571 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
572 value |= TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT;
573 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
574}
575
576static int tegra186_irq_set_type(struct irq_data *data, unsigned int type)
577{
578 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
579 struct tegra_gpio *gpio = to_tegra_gpio(gc);
580 void __iomem *base;
581 u32 value;
582
583 base = tegra186_gpio_get_base(gpio, data->hwirq);
584 if (WARN_ON(base == NULL))
585 return -ENODEV;
586
587 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
588 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_MASK;
589 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL;
590
591 switch (type & IRQ_TYPE_SENSE_MASK) {
592 case IRQ_TYPE_NONE:
593 break;
594
595 case IRQ_TYPE_EDGE_RISING:
596 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE;
597 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL;
598 break;
599
600 case IRQ_TYPE_EDGE_FALLING:
601 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE;
602 break;
603
604 case IRQ_TYPE_EDGE_BOTH:
605 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE;
606 break;
607
608 case IRQ_TYPE_LEVEL_HIGH:
609 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL;
610 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL;
611 break;
612
613 case IRQ_TYPE_LEVEL_LOW:
614 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL;
615 break;
616
617 default:
618 return -EINVAL;
619 }
620
621 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
622
623 if ((type & IRQ_TYPE_EDGE_BOTH) == 0)
624 irq_set_handler_locked(data, handle_level_irq);
625 else
626 irq_set_handler_locked(data, handle_edge_irq);
627
628 if (data->parent_data)
629 return irq_chip_set_type_parent(data, type);
630
631 return 0;
632}
633
634static int tegra186_irq_set_wake(struct irq_data *data, unsigned int on)
635{
636 if (data->parent_data)
637 return irq_chip_set_wake_parent(data, on);
638
639 return 0;
640}
641
642static void tegra186_irq_print_chip(struct irq_data *data, struct seq_file *p)
643{
644 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
645
646 seq_puts(p, dev_name(gc->parent));
647}
648
649static const struct irq_chip tegra186_gpio_irq_chip = {
650 .irq_ack = tegra186_irq_ack,
651 .irq_mask = tegra186_irq_mask,
652 .irq_unmask = tegra186_irq_unmask,
653 .irq_set_type = tegra186_irq_set_type,
654 .irq_set_wake = tegra186_irq_set_wake,
655 .irq_print_chip = tegra186_irq_print_chip,
656 .flags = IRQCHIP_IMMUTABLE,
657 GPIOCHIP_IRQ_RESOURCE_HELPERS,
658};
659
660static void tegra186_gpio_irq(struct irq_desc *desc)
661{
662 struct tegra_gpio *gpio = irq_desc_get_handler_data(desc);
663 struct irq_domain *domain = gpio->gpio.irq.domain;
664 struct irq_chip *chip = irq_desc_get_chip(desc);
665 unsigned int parent = irq_desc_get_irq(desc);
666 unsigned int i, j, offset = 0;
667
668 chained_irq_enter(chip, desc);
669
670 for (i = 0; i < gpio->soc->num_ports; i++) {
671 const struct tegra_gpio_port *port = &gpio->soc->ports[i];
672 unsigned int pin;
673 unsigned long value;
674 void __iomem *base;
675
676 base = gpio->base + port->bank * 0x1000 + port->port * 0x200;
677
678 /* skip ports that are not associated with this bank */
679 for (j = 0; j < gpio->num_irqs_per_bank; j++) {
680 if (parent == gpio->irq[port->bank * gpio->num_irqs_per_bank + j])
681 break;
682 }
683
684 if (j == gpio->num_irqs_per_bank)
685 goto skip;
686
687 value = readl(base + TEGRA186_GPIO_INTERRUPT_STATUS(1));
688
689 for_each_set_bit(pin, &value, port->pins) {
690 int ret = generic_handle_domain_irq(domain, offset + pin);
691 WARN_RATELIMIT(ret, "hwirq = %d", offset + pin);
692 }
693
694skip:
695 offset += port->pins;
696 }
697
698 chained_irq_exit(chip, desc);
699}
700
701static int tegra186_gpio_irq_domain_translate(struct irq_domain *domain,
702 struct irq_fwspec *fwspec,
703 unsigned long *hwirq,
704 unsigned int *type)
705{
706 struct tegra_gpio *gpio = gpiochip_get_data(domain->host_data);
707 unsigned int port, pin, i, offset = 0;
708
709 if (WARN_ON(gpio->gpio.of_gpio_n_cells < 2))
710 return -EINVAL;
711
712 if (WARN_ON(fwspec->param_count < gpio->gpio.of_gpio_n_cells))
713 return -EINVAL;
714
715 port = fwspec->param[0] / 8;
716 pin = fwspec->param[0] % 8;
717
718 if (port >= gpio->soc->num_ports)
719 return -EINVAL;
720
721 for (i = 0; i < port; i++)
722 offset += gpio->soc->ports[i].pins;
723
724 *type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK;
725 *hwirq = offset + pin;
726
727 return 0;
728}
729
730static int tegra186_gpio_populate_parent_fwspec(struct gpio_chip *chip,
731 union gpio_irq_fwspec *gfwspec,
732 unsigned int parent_hwirq,
733 unsigned int parent_type)
734{
735 struct tegra_gpio *gpio = gpiochip_get_data(chip);
736 struct irq_fwspec *fwspec = &gfwspec->fwspec;
737
738 fwspec->fwnode = chip->irq.parent_domain->fwnode;
739 fwspec->param_count = 3;
740 fwspec->param[0] = gpio->soc->instance;
741 fwspec->param[1] = parent_hwirq;
742 fwspec->param[2] = parent_type;
743
744 return 0;
745}
746
747static int tegra186_gpio_child_to_parent_hwirq(struct gpio_chip *chip,
748 unsigned int hwirq,
749 unsigned int type,
750 unsigned int *parent_hwirq,
751 unsigned int *parent_type)
752{
753 *parent_hwirq = chip->irq.child_offset_to_irq(chip, hwirq);
754 *parent_type = type;
755
756 return 0;
757}
758
759static unsigned int tegra186_gpio_child_offset_to_irq(struct gpio_chip *chip,
760 unsigned int offset)
761{
762 struct tegra_gpio *gpio = gpiochip_get_data(chip);
763 unsigned int i;
764
765 for (i = 0; i < gpio->soc->num_ports; i++) {
766 if (offset < gpio->soc->ports[i].pins)
767 break;
768
769 offset -= gpio->soc->ports[i].pins;
770 }
771
772 return offset + i * 8;
773}
774
775static const struct of_device_id tegra186_pmc_of_match[] = {
776 { .compatible = "nvidia,tegra186-pmc" },
777 { .compatible = "nvidia,tegra194-pmc" },
778 { .compatible = "nvidia,tegra234-pmc" },
779 { /* sentinel */ }
780};
781
782static void tegra186_gpio_init_route_mapping(struct tegra_gpio *gpio)
783{
784 struct device *dev = gpio->gpio.parent;
785 unsigned int i;
786 u32 value;
787
788 for (i = 0; i < gpio->soc->num_ports; i++) {
789 const struct tegra_gpio_port *port = &gpio->soc->ports[i];
790 unsigned int offset, p = port->port;
791 void __iomem *base;
792
793 base = gpio->secure + port->bank * 0x1000 + 0x800;
794
795 value = readl(base + TEGRA186_GPIO_CTL_SCR);
796
797 /*
798 * For controllers that haven't been locked down yet, make
799 * sure to program the default interrupt route mapping.
800 */
801 if ((value & TEGRA186_GPIO_CTL_SCR_SEC_REN) == 0 &&
802 (value & TEGRA186_GPIO_CTL_SCR_SEC_WEN) == 0) {
803 /*
804 * On Tegra194 and later, each pin can be routed to one or more
805 * interrupts.
806 */
807 dev_dbg(dev, "programming default interrupt routing for port %s\n",
808 port->name);
809
810 offset = TEGRA186_GPIO_INT_ROUTE_MAPPING(p, 0);
811
812 /*
813 * By default we only want to route GPIO pins to IRQ 0. This works
814 * only under the assumption that we're running as the host kernel
815 * and hence all GPIO pins are owned by Linux.
816 *
817 * For cases where Linux is the guest OS, the hypervisor will have
818 * to configure the interrupt routing and pass only the valid
819 * interrupts via device tree.
820 */
821 value = readl(base + offset);
822 value = BIT(port->pins) - 1;
823 writel(value, base + offset);
824 }
825 }
826}
827
828static unsigned int tegra186_gpio_irqs_per_bank(struct tegra_gpio *gpio)
829{
830 struct device *dev = gpio->gpio.parent;
831
832 if (gpio->num_irq > gpio->num_banks) {
833 if (gpio->num_irq % gpio->num_banks != 0)
834 goto error;
835 }
836
837 if (gpio->num_irq < gpio->num_banks)
838 goto error;
839
840 gpio->num_irqs_per_bank = gpio->num_irq / gpio->num_banks;
841
842 if (gpio->num_irqs_per_bank > gpio->soc->num_irqs_per_bank)
843 goto error;
844
845 return 0;
846
847error:
848 dev_err(dev, "invalid number of interrupts (%u) for %u banks\n",
849 gpio->num_irq, gpio->num_banks);
850 return -EINVAL;
851}
852
853static int tegra186_gpio_probe(struct platform_device *pdev)
854{
855 unsigned int i, j, offset;
856 struct gpio_irq_chip *irq;
857 struct tegra_gpio *gpio;
858 struct device_node *np;
859 struct resource *res;
860 char **names;
861 int node, err;
862
863 err = platform_irq_count(pdev);
864 if (err < 0)
865 return err;
866
867 gpio = devm_kzalloc(&pdev->dev, struct_size(gpio, irq, err), GFP_KERNEL);
868 if (!gpio)
869 return -ENOMEM;
870
871 gpio->num_irq = err;
872
873 gpio->soc = device_get_match_data(&pdev->dev);
874 gpio->gpio.label = gpio->soc->name;
875 gpio->gpio.parent = &pdev->dev;
876
877 /* count the number of banks in the controller */
878 for (i = 0; i < gpio->soc->num_ports; i++)
879 if (gpio->soc->ports[i].bank > gpio->num_banks)
880 gpio->num_banks = gpio->soc->ports[i].bank;
881
882 gpio->num_banks++;
883
884 /* get register apertures */
885 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "security");
886 if (!res)
887 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
888 gpio->secure = devm_ioremap_resource(&pdev->dev, res);
889 if (IS_ERR(gpio->secure))
890 return PTR_ERR(gpio->secure);
891
892 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "gpio");
893 if (!res)
894 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
895 gpio->base = devm_ioremap_resource(&pdev->dev, res);
896 if (IS_ERR(gpio->base))
897 return PTR_ERR(gpio->base);
898
899 err = tegra186_gpio_irqs_per_bank(gpio);
900 if (err < 0)
901 return err;
902
903 for (i = 0; i < gpio->num_irq; i++) {
904 err = platform_get_irq(pdev, i);
905 if (err < 0)
906 return err;
907
908 gpio->irq[i] = err;
909 }
910
911 gpio->gpio.request = gpiochip_generic_request;
912 gpio->gpio.free = gpiochip_generic_free;
913 gpio->gpio.get_direction = tegra186_gpio_get_direction;
914 gpio->gpio.direction_input = tegra186_gpio_direction_input;
915 gpio->gpio.direction_output = tegra186_gpio_direction_output;
916 gpio->gpio.get = tegra186_gpio_get;
917 gpio->gpio.set = tegra186_gpio_set;
918 gpio->gpio.set_config = tegra186_gpio_set_config;
919 gpio->gpio.add_pin_ranges = tegra186_gpio_add_pin_ranges;
920 gpio->gpio.init_valid_mask = tegra186_init_valid_mask;
921 if (gpio->soc->has_gte) {
922 gpio->gpio.en_hw_timestamp = tegra186_gpio_en_hw_ts;
923 gpio->gpio.dis_hw_timestamp = tegra186_gpio_dis_hw_ts;
924 }
925
926 gpio->gpio.base = -1;
927
928 for (i = 0; i < gpio->soc->num_ports; i++)
929 gpio->gpio.ngpio += gpio->soc->ports[i].pins;
930
931 names = devm_kcalloc(gpio->gpio.parent, gpio->gpio.ngpio,
932 sizeof(*names), GFP_KERNEL);
933 if (!names)
934 return -ENOMEM;
935
936 node = dev_to_node(&pdev->dev);
937
938 for (i = 0, offset = 0; i < gpio->soc->num_ports; i++) {
939 const struct tegra_gpio_port *port = &gpio->soc->ports[i];
940 char *name;
941
942 for (j = 0; j < port->pins; j++) {
943 if (node >= 0)
944 name = devm_kasprintf(gpio->gpio.parent, GFP_KERNEL,
945 "%d-%sP%s.%02x", node,
946 gpio->soc->prefix ?: "",
947 port->name, j);
948 else
949 name = devm_kasprintf(gpio->gpio.parent, GFP_KERNEL,
950 "%sP%s.%02x",
951 gpio->soc->prefix ?: "",
952 port->name, j);
953 if (!name)
954 return -ENOMEM;
955
956 names[offset + j] = name;
957 }
958
959 offset += port->pins;
960 }
961
962 gpio->gpio.names = (const char * const *)names;
963
964#if defined(CONFIG_OF_GPIO)
965 gpio->gpio.of_gpio_n_cells = 2;
966 gpio->gpio.of_xlate = tegra186_gpio_of_xlate;
967#endif /* CONFIG_OF_GPIO */
968
969 irq = &gpio->gpio.irq;
970 gpio_irq_chip_set_chip(irq, &tegra186_gpio_irq_chip);
971 irq->fwnode = dev_fwnode(&pdev->dev);
972 irq->child_to_parent_hwirq = tegra186_gpio_child_to_parent_hwirq;
973 irq->populate_parent_alloc_arg = tegra186_gpio_populate_parent_fwspec;
974 irq->child_offset_to_irq = tegra186_gpio_child_offset_to_irq;
975 irq->child_irq_domain_ops.translate = tegra186_gpio_irq_domain_translate;
976 irq->handler = handle_simple_irq;
977 irq->default_type = IRQ_TYPE_NONE;
978 irq->parent_handler = tegra186_gpio_irq;
979 irq->parent_handler_data = gpio;
980 irq->num_parents = gpio->num_irq;
981
982 /*
983 * To simplify things, use a single interrupt per bank for now. Some
984 * chips support up to 8 interrupts per bank, which can be useful to
985 * distribute the load and decrease the processing latency for GPIOs
986 * but it also requires a more complicated interrupt routing than we
987 * currently program.
988 */
989 if (gpio->num_irqs_per_bank > 1) {
990 irq->parents = devm_kcalloc(&pdev->dev, gpio->num_banks,
991 sizeof(*irq->parents), GFP_KERNEL);
992 if (!irq->parents)
993 return -ENOMEM;
994
995 for (i = 0; i < gpio->num_banks; i++)
996 irq->parents[i] = gpio->irq[i * gpio->num_irqs_per_bank];
997
998 irq->num_parents = gpio->num_banks;
999 } else {
1000 irq->num_parents = gpio->num_irq;
1001 irq->parents = gpio->irq;
1002 }
1003
1004 if (gpio->soc->num_irqs_per_bank > 1)
1005 tegra186_gpio_init_route_mapping(gpio);
1006
1007 np = of_parse_phandle(pdev->dev.of_node, "wakeup-parent", 0);
1008 if (!np)
1009 np = of_find_matching_node(NULL, tegra186_pmc_of_match);
1010 if (np) {
1011 if (of_device_is_available(np)) {
1012 irq->parent_domain = irq_find_host(np);
1013 of_node_put(np);
1014
1015 if (!irq->parent_domain)
1016 return -EPROBE_DEFER;
1017 } else {
1018 of_node_put(np);
1019 }
1020 }
1021
1022 irq->map = devm_kcalloc(&pdev->dev, gpio->gpio.ngpio,
1023 sizeof(*irq->map), GFP_KERNEL);
1024 if (!irq->map)
1025 return -ENOMEM;
1026
1027 for (i = 0, offset = 0; i < gpio->soc->num_ports; i++) {
1028 const struct tegra_gpio_port *port = &gpio->soc->ports[i];
1029
1030 for (j = 0; j < port->pins; j++)
1031 irq->map[offset + j] = irq->parents[port->bank];
1032
1033 offset += port->pins;
1034 }
1035
1036 return devm_gpiochip_add_data(&pdev->dev, &gpio->gpio, gpio);
1037}
1038
1039#define TEGRA_GPIO_PORT(_prefix, _name, _bank, _port, _pins) \
1040 [_prefix##_GPIO_PORT_##_name] = { \
1041 .name = #_name, \
1042 .bank = _bank, \
1043 .port = _port, \
1044 .pins = _pins, \
1045 }
1046
1047#define TEGRA186_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \
1048 TEGRA_GPIO_PORT(TEGRA186_MAIN, _name, _bank, _port, _pins)
1049
1050static const struct tegra_gpio_port tegra186_main_ports[] = {
1051 TEGRA186_MAIN_GPIO_PORT( A, 2, 0, 7),
1052 TEGRA186_MAIN_GPIO_PORT( B, 3, 0, 7),
1053 TEGRA186_MAIN_GPIO_PORT( C, 3, 1, 7),
1054 TEGRA186_MAIN_GPIO_PORT( D, 3, 2, 6),
1055 TEGRA186_MAIN_GPIO_PORT( E, 2, 1, 8),
1056 TEGRA186_MAIN_GPIO_PORT( F, 2, 2, 6),
1057 TEGRA186_MAIN_GPIO_PORT( G, 4, 1, 6),
1058 TEGRA186_MAIN_GPIO_PORT( H, 1, 0, 7),
1059 TEGRA186_MAIN_GPIO_PORT( I, 0, 4, 8),
1060 TEGRA186_MAIN_GPIO_PORT( J, 5, 0, 8),
1061 TEGRA186_MAIN_GPIO_PORT( K, 5, 1, 1),
1062 TEGRA186_MAIN_GPIO_PORT( L, 1, 1, 8),
1063 TEGRA186_MAIN_GPIO_PORT( M, 5, 3, 6),
1064 TEGRA186_MAIN_GPIO_PORT( N, 0, 0, 7),
1065 TEGRA186_MAIN_GPIO_PORT( O, 0, 1, 4),
1066 TEGRA186_MAIN_GPIO_PORT( P, 4, 0, 7),
1067 TEGRA186_MAIN_GPIO_PORT( Q, 0, 2, 6),
1068 TEGRA186_MAIN_GPIO_PORT( R, 0, 5, 6),
1069 TEGRA186_MAIN_GPIO_PORT( T, 0, 3, 4),
1070 TEGRA186_MAIN_GPIO_PORT( X, 1, 2, 8),
1071 TEGRA186_MAIN_GPIO_PORT( Y, 1, 3, 7),
1072 TEGRA186_MAIN_GPIO_PORT(BB, 2, 3, 2),
1073 TEGRA186_MAIN_GPIO_PORT(CC, 5, 2, 4),
1074};
1075
1076static const struct tegra_gpio_soc tegra186_main_soc = {
1077 .num_ports = ARRAY_SIZE(tegra186_main_ports),
1078 .ports = tegra186_main_ports,
1079 .name = "tegra186-gpio",
1080 .instance = 0,
1081 .num_irqs_per_bank = 1,
1082 .has_vm_support = false,
1083};
1084
1085#define TEGRA186_AON_GPIO_PORT(_name, _bank, _port, _pins) \
1086 TEGRA_GPIO_PORT(TEGRA186_AON, _name, _bank, _port, _pins)
1087
1088static const struct tegra_gpio_port tegra186_aon_ports[] = {
1089 TEGRA186_AON_GPIO_PORT( S, 0, 1, 5),
1090 TEGRA186_AON_GPIO_PORT( U, 0, 2, 6),
1091 TEGRA186_AON_GPIO_PORT( V, 0, 4, 8),
1092 TEGRA186_AON_GPIO_PORT( W, 0, 5, 8),
1093 TEGRA186_AON_GPIO_PORT( Z, 0, 7, 4),
1094 TEGRA186_AON_GPIO_PORT(AA, 0, 6, 8),
1095 TEGRA186_AON_GPIO_PORT(EE, 0, 3, 3),
1096 TEGRA186_AON_GPIO_PORT(FF, 0, 0, 5),
1097};
1098
1099static const struct tegra_gpio_soc tegra186_aon_soc = {
1100 .num_ports = ARRAY_SIZE(tegra186_aon_ports),
1101 .ports = tegra186_aon_ports,
1102 .name = "tegra186-gpio-aon",
1103 .instance = 1,
1104 .num_irqs_per_bank = 1,
1105 .has_vm_support = false,
1106};
1107
1108#define TEGRA194_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \
1109 TEGRA_GPIO_PORT(TEGRA194_MAIN, _name, _bank, _port, _pins)
1110
1111static const struct tegra_gpio_port tegra194_main_ports[] = {
1112 TEGRA194_MAIN_GPIO_PORT( A, 1, 2, 8),
1113 TEGRA194_MAIN_GPIO_PORT( B, 4, 7, 2),
1114 TEGRA194_MAIN_GPIO_PORT( C, 4, 3, 8),
1115 TEGRA194_MAIN_GPIO_PORT( D, 4, 4, 4),
1116 TEGRA194_MAIN_GPIO_PORT( E, 4, 5, 8),
1117 TEGRA194_MAIN_GPIO_PORT( F, 4, 6, 6),
1118 TEGRA194_MAIN_GPIO_PORT( G, 4, 0, 8),
1119 TEGRA194_MAIN_GPIO_PORT( H, 4, 1, 8),
1120 TEGRA194_MAIN_GPIO_PORT( I, 4, 2, 5),
1121 TEGRA194_MAIN_GPIO_PORT( J, 5, 1, 6),
1122 TEGRA194_MAIN_GPIO_PORT( K, 3, 0, 8),
1123 TEGRA194_MAIN_GPIO_PORT( L, 3, 1, 4),
1124 TEGRA194_MAIN_GPIO_PORT( M, 2, 3, 8),
1125 TEGRA194_MAIN_GPIO_PORT( N, 2, 4, 3),
1126 TEGRA194_MAIN_GPIO_PORT( O, 5, 0, 6),
1127 TEGRA194_MAIN_GPIO_PORT( P, 2, 5, 8),
1128 TEGRA194_MAIN_GPIO_PORT( Q, 2, 6, 8),
1129 TEGRA194_MAIN_GPIO_PORT( R, 2, 7, 6),
1130 TEGRA194_MAIN_GPIO_PORT( S, 3, 3, 8),
1131 TEGRA194_MAIN_GPIO_PORT( T, 3, 4, 8),
1132 TEGRA194_MAIN_GPIO_PORT( U, 3, 5, 1),
1133 TEGRA194_MAIN_GPIO_PORT( V, 1, 0, 8),
1134 TEGRA194_MAIN_GPIO_PORT( W, 1, 1, 2),
1135 TEGRA194_MAIN_GPIO_PORT( X, 2, 0, 8),
1136 TEGRA194_MAIN_GPIO_PORT( Y, 2, 1, 8),
1137 TEGRA194_MAIN_GPIO_PORT( Z, 2, 2, 8),
1138 TEGRA194_MAIN_GPIO_PORT(FF, 3, 2, 2),
1139 TEGRA194_MAIN_GPIO_PORT(GG, 0, 0, 2)
1140};
1141
1142static const struct tegra186_pin_range tegra194_main_pin_ranges[] = {
1143 { TEGRA194_MAIN_GPIO(GG, 0), "pex_l5_clkreq_n_pgg0" },
1144 { TEGRA194_MAIN_GPIO(GG, 1), "pex_l5_rst_n_pgg1" },
1145};
1146
1147static const struct tegra_gpio_soc tegra194_main_soc = {
1148 .num_ports = ARRAY_SIZE(tegra194_main_ports),
1149 .ports = tegra194_main_ports,
1150 .name = "tegra194-gpio",
1151 .instance = 0,
1152 .num_irqs_per_bank = 8,
1153 .num_pin_ranges = ARRAY_SIZE(tegra194_main_pin_ranges),
1154 .pin_ranges = tegra194_main_pin_ranges,
1155 .pinmux = "nvidia,tegra194-pinmux",
1156 .has_vm_support = true,
1157};
1158
1159#define TEGRA194_AON_GPIO_PORT(_name, _bank, _port, _pins) \
1160 TEGRA_GPIO_PORT(TEGRA194_AON, _name, _bank, _port, _pins)
1161
1162static const struct tegra_gpio_port tegra194_aon_ports[] = {
1163 TEGRA194_AON_GPIO_PORT(AA, 0, 3, 8),
1164 TEGRA194_AON_GPIO_PORT(BB, 0, 4, 4),
1165 TEGRA194_AON_GPIO_PORT(CC, 0, 1, 8),
1166 TEGRA194_AON_GPIO_PORT(DD, 0, 2, 3),
1167 TEGRA194_AON_GPIO_PORT(EE, 0, 0, 7)
1168};
1169
1170static const struct tegra_gpio_soc tegra194_aon_soc = {
1171 .num_ports = ARRAY_SIZE(tegra194_aon_ports),
1172 .ports = tegra194_aon_ports,
1173 .name = "tegra194-gpio-aon",
1174 .instance = 1,
1175 .num_irqs_per_bank = 8,
1176 .has_gte = true,
1177 .has_vm_support = false,
1178};
1179
1180#define TEGRA234_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \
1181 TEGRA_GPIO_PORT(TEGRA234_MAIN, _name, _bank, _port, _pins)
1182
1183static const struct tegra_gpio_port tegra234_main_ports[] = {
1184 TEGRA234_MAIN_GPIO_PORT( A, 0, 0, 8),
1185 TEGRA234_MAIN_GPIO_PORT( B, 0, 3, 1),
1186 TEGRA234_MAIN_GPIO_PORT( C, 5, 1, 8),
1187 TEGRA234_MAIN_GPIO_PORT( D, 5, 2, 4),
1188 TEGRA234_MAIN_GPIO_PORT( E, 5, 3, 8),
1189 TEGRA234_MAIN_GPIO_PORT( F, 5, 4, 6),
1190 TEGRA234_MAIN_GPIO_PORT( G, 4, 0, 8),
1191 TEGRA234_MAIN_GPIO_PORT( H, 4, 1, 8),
1192 TEGRA234_MAIN_GPIO_PORT( I, 4, 2, 7),
1193 TEGRA234_MAIN_GPIO_PORT( J, 5, 0, 6),
1194 TEGRA234_MAIN_GPIO_PORT( K, 3, 0, 8),
1195 TEGRA234_MAIN_GPIO_PORT( L, 3, 1, 4),
1196 TEGRA234_MAIN_GPIO_PORT( M, 2, 0, 8),
1197 TEGRA234_MAIN_GPIO_PORT( N, 2, 1, 8),
1198 TEGRA234_MAIN_GPIO_PORT( P, 2, 2, 8),
1199 TEGRA234_MAIN_GPIO_PORT( Q, 2, 3, 8),
1200 TEGRA234_MAIN_GPIO_PORT( R, 2, 4, 6),
1201 TEGRA234_MAIN_GPIO_PORT( X, 1, 0, 8),
1202 TEGRA234_MAIN_GPIO_PORT( Y, 1, 1, 8),
1203 TEGRA234_MAIN_GPIO_PORT( Z, 1, 2, 8),
1204 TEGRA234_MAIN_GPIO_PORT(AC, 0, 1, 8),
1205 TEGRA234_MAIN_GPIO_PORT(AD, 0, 2, 4),
1206 TEGRA234_MAIN_GPIO_PORT(AE, 3, 3, 2),
1207 TEGRA234_MAIN_GPIO_PORT(AF, 3, 4, 4),
1208 TEGRA234_MAIN_GPIO_PORT(AG, 3, 2, 8),
1209};
1210
1211static const struct tegra_gpio_soc tegra234_main_soc = {
1212 .num_ports = ARRAY_SIZE(tegra234_main_ports),
1213 .ports = tegra234_main_ports,
1214 .name = "tegra234-gpio",
1215 .instance = 0,
1216 .num_irqs_per_bank = 8,
1217 .has_vm_support = true,
1218};
1219
1220#define TEGRA234_AON_GPIO_PORT(_name, _bank, _port, _pins) \
1221 TEGRA_GPIO_PORT(TEGRA234_AON, _name, _bank, _port, _pins)
1222
1223static const struct tegra_gpio_port tegra234_aon_ports[] = {
1224 TEGRA234_AON_GPIO_PORT(AA, 0, 4, 8),
1225 TEGRA234_AON_GPIO_PORT(BB, 0, 5, 4),
1226 TEGRA234_AON_GPIO_PORT(CC, 0, 2, 8),
1227 TEGRA234_AON_GPIO_PORT(DD, 0, 3, 3),
1228 TEGRA234_AON_GPIO_PORT(EE, 0, 0, 8),
1229 TEGRA234_AON_GPIO_PORT(GG, 0, 1, 1),
1230};
1231
1232static const struct tegra_gpio_soc tegra234_aon_soc = {
1233 .num_ports = ARRAY_SIZE(tegra234_aon_ports),
1234 .ports = tegra234_aon_ports,
1235 .name = "tegra234-gpio-aon",
1236 .instance = 1,
1237 .num_irqs_per_bank = 8,
1238 .has_gte = true,
1239 .has_vm_support = false,
1240};
1241
1242#define TEGRA241_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \
1243 TEGRA_GPIO_PORT(TEGRA241_MAIN, _name, _bank, _port, _pins)
1244
1245static const struct tegra_gpio_port tegra241_main_ports[] = {
1246 TEGRA241_MAIN_GPIO_PORT(A, 0, 0, 8),
1247 TEGRA241_MAIN_GPIO_PORT(B, 0, 1, 8),
1248 TEGRA241_MAIN_GPIO_PORT(C, 0, 2, 2),
1249 TEGRA241_MAIN_GPIO_PORT(D, 0, 3, 6),
1250 TEGRA241_MAIN_GPIO_PORT(E, 0, 4, 8),
1251 TEGRA241_MAIN_GPIO_PORT(F, 1, 0, 8),
1252 TEGRA241_MAIN_GPIO_PORT(G, 1, 1, 8),
1253 TEGRA241_MAIN_GPIO_PORT(H, 1, 2, 8),
1254 TEGRA241_MAIN_GPIO_PORT(J, 1, 3, 8),
1255 TEGRA241_MAIN_GPIO_PORT(K, 1, 4, 4),
1256 TEGRA241_MAIN_GPIO_PORT(L, 1, 5, 6),
1257};
1258
1259static const struct tegra_gpio_soc tegra241_main_soc = {
1260 .num_ports = ARRAY_SIZE(tegra241_main_ports),
1261 .ports = tegra241_main_ports,
1262 .name = "tegra241-gpio",
1263 .instance = 0,
1264 .num_irqs_per_bank = 8,
1265 .has_vm_support = false,
1266};
1267
1268#define TEGRA241_AON_GPIO_PORT(_name, _bank, _port, _pins) \
1269 TEGRA_GPIO_PORT(TEGRA241_AON, _name, _bank, _port, _pins)
1270
1271static const struct tegra_gpio_port tegra241_aon_ports[] = {
1272 TEGRA241_AON_GPIO_PORT(AA, 0, 0, 8),
1273 TEGRA241_AON_GPIO_PORT(BB, 0, 0, 4),
1274};
1275
1276static const struct tegra_gpio_soc tegra241_aon_soc = {
1277 .num_ports = ARRAY_SIZE(tegra241_aon_ports),
1278 .ports = tegra241_aon_ports,
1279 .name = "tegra241-gpio-aon",
1280 .instance = 1,
1281 .num_irqs_per_bank = 8,
1282 .has_vm_support = false,
1283};
1284
1285#define TEGRA264_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \
1286 TEGRA_GPIO_PORT(TEGRA264_MAIN, _name, _bank, _port, _pins)
1287
1288static const struct tegra_gpio_port tegra264_main_ports[] = {
1289 TEGRA264_MAIN_GPIO_PORT(F, 3, 0, 8),
1290 TEGRA264_MAIN_GPIO_PORT(G, 3, 1, 5),
1291 TEGRA264_MAIN_GPIO_PORT(H, 1, 0, 8),
1292 TEGRA264_MAIN_GPIO_PORT(J, 1, 1, 8),
1293 TEGRA264_MAIN_GPIO_PORT(K, 1, 2, 8),
1294 TEGRA264_MAIN_GPIO_PORT(L, 1, 3, 8),
1295 TEGRA264_MAIN_GPIO_PORT(M, 1, 4, 6),
1296 TEGRA264_MAIN_GPIO_PORT(P, 2, 0, 8),
1297 TEGRA264_MAIN_GPIO_PORT(Q, 2, 1, 8),
1298 TEGRA264_MAIN_GPIO_PORT(R, 2, 2, 8),
1299 TEGRA264_MAIN_GPIO_PORT(S, 2, 3, 2),
1300 TEGRA264_MAIN_GPIO_PORT(T, 0, 0, 7),
1301 TEGRA264_MAIN_GPIO_PORT(U, 0, 1, 8),
1302 TEGRA264_MAIN_GPIO_PORT(V, 0, 2, 8),
1303 TEGRA264_MAIN_GPIO_PORT(W, 0, 3, 8),
1304 TEGRA264_MAIN_GPIO_PORT(X, 0, 7, 6),
1305 TEGRA264_MAIN_GPIO_PORT(Y, 0, 5, 8),
1306 TEGRA264_MAIN_GPIO_PORT(Z, 0, 6, 8),
1307 TEGRA264_MAIN_GPIO_PORT(AL, 0, 4, 3),
1308};
1309
1310static const struct tegra_gpio_soc tegra264_main_soc = {
1311 .num_ports = ARRAY_SIZE(tegra264_main_ports),
1312 .ports = tegra264_main_ports,
1313 .name = "tegra264-gpio",
1314 .instance = 0,
1315 .num_irqs_per_bank = 8,
1316 .has_vm_support = true,
1317};
1318
1319#define TEGRA264_AON_GPIO_PORT(_name, _bank, _port, _pins) \
1320 TEGRA_GPIO_PORT(TEGRA264_AON, _name, _bank, _port, _pins)
1321
1322static const struct tegra_gpio_port tegra264_aon_ports[] = {
1323 TEGRA264_AON_GPIO_PORT(AA, 0, 0, 8),
1324 TEGRA264_AON_GPIO_PORT(BB, 0, 1, 2),
1325 TEGRA264_AON_GPIO_PORT(CC, 0, 2, 8),
1326 TEGRA264_AON_GPIO_PORT(DD, 0, 3, 8),
1327 TEGRA264_AON_GPIO_PORT(EE, 0, 4, 4)
1328};
1329
1330static const struct tegra_gpio_soc tegra264_aon_soc = {
1331 .num_ports = ARRAY_SIZE(tegra264_aon_ports),
1332 .ports = tegra264_aon_ports,
1333 .name = "tegra264-gpio-aon",
1334 .instance = 1,
1335 .num_irqs_per_bank = 8,
1336 .has_vm_support = true,
1337};
1338
1339#define TEGRA264_UPHY_GPIO_PORT(_name, _bank, _port, _pins) \
1340 TEGRA_GPIO_PORT(TEGRA264_UPHY, _name, _bank, _port, _pins)
1341
1342static const struct tegra_gpio_port tegra264_uphy_ports[] = {
1343 TEGRA264_UPHY_GPIO_PORT(A, 0, 0, 6),
1344 TEGRA264_UPHY_GPIO_PORT(B, 0, 1, 8),
1345 TEGRA264_UPHY_GPIO_PORT(C, 0, 2, 3),
1346 TEGRA264_UPHY_GPIO_PORT(D, 1, 0, 8),
1347 TEGRA264_UPHY_GPIO_PORT(E, 1, 1, 4),
1348};
1349
1350static const struct tegra_gpio_soc tegra264_uphy_soc = {
1351 .num_ports = ARRAY_SIZE(tegra264_uphy_ports),
1352 .ports = tegra264_uphy_ports,
1353 .name = "tegra264-gpio-uphy",
1354 .instance = 2,
1355 .num_irqs_per_bank = 8,
1356 .has_vm_support = true,
1357};
1358
1359#define TEGRA256_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \
1360 TEGRA_GPIO_PORT(TEGRA256_MAIN, _name, _bank, _port, _pins)
1361
1362static const struct tegra_gpio_port tegra256_main_ports[] = {
1363 TEGRA256_MAIN_GPIO_PORT(A, 0, 0, 8),
1364 TEGRA256_MAIN_GPIO_PORT(B, 0, 1, 8),
1365 TEGRA256_MAIN_GPIO_PORT(C, 0, 2, 8),
1366 TEGRA256_MAIN_GPIO_PORT(D, 0, 3, 8),
1367};
1368
1369static const struct tegra_gpio_soc tegra256_main_soc = {
1370 .num_ports = ARRAY_SIZE(tegra256_main_ports),
1371 .ports = tegra256_main_ports,
1372 .name = "tegra256-gpio-main",
1373 .instance = 1,
1374 .num_irqs_per_bank = 8,
1375 .has_vm_support = true,
1376};
1377
1378/* Macro to define GPIO name prefix with separator */
1379#define TEGRA_GPIO_PREFIX(_x) _x "-"
1380
1381#define TEGRA410_COMPUTE_GPIO_PORT(_name, _bank, _port, _pins) \
1382 TEGRA_GPIO_PORT(TEGRA410_COMPUTE, _name, _bank, _port, _pins)
1383
1384static const struct tegra_gpio_port tegra410_compute_ports[] = {
1385 TEGRA410_COMPUTE_GPIO_PORT(A, 0, 0, 3),
1386 TEGRA410_COMPUTE_GPIO_PORT(B, 1, 0, 8),
1387 TEGRA410_COMPUTE_GPIO_PORT(C, 1, 1, 3),
1388 TEGRA410_COMPUTE_GPIO_PORT(D, 2, 0, 8),
1389 TEGRA410_COMPUTE_GPIO_PORT(E, 2, 1, 8),
1390};
1391
1392static const struct tegra_gpio_soc tegra410_compute_soc = {
1393 .num_ports = ARRAY_SIZE(tegra410_compute_ports),
1394 .ports = tegra410_compute_ports,
1395 .name = "tegra410-gpio-compute",
1396 .prefix = TEGRA_GPIO_PREFIX("COMPUTE"),
1397 .num_irqs_per_bank = 8,
1398 .instance = 0,
1399};
1400
1401#define TEGRA410_SYSTEM_GPIO_PORT(_name, _bank, _port, _pins) \
1402 TEGRA_GPIO_PORT(TEGRA410_SYSTEM, _name, _bank, _port, _pins)
1403
1404static const struct tegra_gpio_port tegra410_system_ports[] = {
1405 TEGRA410_SYSTEM_GPIO_PORT(A, 0, 0, 7),
1406 TEGRA410_SYSTEM_GPIO_PORT(B, 0, 1, 8),
1407 TEGRA410_SYSTEM_GPIO_PORT(C, 0, 2, 8),
1408 TEGRA410_SYSTEM_GPIO_PORT(D, 0, 3, 8),
1409 TEGRA410_SYSTEM_GPIO_PORT(E, 0, 4, 6),
1410 TEGRA410_SYSTEM_GPIO_PORT(I, 1, 0, 8),
1411 TEGRA410_SYSTEM_GPIO_PORT(J, 1, 1, 7),
1412 TEGRA410_SYSTEM_GPIO_PORT(K, 1, 2, 7),
1413 TEGRA410_SYSTEM_GPIO_PORT(L, 1, 3, 7),
1414 TEGRA410_SYSTEM_GPIO_PORT(M, 2, 0, 7),
1415 TEGRA410_SYSTEM_GPIO_PORT(N, 2, 1, 6),
1416 TEGRA410_SYSTEM_GPIO_PORT(P, 2, 2, 8),
1417 TEGRA410_SYSTEM_GPIO_PORT(Q, 2, 3, 3),
1418 TEGRA410_SYSTEM_GPIO_PORT(R, 2, 4, 2),
1419 TEGRA410_SYSTEM_GPIO_PORT(V, 1, 4, 2),
1420};
1421
1422static const struct tegra_gpio_soc tegra410_system_soc = {
1423 .num_ports = ARRAY_SIZE(tegra410_system_ports),
1424 .ports = tegra410_system_ports,
1425 .name = "tegra410-gpio-system",
1426 .prefix = TEGRA_GPIO_PREFIX("SYSTEM"),
1427 .num_irqs_per_bank = 8,
1428 .instance = 0,
1429};
1430
1431static const struct of_device_id tegra186_gpio_of_match[] = {
1432 {
1433 .compatible = "nvidia,tegra186-gpio",
1434 .data = &tegra186_main_soc
1435 }, {
1436 .compatible = "nvidia,tegra186-gpio-aon",
1437 .data = &tegra186_aon_soc
1438 }, {
1439 .compatible = "nvidia,tegra194-gpio",
1440 .data = &tegra194_main_soc
1441 }, {
1442 .compatible = "nvidia,tegra194-gpio-aon",
1443 .data = &tegra194_aon_soc
1444 }, {
1445 .compatible = "nvidia,tegra234-gpio",
1446 .data = &tegra234_main_soc
1447 }, {
1448 .compatible = "nvidia,tegra234-gpio-aon",
1449 .data = &tegra234_aon_soc
1450 }, {
1451 .compatible = "nvidia,tegra256-gpio",
1452 .data = &tegra256_main_soc
1453 }, {
1454 .compatible = "nvidia,tegra264-gpio",
1455 .data = &tegra264_main_soc
1456 }, {
1457 .compatible = "nvidia,tegra264-gpio-aon",
1458 .data = &tegra264_aon_soc
1459 }, {
1460 .compatible = "nvidia,tegra264-gpio-uphy",
1461 .data = &tegra264_uphy_soc
1462 }, {
1463 /* sentinel */
1464 }
1465};
1466MODULE_DEVICE_TABLE(of, tegra186_gpio_of_match);
1467
1468static const struct acpi_device_id tegra186_gpio_acpi_match[] = {
1469 { .id = "NVDA0108", .driver_data = (kernel_ulong_t)&tegra186_main_soc },
1470 { .id = "NVDA0208", .driver_data = (kernel_ulong_t)&tegra186_aon_soc },
1471 { .id = "NVDA0308", .driver_data = (kernel_ulong_t)&tegra194_main_soc },
1472 { .id = "NVDA0408", .driver_data = (kernel_ulong_t)&tegra194_aon_soc },
1473 { .id = "NVDA0508", .driver_data = (kernel_ulong_t)&tegra241_main_soc },
1474 { .id = "NVDA0608", .driver_data = (kernel_ulong_t)&tegra241_aon_soc },
1475 { .id = "NVDA0708", .driver_data = (kernel_ulong_t)&tegra410_compute_soc },
1476 { .id = "NVDA0808", .driver_data = (kernel_ulong_t)&tegra410_system_soc },
1477 {}
1478};
1479MODULE_DEVICE_TABLE(acpi, tegra186_gpio_acpi_match);
1480
1481static struct platform_driver tegra186_gpio_driver = {
1482 .driver = {
1483 .name = "tegra186-gpio",
1484 .of_match_table = tegra186_gpio_of_match,
1485 .acpi_match_table = tegra186_gpio_acpi_match,
1486 },
1487 .probe = tegra186_gpio_probe,
1488};
1489module_platform_driver(tegra186_gpio_driver);
1490
1491MODULE_DESCRIPTION("NVIDIA Tegra186 GPIO controller driver");
1492MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
1493MODULE_LICENSE("GPL v2");