Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 *
25 * Authors: Christian König <christian.koenig@amd.com>
26 */
27
28#include <linux/firmware.h>
29#include <linux/module.h>
30
31#include <drm/drm.h>
32#include <drm/drm_drv.h>
33
34#include "amdgpu.h"
35#include "amdgpu_pm.h"
36#include "amdgpu_vce.h"
37#include "amdgpu_cs.h"
38#include "cikd.h"
39
40/* 1 second timeout */
41#define VCE_IDLE_TIMEOUT msecs_to_jiffies(1000)
42
43/* Firmware Names */
44#ifdef CONFIG_DRM_AMDGPU_SI
45#define FIRMWARE_VCE_V1_0 "amdgpu/vce_1_0_0.bin"
46#endif
47#ifdef CONFIG_DRM_AMDGPU_CIK
48#define FIRMWARE_BONAIRE "amdgpu/bonaire_vce.bin"
49#define FIRMWARE_KABINI "amdgpu/kabini_vce.bin"
50#define FIRMWARE_KAVERI "amdgpu/kaveri_vce.bin"
51#define FIRMWARE_HAWAII "amdgpu/hawaii_vce.bin"
52#define FIRMWARE_MULLINS "amdgpu/mullins_vce.bin"
53#endif
54#define FIRMWARE_TONGA "amdgpu/tonga_vce.bin"
55#define FIRMWARE_CARRIZO "amdgpu/carrizo_vce.bin"
56#define FIRMWARE_FIJI "amdgpu/fiji_vce.bin"
57#define FIRMWARE_STONEY "amdgpu/stoney_vce.bin"
58#define FIRMWARE_POLARIS10 "amdgpu/polaris10_vce.bin"
59#define FIRMWARE_POLARIS11 "amdgpu/polaris11_vce.bin"
60#define FIRMWARE_POLARIS12 "amdgpu/polaris12_vce.bin"
61#define FIRMWARE_VEGAM "amdgpu/vegam_vce.bin"
62
63#define FIRMWARE_VEGA10 "amdgpu/vega10_vce.bin"
64#define FIRMWARE_VEGA12 "amdgpu/vega12_vce.bin"
65#define FIRMWARE_VEGA20 "amdgpu/vega20_vce.bin"
66
67#ifdef CONFIG_DRM_AMDGPU_SI
68MODULE_FIRMWARE(FIRMWARE_VCE_V1_0);
69#endif
70#ifdef CONFIG_DRM_AMDGPU_CIK
71MODULE_FIRMWARE(FIRMWARE_BONAIRE);
72MODULE_FIRMWARE(FIRMWARE_KABINI);
73MODULE_FIRMWARE(FIRMWARE_KAVERI);
74MODULE_FIRMWARE(FIRMWARE_HAWAII);
75MODULE_FIRMWARE(FIRMWARE_MULLINS);
76#endif
77MODULE_FIRMWARE(FIRMWARE_TONGA);
78MODULE_FIRMWARE(FIRMWARE_CARRIZO);
79MODULE_FIRMWARE(FIRMWARE_FIJI);
80MODULE_FIRMWARE(FIRMWARE_STONEY);
81MODULE_FIRMWARE(FIRMWARE_POLARIS10);
82MODULE_FIRMWARE(FIRMWARE_POLARIS11);
83MODULE_FIRMWARE(FIRMWARE_POLARIS12);
84MODULE_FIRMWARE(FIRMWARE_VEGAM);
85
86MODULE_FIRMWARE(FIRMWARE_VEGA10);
87MODULE_FIRMWARE(FIRMWARE_VEGA12);
88MODULE_FIRMWARE(FIRMWARE_VEGA20);
89
90static void amdgpu_vce_idle_work_handler(struct work_struct *work);
91static int amdgpu_vce_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
92 struct dma_fence **fence);
93static int amdgpu_vce_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
94 bool direct, struct dma_fence **fence);
95
96/**
97 * amdgpu_vce_firmware_name() - determine the firmware file name for VCE
98 *
99 * @adev: amdgpu_device pointer
100 *
101 * Each chip that has VCE IP may need a different firmware.
102 * This function returns the name of the VCE firmware file
103 * appropriate for the current chip.
104 */
105static const char *amdgpu_vce_firmware_name(struct amdgpu_device *adev)
106{
107 switch (adev->asic_type) {
108#ifdef CONFIG_DRM_AMDGPU_SI
109 case CHIP_PITCAIRN:
110 case CHIP_TAHITI:
111 case CHIP_VERDE:
112 return FIRMWARE_VCE_V1_0;
113#endif
114#ifdef CONFIG_DRM_AMDGPU_CIK
115 case CHIP_BONAIRE:
116 return FIRMWARE_BONAIRE;
117 case CHIP_KAVERI:
118 return FIRMWARE_KAVERI;
119 case CHIP_KABINI:
120 return FIRMWARE_KABINI;
121 case CHIP_HAWAII:
122 return FIRMWARE_HAWAII;
123 case CHIP_MULLINS:
124 return FIRMWARE_MULLINS;
125#endif
126 case CHIP_TONGA:
127 return FIRMWARE_TONGA;
128 case CHIP_CARRIZO:
129 return FIRMWARE_CARRIZO;
130 case CHIP_FIJI:
131 return FIRMWARE_FIJI;
132 case CHIP_STONEY:
133 return FIRMWARE_STONEY;
134 case CHIP_POLARIS10:
135 return FIRMWARE_POLARIS10;
136 case CHIP_POLARIS11:
137 return FIRMWARE_POLARIS11;
138 case CHIP_POLARIS12:
139 return FIRMWARE_POLARIS12;
140 case CHIP_VEGAM:
141 return FIRMWARE_VEGAM;
142 case CHIP_VEGA10:
143 return FIRMWARE_VEGA10;
144 case CHIP_VEGA12:
145 return FIRMWARE_VEGA12;
146 case CHIP_VEGA20:
147 return FIRMWARE_VEGA20;
148
149 default:
150 return NULL;
151 }
152}
153
154/**
155 * amdgpu_vce_early_init() - try to load VCE firmware
156 *
157 * @adev: amdgpu_device pointer
158 *
159 * Tries to load the VCE firmware.
160 *
161 * When not found, returns ENOENT so that the driver can
162 * still load and initialize the rest of the IP blocks.
163 * The GPU can function just fine without VCE, they will just
164 * not support video encoding.
165 */
166int amdgpu_vce_early_init(struct amdgpu_device *adev)
167{
168 const char *fw_name = amdgpu_vce_firmware_name(adev);
169 const struct common_firmware_header *hdr;
170 unsigned int ucode_version, version_major, version_minor, binary_id;
171 int r;
172
173 if (!fw_name)
174 return -ENOENT;
175
176 r = amdgpu_ucode_request(adev, &adev->vce.fw, AMDGPU_UCODE_REQUIRED, "%s", fw_name);
177 if (r) {
178 dev_err(adev->dev,
179 "amdgpu_vce: Firmware \"%s\" not found or failed to validate (%d)\n",
180 fw_name, r);
181
182 amdgpu_ucode_release(&adev->vce.fw);
183 return -ENOENT;
184 }
185
186 hdr = (const struct common_firmware_header *)adev->vce.fw->data;
187
188 ucode_version = le32_to_cpu(hdr->ucode_version);
189 version_major = (ucode_version >> 20) & 0xfff;
190 version_minor = (ucode_version >> 8) & 0xfff;
191 binary_id = ucode_version & 0xff;
192 dev_info(adev->dev, "Found VCE firmware Version: %d.%d Binary ID: %d\n",
193 version_major, version_minor, binary_id);
194 adev->vce.fw_version = ((version_major << 24) | (version_minor << 16) |
195 (binary_id << 8));
196
197 return 0;
198}
199
200/**
201 * amdgpu_vce_sw_init() - allocate memory for VCE BO
202 *
203 * @adev: amdgpu_device pointer
204 * @size: size for the new BO
205 *
206 * First step to get VCE online: allocate memory for VCE BO.
207 * The VCE firmware binary is copied into the VCE BO later,
208 * in amdgpu_vce_resume. The VCE executes its code from the
209 * VCE BO and also uses the space in this BO for its stack and data.
210 *
211 * Ideally this BO should be placed in VRAM for optimal performance,
212 * although technically it also runs from system RAM (albeit slowly).
213 */
214int amdgpu_vce_sw_init(struct amdgpu_device *adev, unsigned long size)
215{
216 int i, r;
217
218 if (!adev->vce.fw)
219 return -ENOENT;
220
221 r = amdgpu_bo_create_kernel(adev, size, PAGE_SIZE,
222 AMDGPU_GEM_DOMAIN_VRAM |
223 AMDGPU_GEM_DOMAIN_GTT,
224 &adev->vce.vcpu_bo,
225 &adev->vce.gpu_addr, &adev->vce.cpu_addr);
226 if (r) {
227 dev_err(adev->dev, "(%d) failed to allocate VCE bo\n", r);
228 return r;
229 }
230
231 for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i) {
232 atomic_set(&adev->vce.handles[i], 0);
233 adev->vce.filp[i] = NULL;
234 }
235
236 INIT_DELAYED_WORK(&adev->vce.idle_work, amdgpu_vce_idle_work_handler);
237 mutex_init(&adev->vce.idle_mutex);
238
239 return 0;
240}
241
242/**
243 * amdgpu_vce_sw_fini - free memory
244 *
245 * @adev: amdgpu_device pointer
246 *
247 * Last step on VCE teardown, free firmware memory
248 */
249int amdgpu_vce_sw_fini(struct amdgpu_device *adev)
250{
251 unsigned int i;
252
253 if (adev->vce.vcpu_bo == NULL)
254 return 0;
255
256 drm_sched_entity_destroy(&adev->vce.entity);
257
258 for (i = 0; i < adev->vce.num_rings; i++)
259 amdgpu_ring_fini(&adev->vce.ring[i]);
260
261 amdgpu_ucode_release(&adev->vce.fw);
262 mutex_destroy(&adev->vce.idle_mutex);
263
264 amdgpu_bo_free_kernel(&adev->vce.vcpu_bo, &adev->vce.gpu_addr,
265 (void **)&adev->vce.cpu_addr);
266
267 return 0;
268}
269
270/**
271 * amdgpu_vce_entity_init - init entity
272 *
273 * @adev: amdgpu_device pointer
274 * @ring: amdgpu_ring pointer to check
275 *
276 * Initialize the entity used for handle management in the kernel driver.
277 */
278int amdgpu_vce_entity_init(struct amdgpu_device *adev, struct amdgpu_ring *ring)
279{
280 if (ring == &adev->vce.ring[0]) {
281 struct drm_gpu_scheduler *sched = &ring->sched;
282 int r;
283
284 r = drm_sched_entity_init(&adev->vce.entity, DRM_SCHED_PRIORITY_NORMAL,
285 &sched, 1, NULL);
286 if (r != 0) {
287 DRM_ERROR("Failed setting up VCE run queue.\n");
288 return r;
289 }
290 }
291
292 return 0;
293}
294
295/**
296 * amdgpu_vce_suspend - unpin VCE fw memory
297 *
298 * @adev: amdgpu_device pointer
299 *
300 */
301int amdgpu_vce_suspend(struct amdgpu_device *adev)
302{
303 int i;
304
305 cancel_delayed_work_sync(&adev->vce.idle_work);
306
307 if (adev->vce.vcpu_bo == NULL)
308 return 0;
309
310 for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i)
311 if (atomic_read(&adev->vce.handles[i]))
312 break;
313
314 if (i == AMDGPU_MAX_VCE_HANDLES)
315 return 0;
316
317 /* TODO: suspending running encoding sessions isn't supported */
318 return -EINVAL;
319}
320
321/**
322 * amdgpu_vce_resume - pin VCE fw memory
323 *
324 * @adev: amdgpu_device pointer
325 *
326 */
327int amdgpu_vce_resume(struct amdgpu_device *adev)
328{
329 const struct common_firmware_header *hdr;
330 unsigned int offset;
331 int idx;
332
333 if (adev->vce.vcpu_bo == NULL)
334 return -EINVAL;
335
336 hdr = (const struct common_firmware_header *)adev->vce.fw->data;
337 offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
338
339 if (drm_dev_enter(adev_to_drm(adev), &idx)) {
340 memset_io(adev->vce.cpu_addr, 0, amdgpu_bo_size(adev->vce.vcpu_bo));
341 memcpy_toio(adev->vce.cpu_addr, adev->vce.fw->data + offset,
342 adev->vce.fw->size - offset);
343 drm_dev_exit(idx);
344 }
345
346 return 0;
347}
348
349/**
350 * amdgpu_vce_idle_work_handler - power off VCE
351 *
352 * @work: pointer to work structure
353 *
354 * power of VCE when it's not used any more
355 */
356static void amdgpu_vce_idle_work_handler(struct work_struct *work)
357{
358 struct amdgpu_device *adev =
359 container_of(work, struct amdgpu_device, vce.idle_work.work);
360 unsigned int i, count = 0;
361
362 for (i = 0; i < adev->vce.num_rings; i++)
363 count += amdgpu_fence_count_emitted(&adev->vce.ring[i]);
364
365 if (count == 0) {
366 if (adev->pm.dpm_enabled) {
367 amdgpu_dpm_enable_vce(adev, false);
368 } else {
369 amdgpu_asic_set_vce_clocks(adev, 0, 0);
370 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
371 AMD_PG_STATE_GATE);
372 amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
373 AMD_CG_STATE_GATE);
374 }
375 } else {
376 schedule_delayed_work(&adev->vce.idle_work, VCE_IDLE_TIMEOUT);
377 }
378}
379
380/**
381 * amdgpu_vce_ring_begin_use - power up VCE
382 *
383 * @ring: amdgpu ring
384 *
385 * Make sure VCE is powerd up when we want to use it
386 */
387void amdgpu_vce_ring_begin_use(struct amdgpu_ring *ring)
388{
389 struct amdgpu_device *adev = ring->adev;
390 bool set_clocks;
391
392 if (amdgpu_sriov_vf(adev))
393 return;
394
395 mutex_lock(&adev->vce.idle_mutex);
396 set_clocks = !cancel_delayed_work_sync(&adev->vce.idle_work);
397 if (set_clocks) {
398 if (adev->pm.dpm_enabled) {
399 amdgpu_dpm_enable_vce(adev, true);
400 } else {
401 amdgpu_asic_set_vce_clocks(adev, 53300, 40000);
402 amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
403 AMD_CG_STATE_UNGATE);
404 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
405 AMD_PG_STATE_UNGATE);
406
407 }
408 }
409 mutex_unlock(&adev->vce.idle_mutex);
410}
411
412/**
413 * amdgpu_vce_ring_end_use - power VCE down
414 *
415 * @ring: amdgpu ring
416 *
417 * Schedule work to power VCE down again
418 */
419void amdgpu_vce_ring_end_use(struct amdgpu_ring *ring)
420{
421 if (!amdgpu_sriov_vf(ring->adev))
422 schedule_delayed_work(&ring->adev->vce.idle_work, VCE_IDLE_TIMEOUT);
423}
424
425/**
426 * amdgpu_vce_free_handles - free still open VCE handles
427 *
428 * @adev: amdgpu_device pointer
429 * @filp: drm file pointer
430 *
431 * Close all VCE handles still open by this file pointer
432 */
433void amdgpu_vce_free_handles(struct amdgpu_device *adev, struct drm_file *filp)
434{
435 struct amdgpu_ring *ring = &adev->vce.ring[0];
436 int i, r;
437
438 for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i) {
439 uint32_t handle = atomic_read(&adev->vce.handles[i]);
440
441 if (!handle || adev->vce.filp[i] != filp)
442 continue;
443
444 r = amdgpu_vce_get_destroy_msg(ring, handle, false, NULL);
445 if (r)
446 DRM_ERROR("Error destroying VCE handle (%d)!\n", r);
447
448 adev->vce.filp[i] = NULL;
449 atomic_set(&adev->vce.handles[i], 0);
450 }
451}
452
453/**
454 * amdgpu_vce_get_create_msg - generate a VCE create msg
455 *
456 * @ring: ring we should submit the msg to
457 * @handle: VCE session handle to use
458 * @fence: optional fence to return
459 *
460 * Open up a stream for HW test
461 */
462static int amdgpu_vce_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
463 struct dma_fence **fence)
464{
465 const unsigned int ib_size_dw = 1024;
466 struct amdgpu_job *job;
467 struct amdgpu_ib *ib;
468 struct amdgpu_ib ib_msg;
469 struct dma_fence *f = NULL;
470 uint64_t addr;
471 int i, r;
472
473 r = amdgpu_job_alloc_with_ib(ring->adev, &ring->adev->vce.entity,
474 AMDGPU_FENCE_OWNER_UNDEFINED,
475 ib_size_dw * 4, AMDGPU_IB_POOL_DIRECT,
476 &job, AMDGPU_KERNEL_JOB_ID_VCN_RING_TEST);
477 if (r)
478 return r;
479
480 memset(&ib_msg, 0, sizeof(ib_msg));
481 /* only one gpu page is needed, alloc +1 page to make addr aligned. */
482 r = amdgpu_ib_get(ring->adev, NULL, AMDGPU_GPU_PAGE_SIZE * 2,
483 AMDGPU_IB_POOL_DIRECT,
484 &ib_msg);
485 if (r)
486 goto err;
487
488 ib = &job->ibs[0];
489 /* let addr point to page boundary */
490 addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg.gpu_addr);
491
492 /* stitch together an VCE create msg */
493 ib->length_dw = 0;
494 ib->ptr[ib->length_dw++] = 0x0000000c; /* len */
495 ib->ptr[ib->length_dw++] = 0x00000001; /* session cmd */
496 ib->ptr[ib->length_dw++] = handle;
497
498 if ((ring->adev->vce.fw_version >> 24) >= 52)
499 ib->ptr[ib->length_dw++] = 0x00000040; /* len */
500 else
501 ib->ptr[ib->length_dw++] = 0x00000030; /* len */
502 ib->ptr[ib->length_dw++] = 0x01000001; /* create cmd */
503 ib->ptr[ib->length_dw++] = 0x00000000;
504 ib->ptr[ib->length_dw++] = 0x00000042;
505 ib->ptr[ib->length_dw++] = 0x0000000a;
506 ib->ptr[ib->length_dw++] = 0x00000001;
507 ib->ptr[ib->length_dw++] = 0x00000080;
508 ib->ptr[ib->length_dw++] = 0x00000060;
509 ib->ptr[ib->length_dw++] = 0x00000100;
510 ib->ptr[ib->length_dw++] = 0x00000100;
511 ib->ptr[ib->length_dw++] = 0x0000000c;
512 ib->ptr[ib->length_dw++] = 0x00000000;
513 if ((ring->adev->vce.fw_version >> 24) >= 52) {
514 ib->ptr[ib->length_dw++] = 0x00000000;
515 ib->ptr[ib->length_dw++] = 0x00000000;
516 ib->ptr[ib->length_dw++] = 0x00000000;
517 ib->ptr[ib->length_dw++] = 0x00000000;
518 }
519
520 ib->ptr[ib->length_dw++] = 0x00000014; /* len */
521 ib->ptr[ib->length_dw++] = 0x05000005; /* feedback buffer */
522 ib->ptr[ib->length_dw++] = upper_32_bits(addr);
523 ib->ptr[ib->length_dw++] = addr;
524 ib->ptr[ib->length_dw++] = 0x00000001;
525
526 for (i = ib->length_dw; i < ib_size_dw; ++i)
527 ib->ptr[i] = 0x0;
528
529 r = amdgpu_job_submit_direct(job, ring, &f);
530 amdgpu_ib_free(&ib_msg, f);
531 if (r)
532 goto err;
533
534 if (fence)
535 *fence = dma_fence_get(f);
536 dma_fence_put(f);
537 return 0;
538
539err:
540 amdgpu_job_free(job);
541 return r;
542}
543
544/**
545 * amdgpu_vce_get_destroy_msg - generate a VCE destroy msg
546 *
547 * @ring: ring we should submit the msg to
548 * @handle: VCE session handle to use
549 * @direct: direct or delayed pool
550 * @fence: optional fence to return
551 *
552 * Close up a stream for HW test or if userspace failed to do so
553 */
554static int amdgpu_vce_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
555 bool direct, struct dma_fence **fence)
556{
557 const unsigned int ib_size_dw = 1024;
558 struct amdgpu_job *job;
559 struct amdgpu_ib *ib;
560 struct dma_fence *f = NULL;
561 int i, r;
562
563 r = amdgpu_job_alloc_with_ib(ring->adev, &ring->adev->vce.entity,
564 AMDGPU_FENCE_OWNER_UNDEFINED,
565 ib_size_dw * 4,
566 direct ? AMDGPU_IB_POOL_DIRECT :
567 AMDGPU_IB_POOL_DELAYED, &job,
568 AMDGPU_KERNEL_JOB_ID_VCN_RING_TEST);
569 if (r)
570 return r;
571
572 ib = &job->ibs[0];
573
574 /* stitch together an VCE destroy msg */
575 ib->length_dw = 0;
576 ib->ptr[ib->length_dw++] = 0x0000000c; /* len */
577 ib->ptr[ib->length_dw++] = 0x00000001; /* session cmd */
578 ib->ptr[ib->length_dw++] = handle;
579
580 ib->ptr[ib->length_dw++] = 0x00000020; /* len */
581 ib->ptr[ib->length_dw++] = 0x00000002; /* task info */
582 ib->ptr[ib->length_dw++] = 0xffffffff; /* next task info, set to 0xffffffff if no */
583 ib->ptr[ib->length_dw++] = 0x00000001; /* destroy session */
584 ib->ptr[ib->length_dw++] = 0x00000000;
585 ib->ptr[ib->length_dw++] = 0x00000000;
586 ib->ptr[ib->length_dw++] = 0xffffffff; /* feedback is not needed, set to 0xffffffff and firmware will not output feedback */
587 ib->ptr[ib->length_dw++] = 0x00000000;
588
589 ib->ptr[ib->length_dw++] = 0x00000008; /* len */
590 ib->ptr[ib->length_dw++] = 0x02000001; /* destroy cmd */
591
592 for (i = ib->length_dw; i < ib_size_dw; ++i)
593 ib->ptr[i] = 0x0;
594
595 if (direct)
596 r = amdgpu_job_submit_direct(job, ring, &f);
597 else
598 f = amdgpu_job_submit(job);
599 if (r)
600 goto err;
601
602 if (fence)
603 *fence = dma_fence_get(f);
604 dma_fence_put(f);
605 return 0;
606
607err:
608 amdgpu_job_free(job);
609 return r;
610}
611
612/**
613 * amdgpu_vce_validate_bo - make sure not to cross 4GB boundary
614 *
615 * @p: cs parser
616 * @ib: indirect buffer to use
617 * @lo: address of lower dword
618 * @hi: address of higher dword
619 * @size: minimum size
620 * @index: bs/fb index
621 *
622 * Make sure that no BO cross a 4GB boundary.
623 */
624static int amdgpu_vce_validate_bo(struct amdgpu_cs_parser *p,
625 struct amdgpu_ib *ib, int lo, int hi,
626 unsigned int size, int32_t index)
627{
628 int64_t offset = ((uint64_t)size) * ((int64_t)index);
629 struct ttm_operation_ctx ctx = { false, false };
630 struct amdgpu_bo_va_mapping *mapping;
631 unsigned int i, fpfn, lpfn;
632 struct amdgpu_bo *bo;
633 uint64_t addr;
634 int r;
635
636 addr = ((uint64_t)amdgpu_ib_get_value(ib, lo)) |
637 ((uint64_t)amdgpu_ib_get_value(ib, hi)) << 32;
638 if (index >= 0) {
639 addr += offset;
640 fpfn = PAGE_ALIGN(offset) >> PAGE_SHIFT;
641 lpfn = 0x100000000ULL >> PAGE_SHIFT;
642 } else {
643 fpfn = 0;
644 lpfn = (0x100000000ULL - PAGE_ALIGN(offset)) >> PAGE_SHIFT;
645 }
646
647 r = amdgpu_cs_find_mapping(p, addr, &bo, &mapping);
648 if (r) {
649 DRM_ERROR("Can't find BO for addr 0x%010llx %d %d %d %d\n",
650 addr, lo, hi, size, index);
651 return r;
652 }
653
654 for (i = 0; i < bo->placement.num_placement; ++i) {
655 bo->placements[i].fpfn = max(bo->placements[i].fpfn, fpfn);
656 bo->placements[i].lpfn = bo->placements[i].lpfn ?
657 min(bo->placements[i].lpfn, lpfn) : lpfn;
658 }
659 return ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
660}
661
662
663/**
664 * amdgpu_vce_cs_reloc - command submission relocation
665 *
666 * @p: parser context
667 * @ib: indirect buffer to use
668 * @lo: address of lower dword
669 * @hi: address of higher dword
670 * @size: minimum size
671 * @index: bs/fb index
672 *
673 * Patch relocation inside command stream with real buffer address
674 */
675static int amdgpu_vce_cs_reloc(struct amdgpu_cs_parser *p, struct amdgpu_ib *ib,
676 int lo, int hi, unsigned int size, uint32_t index)
677{
678 struct amdgpu_bo_va_mapping *mapping;
679 struct amdgpu_bo *bo;
680 uint64_t addr;
681 int r;
682
683 if (lo >= ib->length_dw || hi >= ib->length_dw)
684 return -EINVAL;
685
686 if (index == 0xffffffff)
687 index = 0;
688
689 addr = ((uint64_t)amdgpu_ib_get_value(ib, lo)) |
690 ((uint64_t)amdgpu_ib_get_value(ib, hi)) << 32;
691 addr += ((uint64_t)size) * ((uint64_t)index);
692
693 r = amdgpu_cs_find_mapping(p, addr, &bo, &mapping);
694 if (r) {
695 DRM_ERROR("Can't find BO for addr 0x%010llx %d %d %d %d\n",
696 addr, lo, hi, size, index);
697 return r;
698 }
699
700 if ((addr + (uint64_t)size) >
701 (mapping->last + 1) * AMDGPU_GPU_PAGE_SIZE) {
702 DRM_ERROR("BO too small for addr 0x%010llx %d %d\n",
703 addr, lo, hi);
704 return -EINVAL;
705 }
706
707 addr -= mapping->start * AMDGPU_GPU_PAGE_SIZE;
708 addr += amdgpu_bo_gpu_offset(bo);
709 addr -= ((uint64_t)size) * ((uint64_t)index);
710
711 amdgpu_ib_set_value(ib, lo, lower_32_bits(addr));
712 amdgpu_ib_set_value(ib, hi, upper_32_bits(addr));
713
714 return 0;
715}
716
717/**
718 * amdgpu_vce_validate_handle - validate stream handle
719 *
720 * @p: parser context
721 * @handle: handle to validate
722 * @allocated: allocated a new handle?
723 *
724 * Validates the handle and return the found session index or -EINVAL
725 * we don't have another free session index.
726 */
727static int amdgpu_vce_validate_handle(struct amdgpu_cs_parser *p,
728 uint32_t handle, uint32_t *allocated)
729{
730 unsigned int i;
731
732 /* validate the handle */
733 for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i) {
734 if (atomic_read(&p->adev->vce.handles[i]) == handle) {
735 if (p->adev->vce.filp[i] != p->filp) {
736 DRM_ERROR("VCE handle collision detected!\n");
737 return -EINVAL;
738 }
739 return i;
740 }
741 }
742
743 /* handle not found try to alloc a new one */
744 for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i) {
745 if (!atomic_cmpxchg(&p->adev->vce.handles[i], 0, handle)) {
746 p->adev->vce.filp[i] = p->filp;
747 p->adev->vce.img_size[i] = 0;
748 *allocated |= 1 << i;
749 return i;
750 }
751 }
752
753 DRM_ERROR("No more free VCE handles!\n");
754 return -EINVAL;
755}
756
757/**
758 * amdgpu_vce_ring_parse_cs - parse and validate the command stream
759 *
760 * @p: parser context
761 * @job: the job to parse
762 * @ib: the IB to patch
763 */
764int amdgpu_vce_ring_parse_cs(struct amdgpu_cs_parser *p,
765 struct amdgpu_job *job,
766 struct amdgpu_ib *ib)
767{
768 unsigned int fb_idx = 0, bs_idx = 0;
769 int session_idx = -1;
770 uint32_t destroyed = 0;
771 uint32_t created = 0;
772 uint32_t allocated = 0;
773 uint32_t tmp, handle = 0;
774 uint32_t dummy = 0xffffffff;
775 uint32_t *size = &dummy;
776 unsigned int idx;
777 int i, r = 0;
778
779 job->vm = NULL;
780
781 for (idx = 0; idx < ib->length_dw;) {
782 uint32_t len = amdgpu_ib_get_value(ib, idx);
783 uint32_t cmd = amdgpu_ib_get_value(ib, idx + 1);
784
785 if ((len < 8) || (len & 3)) {
786 DRM_ERROR("invalid VCE command length (%d)!\n", len);
787 r = -EINVAL;
788 goto out;
789 }
790
791 switch (cmd) {
792 case 0x00000002: /* task info */
793 fb_idx = amdgpu_ib_get_value(ib, idx + 6);
794 bs_idx = amdgpu_ib_get_value(ib, idx + 7);
795 break;
796
797 case 0x03000001: /* encode */
798 r = amdgpu_vce_validate_bo(p, ib, idx + 10, idx + 9,
799 0, 0);
800 if (r)
801 goto out;
802
803 r = amdgpu_vce_validate_bo(p, ib, idx + 12, idx + 11,
804 0, 0);
805 if (r)
806 goto out;
807 break;
808
809 case 0x05000001: /* context buffer */
810 r = amdgpu_vce_validate_bo(p, ib, idx + 3, idx + 2,
811 0, 0);
812 if (r)
813 goto out;
814 break;
815
816 case 0x05000004: /* video bitstream buffer */
817 tmp = amdgpu_ib_get_value(ib, idx + 4);
818 r = amdgpu_vce_validate_bo(p, ib, idx + 3, idx + 2,
819 tmp, bs_idx);
820 if (r)
821 goto out;
822 break;
823
824 case 0x05000005: /* feedback buffer */
825 r = amdgpu_vce_validate_bo(p, ib, idx + 3, idx + 2,
826 4096, fb_idx);
827 if (r)
828 goto out;
829 break;
830
831 case 0x0500000d: /* MV buffer */
832 r = amdgpu_vce_validate_bo(p, ib, idx + 3, idx + 2,
833 0, 0);
834 if (r)
835 goto out;
836
837 r = amdgpu_vce_validate_bo(p, ib, idx + 8, idx + 7,
838 0, 0);
839 if (r)
840 goto out;
841 break;
842 }
843
844 idx += len / 4;
845 }
846
847 for (idx = 0; idx < ib->length_dw;) {
848 uint32_t len = amdgpu_ib_get_value(ib, idx);
849 uint32_t cmd = amdgpu_ib_get_value(ib, idx + 1);
850
851 switch (cmd) {
852 case 0x00000001: /* session */
853 handle = amdgpu_ib_get_value(ib, idx + 2);
854 session_idx = amdgpu_vce_validate_handle(p, handle,
855 &allocated);
856 if (session_idx < 0) {
857 r = session_idx;
858 goto out;
859 }
860 size = &p->adev->vce.img_size[session_idx];
861 break;
862
863 case 0x00000002: /* task info */
864 fb_idx = amdgpu_ib_get_value(ib, idx + 6);
865 bs_idx = amdgpu_ib_get_value(ib, idx + 7);
866 break;
867
868 case 0x01000001: /* create */
869 created |= 1 << session_idx;
870 if (destroyed & (1 << session_idx)) {
871 destroyed &= ~(1 << session_idx);
872 allocated |= 1 << session_idx;
873
874 } else if (!(allocated & (1 << session_idx))) {
875 DRM_ERROR("Handle already in use!\n");
876 r = -EINVAL;
877 goto out;
878 }
879
880 *size = amdgpu_ib_get_value(ib, idx + 8) *
881 amdgpu_ib_get_value(ib, idx + 10) *
882 8 * 3 / 2;
883 break;
884
885 case 0x04000001: /* config extension */
886 case 0x04000002: /* pic control */
887 case 0x04000005: /* rate control */
888 case 0x04000007: /* motion estimation */
889 case 0x04000008: /* rdo */
890 case 0x04000009: /* vui */
891 case 0x05000002: /* auxiliary buffer */
892 case 0x05000009: /* clock table */
893 break;
894
895 case 0x0500000c: /* hw config */
896 switch (p->adev->asic_type) {
897#ifdef CONFIG_DRM_AMDGPU_CIK
898 case CHIP_KAVERI:
899 case CHIP_MULLINS:
900#endif
901 case CHIP_CARRIZO:
902 break;
903 default:
904 r = -EINVAL;
905 goto out;
906 }
907 break;
908
909 case 0x03000001: /* encode */
910 r = amdgpu_vce_cs_reloc(p, ib, idx + 10, idx + 9,
911 *size, 0);
912 if (r)
913 goto out;
914
915 r = amdgpu_vce_cs_reloc(p, ib, idx + 12, idx + 11,
916 *size / 3, 0);
917 if (r)
918 goto out;
919 break;
920
921 case 0x02000001: /* destroy */
922 destroyed |= 1 << session_idx;
923 break;
924
925 case 0x05000001: /* context buffer */
926 r = amdgpu_vce_cs_reloc(p, ib, idx + 3, idx + 2,
927 *size * 2, 0);
928 if (r)
929 goto out;
930 break;
931
932 case 0x05000004: /* video bitstream buffer */
933 tmp = amdgpu_ib_get_value(ib, idx + 4);
934 r = amdgpu_vce_cs_reloc(p, ib, idx + 3, idx + 2,
935 tmp, bs_idx);
936 if (r)
937 goto out;
938 break;
939
940 case 0x05000005: /* feedback buffer */
941 r = amdgpu_vce_cs_reloc(p, ib, idx + 3, idx + 2,
942 4096, fb_idx);
943 if (r)
944 goto out;
945 break;
946
947 case 0x0500000d: /* MV buffer */
948 r = amdgpu_vce_cs_reloc(p, ib, idx + 3,
949 idx + 2, *size, 0);
950 if (r)
951 goto out;
952
953 r = amdgpu_vce_cs_reloc(p, ib, idx + 8,
954 idx + 7, *size / 12, 0);
955 if (r)
956 goto out;
957 break;
958
959 default:
960 DRM_ERROR("invalid VCE command (0x%x)!\n", cmd);
961 r = -EINVAL;
962 goto out;
963 }
964
965 if (session_idx == -1) {
966 DRM_ERROR("no session command at start of IB\n");
967 r = -EINVAL;
968 goto out;
969 }
970
971 idx += len / 4;
972 }
973
974 if (allocated & ~created) {
975 DRM_ERROR("New session without create command!\n");
976 r = -ENOENT;
977 }
978
979out:
980 if (!r) {
981 /* No error, free all destroyed handle slots */
982 tmp = destroyed;
983 } else {
984 /* Error during parsing, free all allocated handle slots */
985 tmp = allocated;
986 }
987
988 for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i)
989 if (tmp & (1 << i))
990 atomic_set(&p->adev->vce.handles[i], 0);
991
992 return r;
993}
994
995/**
996 * amdgpu_vce_ring_parse_cs_vm - parse the command stream in VM mode
997 *
998 * @p: parser context
999 * @job: the job to parse
1000 * @ib: the IB to patch
1001 */
1002int amdgpu_vce_ring_parse_cs_vm(struct amdgpu_cs_parser *p,
1003 struct amdgpu_job *job,
1004 struct amdgpu_ib *ib)
1005{
1006 int session_idx = -1;
1007 uint32_t destroyed = 0;
1008 uint32_t created = 0;
1009 uint32_t allocated = 0;
1010 uint32_t tmp, handle = 0;
1011 int i, r = 0, idx = 0;
1012
1013 while (idx < ib->length_dw) {
1014 uint32_t len = amdgpu_ib_get_value(ib, idx);
1015 uint32_t cmd = amdgpu_ib_get_value(ib, idx + 1);
1016
1017 if ((len < 8) || (len & 3)) {
1018 DRM_ERROR("invalid VCE command length (%d)!\n", len);
1019 r = -EINVAL;
1020 goto out;
1021 }
1022
1023 switch (cmd) {
1024 case 0x00000001: /* session */
1025 handle = amdgpu_ib_get_value(ib, idx + 2);
1026 session_idx = amdgpu_vce_validate_handle(p, handle,
1027 &allocated);
1028 if (session_idx < 0) {
1029 r = session_idx;
1030 goto out;
1031 }
1032 break;
1033
1034 case 0x01000001: /* create */
1035 created |= 1 << session_idx;
1036 if (destroyed & (1 << session_idx)) {
1037 destroyed &= ~(1 << session_idx);
1038 allocated |= 1 << session_idx;
1039
1040 } else if (!(allocated & (1 << session_idx))) {
1041 DRM_ERROR("Handle already in use!\n");
1042 r = -EINVAL;
1043 goto out;
1044 }
1045
1046 break;
1047
1048 case 0x02000001: /* destroy */
1049 destroyed |= 1 << session_idx;
1050 break;
1051
1052 default:
1053 break;
1054 }
1055
1056 if (session_idx == -1) {
1057 DRM_ERROR("no session command at start of IB\n");
1058 r = -EINVAL;
1059 goto out;
1060 }
1061
1062 idx += len / 4;
1063 }
1064
1065 if (allocated & ~created) {
1066 DRM_ERROR("New session without create command!\n");
1067 r = -ENOENT;
1068 }
1069
1070out:
1071 if (!r) {
1072 /* No error, free all destroyed handle slots */
1073 tmp = destroyed;
1074 } else {
1075 /* Error during parsing, free all allocated handle slots */
1076 tmp = allocated;
1077 }
1078
1079 for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i)
1080 if (tmp & (1 << i))
1081 atomic_set(&p->adev->vce.handles[i], 0);
1082
1083 return r;
1084}
1085
1086/**
1087 * amdgpu_vce_ring_emit_ib - execute indirect buffer
1088 *
1089 * @ring: engine to use
1090 * @job: job to retrieve vmid from
1091 * @ib: the IB to execute
1092 * @flags: unused
1093 *
1094 */
1095void amdgpu_vce_ring_emit_ib(struct amdgpu_ring *ring,
1096 struct amdgpu_job *job,
1097 struct amdgpu_ib *ib,
1098 uint32_t flags)
1099{
1100 amdgpu_ring_write(ring, VCE_CMD_IB);
1101 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1102 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1103 amdgpu_ring_write(ring, ib->length_dw);
1104}
1105
1106/**
1107 * amdgpu_vce_ring_emit_fence - add a fence command to the ring
1108 *
1109 * @ring: engine to use
1110 * @addr: address
1111 * @seq: sequence number
1112 * @flags: fence related flags
1113 *
1114 */
1115void amdgpu_vce_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
1116 unsigned int flags)
1117{
1118 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
1119
1120 amdgpu_ring_write(ring, VCE_CMD_FENCE);
1121 amdgpu_ring_write(ring, addr);
1122 amdgpu_ring_write(ring, upper_32_bits(addr));
1123 amdgpu_ring_write(ring, seq);
1124 amdgpu_ring_write(ring, VCE_CMD_TRAP);
1125 amdgpu_ring_write(ring, VCE_CMD_END);
1126}
1127
1128/**
1129 * amdgpu_vce_ring_test_ring - test if VCE ring is working
1130 *
1131 * @ring: the engine to test on
1132 *
1133 */
1134int amdgpu_vce_ring_test_ring(struct amdgpu_ring *ring)
1135{
1136 struct amdgpu_device *adev = ring->adev;
1137 uint32_t rptr;
1138 unsigned int i;
1139 int r, timeout = adev->usec_timeout;
1140
1141 /* skip ring test for sriov*/
1142 if (amdgpu_sriov_vf(adev))
1143 return 0;
1144
1145 r = amdgpu_ring_alloc(ring, 16);
1146 if (r)
1147 return r;
1148
1149 rptr = amdgpu_ring_get_rptr(ring);
1150
1151 amdgpu_ring_write(ring, VCE_CMD_END);
1152 amdgpu_ring_commit(ring);
1153
1154 for (i = 0; i < timeout; i++) {
1155 if (amdgpu_ring_get_rptr(ring) != rptr)
1156 break;
1157 udelay(1);
1158 }
1159
1160 if (i >= timeout)
1161 r = -ETIMEDOUT;
1162
1163 return r;
1164}
1165
1166/**
1167 * amdgpu_vce_ring_test_ib - test if VCE IBs are working
1168 *
1169 * @ring: the engine to test on
1170 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT
1171 *
1172 */
1173int amdgpu_vce_ring_test_ib(struct amdgpu_ring *ring, long timeout)
1174{
1175 struct dma_fence *fence = NULL;
1176 long r;
1177
1178 /* skip vce ring1/2 ib test for now, since it's not reliable */
1179 if (ring != &ring->adev->vce.ring[0])
1180 return 0;
1181
1182 r = amdgpu_vce_get_create_msg(ring, 1, NULL);
1183 if (r)
1184 goto error;
1185
1186 r = amdgpu_vce_get_destroy_msg(ring, 1, true, &fence);
1187 if (r)
1188 goto error;
1189
1190 r = dma_fence_wait_timeout(fence, false, timeout);
1191 if (r == 0)
1192 r = -ETIMEDOUT;
1193 else if (r > 0)
1194 r = 0;
1195
1196error:
1197 dma_fence_put(fence);
1198 return r;
1199}
1200
1201enum amdgpu_ring_priority_level amdgpu_vce_get_ring_prio(int ring)
1202{
1203 switch (ring) {
1204 case 0:
1205 return AMDGPU_RING_PRIO_0;
1206 case 1:
1207 return AMDGPU_RING_PRIO_1;
1208 case 2:
1209 return AMDGPU_RING_PRIO_2;
1210 default:
1211 return AMDGPU_RING_PRIO_0;
1212 }
1213}