Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Copyright (C) 2013-2015 ARM Limited
3 * Author: Liviu Dudau <Liviu.Dudau@arm.com>
4 *
5 * This file is subject to the terms and conditions of the GNU General Public
6 * License. See the file COPYING in the main directory of this archive
7 * for more details.
8 *
9 * ARM HDLCD Driver
10 */
11
12#include <linux/aperture.h>
13#include <linux/module.h>
14#include <linux/spinlock.h>
15#include <linux/clk.h>
16#include <linux/component.h>
17#include <linux/console.h>
18#include <linux/dma-mapping.h>
19#include <linux/list.h>
20#include <linux/of_graph.h>
21#include <linux/of_reserved_mem.h>
22#include <linux/platform_device.h>
23#include <linux/pm_runtime.h>
24
25#include <drm/clients/drm_client_setup.h>
26#include <drm/drm_atomic_helper.h>
27#include <drm/drm_crtc.h>
28#include <drm/drm_debugfs.h>
29#include <drm/drm_drv.h>
30#include <drm/drm_fbdev_dma.h>
31#include <drm/drm_gem_dma_helper.h>
32#include <drm/drm_gem_framebuffer_helper.h>
33#include <drm/drm_modeset_helper.h>
34#include <drm/drm_module.h>
35#include <drm/drm_of.h>
36#include <drm/drm_print.h>
37#include <drm/drm_probe_helper.h>
38#include <drm/drm_vblank.h>
39
40#include "hdlcd_drv.h"
41#include "hdlcd_regs.h"
42
43static irqreturn_t hdlcd_irq(int irq, void *arg)
44{
45 struct hdlcd_drm_private *hdlcd = arg;
46 unsigned long irq_status;
47
48 irq_status = hdlcd_read(hdlcd, HDLCD_REG_INT_STATUS);
49
50#ifdef CONFIG_DEBUG_FS
51 if (irq_status & HDLCD_INTERRUPT_UNDERRUN)
52 atomic_inc(&hdlcd->buffer_underrun_count);
53
54 if (irq_status & HDLCD_INTERRUPT_DMA_END)
55 atomic_inc(&hdlcd->dma_end_count);
56
57 if (irq_status & HDLCD_INTERRUPT_BUS_ERROR)
58 atomic_inc(&hdlcd->bus_error_count);
59
60 if (irq_status & HDLCD_INTERRUPT_VSYNC)
61 atomic_inc(&hdlcd->vsync_count);
62
63#endif
64 if (irq_status & HDLCD_INTERRUPT_VSYNC)
65 drm_crtc_handle_vblank(&hdlcd->crtc);
66
67 /* acknowledge interrupt(s) */
68 hdlcd_write(hdlcd, HDLCD_REG_INT_CLEAR, irq_status);
69
70 return IRQ_HANDLED;
71}
72
73static int hdlcd_irq_install(struct hdlcd_drm_private *hdlcd)
74{
75 int ret;
76
77 /* Ensure interrupts are disabled */
78 hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, 0);
79 hdlcd_write(hdlcd, HDLCD_REG_INT_CLEAR, ~0);
80
81 ret = request_irq(hdlcd->irq, hdlcd_irq, 0, "hdlcd", hdlcd);
82 if (ret)
83 return ret;
84
85#ifdef CONFIG_DEBUG_FS
86 /* enable debug interrupts */
87 hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, HDLCD_DEBUG_INT_MASK);
88#endif
89
90 return 0;
91}
92
93static void hdlcd_irq_uninstall(struct hdlcd_drm_private *hdlcd)
94{
95 /* disable all the interrupts that we might have enabled */
96 hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, 0);
97
98 free_irq(hdlcd->irq, hdlcd);
99}
100
101static int hdlcd_load(struct drm_device *drm, unsigned long flags)
102{
103 struct hdlcd_drm_private *hdlcd = drm_to_hdlcd_priv(drm);
104 struct platform_device *pdev = to_platform_device(drm->dev);
105 u32 version;
106 int ret;
107
108 hdlcd->clk = devm_clk_get(drm->dev, "pxlclk");
109 if (IS_ERR(hdlcd->clk))
110 return PTR_ERR(hdlcd->clk);
111
112#ifdef CONFIG_DEBUG_FS
113 atomic_set(&hdlcd->buffer_underrun_count, 0);
114 atomic_set(&hdlcd->bus_error_count, 0);
115 atomic_set(&hdlcd->vsync_count, 0);
116 atomic_set(&hdlcd->dma_end_count, 0);
117#endif
118
119 hdlcd->mmio = devm_platform_ioremap_resource(pdev, 0);
120 if (IS_ERR(hdlcd->mmio)) {
121 DRM_ERROR("failed to map control registers area\n");
122 ret = PTR_ERR(hdlcd->mmio);
123 hdlcd->mmio = NULL;
124 return ret;
125 }
126
127 version = hdlcd_read(hdlcd, HDLCD_REG_VERSION);
128 if ((version & HDLCD_PRODUCT_MASK) != HDLCD_PRODUCT_ID) {
129 DRM_ERROR("unknown product id: 0x%x\n", version);
130 return -EINVAL;
131 }
132 DRM_INFO("found ARM HDLCD version r%dp%d\n",
133 (version & HDLCD_VERSION_MAJOR_MASK) >> 8,
134 version & HDLCD_VERSION_MINOR_MASK);
135
136 /* Get the optional framebuffer memory resource */
137 ret = of_reserved_mem_device_init(drm->dev);
138 if (ret && ret != -ENODEV)
139 return ret;
140
141 ret = dma_set_mask_and_coherent(drm->dev, DMA_BIT_MASK(32));
142 if (ret)
143 goto setup_fail;
144
145 ret = hdlcd_setup_crtc(drm);
146 if (ret < 0) {
147 DRM_ERROR("failed to create crtc\n");
148 goto setup_fail;
149 }
150
151 ret = platform_get_irq(pdev, 0);
152 if (ret < 0)
153 goto irq_fail;
154 hdlcd->irq = ret;
155
156 ret = hdlcd_irq_install(hdlcd);
157 if (ret < 0) {
158 DRM_ERROR("failed to install IRQ handler\n");
159 goto irq_fail;
160 }
161
162 return 0;
163
164irq_fail:
165 drm_crtc_cleanup(&hdlcd->crtc);
166setup_fail:
167 of_reserved_mem_device_release(drm->dev);
168
169 return ret;
170}
171
172static const struct drm_mode_config_funcs hdlcd_mode_config_funcs = {
173 .fb_create = drm_gem_fb_create,
174 .atomic_check = drm_atomic_helper_check,
175 .atomic_commit = drm_atomic_helper_commit,
176};
177
178static int hdlcd_setup_mode_config(struct drm_device *drm)
179{
180 int ret;
181
182 ret = drmm_mode_config_init(drm);
183 if (ret)
184 return ret;
185
186 drm->mode_config.min_width = 0;
187 drm->mode_config.min_height = 0;
188 drm->mode_config.max_width = HDLCD_MAX_XRES;
189 drm->mode_config.max_height = HDLCD_MAX_YRES;
190 drm->mode_config.funcs = &hdlcd_mode_config_funcs;
191
192 return 0;
193}
194
195#ifdef CONFIG_DEBUG_FS
196static int hdlcd_show_underrun_count(struct seq_file *m, void *arg)
197{
198 struct drm_debugfs_entry *entry = m->private;
199 struct drm_device *drm = entry->dev;
200 struct hdlcd_drm_private *hdlcd = drm_to_hdlcd_priv(drm);
201
202 seq_printf(m, "underrun : %d\n", atomic_read(&hdlcd->buffer_underrun_count));
203 seq_printf(m, "dma_end : %d\n", atomic_read(&hdlcd->dma_end_count));
204 seq_printf(m, "bus_error: %d\n", atomic_read(&hdlcd->bus_error_count));
205 seq_printf(m, "vsync : %d\n", atomic_read(&hdlcd->vsync_count));
206 return 0;
207}
208
209static int hdlcd_show_pxlclock(struct seq_file *m, void *arg)
210{
211 struct drm_debugfs_entry *entry = m->private;
212 struct drm_device *drm = entry->dev;
213 struct hdlcd_drm_private *hdlcd = drm_to_hdlcd_priv(drm);
214 unsigned long clkrate = clk_get_rate(hdlcd->clk);
215 unsigned long mode_clock = hdlcd->crtc.mode.crtc_clock * 1000;
216
217 seq_printf(m, "hw : %lu\n", clkrate);
218 seq_printf(m, "mode: %lu\n", mode_clock);
219 return 0;
220}
221
222static struct drm_debugfs_info hdlcd_debugfs_list[] = {
223 { "interrupt_count", hdlcd_show_underrun_count, 0 },
224 { "clocks", hdlcd_show_pxlclock, 0 },
225};
226#endif
227
228DEFINE_DRM_GEM_DMA_FOPS(fops);
229
230static const struct drm_driver hdlcd_driver = {
231 .driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
232 DRM_GEM_DMA_DRIVER_OPS,
233 DRM_FBDEV_DMA_DRIVER_OPS,
234 .fops = &fops,
235 .name = "hdlcd",
236 .desc = "ARM HDLCD Controller DRM",
237 .major = 1,
238 .minor = 0,
239};
240
241static int hdlcd_drm_bind(struct device *dev)
242{
243 struct drm_device *drm;
244 struct hdlcd_drm_private *hdlcd;
245 int ret;
246
247 hdlcd = devm_drm_dev_alloc(dev, &hdlcd_driver, typeof(*hdlcd), base);
248 if (IS_ERR(hdlcd))
249 return PTR_ERR(hdlcd);
250
251 drm = &hdlcd->base;
252
253 dev_set_drvdata(dev, drm);
254
255 ret = hdlcd_setup_mode_config(drm);
256 if (ret)
257 goto err_free;
258
259 ret = hdlcd_load(drm, 0);
260 if (ret)
261 goto err_free;
262
263 /* Set the CRTC's port so that the encoder component can find it */
264 hdlcd->crtc.port = of_graph_get_port_by_id(dev->of_node, 0);
265
266 ret = component_bind_all(dev, drm);
267 if (ret) {
268 DRM_ERROR("Failed to bind all components\n");
269 goto err_unload;
270 }
271
272 ret = pm_runtime_set_active(dev);
273 if (ret)
274 goto err_pm_active;
275
276 pm_runtime_enable(dev);
277
278 ret = drm_vblank_init(drm, drm->mode_config.num_crtc);
279 if (ret < 0) {
280 DRM_ERROR("failed to initialise vblank\n");
281 goto err_vblank;
282 }
283
284 /*
285 * If EFI left us running, take over from simple framebuffer
286 * drivers. Read HDLCD_REG_COMMAND to see if we are enabled.
287 */
288 if (hdlcd_read(hdlcd, HDLCD_REG_COMMAND)) {
289 hdlcd_write(hdlcd, HDLCD_REG_COMMAND, 0);
290 aperture_remove_all_conflicting_devices(hdlcd_driver.name);
291 }
292
293 drm_mode_config_reset(drm);
294 drm_kms_helper_poll_init(drm);
295
296#ifdef CONFIG_DEBUG_FS
297 drm_debugfs_add_files(drm, hdlcd_debugfs_list, ARRAY_SIZE(hdlcd_debugfs_list));
298#endif
299
300 ret = drm_dev_register(drm, 0);
301 if (ret)
302 goto err_register;
303
304 drm_client_setup(drm, NULL);
305
306 return 0;
307
308err_register:
309 drm_kms_helper_poll_fini(drm);
310err_vblank:
311 pm_runtime_disable(drm->dev);
312err_pm_active:
313 drm_atomic_helper_shutdown(drm);
314 component_unbind_all(dev, drm);
315err_unload:
316 of_node_put(hdlcd->crtc.port);
317 hdlcd->crtc.port = NULL;
318 hdlcd_irq_uninstall(hdlcd);
319 of_reserved_mem_device_release(drm->dev);
320err_free:
321 dev_set_drvdata(dev, NULL);
322 return ret;
323}
324
325static void hdlcd_drm_unbind(struct device *dev)
326{
327 struct drm_device *drm = dev_get_drvdata(dev);
328 struct hdlcd_drm_private *hdlcd = drm_to_hdlcd_priv(drm);
329
330 drm_dev_unregister(drm);
331 drm_kms_helper_poll_fini(drm);
332 component_unbind_all(dev, drm);
333 of_node_put(hdlcd->crtc.port);
334 hdlcd->crtc.port = NULL;
335 pm_runtime_get_sync(dev);
336 drm_atomic_helper_shutdown(drm);
337 hdlcd_irq_uninstall(hdlcd);
338 pm_runtime_put(dev);
339 if (pm_runtime_enabled(dev))
340 pm_runtime_disable(dev);
341 of_reserved_mem_device_release(dev);
342 dev_set_drvdata(dev, NULL);
343}
344
345static const struct component_master_ops hdlcd_master_ops = {
346 .bind = hdlcd_drm_bind,
347 .unbind = hdlcd_drm_unbind,
348};
349
350static int compare_dev(struct device *dev, void *data)
351{
352 return dev->of_node == data;
353}
354
355static int hdlcd_probe(struct platform_device *pdev)
356{
357 struct device_node *port;
358 struct component_match *match = NULL;
359
360 /* there is only one output port inside each device, find it */
361 port = of_graph_get_remote_node(pdev->dev.of_node, 0, 0);
362 if (!port)
363 return -ENODEV;
364
365 drm_of_component_match_add(&pdev->dev, &match, compare_dev, port);
366 of_node_put(port);
367
368 return component_master_add_with_match(&pdev->dev, &hdlcd_master_ops,
369 match);
370}
371
372static void hdlcd_remove(struct platform_device *pdev)
373{
374 component_master_del(&pdev->dev, &hdlcd_master_ops);
375}
376
377static void hdlcd_shutdown(struct platform_device *pdev)
378{
379 drm_atomic_helper_shutdown(platform_get_drvdata(pdev));
380}
381
382static const struct of_device_id hdlcd_of_match[] = {
383 { .compatible = "arm,hdlcd" },
384 {},
385};
386MODULE_DEVICE_TABLE(of, hdlcd_of_match);
387
388static int __maybe_unused hdlcd_pm_suspend(struct device *dev)
389{
390 struct drm_device *drm = dev_get_drvdata(dev);
391
392 return drm_mode_config_helper_suspend(drm);
393}
394
395static int __maybe_unused hdlcd_pm_resume(struct device *dev)
396{
397 struct drm_device *drm = dev_get_drvdata(dev);
398
399 drm_mode_config_helper_resume(drm);
400
401 return 0;
402}
403
404static SIMPLE_DEV_PM_OPS(hdlcd_pm_ops, hdlcd_pm_suspend, hdlcd_pm_resume);
405
406static struct platform_driver hdlcd_platform_driver = {
407 .probe = hdlcd_probe,
408 .remove = hdlcd_remove,
409 .shutdown = hdlcd_shutdown,
410 .driver = {
411 .name = "hdlcd",
412 .pm = &hdlcd_pm_ops,
413 .of_match_table = hdlcd_of_match,
414 },
415};
416
417drm_module_platform_driver(hdlcd_platform_driver);
418
419MODULE_AUTHOR("Liviu Dudau");
420MODULE_DESCRIPTION("ARM HDLCD DRM driver");
421MODULE_LICENSE("GPL v2");