Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2025 Icenowy Zheng <uwu@icenowy.me>
4 *
5 * Based on rcar_dw_hdmi.c, which is:
6 * Copyright (C) 2016 Renesas Electronics Corporation
7 * Based on imx8mp-hdmi-tx.c, which is:
8 * Copyright (C) 2022 Pengutronix, Lucas Stach <kernel@pengutronix.de>
9 */
10
11#include <linux/clk.h>
12#include <linux/mod_devicetable.h>
13#include <linux/module.h>
14#include <linux/platform_device.h>
15#include <linux/reset.h>
16
17#include <drm/bridge/dw_hdmi.h>
18#include <drm/drm_modes.h>
19
20#define TH1520_HDMI_PHY_OPMODE_PLLCFG 0x06 /* Mode of operation and PLL dividers */
21#define TH1520_HDMI_PHY_CKSYMTXCTRL 0x09 /* Clock Symbol and Transmitter Control Register */
22#define TH1520_HDMI_PHY_VLEVCTRL 0x0e /* Voltage Level Control Register */
23#define TH1520_HDMI_PHY_PLLCURRGMPCTRL 0x10 /* PLL current and Gmp (conductance) */
24#define TH1520_HDMI_PHY_PLLDIVCTRL 0x11 /* PLL dividers */
25#define TH1520_HDMI_PHY_TXTERM 0x19 /* Transmission Termination Register */
26
27struct th1520_hdmi_phy_params {
28 unsigned long mpixelclock;
29 u16 opmode_pllcfg;
30 u16 pllcurrgmpctrl;
31 u16 plldivctrl;
32 u16 cksymtxctrl;
33 u16 vlevctrl;
34 u16 txterm;
35};
36
37static const struct th1520_hdmi_phy_params th1520_hdmi_phy_params[] = {
38 { 35500000, 0x0003, 0x0283, 0x0628, 0x8088, 0x01a0, 0x0007 },
39 { 44900000, 0x0003, 0x0285, 0x0228, 0x8088, 0x01a0, 0x0007 },
40 { 71000000, 0x0002, 0x1183, 0x0614, 0x8088, 0x01a0, 0x0007 },
41 { 90000000, 0x0002, 0x1142, 0x0214, 0x8088, 0x01a0, 0x0007 },
42 { 121750000, 0x0001, 0x20c0, 0x060a, 0x8088, 0x01a0, 0x0007 },
43 { 165000000, 0x0001, 0x2080, 0x020a, 0x8088, 0x01a0, 0x0007 },
44 { 198000000, 0x0000, 0x3040, 0x0605, 0x83c8, 0x0120, 0x0004 },
45 { 297000000, 0x0000, 0x3041, 0x0205, 0x81dc, 0x0200, 0x0005 },
46 { 371250000, 0x0640, 0x3041, 0x0205, 0x80f6, 0x0140, 0x0000 },
47 { 495000000, 0x0640, 0x3080, 0x0005, 0x80f6, 0x0140, 0x0000 },
48 { 594000000, 0x0640, 0x3080, 0x0005, 0x80fa, 0x01e0, 0x0004 },
49};
50
51struct th1520_hdmi {
52 struct dw_hdmi_plat_data plat_data;
53 struct dw_hdmi *dw_hdmi;
54 struct clk *pixclk;
55 struct reset_control *mainrst, *prst;
56};
57
58static enum drm_mode_status
59th1520_hdmi_mode_valid(struct dw_hdmi *hdmi, void *data,
60 const struct drm_display_info *info,
61 const struct drm_display_mode *mode)
62{
63 /*
64 * The maximum supported clock frequency is 594 MHz, as shown in the PHY
65 * parameters table.
66 */
67 if (mode->clock > 594000)
68 return MODE_CLOCK_HIGH;
69
70 return MODE_OK;
71}
72
73static void th1520_hdmi_phy_set_params(struct dw_hdmi *hdmi,
74 const struct th1520_hdmi_phy_params *params)
75{
76 dw_hdmi_phy_i2c_write(hdmi, params->opmode_pllcfg,
77 TH1520_HDMI_PHY_OPMODE_PLLCFG);
78 dw_hdmi_phy_i2c_write(hdmi, params->pllcurrgmpctrl,
79 TH1520_HDMI_PHY_PLLCURRGMPCTRL);
80 dw_hdmi_phy_i2c_write(hdmi, params->plldivctrl,
81 TH1520_HDMI_PHY_PLLDIVCTRL);
82 dw_hdmi_phy_i2c_write(hdmi, params->vlevctrl,
83 TH1520_HDMI_PHY_VLEVCTRL);
84 dw_hdmi_phy_i2c_write(hdmi, params->cksymtxctrl,
85 TH1520_HDMI_PHY_CKSYMTXCTRL);
86 dw_hdmi_phy_i2c_write(hdmi, params->txterm,
87 TH1520_HDMI_PHY_TXTERM);
88}
89
90static int th1520_hdmi_phy_configure(struct dw_hdmi *hdmi, void *data,
91 unsigned long mpixelclock)
92{
93 unsigned int i;
94
95 for (i = 0; i < ARRAY_SIZE(th1520_hdmi_phy_params); i++) {
96 if (mpixelclock <= th1520_hdmi_phy_params[i].mpixelclock) {
97 th1520_hdmi_phy_set_params(hdmi,
98 &th1520_hdmi_phy_params[i]);
99 return 0;
100 }
101 }
102
103 return -EINVAL;
104}
105
106static int th1520_dw_hdmi_probe(struct platform_device *pdev)
107{
108 struct th1520_hdmi *hdmi;
109 struct dw_hdmi_plat_data *plat_data;
110 struct device *dev = &pdev->dev;
111
112 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
113 if (!hdmi)
114 return -ENOMEM;
115
116 plat_data = &hdmi->plat_data;
117
118 hdmi->pixclk = devm_clk_get_enabled(dev, "pix");
119 if (IS_ERR(hdmi->pixclk))
120 return dev_err_probe(dev, PTR_ERR(hdmi->pixclk),
121 "Unable to get pixel clock\n");
122
123 hdmi->mainrst = devm_reset_control_get_exclusive_deasserted(dev, "main");
124 if (IS_ERR(hdmi->mainrst))
125 return dev_err_probe(dev, PTR_ERR(hdmi->mainrst),
126 "Unable to get main reset\n");
127
128 hdmi->prst = devm_reset_control_get_exclusive_deasserted(dev, "apb");
129 if (IS_ERR(hdmi->prst))
130 return dev_err_probe(dev, PTR_ERR(hdmi->prst),
131 "Unable to get apb reset\n");
132
133 plat_data->output_port = 1;
134 plat_data->mode_valid = th1520_hdmi_mode_valid;
135 plat_data->configure_phy = th1520_hdmi_phy_configure;
136 plat_data->priv_data = hdmi;
137
138 hdmi->dw_hdmi = dw_hdmi_probe(pdev, plat_data);
139 if (IS_ERR(hdmi))
140 return PTR_ERR(hdmi);
141
142 platform_set_drvdata(pdev, hdmi);
143
144 return 0;
145}
146
147static void th1520_dw_hdmi_remove(struct platform_device *pdev)
148{
149 struct dw_hdmi *hdmi = platform_get_drvdata(pdev);
150
151 dw_hdmi_remove(hdmi);
152}
153
154static const struct of_device_id th1520_dw_hdmi_of_table[] = {
155 { .compatible = "thead,th1520-dw-hdmi" },
156 { /* Sentinel */ },
157};
158MODULE_DEVICE_TABLE(of, th1520_dw_hdmi_of_table);
159
160static struct platform_driver th1520_dw_hdmi_platform_driver = {
161 .probe = th1520_dw_hdmi_probe,
162 .remove = th1520_dw_hdmi_remove,
163 .driver = {
164 .name = "th1520-dw-hdmi",
165 .of_match_table = th1520_dw_hdmi_of_table,
166 },
167};
168
169module_platform_driver(th1520_dw_hdmi_platform_driver);
170
171MODULE_AUTHOR("Icenowy Zheng <uwu@icenowy.me>");
172MODULE_DESCRIPTION("T-Head TH1520 HDMI Encoder Driver");
173MODULE_LICENSE("GPL");