Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2015 MediaTek Inc.
4 */
5
6#include <linux/bitfield.h>
7#include <linux/clk.h>
8#include <linux/component.h>
9#include <linux/iopoll.h>
10#include <linux/irq.h>
11#include <linux/of.h>
12#include <linux/of_platform.h>
13#include <linux/phy/phy.h>
14#include <linux/platform_device.h>
15#include <linux/reset.h>
16#include <linux/units.h>
17
18#include <video/mipi_display.h>
19#include <video/videomode.h>
20
21#include <drm/drm_atomic_helper.h>
22#include <drm/drm_bridge.h>
23#include <drm/drm_bridge_connector.h>
24#include <drm/drm_mipi_dsi.h>
25#include <drm/drm_of.h>
26#include <drm/drm_panel.h>
27#include <drm/drm_print.h>
28#include <drm/drm_probe_helper.h>
29#include <drm/drm_simple_kms_helper.h>
30
31#include "mtk_ddp_comp.h"
32#include "mtk_disp_drv.h"
33#include "mtk_drm_drv.h"
34
35#define DSI_START 0x00
36
37#define DSI_INTEN 0x08
38
39#define DSI_INTSTA 0x0c
40#define LPRX_RD_RDY_INT_FLAG BIT(0)
41#define CMD_DONE_INT_FLAG BIT(1)
42#define TE_RDY_INT_FLAG BIT(2)
43#define VM_DONE_INT_FLAG BIT(3)
44#define EXT_TE_RDY_INT_FLAG BIT(4)
45#define DSI_BUSY BIT(31)
46
47#define DSI_CON_CTRL 0x10
48#define DSI_RESET BIT(0)
49#define DSI_EN BIT(1)
50#define DPHY_RESET BIT(2)
51
52#define DSI_MODE_CTRL 0x14
53#define MODE (3)
54#define CMD_MODE 0
55#define SYNC_PULSE_MODE 1
56#define SYNC_EVENT_MODE 2
57#define BURST_MODE 3
58#define FRM_MODE BIT(16)
59#define MIX_MODE BIT(17)
60
61#define DSI_TXRX_CTRL 0x18
62#define VC_NUM BIT(1)
63#define LANE_NUM GENMASK(5, 2)
64#define DIS_EOT BIT(6)
65#define NULL_EN BIT(7)
66#define TE_FREERUN BIT(8)
67#define EXT_TE_EN BIT(9)
68#define EXT_TE_EDGE BIT(10)
69#define MAX_RTN_SIZE GENMASK(15, 12)
70#define HSTX_CKLP_EN BIT(16)
71
72#define DSI_PSCTRL 0x1c
73#define DSI_PS_WC GENMASK(13, 0)
74#define DSI_PS_SEL GENMASK(17, 16)
75#define PACKED_PS_16BIT_RGB565 0
76#define PACKED_PS_18BIT_RGB666 1
77#define LOOSELY_PS_24BIT_RGB666 2
78#define PACKED_PS_24BIT_RGB888 3
79
80#define DSI_VSA_NL 0x20
81#define DSI_VBP_NL 0x24
82#define DSI_VFP_NL 0x28
83#define DSI_VACT_NL 0x2C
84#define VACT_NL GENMASK(14, 0)
85#define DSI_SIZE_CON 0x38
86#define DSI_HEIGHT GENMASK(30, 16)
87#define DSI_WIDTH GENMASK(14, 0)
88#define DSI_HSA_WC 0x50
89#define DSI_HBP_WC 0x54
90#define DSI_HFP_WC 0x58
91#define HFP_HS_VB_PS_WC GENMASK(30, 16)
92#define HFP_HS_EN BIT(31)
93
94#define DSI_CMDQ_SIZE 0x60
95#define CMDQ_SIZE 0x3f
96#define CMDQ_SIZE_SEL BIT(15)
97
98#define DSI_HSTX_CKL_WC 0x64
99#define HSTX_CKL_WC GENMASK(15, 2)
100
101#define DSI_RX_DATA0 0x74
102#define DSI_RX_DATA1 0x78
103#define DSI_RX_DATA2 0x7c
104#define DSI_RX_DATA3 0x80
105
106#define DSI_RACK 0x84
107#define RACK BIT(0)
108
109#define DSI_PHY_LCCON 0x104
110#define LC_HS_TX_EN BIT(0)
111#define LC_ULPM_EN BIT(1)
112#define LC_WAKEUP_EN BIT(2)
113
114#define DSI_PHY_LD0CON 0x108
115#define LD0_HS_TX_EN BIT(0)
116#define LD0_ULPM_EN BIT(1)
117#define LD0_WAKEUP_EN BIT(2)
118
119#define DSI_PHY_TIMECON0 0x110
120#define LPX GENMASK(7, 0)
121#define HS_PREP GENMASK(15, 8)
122#define HS_ZERO GENMASK(23, 16)
123#define HS_TRAIL GENMASK(31, 24)
124
125#define DSI_PHY_TIMECON1 0x114
126#define TA_GO GENMASK(7, 0)
127#define TA_SURE GENMASK(15, 8)
128#define TA_GET GENMASK(23, 16)
129#define DA_HS_EXIT GENMASK(31, 24)
130
131#define DSI_PHY_TIMECON2 0x118
132#define CONT_DET GENMASK(7, 0)
133#define DA_HS_SYNC GENMASK(15, 8)
134#define CLK_ZERO GENMASK(23, 16)
135#define CLK_TRAIL GENMASK(31, 24)
136
137#define DSI_PHY_TIMECON3 0x11c
138#define CLK_HS_PREP GENMASK(7, 0)
139#define CLK_HS_POST GENMASK(15, 8)
140#define CLK_HS_EXIT GENMASK(23, 16)
141
142/* DSI_VM_CMD_CON */
143#define VM_CMD_EN BIT(0)
144#define TS_VFP_EN BIT(5)
145
146/* DSI_SHADOW_DEBUG */
147#define FORCE_COMMIT BIT(0)
148#define BYPASS_SHADOW BIT(1)
149
150/* CMDQ related bits */
151#define CONFIG GENMASK(7, 0)
152#define SHORT_PACKET 0
153#define LONG_PACKET 2
154#define BTA BIT(2)
155#define HSTX BIT(3)
156#define DATA_ID GENMASK(15, 8)
157#define DATA_0 GENMASK(23, 16)
158#define DATA_1 GENMASK(31, 24)
159
160#define NS_TO_CYCLE(n, c) ((n) / (c) + (((n) % (c)) ? 1 : 0))
161
162#define MTK_DSI_HOST_IS_READ(type) \
163 ((type == MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM) || \
164 (type == MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM) || \
165 (type == MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM) || \
166 (type == MIPI_DSI_DCS_READ))
167
168struct mtk_phy_timing {
169 u32 lpx;
170 u32 da_hs_prepare;
171 u32 da_hs_zero;
172 u32 da_hs_trail;
173
174 u32 ta_go;
175 u32 ta_sure;
176 u32 ta_get;
177 u32 da_hs_exit;
178
179 u32 clk_hs_zero;
180 u32 clk_hs_trail;
181
182 u32 clk_hs_prepare;
183 u32 clk_hs_post;
184 u32 clk_hs_exit;
185};
186
187struct phy;
188
189struct mtk_dsi_driver_data {
190 const u32 reg_cmdq_off;
191 const u32 reg_vm_cmd_off;
192 const u32 reg_shadow_dbg_off;
193 bool has_shadow_ctl;
194 bool has_size_ctl;
195 bool cmdq_long_packet_ctl;
196 bool support_per_frame_lp;
197};
198
199struct mtk_dsi {
200 struct device *dev;
201 struct mipi_dsi_host host;
202 struct drm_encoder encoder;
203 struct drm_bridge bridge;
204 struct drm_bridge *next_bridge;
205 struct drm_connector *connector;
206 struct phy *phy;
207
208 void __iomem *regs;
209
210 struct clk *engine_clk;
211 struct clk *digital_clk;
212 struct clk *hs_clk;
213
214 u32 data_rate;
215
216 unsigned long mode_flags;
217 enum mipi_dsi_pixel_format format;
218 unsigned int lanes;
219 struct videomode vm;
220 struct mtk_phy_timing phy_timing;
221 int refcount;
222 bool enabled;
223 bool lanes_ready;
224 u32 irq_data;
225 wait_queue_head_t irq_wait_queue;
226 const struct mtk_dsi_driver_data *driver_data;
227};
228
229static inline struct mtk_dsi *bridge_to_dsi(struct drm_bridge *b)
230{
231 return container_of(b, struct mtk_dsi, bridge);
232}
233
234static inline struct mtk_dsi *host_to_dsi(struct mipi_dsi_host *h)
235{
236 return container_of(h, struct mtk_dsi, host);
237}
238
239static void mtk_dsi_mask(struct mtk_dsi *dsi, u32 offset, u32 mask, u32 data)
240{
241 u32 temp = readl(dsi->regs + offset);
242
243 writel((temp & ~mask) | (data & mask), dsi->regs + offset);
244}
245
246static void mtk_dsi_phy_timconfig(struct mtk_dsi *dsi)
247{
248 u32 timcon0, timcon1, timcon2, timcon3;
249 u32 data_rate_mhz = DIV_ROUND_UP(dsi->data_rate, HZ_PER_MHZ);
250 struct mtk_phy_timing *timing = &dsi->phy_timing;
251
252 timing->lpx = (60 * data_rate_mhz / (8 * 1000)) + 1;
253 timing->da_hs_prepare = (80 * data_rate_mhz + 4 * 1000) / 8000;
254 timing->da_hs_zero = (170 * data_rate_mhz + 10 * 1000) / 8000 + 1 -
255 timing->da_hs_prepare;
256 timing->da_hs_trail = timing->da_hs_prepare + 1;
257
258 timing->ta_go = 4 * timing->lpx - 2;
259 timing->ta_sure = timing->lpx + 2;
260 timing->ta_get = 4 * timing->lpx;
261 timing->da_hs_exit = 2 * timing->lpx + 1;
262
263 timing->clk_hs_prepare = 70 * data_rate_mhz / (8 * 1000);
264 timing->clk_hs_post = timing->clk_hs_prepare + 8;
265 timing->clk_hs_trail = timing->clk_hs_prepare;
266 timing->clk_hs_zero = timing->clk_hs_trail * 4;
267 timing->clk_hs_exit = 2 * timing->clk_hs_trail;
268
269 timcon0 = FIELD_PREP(LPX, timing->lpx) |
270 FIELD_PREP(HS_PREP, timing->da_hs_prepare) |
271 FIELD_PREP(HS_ZERO, timing->da_hs_zero) |
272 FIELD_PREP(HS_TRAIL, timing->da_hs_trail);
273
274 timcon1 = FIELD_PREP(TA_GO, timing->ta_go) |
275 FIELD_PREP(TA_SURE, timing->ta_sure) |
276 FIELD_PREP(TA_GET, timing->ta_get) |
277 FIELD_PREP(DA_HS_EXIT, timing->da_hs_exit);
278
279 timcon2 = FIELD_PREP(DA_HS_SYNC, 1) |
280 FIELD_PREP(CLK_ZERO, timing->clk_hs_zero) |
281 FIELD_PREP(CLK_TRAIL, timing->clk_hs_trail);
282
283 timcon3 = FIELD_PREP(CLK_HS_PREP, timing->clk_hs_prepare) |
284 FIELD_PREP(CLK_HS_POST, timing->clk_hs_post) |
285 FIELD_PREP(CLK_HS_EXIT, timing->clk_hs_exit);
286
287 writel(timcon0, dsi->regs + DSI_PHY_TIMECON0);
288 writel(timcon1, dsi->regs + DSI_PHY_TIMECON1);
289 writel(timcon2, dsi->regs + DSI_PHY_TIMECON2);
290 writel(timcon3, dsi->regs + DSI_PHY_TIMECON3);
291}
292
293static void mtk_dsi_enable(struct mtk_dsi *dsi)
294{
295 mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_EN, DSI_EN);
296}
297
298static void mtk_dsi_disable(struct mtk_dsi *dsi)
299{
300 mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_EN, 0);
301}
302
303static void mtk_dsi_reset_engine(struct mtk_dsi *dsi)
304{
305 mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_RESET, DSI_RESET);
306 mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_RESET, 0);
307}
308
309static void mtk_dsi_reset_dphy(struct mtk_dsi *dsi)
310{
311 mtk_dsi_mask(dsi, DSI_CON_CTRL, DPHY_RESET, DPHY_RESET);
312 mtk_dsi_mask(dsi, DSI_CON_CTRL, DPHY_RESET, 0);
313}
314
315static void mtk_dsi_clk_ulp_mode_enter(struct mtk_dsi *dsi)
316{
317 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, 0);
318 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_ULPM_EN, 0);
319}
320
321static void mtk_dsi_clk_ulp_mode_leave(struct mtk_dsi *dsi)
322{
323 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_ULPM_EN, 0);
324 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_WAKEUP_EN, LC_WAKEUP_EN);
325 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_WAKEUP_EN, 0);
326}
327
328static void mtk_dsi_lane0_ulp_mode_enter(struct mtk_dsi *dsi)
329{
330 mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_HS_TX_EN, 0);
331 mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_ULPM_EN, 0);
332}
333
334static void mtk_dsi_lane0_ulp_mode_leave(struct mtk_dsi *dsi)
335{
336 mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_ULPM_EN, 0);
337 mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_WAKEUP_EN, LD0_WAKEUP_EN);
338 mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_WAKEUP_EN, 0);
339}
340
341static bool mtk_dsi_clk_hs_state(struct mtk_dsi *dsi)
342{
343 return readl(dsi->regs + DSI_PHY_LCCON) & LC_HS_TX_EN;
344}
345
346static void mtk_dsi_clk_hs_mode(struct mtk_dsi *dsi, bool enter)
347{
348 if (enter && !mtk_dsi_clk_hs_state(dsi))
349 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, LC_HS_TX_EN);
350 else if (!enter && mtk_dsi_clk_hs_state(dsi))
351 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, 0);
352}
353
354static void mtk_dsi_set_mode(struct mtk_dsi *dsi)
355{
356 u32 vid_mode = CMD_MODE;
357
358 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
359 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
360 vid_mode = BURST_MODE;
361 else if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
362 vid_mode = SYNC_PULSE_MODE;
363 else
364 vid_mode = SYNC_EVENT_MODE;
365 }
366
367 writel(vid_mode, dsi->regs + DSI_MODE_CTRL);
368}
369
370static void mtk_dsi_set_vm_cmd(struct mtk_dsi *dsi)
371{
372 mtk_dsi_mask(dsi, dsi->driver_data->reg_vm_cmd_off, VM_CMD_EN, VM_CMD_EN);
373 mtk_dsi_mask(dsi, dsi->driver_data->reg_vm_cmd_off, TS_VFP_EN, TS_VFP_EN);
374}
375
376static void mtk_dsi_rxtx_control(struct mtk_dsi *dsi)
377{
378 u32 regval, tmp_reg = 0;
379 u8 i;
380
381 /* Number of DSI lanes (max 4 lanes), each bit enables one DSI lane. */
382 for (i = 0; i < dsi->lanes; i++)
383 tmp_reg |= BIT(i);
384
385 regval = FIELD_PREP(LANE_NUM, tmp_reg);
386
387 if (dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)
388 regval |= HSTX_CKLP_EN;
389
390 if (dsi->mode_flags & MIPI_DSI_MODE_NO_EOT_PACKET)
391 regval |= DIS_EOT;
392
393 writel(regval, dsi->regs + DSI_TXRX_CTRL);
394}
395
396static void mtk_dsi_ps_control(struct mtk_dsi *dsi, bool config_vact)
397{
398 u32 dsi_buf_bpp, ps_val, ps_wc, vact_nl;
399
400 if (dsi->format == MIPI_DSI_FMT_RGB565)
401 dsi_buf_bpp = 2;
402 else
403 dsi_buf_bpp = 3;
404
405 /* Word count */
406 ps_wc = FIELD_PREP(DSI_PS_WC, dsi->vm.hactive * dsi_buf_bpp);
407 ps_val = ps_wc;
408
409 /* Pixel Stream type */
410 switch (dsi->format) {
411 default:
412 fallthrough;
413 case MIPI_DSI_FMT_RGB888:
414 ps_val |= FIELD_PREP(DSI_PS_SEL, PACKED_PS_24BIT_RGB888);
415 break;
416 case MIPI_DSI_FMT_RGB666:
417 ps_val |= FIELD_PREP(DSI_PS_SEL, LOOSELY_PS_24BIT_RGB666);
418 break;
419 case MIPI_DSI_FMT_RGB666_PACKED:
420 ps_val |= FIELD_PREP(DSI_PS_SEL, PACKED_PS_18BIT_RGB666);
421 break;
422 case MIPI_DSI_FMT_RGB565:
423 ps_val |= FIELD_PREP(DSI_PS_SEL, PACKED_PS_16BIT_RGB565);
424 break;
425 }
426
427 if (config_vact) {
428 vact_nl = FIELD_PREP(VACT_NL, dsi->vm.vactive);
429 writel(vact_nl, dsi->regs + DSI_VACT_NL);
430 writel(ps_wc, dsi->regs + DSI_HSTX_CKL_WC);
431 }
432 writel(ps_val, dsi->regs + DSI_PSCTRL);
433}
434
435static void mtk_dsi_config_vdo_timing_per_frame_lp(struct mtk_dsi *dsi)
436{
437 u32 horizontal_sync_active_byte;
438 u32 horizontal_backporch_byte;
439 u32 horizontal_frontporch_byte;
440 u32 hfp_byte_adjust, v_active_adjust;
441 u32 cklp_wc_min_adjust, cklp_wc_max_adjust;
442 u32 dsi_tmp_buf_bpp;
443 unsigned int da_hs_trail;
444 unsigned int ps_wc, hs_vb_ps_wc;
445 u32 v_active_roundup, hstx_cklp_wc;
446 u32 hstx_cklp_wc_max, hstx_cklp_wc_min;
447 struct videomode *vm = &dsi->vm;
448
449 if (dsi->format == MIPI_DSI_FMT_RGB565)
450 dsi_tmp_buf_bpp = 2;
451 else
452 dsi_tmp_buf_bpp = 3;
453
454 da_hs_trail = dsi->phy_timing.da_hs_trail;
455 ps_wc = vm->hactive * dsi_tmp_buf_bpp;
456
457 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) {
458 horizontal_sync_active_byte =
459 vm->hsync_len * dsi_tmp_buf_bpp - 10;
460 horizontal_backporch_byte =
461 vm->hback_porch * dsi_tmp_buf_bpp - 10;
462 hfp_byte_adjust = 12;
463 v_active_adjust = 32 + horizontal_sync_active_byte;
464 cklp_wc_min_adjust = 12 + 2 + 4 + horizontal_sync_active_byte;
465 cklp_wc_max_adjust = 20 + 6 + 4 + horizontal_sync_active_byte;
466 } else {
467 horizontal_sync_active_byte = vm->hsync_len * dsi_tmp_buf_bpp - 4;
468 horizontal_backporch_byte = (vm->hback_porch + vm->hsync_len) *
469 dsi_tmp_buf_bpp - 10;
470 cklp_wc_min_adjust = 4;
471 cklp_wc_max_adjust = 12 + 4 + 4;
472 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) {
473 hfp_byte_adjust = 18;
474 v_active_adjust = 28;
475 } else {
476 hfp_byte_adjust = 12;
477 v_active_adjust = 22;
478 }
479 }
480 horizontal_frontporch_byte = vm->hfront_porch * dsi_tmp_buf_bpp - hfp_byte_adjust;
481 v_active_roundup = (v_active_adjust + horizontal_backporch_byte + ps_wc +
482 horizontal_frontporch_byte) % dsi->lanes;
483 if (v_active_roundup)
484 horizontal_backporch_byte += dsi->lanes - v_active_roundup;
485 hstx_cklp_wc_min = (DIV_ROUND_UP(cklp_wc_min_adjust, dsi->lanes) + da_hs_trail + 1)
486 * dsi->lanes / 6 - 1;
487 hstx_cklp_wc_max = (DIV_ROUND_UP((cklp_wc_max_adjust + horizontal_backporch_byte +
488 ps_wc), dsi->lanes) + da_hs_trail + 1) * dsi->lanes / 6 - 1;
489
490 hstx_cklp_wc = FIELD_PREP(HSTX_CKL_WC, (hstx_cklp_wc_min + hstx_cklp_wc_max) / 2);
491 writel(hstx_cklp_wc, dsi->regs + DSI_HSTX_CKL_WC);
492
493 hs_vb_ps_wc = ps_wc - (dsi->phy_timing.lpx + dsi->phy_timing.da_hs_exit +
494 dsi->phy_timing.da_hs_prepare + dsi->phy_timing.da_hs_zero + 2) * dsi->lanes;
495 horizontal_frontporch_byte |= FIELD_PREP(HFP_HS_EN, 1) |
496 FIELD_PREP(HFP_HS_VB_PS_WC, hs_vb_ps_wc);
497
498 writel(horizontal_sync_active_byte, dsi->regs + DSI_HSA_WC);
499 writel(horizontal_backporch_byte, dsi->regs + DSI_HBP_WC);
500 writel(horizontal_frontporch_byte, dsi->regs + DSI_HFP_WC);
501}
502
503static void mtk_dsi_config_vdo_timing_per_line_lp(struct mtk_dsi *dsi)
504{
505 u32 horizontal_sync_active_byte;
506 u32 horizontal_backporch_byte;
507 u32 horizontal_frontporch_byte;
508 u32 horizontal_front_back_byte;
509 u32 data_phy_cycles_byte;
510 u32 dsi_tmp_buf_bpp, data_phy_cycles;
511 u32 delta;
512 struct mtk_phy_timing *timing = &dsi->phy_timing;
513 struct videomode *vm = &dsi->vm;
514
515 if (dsi->format == MIPI_DSI_FMT_RGB565)
516 dsi_tmp_buf_bpp = 2;
517 else
518 dsi_tmp_buf_bpp = 3;
519
520 horizontal_sync_active_byte = (vm->hsync_len * dsi_tmp_buf_bpp - 10);
521
522 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
523 horizontal_backporch_byte = vm->hback_porch * dsi_tmp_buf_bpp - 10;
524 else
525 horizontal_backporch_byte = (vm->hback_porch + vm->hsync_len) *
526 dsi_tmp_buf_bpp - 10;
527
528 data_phy_cycles = timing->lpx + timing->da_hs_prepare +
529 timing->da_hs_zero + timing->da_hs_exit + 3;
530
531 delta = dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST ? 18 : 12;
532 delta += dsi->mode_flags & MIPI_DSI_MODE_NO_EOT_PACKET ? 0 : 2;
533
534 horizontal_frontporch_byte = vm->hfront_porch * dsi_tmp_buf_bpp;
535 horizontal_front_back_byte = horizontal_frontporch_byte + horizontal_backporch_byte;
536 data_phy_cycles_byte = data_phy_cycles * dsi->lanes + delta;
537
538 if (horizontal_front_back_byte > data_phy_cycles_byte) {
539 horizontal_frontporch_byte -= data_phy_cycles_byte *
540 horizontal_frontporch_byte /
541 horizontal_front_back_byte;
542
543 horizontal_backporch_byte -= data_phy_cycles_byte *
544 horizontal_backporch_byte /
545 horizontal_front_back_byte;
546 } else {
547 DRM_WARN("HFP + HBP less than d-phy, FPS will under 60Hz\n");
548 }
549
550 if ((dsi->mode_flags & MIPI_DSI_HS_PKT_END_ALIGNED) &&
551 (dsi->lanes == 4)) {
552 horizontal_sync_active_byte =
553 roundup(horizontal_sync_active_byte, dsi->lanes) - 2;
554 horizontal_frontporch_byte =
555 roundup(horizontal_frontporch_byte, dsi->lanes) - 2;
556 horizontal_backporch_byte =
557 roundup(horizontal_backporch_byte, dsi->lanes) - 2;
558 horizontal_backporch_byte -=
559 (vm->hactive * dsi_tmp_buf_bpp + 2) % dsi->lanes;
560 }
561
562 writel(horizontal_sync_active_byte, dsi->regs + DSI_HSA_WC);
563 writel(horizontal_backporch_byte, dsi->regs + DSI_HBP_WC);
564 writel(horizontal_frontporch_byte, dsi->regs + DSI_HFP_WC);
565}
566
567static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi)
568{
569 struct videomode *vm = &dsi->vm;
570
571 writel(vm->vsync_len, dsi->regs + DSI_VSA_NL);
572 writel(vm->vback_porch, dsi->regs + DSI_VBP_NL);
573 writel(vm->vfront_porch, dsi->regs + DSI_VFP_NL);
574 writel(vm->vactive, dsi->regs + DSI_VACT_NL);
575
576 if (dsi->driver_data->has_size_ctl)
577 writel(FIELD_PREP(DSI_HEIGHT, vm->vactive) |
578 FIELD_PREP(DSI_WIDTH, vm->hactive),
579 dsi->regs + DSI_SIZE_CON);
580
581 if (dsi->driver_data->support_per_frame_lp)
582 mtk_dsi_config_vdo_timing_per_frame_lp(dsi);
583 else
584 mtk_dsi_config_vdo_timing_per_line_lp(dsi);
585
586 mtk_dsi_ps_control(dsi, false);
587}
588
589static void mtk_dsi_start(struct mtk_dsi *dsi)
590{
591 writel(0, dsi->regs + DSI_START);
592 writel(1, dsi->regs + DSI_START);
593}
594
595static void mtk_dsi_stop(struct mtk_dsi *dsi)
596{
597 writel(0, dsi->regs + DSI_START);
598}
599
600static void mtk_dsi_set_cmd_mode(struct mtk_dsi *dsi)
601{
602 writel(CMD_MODE, dsi->regs + DSI_MODE_CTRL);
603}
604
605static void mtk_dsi_set_interrupt_enable(struct mtk_dsi *dsi)
606{
607 u32 inten = LPRX_RD_RDY_INT_FLAG | CMD_DONE_INT_FLAG | VM_DONE_INT_FLAG;
608
609 writel(inten, dsi->regs + DSI_INTEN);
610}
611
612static void mtk_dsi_irq_data_set(struct mtk_dsi *dsi, u32 irq_bit)
613{
614 dsi->irq_data |= irq_bit;
615}
616
617static void mtk_dsi_irq_data_clear(struct mtk_dsi *dsi, u32 irq_bit)
618{
619 dsi->irq_data &= ~irq_bit;
620}
621
622static s32 mtk_dsi_wait_for_irq_done(struct mtk_dsi *dsi, u32 irq_flag,
623 unsigned int timeout)
624{
625 s32 ret = 0;
626 unsigned long jiffies = msecs_to_jiffies(timeout);
627
628 ret = wait_event_interruptible_timeout(dsi->irq_wait_queue,
629 dsi->irq_data & irq_flag,
630 jiffies);
631 if (ret == 0) {
632 DRM_WARN("Wait DSI IRQ(0x%08x) Timeout\n", irq_flag);
633
634 mtk_dsi_enable(dsi);
635 mtk_dsi_reset_engine(dsi);
636 }
637
638 return ret;
639}
640
641static irqreturn_t mtk_dsi_irq(int irq, void *dev_id)
642{
643 struct mtk_dsi *dsi = dev_id;
644 u32 status, tmp;
645 u32 flag = LPRX_RD_RDY_INT_FLAG | CMD_DONE_INT_FLAG | VM_DONE_INT_FLAG;
646
647 status = readl(dsi->regs + DSI_INTSTA) & flag;
648
649 if (status) {
650 do {
651 mtk_dsi_mask(dsi, DSI_RACK, RACK, RACK);
652 tmp = readl(dsi->regs + DSI_INTSTA);
653 } while (tmp & DSI_BUSY);
654
655 mtk_dsi_mask(dsi, DSI_INTSTA, status, 0);
656 mtk_dsi_irq_data_set(dsi, status);
657 wake_up_interruptible(&dsi->irq_wait_queue);
658 }
659
660 return IRQ_HANDLED;
661}
662
663static s32 mtk_dsi_switch_to_cmd_mode(struct mtk_dsi *dsi, u8 irq_flag, u32 t)
664{
665 mtk_dsi_irq_data_clear(dsi, irq_flag);
666 mtk_dsi_set_cmd_mode(dsi);
667
668 if (!mtk_dsi_wait_for_irq_done(dsi, irq_flag, t)) {
669 DRM_ERROR("failed to switch cmd mode\n");
670 return -ETIME;
671 } else {
672 return 0;
673 }
674}
675
676static void mtk_dsi_lane_ready(struct mtk_dsi *dsi)
677{
678 if (!dsi->lanes_ready) {
679 dsi->lanes_ready = true;
680 mtk_dsi_rxtx_control(dsi);
681 usleep_range(30, 100);
682 mtk_dsi_reset_dphy(dsi);
683 mtk_dsi_clk_ulp_mode_leave(dsi);
684 mtk_dsi_lane0_ulp_mode_leave(dsi);
685 mtk_dsi_clk_hs_mode(dsi, 0);
686 usleep_range(1000, 3000);
687 /* The reaction time after pulling up the mipi signal for dsi_rx */
688 }
689}
690
691static int mtk_dsi_poweron(struct mtk_dsi *dsi)
692{
693 struct device *dev = dsi->host.dev;
694 int ret;
695 u32 bit_per_pixel;
696
697 if (++dsi->refcount != 1)
698 return 0;
699
700 ret = mipi_dsi_pixel_format_to_bpp(dsi->format);
701 if (ret < 0) {
702 dev_err(dev, "Unknown MIPI DSI format %d\n", dsi->format);
703 return ret;
704 }
705 bit_per_pixel = ret;
706
707 dsi->data_rate = DIV_ROUND_UP_ULL(dsi->vm.pixelclock * bit_per_pixel,
708 dsi->lanes);
709
710 ret = clk_set_rate(dsi->hs_clk, dsi->data_rate);
711 if (ret < 0) {
712 dev_err(dev, "Failed to set data rate: %d\n", ret);
713 goto err_refcount;
714 }
715
716 phy_power_on(dsi->phy);
717
718 ret = clk_prepare_enable(dsi->engine_clk);
719 if (ret < 0) {
720 dev_err(dev, "Failed to enable engine clock: %d\n", ret);
721 goto err_phy_power_off;
722 }
723
724 ret = clk_prepare_enable(dsi->digital_clk);
725 if (ret < 0) {
726 dev_err(dev, "Failed to enable digital clock: %d\n", ret);
727 goto err_disable_engine_clk;
728 }
729
730 mtk_dsi_enable(dsi);
731
732 if (dsi->driver_data->has_shadow_ctl)
733 writel(FORCE_COMMIT | BYPASS_SHADOW,
734 dsi->regs + dsi->driver_data->reg_shadow_dbg_off);
735
736 mtk_dsi_reset_engine(dsi);
737 mtk_dsi_phy_timconfig(dsi);
738
739 mtk_dsi_ps_control(dsi, true);
740 mtk_dsi_set_vm_cmd(dsi);
741 mtk_dsi_config_vdo_timing(dsi);
742 mtk_dsi_set_interrupt_enable(dsi);
743 mtk_dsi_lane_ready(dsi);
744 mtk_dsi_clk_hs_mode(dsi, 1);
745
746 return 0;
747err_disable_engine_clk:
748 clk_disable_unprepare(dsi->engine_clk);
749err_phy_power_off:
750 phy_power_off(dsi->phy);
751err_refcount:
752 dsi->refcount--;
753 return ret;
754}
755
756static void mtk_dsi_poweroff(struct mtk_dsi *dsi)
757{
758 if (WARN_ON(dsi->refcount == 0))
759 return;
760
761 if (--dsi->refcount != 0)
762 return;
763
764 /*
765 * mtk_dsi_stop() and mtk_dsi_start() is asymmetric, since
766 * mtk_dsi_stop() should be called after mtk_crtc_atomic_disable(),
767 * which needs irq for vblank, and mtk_dsi_stop() will disable irq.
768 * mtk_dsi_start() needs to be called in mtk_output_dsi_enable(),
769 * after dsi is fully set.
770 */
771 mtk_dsi_stop(dsi);
772
773 mtk_dsi_switch_to_cmd_mode(dsi, VM_DONE_INT_FLAG, 500);
774 mtk_dsi_reset_engine(dsi);
775 mtk_dsi_lane0_ulp_mode_enter(dsi);
776 mtk_dsi_clk_ulp_mode_enter(dsi);
777 /* set the lane number as 0 to pull down mipi */
778 writel(0, dsi->regs + DSI_TXRX_CTRL);
779
780 mtk_dsi_disable(dsi);
781
782 clk_disable_unprepare(dsi->engine_clk);
783 clk_disable_unprepare(dsi->digital_clk);
784
785 phy_power_off(dsi->phy);
786
787 dsi->lanes_ready = false;
788}
789
790static void mtk_output_dsi_enable(struct mtk_dsi *dsi)
791{
792 if (dsi->enabled)
793 return;
794
795 mtk_dsi_set_mode(dsi);
796 mtk_dsi_start(dsi);
797
798 dsi->enabled = true;
799}
800
801static void mtk_output_dsi_disable(struct mtk_dsi *dsi)
802{
803 if (!dsi->enabled)
804 return;
805
806 dsi->enabled = false;
807}
808
809static int mtk_dsi_bridge_attach(struct drm_bridge *bridge,
810 struct drm_encoder *encoder,
811 enum drm_bridge_attach_flags flags)
812{
813 struct mtk_dsi *dsi = bridge_to_dsi(bridge);
814
815 /* Attach the panel or bridge to the dsi bridge */
816 return drm_bridge_attach(encoder, dsi->next_bridge,
817 &dsi->bridge, flags);
818}
819
820static void mtk_dsi_bridge_mode_set(struct drm_bridge *bridge,
821 const struct drm_display_mode *mode,
822 const struct drm_display_mode *adjusted)
823{
824 struct mtk_dsi *dsi = bridge_to_dsi(bridge);
825
826 drm_display_mode_to_videomode(adjusted, &dsi->vm);
827}
828
829static void mtk_dsi_bridge_atomic_disable(struct drm_bridge *bridge,
830 struct drm_atomic_state *state)
831{
832 struct mtk_dsi *dsi = bridge_to_dsi(bridge);
833
834 mtk_output_dsi_disable(dsi);
835}
836
837static void mtk_dsi_bridge_atomic_enable(struct drm_bridge *bridge,
838 struct drm_atomic_state *state)
839{
840 struct mtk_dsi *dsi = bridge_to_dsi(bridge);
841
842 if (dsi->refcount == 0)
843 return;
844
845 mtk_output_dsi_enable(dsi);
846}
847
848static void mtk_dsi_bridge_atomic_pre_enable(struct drm_bridge *bridge,
849 struct drm_atomic_state *state)
850{
851 struct mtk_dsi *dsi = bridge_to_dsi(bridge);
852 int ret;
853
854 ret = mtk_dsi_poweron(dsi);
855 if (ret < 0)
856 DRM_ERROR("failed to power on dsi\n");
857}
858
859static void mtk_dsi_bridge_atomic_post_disable(struct drm_bridge *bridge,
860 struct drm_atomic_state *state)
861{
862 struct mtk_dsi *dsi = bridge_to_dsi(bridge);
863
864 mtk_dsi_poweroff(dsi);
865}
866
867static enum drm_mode_status
868mtk_dsi_bridge_mode_valid(struct drm_bridge *bridge,
869 const struct drm_display_info *info,
870 const struct drm_display_mode *mode)
871{
872 struct mtk_dsi *dsi = bridge_to_dsi(bridge);
873 int bpp;
874
875 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
876 if (bpp < 0)
877 return MODE_ERROR;
878
879 if (mode->clock * bpp / dsi->lanes > 1500000)
880 return MODE_CLOCK_HIGH;
881
882 return MODE_OK;
883}
884
885static const struct drm_bridge_funcs mtk_dsi_bridge_funcs = {
886 .attach = mtk_dsi_bridge_attach,
887 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
888 .atomic_disable = mtk_dsi_bridge_atomic_disable,
889 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
890 .atomic_enable = mtk_dsi_bridge_atomic_enable,
891 .atomic_pre_enable = mtk_dsi_bridge_atomic_pre_enable,
892 .atomic_post_disable = mtk_dsi_bridge_atomic_post_disable,
893 .atomic_reset = drm_atomic_helper_bridge_reset,
894 .mode_valid = mtk_dsi_bridge_mode_valid,
895 .mode_set = mtk_dsi_bridge_mode_set,
896};
897
898void mtk_dsi_ddp_start(struct device *dev)
899{
900 struct mtk_dsi *dsi = dev_get_drvdata(dev);
901
902 mtk_dsi_poweron(dsi);
903}
904
905void mtk_dsi_ddp_stop(struct device *dev)
906{
907 struct mtk_dsi *dsi = dev_get_drvdata(dev);
908
909 mtk_dsi_poweroff(dsi);
910}
911
912static int mtk_dsi_encoder_init(struct drm_device *drm, struct mtk_dsi *dsi)
913{
914 int ret;
915
916 ret = drm_simple_encoder_init(drm, &dsi->encoder,
917 DRM_MODE_ENCODER_DSI);
918 if (ret) {
919 DRM_ERROR("Failed to encoder init to drm\n");
920 return ret;
921 }
922
923 ret = mtk_find_possible_crtcs(drm, dsi->host.dev);
924 if (ret < 0)
925 goto err_cleanup_encoder;
926 dsi->encoder.possible_crtcs = ret;
927
928 ret = drm_bridge_attach(&dsi->encoder, &dsi->bridge, NULL,
929 DRM_BRIDGE_ATTACH_NO_CONNECTOR);
930 if (ret)
931 goto err_cleanup_encoder;
932
933 dsi->connector = drm_bridge_connector_init(drm, &dsi->encoder);
934 if (IS_ERR(dsi->connector)) {
935 DRM_ERROR("Unable to create bridge connector\n");
936 ret = PTR_ERR(dsi->connector);
937 goto err_cleanup_encoder;
938 }
939 drm_connector_attach_encoder(dsi->connector, &dsi->encoder);
940
941 return 0;
942
943err_cleanup_encoder:
944 drm_encoder_cleanup(&dsi->encoder);
945 return ret;
946}
947
948unsigned int mtk_dsi_encoder_index(struct device *dev)
949{
950 struct mtk_dsi *dsi = dev_get_drvdata(dev);
951 unsigned int encoder_index = drm_encoder_index(&dsi->encoder);
952
953 dev_dbg(dev, "encoder index:%d\n", encoder_index);
954 return encoder_index;
955}
956
957static int mtk_dsi_bind(struct device *dev, struct device *master, void *data)
958{
959 int ret;
960 struct drm_device *drm = data;
961 struct mtk_dsi *dsi = dev_get_drvdata(dev);
962
963 ret = mtk_dsi_encoder_init(drm, dsi);
964 if (ret)
965 return ret;
966
967 return device_reset_optional(dev);
968}
969
970static void mtk_dsi_unbind(struct device *dev, struct device *master,
971 void *data)
972{
973 struct mtk_dsi *dsi = dev_get_drvdata(dev);
974
975 drm_encoder_cleanup(&dsi->encoder);
976}
977
978static const struct component_ops mtk_dsi_component_ops = {
979 .bind = mtk_dsi_bind,
980 .unbind = mtk_dsi_unbind,
981};
982
983static int mtk_dsi_host_attach(struct mipi_dsi_host *host,
984 struct mipi_dsi_device *device)
985{
986 struct mtk_dsi *dsi = host_to_dsi(host);
987 struct device *dev = host->dev;
988 int ret;
989
990 dsi->lanes = device->lanes;
991 dsi->format = device->format;
992 dsi->mode_flags = device->mode_flags;
993 dsi->next_bridge = devm_drm_of_get_bridge(dev, dev->of_node, 1, 0);
994 if (IS_ERR(dsi->next_bridge)) {
995 ret = PTR_ERR(dsi->next_bridge);
996 if (ret == -EPROBE_DEFER)
997 return ret;
998
999 /* Old devicetree has only one endpoint */
1000 dsi->next_bridge = devm_drm_of_get_bridge(dev, dev->of_node, 0, 0);
1001 if (IS_ERR(dsi->next_bridge))
1002 return PTR_ERR(dsi->next_bridge);
1003 }
1004
1005 drm_bridge_add(&dsi->bridge);
1006
1007 ret = component_add(host->dev, &mtk_dsi_component_ops);
1008 if (ret) {
1009 DRM_ERROR("failed to add dsi_host component: %d\n", ret);
1010 drm_bridge_remove(&dsi->bridge);
1011 return ret;
1012 }
1013
1014 return 0;
1015}
1016
1017static int mtk_dsi_host_detach(struct mipi_dsi_host *host,
1018 struct mipi_dsi_device *device)
1019{
1020 struct mtk_dsi *dsi = host_to_dsi(host);
1021
1022 component_del(host->dev, &mtk_dsi_component_ops);
1023 drm_bridge_remove(&dsi->bridge);
1024 return 0;
1025}
1026
1027static void mtk_dsi_wait_for_idle(struct mtk_dsi *dsi)
1028{
1029 int ret;
1030 u32 val;
1031
1032 ret = readl_poll_timeout(dsi->regs + DSI_INTSTA, val, !(val & DSI_BUSY),
1033 4, 2000000);
1034 if (ret) {
1035 DRM_WARN("polling dsi wait not busy timeout!\n");
1036
1037 mtk_dsi_enable(dsi);
1038 mtk_dsi_reset_engine(dsi);
1039 }
1040}
1041
1042static u32 mtk_dsi_recv_cnt(u8 type, u8 *read_data)
1043{
1044 switch (type) {
1045 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE:
1046 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
1047 return 1;
1048 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE:
1049 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
1050 return 2;
1051 case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE:
1052 case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE:
1053 return read_data[1] + read_data[2] * 16;
1054 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
1055 DRM_INFO("type is 0x02, try again\n");
1056 break;
1057 default:
1058 DRM_INFO("type(0x%x) not recognized\n", type);
1059 break;
1060 }
1061
1062 return 0;
1063}
1064
1065static void mtk_dsi_cmdq(struct mtk_dsi *dsi, const struct mipi_dsi_msg *msg)
1066{
1067 const char *tx_buf = msg->tx_buf;
1068 u8 config, cmdq_size, cmdq_off, type = msg->type;
1069 u32 reg_val, cmdq_mask, i;
1070 u32 reg_cmdq_off = dsi->driver_data->reg_cmdq_off;
1071
1072 if (MTK_DSI_HOST_IS_READ(type))
1073 config = BTA;
1074 else
1075 config = (msg->tx_len > 2) ? LONG_PACKET : SHORT_PACKET;
1076
1077 if (!(msg->flags & MIPI_DSI_MSG_USE_LPM))
1078 config |= HSTX;
1079
1080 if (msg->tx_len > 2) {
1081 cmdq_size = 1 + (msg->tx_len + 3) / 4;
1082 cmdq_off = 4;
1083 cmdq_mask = CONFIG | DATA_ID | DATA_0 | DATA_1;
1084 reg_val = (msg->tx_len << 16) | (type << 8) | config;
1085 } else {
1086 cmdq_size = 1;
1087 cmdq_off = 2;
1088 cmdq_mask = CONFIG | DATA_ID;
1089 reg_val = (type << 8) | config;
1090 }
1091
1092 for (i = 0; i < msg->tx_len; i++)
1093 mtk_dsi_mask(dsi, (reg_cmdq_off + cmdq_off + i) & (~0x3U),
1094 (0xffUL << (((i + cmdq_off) & 3U) * 8U)),
1095 tx_buf[i] << (((i + cmdq_off) & 3U) * 8U));
1096
1097 mtk_dsi_mask(dsi, reg_cmdq_off, cmdq_mask, reg_val);
1098 mtk_dsi_mask(dsi, DSI_CMDQ_SIZE, CMDQ_SIZE, cmdq_size);
1099 if (dsi->driver_data->cmdq_long_packet_ctl) {
1100 /* Disable setting cmdq_size automatically for long packets */
1101 mtk_dsi_mask(dsi, DSI_CMDQ_SIZE, CMDQ_SIZE_SEL, CMDQ_SIZE_SEL);
1102 }
1103}
1104
1105static ssize_t mtk_dsi_host_send_cmd(struct mtk_dsi *dsi,
1106 const struct mipi_dsi_msg *msg, u8 flag)
1107{
1108 mtk_dsi_wait_for_idle(dsi);
1109 mtk_dsi_irq_data_clear(dsi, flag);
1110 mtk_dsi_cmdq(dsi, msg);
1111 mtk_dsi_start(dsi);
1112
1113 if (!mtk_dsi_wait_for_irq_done(dsi, flag, 2000))
1114 return -ETIME;
1115 else
1116 return 0;
1117}
1118
1119static ssize_t mtk_dsi_host_transfer(struct mipi_dsi_host *host,
1120 const struct mipi_dsi_msg *msg)
1121{
1122 struct mtk_dsi *dsi = host_to_dsi(host);
1123 ssize_t recv_cnt;
1124 u8 read_data[16];
1125 void *src_addr;
1126 u8 irq_flag = CMD_DONE_INT_FLAG;
1127 u32 dsi_mode;
1128 int ret, i;
1129
1130 dsi_mode = readl(dsi->regs + DSI_MODE_CTRL);
1131 if (dsi_mode & MODE) {
1132 mtk_dsi_stop(dsi);
1133 ret = mtk_dsi_switch_to_cmd_mode(dsi, VM_DONE_INT_FLAG, 500);
1134 if (ret)
1135 goto restore_dsi_mode;
1136 }
1137
1138 if (MTK_DSI_HOST_IS_READ(msg->type))
1139 irq_flag |= LPRX_RD_RDY_INT_FLAG;
1140
1141 mtk_dsi_lane_ready(dsi);
1142
1143 ret = mtk_dsi_host_send_cmd(dsi, msg, irq_flag);
1144 if (ret)
1145 goto restore_dsi_mode;
1146
1147 if (!MTK_DSI_HOST_IS_READ(msg->type)) {
1148 recv_cnt = 0;
1149 goto restore_dsi_mode;
1150 }
1151
1152 if (!msg->rx_buf) {
1153 DRM_ERROR("dsi receive buffer size may be NULL\n");
1154 ret = -EINVAL;
1155 goto restore_dsi_mode;
1156 }
1157
1158 for (i = 0; i < 16; i++)
1159 *(read_data + i) = readb(dsi->regs + DSI_RX_DATA0 + i);
1160
1161 recv_cnt = mtk_dsi_recv_cnt(read_data[0], read_data);
1162
1163 if (recv_cnt > 2)
1164 src_addr = &read_data[4];
1165 else
1166 src_addr = &read_data[1];
1167
1168 if (recv_cnt > 10)
1169 recv_cnt = 10;
1170
1171 if (recv_cnt > msg->rx_len)
1172 recv_cnt = msg->rx_len;
1173
1174 if (recv_cnt)
1175 memcpy(msg->rx_buf, src_addr, recv_cnt);
1176
1177 DRM_INFO("dsi get %zd byte data from the panel address(0x%x)\n",
1178 recv_cnt, *((u8 *)(msg->tx_buf)));
1179
1180restore_dsi_mode:
1181 if (dsi_mode & MODE) {
1182 mtk_dsi_set_mode(dsi);
1183 mtk_dsi_start(dsi);
1184 }
1185
1186 return ret < 0 ? ret : recv_cnt;
1187}
1188
1189static const struct mipi_dsi_host_ops mtk_dsi_ops = {
1190 .attach = mtk_dsi_host_attach,
1191 .detach = mtk_dsi_host_detach,
1192 .transfer = mtk_dsi_host_transfer,
1193};
1194
1195static int mtk_dsi_probe(struct platform_device *pdev)
1196{
1197 struct mtk_dsi *dsi;
1198 struct device *dev = &pdev->dev;
1199 int irq_num;
1200 int ret;
1201
1202 dsi = devm_drm_bridge_alloc(dev, struct mtk_dsi, bridge,
1203 &mtk_dsi_bridge_funcs);
1204 if (IS_ERR(dsi))
1205 return PTR_ERR(dsi);
1206
1207 dsi->driver_data = of_device_get_match_data(dev);
1208
1209 dsi->engine_clk = devm_clk_get(dev, "engine");
1210 if (IS_ERR(dsi->engine_clk))
1211 return dev_err_probe(dev, PTR_ERR(dsi->engine_clk),
1212 "Failed to get engine clock\n");
1213
1214
1215 dsi->digital_clk = devm_clk_get(dev, "digital");
1216 if (IS_ERR(dsi->digital_clk))
1217 return dev_err_probe(dev, PTR_ERR(dsi->digital_clk),
1218 "Failed to get digital clock\n");
1219
1220 dsi->hs_clk = devm_clk_get(dev, "hs");
1221 if (IS_ERR(dsi->hs_clk))
1222 return dev_err_probe(dev, PTR_ERR(dsi->hs_clk), "Failed to get hs clock\n");
1223
1224 dsi->regs = devm_platform_ioremap_resource(pdev, 0);
1225 if (IS_ERR(dsi->regs))
1226 return dev_err_probe(dev, PTR_ERR(dsi->regs), "Failed to ioremap memory\n");
1227
1228 dsi->phy = devm_phy_get(dev, "dphy");
1229 if (IS_ERR(dsi->phy))
1230 return dev_err_probe(dev, PTR_ERR(dsi->phy), "Failed to get MIPI-DPHY\n");
1231
1232 irq_num = platform_get_irq(pdev, 0);
1233 if (irq_num < 0)
1234 return irq_num;
1235
1236 dsi->host.ops = &mtk_dsi_ops;
1237 dsi->host.dev = dev;
1238
1239 init_waitqueue_head(&dsi->irq_wait_queue);
1240
1241 platform_set_drvdata(pdev, dsi);
1242
1243 ret = mipi_dsi_host_register(&dsi->host);
1244 if (ret < 0)
1245 return dev_err_probe(dev, ret, "Failed to register DSI host\n");
1246
1247 ret = devm_request_irq(&pdev->dev, irq_num, mtk_dsi_irq,
1248 IRQF_TRIGGER_NONE, dev_name(&pdev->dev), dsi);
1249 if (ret) {
1250 mipi_dsi_host_unregister(&dsi->host);
1251 return dev_err_probe(&pdev->dev, ret, "Failed to request DSI irq\n");
1252 }
1253
1254 dsi->bridge.of_node = dev->of_node;
1255 dsi->bridge.type = DRM_MODE_CONNECTOR_DSI;
1256
1257 return 0;
1258}
1259
1260static void mtk_dsi_remove(struct platform_device *pdev)
1261{
1262 struct mtk_dsi *dsi = platform_get_drvdata(pdev);
1263
1264 mtk_output_dsi_disable(dsi);
1265 mipi_dsi_host_unregister(&dsi->host);
1266}
1267
1268static const struct mtk_dsi_driver_data mt8173_dsi_driver_data = {
1269 .reg_cmdq_off = 0x200,
1270 .reg_vm_cmd_off = 0x130,
1271 .reg_shadow_dbg_off = 0x190
1272};
1273
1274static const struct mtk_dsi_driver_data mt2701_dsi_driver_data = {
1275 .reg_cmdq_off = 0x180,
1276 .reg_vm_cmd_off = 0x130,
1277 .reg_shadow_dbg_off = 0x190
1278};
1279
1280static const struct mtk_dsi_driver_data mt8183_dsi_driver_data = {
1281 .reg_cmdq_off = 0x200,
1282 .reg_vm_cmd_off = 0x130,
1283 .reg_shadow_dbg_off = 0x190,
1284 .has_shadow_ctl = true,
1285 .has_size_ctl = true,
1286};
1287
1288static const struct mtk_dsi_driver_data mt8186_dsi_driver_data = {
1289 .reg_cmdq_off = 0xd00,
1290 .reg_vm_cmd_off = 0x200,
1291 .reg_shadow_dbg_off = 0xc00,
1292 .has_shadow_ctl = true,
1293 .has_size_ctl = true,
1294};
1295
1296static const struct mtk_dsi_driver_data mt8188_dsi_driver_data = {
1297 .reg_cmdq_off = 0xd00,
1298 .reg_vm_cmd_off = 0x200,
1299 .reg_shadow_dbg_off = 0xc00,
1300 .has_shadow_ctl = true,
1301 .has_size_ctl = true,
1302 .cmdq_long_packet_ctl = true,
1303 .support_per_frame_lp = true,
1304};
1305
1306static const struct of_device_id mtk_dsi_of_match[] = {
1307 { .compatible = "mediatek,mt2701-dsi", .data = &mt2701_dsi_driver_data },
1308 { .compatible = "mediatek,mt8173-dsi", .data = &mt8173_dsi_driver_data },
1309 { .compatible = "mediatek,mt8183-dsi", .data = &mt8183_dsi_driver_data },
1310 { .compatible = "mediatek,mt8186-dsi", .data = &mt8186_dsi_driver_data },
1311 { .compatible = "mediatek,mt8188-dsi", .data = &mt8188_dsi_driver_data },
1312 { /* sentinel */ }
1313};
1314MODULE_DEVICE_TABLE(of, mtk_dsi_of_match);
1315
1316struct platform_driver mtk_dsi_driver = {
1317 .probe = mtk_dsi_probe,
1318 .remove = mtk_dsi_remove,
1319 .driver = {
1320 .name = "mtk-dsi",
1321 .of_match_table = mtk_dsi_of_match,
1322 },
1323};