Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2013 NVIDIA Corporation
4 */
5
6#include <linux/clk.h>
7#include <linux/debugfs.h>
8#include <linux/delay.h>
9#include <linux/host1x.h>
10#include <linux/module.h>
11#include <linux/of.h>
12#include <linux/of_platform.h>
13#include <linux/platform_device.h>
14#include <linux/pm_runtime.h>
15#include <linux/regulator/consumer.h>
16#include <linux/reset.h>
17#include <linux/tegra-mipi-cal.h>
18
19#include <video/mipi_display.h>
20
21#include <drm/drm_atomic_helper.h>
22#include <drm/drm_debugfs.h>
23#include <drm/drm_file.h>
24#include <drm/drm_mipi_dsi.h>
25#include <drm/drm_panel.h>
26#include <drm/drm_print.h>
27#include <drm/drm_simple_kms_helper.h>
28
29#include "dc.h"
30#include "drm.h"
31#include "dsi.h"
32#include "mipi-phy.h"
33#include "trace.h"
34
35struct tegra_dsi_state {
36 struct drm_connector_state base;
37
38 struct mipi_dphy_timing timing;
39 unsigned long period;
40
41 unsigned int vrefresh;
42 unsigned int lanes;
43 unsigned long pclk;
44 unsigned long bclk;
45
46 enum tegra_dsi_format format;
47 unsigned int mul;
48 unsigned int div;
49};
50
51static inline struct tegra_dsi_state *
52to_dsi_state(struct drm_connector_state *state)
53{
54 return container_of(state, struct tegra_dsi_state, base);
55}
56
57struct tegra_dsi {
58 struct host1x_client client;
59 struct tegra_output output;
60 struct device *dev;
61
62 void __iomem *regs;
63
64 struct reset_control *rst;
65 struct clk *clk_parent;
66 struct clk *clk_lp;
67 struct clk *clk;
68
69 struct drm_info_list *debugfs_files;
70
71 unsigned long flags;
72 enum mipi_dsi_pixel_format format;
73 unsigned int lanes;
74
75 struct tegra_mipi_device *mipi;
76 struct mipi_dsi_host host;
77
78 struct regulator *vdd;
79
80 unsigned int video_fifo_depth;
81 unsigned int host_fifo_depth;
82
83 /* for ganged-mode support */
84 struct tegra_dsi *master;
85 struct tegra_dsi *slave;
86};
87
88static inline struct tegra_dsi *
89host1x_client_to_dsi(struct host1x_client *client)
90{
91 return container_of(client, struct tegra_dsi, client);
92}
93
94static inline struct tegra_dsi *host_to_tegra(struct mipi_dsi_host *host)
95{
96 return container_of(host, struct tegra_dsi, host);
97}
98
99static inline struct tegra_dsi *to_dsi(struct tegra_output *output)
100{
101 return container_of(output, struct tegra_dsi, output);
102}
103
104static struct tegra_dsi_state *tegra_dsi_get_state(struct tegra_dsi *dsi)
105{
106 return to_dsi_state(dsi->output.connector.state);
107}
108
109static inline u32 tegra_dsi_readl(struct tegra_dsi *dsi, unsigned int offset)
110{
111 u32 value = readl(dsi->regs + (offset << 2));
112
113 trace_dsi_readl(dsi->dev, offset, value);
114
115 return value;
116}
117
118static inline void tegra_dsi_writel(struct tegra_dsi *dsi, u32 value,
119 unsigned int offset)
120{
121 trace_dsi_writel(dsi->dev, offset, value);
122 writel(value, dsi->regs + (offset << 2));
123}
124
125#define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name }
126
127static const struct debugfs_reg32 tegra_dsi_regs[] = {
128 DEBUGFS_REG32(DSI_INCR_SYNCPT),
129 DEBUGFS_REG32(DSI_INCR_SYNCPT_CONTROL),
130 DEBUGFS_REG32(DSI_INCR_SYNCPT_ERROR),
131 DEBUGFS_REG32(DSI_CTXSW),
132 DEBUGFS_REG32(DSI_RD_DATA),
133 DEBUGFS_REG32(DSI_WR_DATA),
134 DEBUGFS_REG32(DSI_POWER_CONTROL),
135 DEBUGFS_REG32(DSI_INT_ENABLE),
136 DEBUGFS_REG32(DSI_INT_STATUS),
137 DEBUGFS_REG32(DSI_INT_MASK),
138 DEBUGFS_REG32(DSI_HOST_CONTROL),
139 DEBUGFS_REG32(DSI_CONTROL),
140 DEBUGFS_REG32(DSI_SOL_DELAY),
141 DEBUGFS_REG32(DSI_MAX_THRESHOLD),
142 DEBUGFS_REG32(DSI_TRIGGER),
143 DEBUGFS_REG32(DSI_TX_CRC),
144 DEBUGFS_REG32(DSI_STATUS),
145 DEBUGFS_REG32(DSI_INIT_SEQ_CONTROL),
146 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_0),
147 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_1),
148 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_2),
149 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_3),
150 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_4),
151 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_5),
152 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_6),
153 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_7),
154 DEBUGFS_REG32(DSI_PKT_SEQ_0_LO),
155 DEBUGFS_REG32(DSI_PKT_SEQ_0_HI),
156 DEBUGFS_REG32(DSI_PKT_SEQ_1_LO),
157 DEBUGFS_REG32(DSI_PKT_SEQ_1_HI),
158 DEBUGFS_REG32(DSI_PKT_SEQ_2_LO),
159 DEBUGFS_REG32(DSI_PKT_SEQ_2_HI),
160 DEBUGFS_REG32(DSI_PKT_SEQ_3_LO),
161 DEBUGFS_REG32(DSI_PKT_SEQ_3_HI),
162 DEBUGFS_REG32(DSI_PKT_SEQ_4_LO),
163 DEBUGFS_REG32(DSI_PKT_SEQ_4_HI),
164 DEBUGFS_REG32(DSI_PKT_SEQ_5_LO),
165 DEBUGFS_REG32(DSI_PKT_SEQ_5_HI),
166 DEBUGFS_REG32(DSI_DCS_CMDS),
167 DEBUGFS_REG32(DSI_PKT_LEN_0_1),
168 DEBUGFS_REG32(DSI_PKT_LEN_2_3),
169 DEBUGFS_REG32(DSI_PKT_LEN_4_5),
170 DEBUGFS_REG32(DSI_PKT_LEN_6_7),
171 DEBUGFS_REG32(DSI_PHY_TIMING_0),
172 DEBUGFS_REG32(DSI_PHY_TIMING_1),
173 DEBUGFS_REG32(DSI_PHY_TIMING_2),
174 DEBUGFS_REG32(DSI_BTA_TIMING),
175 DEBUGFS_REG32(DSI_TIMEOUT_0),
176 DEBUGFS_REG32(DSI_TIMEOUT_1),
177 DEBUGFS_REG32(DSI_TO_TALLY),
178 DEBUGFS_REG32(DSI_PAD_CONTROL_0),
179 DEBUGFS_REG32(DSI_PAD_CONTROL_CD),
180 DEBUGFS_REG32(DSI_PAD_CD_STATUS),
181 DEBUGFS_REG32(DSI_VIDEO_MODE_CONTROL),
182 DEBUGFS_REG32(DSI_PAD_CONTROL_1),
183 DEBUGFS_REG32(DSI_PAD_CONTROL_2),
184 DEBUGFS_REG32(DSI_PAD_CONTROL_3),
185 DEBUGFS_REG32(DSI_PAD_CONTROL_4),
186 DEBUGFS_REG32(DSI_GANGED_MODE_CONTROL),
187 DEBUGFS_REG32(DSI_GANGED_MODE_START),
188 DEBUGFS_REG32(DSI_GANGED_MODE_SIZE),
189 DEBUGFS_REG32(DSI_RAW_DATA_BYTE_COUNT),
190 DEBUGFS_REG32(DSI_ULTRA_LOW_POWER_CONTROL),
191 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_8),
192 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_9),
193 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_10),
194 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_11),
195 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_12),
196 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_13),
197 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_14),
198 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_15),
199};
200
201static int tegra_dsi_show_regs(struct seq_file *s, void *data)
202{
203 struct drm_info_node *node = s->private;
204 struct tegra_dsi *dsi = node->info_ent->data;
205 struct drm_crtc *crtc = dsi->output.encoder.crtc;
206 struct drm_device *drm = node->minor->dev;
207 unsigned int i;
208 int err = 0;
209
210 drm_modeset_lock_all(drm);
211
212 if (!crtc || !crtc->state->active) {
213 err = -EBUSY;
214 goto unlock;
215 }
216
217 for (i = 0; i < ARRAY_SIZE(tegra_dsi_regs); i++) {
218 unsigned int offset = tegra_dsi_regs[i].offset;
219
220 seq_printf(s, "%-32s %#05x %08x\n", tegra_dsi_regs[i].name,
221 offset, tegra_dsi_readl(dsi, offset));
222 }
223
224unlock:
225 drm_modeset_unlock_all(drm);
226 return err;
227}
228
229static struct drm_info_list debugfs_files[] = {
230 { "regs", tegra_dsi_show_regs, 0, NULL },
231};
232
233static int tegra_dsi_late_register(struct drm_connector *connector)
234{
235 struct tegra_output *output = connector_to_output(connector);
236 unsigned int i, count = ARRAY_SIZE(debugfs_files);
237 struct drm_minor *minor = connector->dev->primary;
238 struct dentry *root = connector->debugfs_entry;
239 struct tegra_dsi *dsi = to_dsi(output);
240
241 dsi->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
242 GFP_KERNEL);
243 if (!dsi->debugfs_files)
244 return -ENOMEM;
245
246 for (i = 0; i < count; i++)
247 dsi->debugfs_files[i].data = dsi;
248
249 drm_debugfs_create_files(dsi->debugfs_files, count, root, minor);
250
251 return 0;
252}
253
254static void tegra_dsi_early_unregister(struct drm_connector *connector)
255{
256 struct tegra_output *output = connector_to_output(connector);
257 unsigned int count = ARRAY_SIZE(debugfs_files);
258 struct tegra_dsi *dsi = to_dsi(output);
259
260 drm_debugfs_remove_files(dsi->debugfs_files, count,
261 connector->debugfs_entry,
262 connector->dev->primary);
263 kfree(dsi->debugfs_files);
264 dsi->debugfs_files = NULL;
265}
266
267#define PKT_ID0(id) ((((id) & 0x3f) << 3) | (1 << 9))
268#define PKT_LEN0(len) (((len) & 0x07) << 0)
269#define PKT_ID1(id) ((((id) & 0x3f) << 13) | (1 << 19))
270#define PKT_LEN1(len) (((len) & 0x07) << 10)
271#define PKT_ID2(id) ((((id) & 0x3f) << 23) | (1 << 29))
272#define PKT_LEN2(len) (((len) & 0x07) << 20)
273
274#define PKT_LP (1 << 30)
275#define NUM_PKT_SEQ 12
276
277/*
278 * non-burst mode with sync pulses
279 */
280static const u32 pkt_seq_video_non_burst_sync_pulses[NUM_PKT_SEQ] = {
281 [ 0] = PKT_ID0(MIPI_DSI_V_SYNC_START) | PKT_LEN0(0) |
282 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
283 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
284 PKT_LP,
285 [ 1] = 0,
286 [ 2] = PKT_ID0(MIPI_DSI_V_SYNC_END) | PKT_LEN0(0) |
287 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
288 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
289 PKT_LP,
290 [ 3] = 0,
291 [ 4] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
292 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
293 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
294 PKT_LP,
295 [ 5] = 0,
296 [ 6] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
297 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
298 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0),
299 [ 7] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(2) |
300 PKT_ID1(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN1(3) |
301 PKT_ID2(MIPI_DSI_BLANKING_PACKET) | PKT_LEN2(4),
302 [ 8] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
303 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
304 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
305 PKT_LP,
306 [ 9] = 0,
307 [10] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
308 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
309 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0),
310 [11] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(2) |
311 PKT_ID1(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN1(3) |
312 PKT_ID2(MIPI_DSI_BLANKING_PACKET) | PKT_LEN2(4),
313};
314
315/*
316 * non-burst mode with sync events
317 */
318static const u32 pkt_seq_video_non_burst_sync_events[NUM_PKT_SEQ] = {
319 [ 0] = PKT_ID0(MIPI_DSI_V_SYNC_START) | PKT_LEN0(0) |
320 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
321 PKT_LP,
322 [ 1] = 0,
323 [ 2] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
324 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
325 PKT_LP,
326 [ 3] = 0,
327 [ 4] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
328 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
329 PKT_LP,
330 [ 5] = 0,
331 [ 6] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
332 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(2) |
333 PKT_ID2(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN2(3),
334 [ 7] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(4),
335 [ 8] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
336 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
337 PKT_LP,
338 [ 9] = 0,
339 [10] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
340 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(2) |
341 PKT_ID2(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN2(3),
342 [11] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(4),
343};
344
345static const u32 pkt_seq_command_mode[NUM_PKT_SEQ] = {
346 [ 0] = 0,
347 [ 1] = 0,
348 [ 2] = 0,
349 [ 3] = 0,
350 [ 4] = 0,
351 [ 5] = 0,
352 [ 6] = PKT_ID0(MIPI_DSI_DCS_LONG_WRITE) | PKT_LEN0(3) | PKT_LP,
353 [ 7] = 0,
354 [ 8] = 0,
355 [ 9] = 0,
356 [10] = PKT_ID0(MIPI_DSI_DCS_LONG_WRITE) | PKT_LEN0(5) | PKT_LP,
357 [11] = 0,
358};
359
360static void tegra_dsi_set_phy_timing(struct tegra_dsi *dsi,
361 unsigned long period,
362 const struct mipi_dphy_timing *timing)
363{
364 u32 value;
365
366 value = DSI_TIMING_FIELD(timing->hsexit, period, 1) << 24 |
367 DSI_TIMING_FIELD(timing->hstrail, period, 0) << 16 |
368 DSI_TIMING_FIELD(timing->hszero, period, 3) << 8 |
369 DSI_TIMING_FIELD(timing->hsprepare, period, 1);
370 tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_0);
371
372 value = DSI_TIMING_FIELD(timing->clktrail, period, 1) << 24 |
373 DSI_TIMING_FIELD(timing->clkpost, period, 1) << 16 |
374 DSI_TIMING_FIELD(timing->clkzero, period, 1) << 8 |
375 DSI_TIMING_FIELD(timing->lpx, period, 1);
376 tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_1);
377
378 value = DSI_TIMING_FIELD(timing->clkprepare, period, 1) << 16 |
379 DSI_TIMING_FIELD(timing->clkpre, period, 1) << 8 |
380 DSI_TIMING_FIELD(0xff * period, period, 0) << 0;
381 tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_2);
382
383 value = DSI_TIMING_FIELD(timing->taget, period, 1) << 16 |
384 DSI_TIMING_FIELD(timing->tasure, period, 1) << 8 |
385 DSI_TIMING_FIELD(timing->tago, period, 1);
386 tegra_dsi_writel(dsi, value, DSI_BTA_TIMING);
387
388 if (dsi->slave)
389 tegra_dsi_set_phy_timing(dsi->slave, period, timing);
390}
391
392static int tegra_dsi_get_muldiv(enum mipi_dsi_pixel_format format,
393 unsigned int *mulp, unsigned int *divp)
394{
395 switch (format) {
396 case MIPI_DSI_FMT_RGB666_PACKED:
397 case MIPI_DSI_FMT_RGB888:
398 *mulp = 3;
399 *divp = 1;
400 break;
401
402 case MIPI_DSI_FMT_RGB565:
403 *mulp = 2;
404 *divp = 1;
405 break;
406
407 case MIPI_DSI_FMT_RGB666:
408 *mulp = 9;
409 *divp = 4;
410 break;
411
412 default:
413 return -EINVAL;
414 }
415
416 return 0;
417}
418
419static int tegra_dsi_get_format(enum mipi_dsi_pixel_format format,
420 enum tegra_dsi_format *fmt)
421{
422 switch (format) {
423 case MIPI_DSI_FMT_RGB888:
424 *fmt = TEGRA_DSI_FORMAT_24P;
425 break;
426
427 case MIPI_DSI_FMT_RGB666:
428 *fmt = TEGRA_DSI_FORMAT_18NP;
429 break;
430
431 case MIPI_DSI_FMT_RGB666_PACKED:
432 *fmt = TEGRA_DSI_FORMAT_18P;
433 break;
434
435 case MIPI_DSI_FMT_RGB565:
436 *fmt = TEGRA_DSI_FORMAT_16P;
437 break;
438
439 default:
440 return -EINVAL;
441 }
442
443 return 0;
444}
445
446static void tegra_dsi_ganged_enable(struct tegra_dsi *dsi, unsigned int start,
447 unsigned int size)
448{
449 u32 value;
450
451 tegra_dsi_writel(dsi, start, DSI_GANGED_MODE_START);
452 tegra_dsi_writel(dsi, size << 16 | size, DSI_GANGED_MODE_SIZE);
453
454 value = DSI_GANGED_MODE_CONTROL_ENABLE;
455 tegra_dsi_writel(dsi, value, DSI_GANGED_MODE_CONTROL);
456}
457
458static void tegra_dsi_enable(struct tegra_dsi *dsi)
459{
460 u32 value;
461
462 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
463 value |= DSI_POWER_CONTROL_ENABLE;
464 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
465
466 if (dsi->slave)
467 tegra_dsi_enable(dsi->slave);
468}
469
470static unsigned int tegra_dsi_get_lanes(struct tegra_dsi *dsi)
471{
472 if (dsi->master)
473 return dsi->master->lanes + dsi->lanes;
474
475 if (dsi->slave)
476 return dsi->lanes + dsi->slave->lanes;
477
478 return dsi->lanes;
479}
480
481static void tegra_dsi_configure(struct tegra_dsi *dsi, unsigned int pipe,
482 const struct drm_display_mode *mode)
483{
484 unsigned int hact, hsw, hbp, hfp, i, mul, div;
485 struct tegra_dsi_state *state;
486 const u32 *pkt_seq;
487 u32 value;
488
489 /* XXX: pass in state into this function? */
490 if (dsi->master)
491 state = tegra_dsi_get_state(dsi->master);
492 else
493 state = tegra_dsi_get_state(dsi);
494
495 mul = state->mul;
496 div = state->div;
497
498 if (dsi->flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) {
499 DRM_DEBUG_KMS("Non-burst video mode with sync pulses\n");
500 pkt_seq = pkt_seq_video_non_burst_sync_pulses;
501 } else if (dsi->flags & MIPI_DSI_MODE_VIDEO) {
502 DRM_DEBUG_KMS("Non-burst video mode with sync events\n");
503 pkt_seq = pkt_seq_video_non_burst_sync_events;
504 } else {
505 DRM_DEBUG_KMS("Command mode\n");
506 pkt_seq = pkt_seq_command_mode;
507 }
508
509 value = DSI_CONTROL_CHANNEL(0) |
510 DSI_CONTROL_FORMAT(state->format) |
511 DSI_CONTROL_LANES(dsi->lanes - 1) |
512 DSI_CONTROL_SOURCE(pipe);
513 tegra_dsi_writel(dsi, value, DSI_CONTROL);
514
515 tegra_dsi_writel(dsi, dsi->video_fifo_depth, DSI_MAX_THRESHOLD);
516
517 value = DSI_HOST_CONTROL_HS;
518 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
519
520 value = tegra_dsi_readl(dsi, DSI_CONTROL);
521
522 if (dsi->flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)
523 value |= DSI_CONTROL_HS_CLK_CTRL;
524
525 value &= ~DSI_CONTROL_TX_TRIG(3);
526
527 /* enable DCS commands for command mode */
528 if (dsi->flags & MIPI_DSI_MODE_VIDEO)
529 value &= ~DSI_CONTROL_DCS_ENABLE;
530 else
531 value |= DSI_CONTROL_DCS_ENABLE;
532
533 value |= DSI_CONTROL_VIDEO_ENABLE;
534 value &= ~DSI_CONTROL_HOST_ENABLE;
535 tegra_dsi_writel(dsi, value, DSI_CONTROL);
536
537 for (i = 0; i < NUM_PKT_SEQ; i++)
538 tegra_dsi_writel(dsi, pkt_seq[i], DSI_PKT_SEQ_0_LO + i);
539
540 if (dsi->flags & MIPI_DSI_MODE_VIDEO) {
541 /* horizontal active pixels */
542 hact = mode->hdisplay * mul / div;
543
544 /* horizontal sync width */
545 hsw = (mode->hsync_end - mode->hsync_start) * mul / div;
546
547 /* horizontal back porch */
548 hbp = (mode->htotal - mode->hsync_end) * mul / div;
549
550 /* horizontal front porch */
551 hfp = (mode->hsync_start - mode->hdisplay) * mul / div;
552
553 if (dsi->master || dsi->slave) {
554 hact /= 2;
555 hsw /= 2;
556 hbp /= 2;
557 hfp /= 2;
558 }
559
560 if ((dsi->flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) == 0)
561 hbp += hsw;
562
563 /* subtract packet overhead */
564 hsw -= 10;
565 hbp -= 14;
566 hfp -= 8;
567
568 tegra_dsi_writel(dsi, hsw << 16 | 0, DSI_PKT_LEN_0_1);
569 tegra_dsi_writel(dsi, hact << 16 | hbp, DSI_PKT_LEN_2_3);
570 tegra_dsi_writel(dsi, hfp, DSI_PKT_LEN_4_5);
571 tegra_dsi_writel(dsi, 0x0f0f << 16, DSI_PKT_LEN_6_7);
572 } else {
573 u16 bytes;
574
575 if (dsi->master || dsi->slave) {
576 /*
577 * For ganged mode, assume symmetric left-right mode.
578 */
579 bytes = 1 + (mode->hdisplay / 2) * mul / div;
580 } else {
581 /* 1 byte (DCS command) + pixel data */
582 bytes = 1 + mode->hdisplay * mul / div;
583 }
584
585 tegra_dsi_writel(dsi, 0, DSI_PKT_LEN_0_1);
586 tegra_dsi_writel(dsi, bytes << 16, DSI_PKT_LEN_2_3);
587 tegra_dsi_writel(dsi, bytes << 16, DSI_PKT_LEN_4_5);
588 tegra_dsi_writel(dsi, 0, DSI_PKT_LEN_6_7);
589
590 value = MIPI_DCS_WRITE_MEMORY_START << 8 |
591 MIPI_DCS_WRITE_MEMORY_CONTINUE;
592 tegra_dsi_writel(dsi, value, DSI_DCS_CMDS);
593 }
594
595 /* set SOL delay */
596 if (dsi->master || dsi->slave) {
597 unsigned long delay, bclk, bclk_ganged;
598 unsigned int lanes = state->lanes;
599
600 /* SOL to valid, valid to FIFO and FIFO write delay */
601 delay = 4 + 4 + 2;
602 delay = DIV_ROUND_UP(delay * mul, div * lanes);
603 /* FIFO read delay */
604 delay = delay + 6;
605
606 bclk = DIV_ROUND_UP(mode->htotal * mul, div * lanes);
607 bclk_ganged = DIV_ROUND_UP(bclk * lanes / 2, lanes);
608 value = bclk - bclk_ganged + delay + 20;
609 } else {
610 value = 8 * mul / div;
611 }
612
613 tegra_dsi_writel(dsi, value, DSI_SOL_DELAY);
614
615 if (dsi->slave) {
616 tegra_dsi_configure(dsi->slave, pipe, mode);
617
618 /*
619 * TODO: Support modes other than symmetrical left-right
620 * split.
621 */
622 tegra_dsi_ganged_enable(dsi, 0, mode->hdisplay / 2);
623 tegra_dsi_ganged_enable(dsi->slave, mode->hdisplay / 2,
624 mode->hdisplay / 2);
625 }
626}
627
628static int tegra_dsi_wait_idle(struct tegra_dsi *dsi, unsigned long timeout)
629{
630 u32 value;
631
632 timeout = jiffies + msecs_to_jiffies(timeout);
633
634 while (time_before(jiffies, timeout)) {
635 value = tegra_dsi_readl(dsi, DSI_STATUS);
636 if (value & DSI_STATUS_IDLE)
637 return 0;
638
639 usleep_range(1000, 2000);
640 }
641
642 return -ETIMEDOUT;
643}
644
645static void tegra_dsi_video_disable(struct tegra_dsi *dsi)
646{
647 u32 value;
648
649 value = tegra_dsi_readl(dsi, DSI_CONTROL);
650 value &= ~DSI_CONTROL_VIDEO_ENABLE;
651 tegra_dsi_writel(dsi, value, DSI_CONTROL);
652
653 if (dsi->slave)
654 tegra_dsi_video_disable(dsi->slave);
655}
656
657static void tegra_dsi_ganged_disable(struct tegra_dsi *dsi)
658{
659 tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_START);
660 tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_SIZE);
661 tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_CONTROL);
662}
663
664static int tegra_dsi_pad_enable(struct tegra_dsi *dsi)
665{
666 u32 value;
667
668 value = DSI_PAD_CONTROL_VS1_PULLDN(0) | DSI_PAD_CONTROL_VS1_PDIO(0);
669 tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_0);
670
671 return 0;
672}
673
674static int tegra_dsi_pad_calibrate(struct tegra_dsi *dsi)
675{
676 u32 value;
677 int err;
678
679 /*
680 * XXX Is this still needed? The module reset is deasserted right
681 * before this function is called.
682 */
683 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_0);
684 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_1);
685 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_2);
686 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_3);
687 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_4);
688
689 /* start calibration */
690 tegra_dsi_pad_enable(dsi);
691
692 value = DSI_PAD_SLEW_UP(0x7) | DSI_PAD_SLEW_DN(0x7) |
693 DSI_PAD_LP_UP(0x1) | DSI_PAD_LP_DN(0x1) |
694 DSI_PAD_OUT_CLK(0x0);
695 tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_2);
696
697 value = DSI_PAD_PREEMP_PD_CLK(0x3) | DSI_PAD_PREEMP_PU_CLK(0x3) |
698 DSI_PAD_PREEMP_PD(0x03) | DSI_PAD_PREEMP_PU(0x3);
699 tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_3);
700
701 err = tegra_mipi_start_calibration(dsi->mipi);
702 if (err < 0)
703 return err;
704
705 return tegra_mipi_finish_calibration(dsi->mipi);
706}
707
708static void tegra_dsi_set_timeout(struct tegra_dsi *dsi, unsigned long bclk,
709 unsigned int vrefresh)
710{
711 unsigned int timeout;
712 u32 value;
713
714 /* one frame high-speed transmission timeout */
715 timeout = (bclk / vrefresh) / 512;
716 value = DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(timeout);
717 tegra_dsi_writel(dsi, value, DSI_TIMEOUT_0);
718
719 /* 2 ms peripheral timeout for panel */
720 timeout = 2 * bclk / 512 * 1000;
721 value = DSI_TIMEOUT_PR(timeout) | DSI_TIMEOUT_TA(0x2000);
722 tegra_dsi_writel(dsi, value, DSI_TIMEOUT_1);
723
724 value = DSI_TALLY_TA(0) | DSI_TALLY_LRX(0) | DSI_TALLY_HTX(0);
725 tegra_dsi_writel(dsi, value, DSI_TO_TALLY);
726
727 if (dsi->slave)
728 tegra_dsi_set_timeout(dsi->slave, bclk, vrefresh);
729}
730
731static void tegra_dsi_disable(struct tegra_dsi *dsi)
732{
733 u32 value;
734
735 if (dsi->slave) {
736 tegra_dsi_ganged_disable(dsi->slave);
737 tegra_dsi_ganged_disable(dsi);
738 }
739
740 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
741 value &= ~DSI_POWER_CONTROL_ENABLE;
742 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
743
744 if (dsi->slave)
745 tegra_dsi_disable(dsi->slave);
746
747 usleep_range(5000, 10000);
748}
749
750static void tegra_dsi_soft_reset(struct tegra_dsi *dsi)
751{
752 u32 value;
753
754 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
755 value &= ~DSI_POWER_CONTROL_ENABLE;
756 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
757
758 usleep_range(300, 1000);
759
760 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
761 value |= DSI_POWER_CONTROL_ENABLE;
762 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
763
764 usleep_range(300, 1000);
765
766 value = tegra_dsi_readl(dsi, DSI_TRIGGER);
767 if (value)
768 tegra_dsi_writel(dsi, 0, DSI_TRIGGER);
769
770 if (dsi->slave)
771 tegra_dsi_soft_reset(dsi->slave);
772}
773
774static void tegra_dsi_connector_reset(struct drm_connector *connector)
775{
776 struct tegra_dsi_state *state = kzalloc_obj(*state);
777
778 if (!state)
779 return;
780
781 if (connector->state) {
782 __drm_atomic_helper_connector_destroy_state(connector->state);
783 kfree(connector->state);
784 }
785
786 __drm_atomic_helper_connector_reset(connector, &state->base);
787}
788
789static struct drm_connector_state *
790tegra_dsi_connector_duplicate_state(struct drm_connector *connector)
791{
792 struct tegra_dsi_state *state = to_dsi_state(connector->state);
793 struct tegra_dsi_state *copy;
794
795 copy = kmemdup(state, sizeof(*state), GFP_KERNEL);
796 if (!copy)
797 return NULL;
798
799 __drm_atomic_helper_connector_duplicate_state(connector,
800 ©->base);
801
802 return ©->base;
803}
804
805static const struct drm_connector_funcs tegra_dsi_connector_funcs = {
806 .reset = tegra_dsi_connector_reset,
807 .detect = tegra_output_connector_detect,
808 .fill_modes = drm_helper_probe_single_connector_modes,
809 .destroy = tegra_output_connector_destroy,
810 .atomic_duplicate_state = tegra_dsi_connector_duplicate_state,
811 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
812 .late_register = tegra_dsi_late_register,
813 .early_unregister = tegra_dsi_early_unregister,
814};
815
816static enum drm_mode_status
817tegra_dsi_connector_mode_valid(struct drm_connector *connector,
818 const struct drm_display_mode *mode)
819{
820 return MODE_OK;
821}
822
823static const struct drm_connector_helper_funcs tegra_dsi_connector_helper_funcs = {
824 .get_modes = tegra_output_connector_get_modes,
825 .mode_valid = tegra_dsi_connector_mode_valid,
826};
827
828static void tegra_dsi_unprepare(struct tegra_dsi *dsi)
829{
830 int err;
831
832 if (dsi->slave)
833 tegra_dsi_unprepare(dsi->slave);
834
835 err = tegra_mipi_disable(dsi->mipi);
836 if (err < 0)
837 dev_err(dsi->dev, "failed to disable MIPI calibration: %d\n",
838 err);
839
840 err = host1x_client_suspend(&dsi->client);
841 if (err < 0)
842 dev_err(dsi->dev, "failed to suspend: %d\n", err);
843}
844
845static void tegra_dsi_encoder_disable(struct drm_encoder *encoder)
846{
847 struct tegra_output *output = encoder_to_output(encoder);
848 struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
849 struct tegra_dsi *dsi = to_dsi(output);
850 u32 value;
851 int err;
852
853 if (output->panel)
854 drm_panel_disable(output->panel);
855
856 tegra_dsi_video_disable(dsi);
857
858 /*
859 * The following accesses registers of the display controller, so make
860 * sure it's only executed when the output is attached to one.
861 */
862 if (dc) {
863 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
864 value &= ~DSI_ENABLE;
865 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
866
867 tegra_dc_commit(dc);
868 }
869
870 err = tegra_dsi_wait_idle(dsi, 100);
871 if (err < 0)
872 dev_dbg(dsi->dev, "failed to idle DSI: %d\n", err);
873
874 tegra_dsi_soft_reset(dsi);
875
876 if (output->panel)
877 drm_panel_unprepare(output->panel);
878
879 tegra_dsi_disable(dsi);
880
881 tegra_dsi_unprepare(dsi);
882}
883
884static int tegra_dsi_prepare(struct tegra_dsi *dsi)
885{
886 int err;
887
888 err = host1x_client_resume(&dsi->client);
889 if (err < 0) {
890 dev_err(dsi->dev, "failed to resume: %d\n", err);
891 return err;
892 }
893
894 err = tegra_mipi_enable(dsi->mipi);
895 if (err < 0)
896 dev_err(dsi->dev, "failed to enable MIPI calibration: %d\n",
897 err);
898
899 err = tegra_dsi_pad_calibrate(dsi);
900 if (err < 0)
901 dev_err(dsi->dev, "MIPI calibration failed: %d\n", err);
902
903 if (dsi->slave)
904 tegra_dsi_prepare(dsi->slave);
905
906 return 0;
907}
908
909static void tegra_dsi_encoder_enable(struct drm_encoder *encoder)
910{
911 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
912 struct tegra_output *output = encoder_to_output(encoder);
913 struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
914 struct tegra_dsi *dsi = to_dsi(output);
915 struct tegra_dsi_state *state;
916 u32 value;
917 int err;
918
919 err = tegra_dsi_prepare(dsi);
920 if (err < 0) {
921 dev_err(dsi->dev, "failed to prepare: %d\n", err);
922 return;
923 }
924
925 state = tegra_dsi_get_state(dsi);
926
927 tegra_dsi_set_timeout(dsi, state->bclk, state->vrefresh);
928
929 /*
930 * The D-PHY timing fields are expressed in byte-clock cycles, so
931 * multiply the period by 8.
932 */
933 tegra_dsi_set_phy_timing(dsi, state->period * 8, &state->timing);
934
935 if (output->panel)
936 drm_panel_prepare(output->panel);
937
938 tegra_dsi_configure(dsi, dc->pipe, mode);
939
940 /* enable display controller */
941 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
942 value |= DSI_ENABLE;
943 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
944
945 tegra_dc_commit(dc);
946
947 /* enable DSI controller */
948 tegra_dsi_enable(dsi);
949
950 if (output->panel)
951 drm_panel_enable(output->panel);
952}
953
954static int
955tegra_dsi_encoder_atomic_check(struct drm_encoder *encoder,
956 struct drm_crtc_state *crtc_state,
957 struct drm_connector_state *conn_state)
958{
959 struct tegra_output *output = encoder_to_output(encoder);
960 struct tegra_dsi_state *state = to_dsi_state(conn_state);
961 struct tegra_dc *dc = to_tegra_dc(conn_state->crtc);
962 struct tegra_dsi *dsi = to_dsi(output);
963 unsigned int scdiv;
964 unsigned long plld;
965 int err;
966
967 state->pclk = crtc_state->mode.clock * 1000;
968
969 err = tegra_dsi_get_muldiv(dsi->format, &state->mul, &state->div);
970 if (err < 0)
971 return err;
972
973 state->lanes = tegra_dsi_get_lanes(dsi);
974
975 err = tegra_dsi_get_format(dsi->format, &state->format);
976 if (err < 0)
977 return err;
978
979 state->vrefresh = drm_mode_vrefresh(&crtc_state->mode);
980
981 /* compute byte clock */
982 state->bclk = (state->pclk * state->mul) / (state->div * state->lanes);
983
984 DRM_DEBUG_KMS("mul: %u, div: %u, lanes: %u\n", state->mul, state->div,
985 state->lanes);
986 DRM_DEBUG_KMS("format: %u, vrefresh: %u\n", state->format,
987 state->vrefresh);
988 DRM_DEBUG_KMS("bclk: %lu\n", state->bclk);
989
990 /*
991 * Compute bit clock and round up to the next MHz.
992 */
993 plld = DIV_ROUND_UP(state->bclk * 8, USEC_PER_SEC) * USEC_PER_SEC;
994 state->period = DIV_ROUND_CLOSEST(NSEC_PER_SEC, plld);
995
996 err = mipi_dphy_timing_get_default(&state->timing, state->period);
997 if (err < 0)
998 return err;
999
1000 err = mipi_dphy_timing_validate(&state->timing, state->period);
1001 if (err < 0) {
1002 dev_err(dsi->dev, "failed to validate D-PHY timing: %d\n", err);
1003 return err;
1004 }
1005
1006 /*
1007 * We divide the frequency by two here, but we make up for that by
1008 * setting the shift clock divider (further below) to half of the
1009 * correct value.
1010 */
1011 plld /= 2;
1012
1013 /*
1014 * Derive pixel clock from bit clock using the shift clock divider.
1015 * Note that this is only half of what we would expect, but we need
1016 * that to make up for the fact that we divided the bit clock by a
1017 * factor of two above.
1018 *
1019 * It's not clear exactly why this is necessary, but the display is
1020 * not working properly otherwise. Perhaps the PLLs cannot generate
1021 * frequencies sufficiently high.
1022 */
1023 scdiv = ((8 * state->mul) / (state->div * state->lanes)) - 2;
1024
1025 err = tegra_dc_state_setup_clock(dc, crtc_state, dsi->clk_parent,
1026 plld, scdiv);
1027 if (err < 0) {
1028 dev_err(output->dev, "failed to setup CRTC state: %d\n", err);
1029 return err;
1030 }
1031
1032 return err;
1033}
1034
1035static const struct drm_encoder_helper_funcs tegra_dsi_encoder_helper_funcs = {
1036 .disable = tegra_dsi_encoder_disable,
1037 .enable = tegra_dsi_encoder_enable,
1038 .atomic_check = tegra_dsi_encoder_atomic_check,
1039};
1040
1041static int tegra_dsi_init(struct host1x_client *client)
1042{
1043 struct drm_device *drm = dev_get_drvdata(client->host);
1044 struct tegra_dsi *dsi = host1x_client_to_dsi(client);
1045 int err;
1046
1047 /* Gangsters must not register their own outputs. */
1048 if (!dsi->master) {
1049 dsi->output.dev = client->dev;
1050
1051 drm_connector_init(drm, &dsi->output.connector,
1052 &tegra_dsi_connector_funcs,
1053 DRM_MODE_CONNECTOR_DSI);
1054 drm_connector_helper_add(&dsi->output.connector,
1055 &tegra_dsi_connector_helper_funcs);
1056 dsi->output.connector.dpms = DRM_MODE_DPMS_OFF;
1057
1058 drm_simple_encoder_init(drm, &dsi->output.encoder,
1059 DRM_MODE_ENCODER_DSI);
1060 drm_encoder_helper_add(&dsi->output.encoder,
1061 &tegra_dsi_encoder_helper_funcs);
1062
1063 drm_connector_attach_encoder(&dsi->output.connector,
1064 &dsi->output.encoder);
1065 drm_connector_register(&dsi->output.connector);
1066
1067 err = tegra_output_init(drm, &dsi->output);
1068 if (err < 0)
1069 dev_err(dsi->dev, "failed to initialize output: %d\n",
1070 err);
1071
1072 dsi->output.encoder.possible_crtcs = 0x3;
1073 }
1074
1075 return 0;
1076}
1077
1078static int tegra_dsi_exit(struct host1x_client *client)
1079{
1080 struct tegra_dsi *dsi = host1x_client_to_dsi(client);
1081
1082 tegra_output_exit(&dsi->output);
1083
1084 return 0;
1085}
1086
1087static int tegra_dsi_runtime_suspend(struct host1x_client *client)
1088{
1089 struct tegra_dsi *dsi = host1x_client_to_dsi(client);
1090 struct device *dev = client->dev;
1091 int err;
1092
1093 if (dsi->rst) {
1094 err = reset_control_assert(dsi->rst);
1095 if (err < 0) {
1096 dev_err(dev, "failed to assert reset: %d\n", err);
1097 return err;
1098 }
1099 }
1100
1101 usleep_range(1000, 2000);
1102
1103 clk_disable_unprepare(dsi->clk_lp);
1104 clk_disable_unprepare(dsi->clk);
1105
1106 regulator_disable(dsi->vdd);
1107 pm_runtime_put_sync(dev);
1108
1109 return 0;
1110}
1111
1112static int tegra_dsi_runtime_resume(struct host1x_client *client)
1113{
1114 struct tegra_dsi *dsi = host1x_client_to_dsi(client);
1115 struct device *dev = client->dev;
1116 int err;
1117
1118 err = pm_runtime_resume_and_get(dev);
1119 if (err < 0) {
1120 dev_err(dev, "failed to get runtime PM: %d\n", err);
1121 return err;
1122 }
1123
1124 err = regulator_enable(dsi->vdd);
1125 if (err < 0) {
1126 dev_err(dev, "failed to enable VDD supply: %d\n", err);
1127 goto put_rpm;
1128 }
1129
1130 err = clk_prepare_enable(dsi->clk);
1131 if (err < 0) {
1132 dev_err(dev, "cannot enable DSI clock: %d\n", err);
1133 goto disable_vdd;
1134 }
1135
1136 err = clk_prepare_enable(dsi->clk_lp);
1137 if (err < 0) {
1138 dev_err(dev, "cannot enable low-power clock: %d\n", err);
1139 goto disable_clk;
1140 }
1141
1142 usleep_range(1000, 2000);
1143
1144 if (dsi->rst) {
1145 err = reset_control_deassert(dsi->rst);
1146 if (err < 0) {
1147 dev_err(dev, "cannot assert reset: %d\n", err);
1148 goto disable_clk_lp;
1149 }
1150 }
1151
1152 return 0;
1153
1154disable_clk_lp:
1155 clk_disable_unprepare(dsi->clk_lp);
1156disable_clk:
1157 clk_disable_unprepare(dsi->clk);
1158disable_vdd:
1159 regulator_disable(dsi->vdd);
1160put_rpm:
1161 pm_runtime_put_sync(dev);
1162 return err;
1163}
1164
1165static const struct host1x_client_ops dsi_client_ops = {
1166 .init = tegra_dsi_init,
1167 .exit = tegra_dsi_exit,
1168 .suspend = tegra_dsi_runtime_suspend,
1169 .resume = tegra_dsi_runtime_resume,
1170};
1171
1172static int tegra_dsi_setup_clocks(struct tegra_dsi *dsi)
1173{
1174 struct clk *parent;
1175 int err;
1176
1177 parent = clk_get_parent(dsi->clk);
1178 if (!parent)
1179 return -EINVAL;
1180
1181 err = clk_set_parent(parent, dsi->clk_parent);
1182 if (err < 0)
1183 return err;
1184
1185 return 0;
1186}
1187
1188static const char * const error_report[16] = {
1189 "SoT Error",
1190 "SoT Sync Error",
1191 "EoT Sync Error",
1192 "Escape Mode Entry Command Error",
1193 "Low-Power Transmit Sync Error",
1194 "Peripheral Timeout Error",
1195 "False Control Error",
1196 "Contention Detected",
1197 "ECC Error, single-bit",
1198 "ECC Error, multi-bit",
1199 "Checksum Error",
1200 "DSI Data Type Not Recognized",
1201 "DSI VC ID Invalid",
1202 "Invalid Transmission Length",
1203 "Reserved",
1204 "DSI Protocol Violation",
1205};
1206
1207static ssize_t tegra_dsi_read_response(struct tegra_dsi *dsi,
1208 const struct mipi_dsi_msg *msg,
1209 size_t count)
1210{
1211 u8 *rx = msg->rx_buf;
1212 unsigned int i, j, k;
1213 size_t size = 0;
1214 u16 errors;
1215 u32 value;
1216
1217 /* read and parse packet header */
1218 value = tegra_dsi_readl(dsi, DSI_RD_DATA);
1219
1220 switch (value & 0x3f) {
1221 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
1222 errors = (value >> 8) & 0xffff;
1223 dev_dbg(dsi->dev, "Acknowledge and error report: %04x\n",
1224 errors);
1225 for (i = 0; i < ARRAY_SIZE(error_report); i++)
1226 if (errors & BIT(i))
1227 dev_dbg(dsi->dev, " %2u: %s\n", i,
1228 error_report[i]);
1229 break;
1230
1231 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
1232 rx[0] = (value >> 8) & 0xff;
1233 size = 1;
1234 break;
1235
1236 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
1237 rx[0] = (value >> 8) & 0xff;
1238 rx[1] = (value >> 16) & 0xff;
1239 size = 2;
1240 break;
1241
1242 case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE:
1243 size = ((value >> 8) & 0xff00) | ((value >> 8) & 0xff);
1244 break;
1245
1246 case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE:
1247 size = ((value >> 8) & 0xff00) | ((value >> 8) & 0xff);
1248 break;
1249
1250 default:
1251 dev_err(dsi->dev, "unhandled response type: %02x\n",
1252 value & 0x3f);
1253 return -EPROTO;
1254 }
1255
1256 size = min(size, msg->rx_len);
1257
1258 if (msg->rx_buf && size > 0) {
1259 for (i = 0, j = 0; i < count - 1; i++, j += 4) {
1260 u8 *rx = msg->rx_buf + j;
1261
1262 value = tegra_dsi_readl(dsi, DSI_RD_DATA);
1263
1264 for (k = 0; k < 4 && (j + k) < msg->rx_len; k++)
1265 rx[j + k] = (value >> (k << 3)) & 0xff;
1266 }
1267 }
1268
1269 return size;
1270}
1271
1272static int tegra_dsi_transmit(struct tegra_dsi *dsi, unsigned long timeout)
1273{
1274 tegra_dsi_writel(dsi, DSI_TRIGGER_HOST, DSI_TRIGGER);
1275
1276 timeout = jiffies + msecs_to_jiffies(timeout);
1277
1278 while (time_before(jiffies, timeout)) {
1279 u32 value = tegra_dsi_readl(dsi, DSI_TRIGGER);
1280 if ((value & DSI_TRIGGER_HOST) == 0)
1281 return 0;
1282
1283 usleep_range(1000, 2000);
1284 }
1285
1286 DRM_DEBUG_KMS("timeout waiting for transmission to complete\n");
1287 return -ETIMEDOUT;
1288}
1289
1290static int tegra_dsi_wait_for_response(struct tegra_dsi *dsi,
1291 unsigned long timeout)
1292{
1293 timeout = jiffies + msecs_to_jiffies(250);
1294
1295 while (time_before(jiffies, timeout)) {
1296 u32 value = tegra_dsi_readl(dsi, DSI_STATUS);
1297 u8 count = value & 0x1f;
1298
1299 if (count > 0)
1300 return count;
1301
1302 usleep_range(1000, 2000);
1303 }
1304
1305 DRM_DEBUG_KMS("peripheral returned no data\n");
1306 return -ETIMEDOUT;
1307}
1308
1309static void tegra_dsi_writesl(struct tegra_dsi *dsi, unsigned long offset,
1310 const void *buffer, size_t size)
1311{
1312 const u8 *buf = buffer;
1313 size_t i, j;
1314 u32 value;
1315
1316 for (j = 0; j < size; j += 4) {
1317 value = 0;
1318
1319 for (i = 0; i < 4 && j + i < size; i++)
1320 value |= buf[j + i] << (i << 3);
1321
1322 tegra_dsi_writel(dsi, value, DSI_WR_DATA);
1323 }
1324}
1325
1326static ssize_t tegra_dsi_host_transfer(struct mipi_dsi_host *host,
1327 const struct mipi_dsi_msg *msg)
1328{
1329 struct tegra_dsi *dsi = host_to_tegra(host);
1330 struct mipi_dsi_packet packet;
1331 const u8 *header;
1332 size_t count;
1333 ssize_t err;
1334 u32 value;
1335
1336 err = mipi_dsi_create_packet(&packet, msg);
1337 if (err < 0)
1338 return err;
1339
1340 header = packet.header;
1341
1342 /* maximum FIFO depth is 1920 words */
1343 if (packet.size > dsi->video_fifo_depth * 4)
1344 return -ENOSPC;
1345
1346 /* reset underflow/overflow flags */
1347 value = tegra_dsi_readl(dsi, DSI_STATUS);
1348 if (value & (DSI_STATUS_UNDERFLOW | DSI_STATUS_OVERFLOW)) {
1349 value = DSI_HOST_CONTROL_FIFO_RESET;
1350 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
1351 usleep_range(10, 20);
1352 }
1353
1354 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
1355 value |= DSI_POWER_CONTROL_ENABLE;
1356 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
1357
1358 usleep_range(5000, 10000);
1359
1360 value = DSI_HOST_CONTROL_CRC_RESET | DSI_HOST_CONTROL_TX_TRIG_HOST |
1361 DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC;
1362
1363 if ((msg->flags & MIPI_DSI_MSG_USE_LPM) == 0)
1364 value |= DSI_HOST_CONTROL_HS;
1365
1366 /*
1367 * The host FIFO has a maximum of 64 words, so larger transmissions
1368 * need to use the video FIFO.
1369 */
1370 if (packet.size > dsi->host_fifo_depth * 4)
1371 value |= DSI_HOST_CONTROL_FIFO_SEL;
1372
1373 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
1374
1375 /*
1376 * For reads and messages with explicitly requested ACK, generate a
1377 * BTA sequence after the transmission of the packet.
1378 */
1379 if ((msg->flags & MIPI_DSI_MSG_REQ_ACK) ||
1380 (msg->rx_buf && msg->rx_len > 0)) {
1381 value = tegra_dsi_readl(dsi, DSI_HOST_CONTROL);
1382 value |= DSI_HOST_CONTROL_PKT_BTA;
1383 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
1384 }
1385
1386 value = DSI_CONTROL_LANES(0) | DSI_CONTROL_HOST_ENABLE;
1387 tegra_dsi_writel(dsi, value, DSI_CONTROL);
1388
1389 /* write packet header, ECC is generated by hardware */
1390 value = header[2] << 16 | header[1] << 8 | header[0];
1391 tegra_dsi_writel(dsi, value, DSI_WR_DATA);
1392
1393 /* write payload (if any) */
1394 if (packet.payload_length > 0)
1395 tegra_dsi_writesl(dsi, DSI_WR_DATA, packet.payload,
1396 packet.payload_length);
1397
1398 err = tegra_dsi_transmit(dsi, 250);
1399 if (err < 0)
1400 return err;
1401
1402 if ((msg->flags & MIPI_DSI_MSG_REQ_ACK) ||
1403 (msg->rx_buf && msg->rx_len > 0)) {
1404 err = tegra_dsi_wait_for_response(dsi, 250);
1405 if (err < 0)
1406 return err;
1407
1408 count = err;
1409
1410 value = tegra_dsi_readl(dsi, DSI_RD_DATA);
1411 switch (value) {
1412 case 0x84:
1413 /*
1414 dev_dbg(dsi->dev, "ACK\n");
1415 */
1416 break;
1417
1418 case 0x87:
1419 /*
1420 dev_dbg(dsi->dev, "ESCAPE\n");
1421 */
1422 break;
1423
1424 default:
1425 dev_err(dsi->dev, "unknown status: %08x\n", value);
1426 break;
1427 }
1428
1429 if (count > 1) {
1430 err = tegra_dsi_read_response(dsi, msg, count);
1431 if (err < 0)
1432 dev_err(dsi->dev,
1433 "failed to parse response: %zd\n",
1434 err);
1435 else {
1436 /*
1437 * For read commands, return the number of
1438 * bytes returned by the peripheral.
1439 */
1440 count = err;
1441 }
1442 }
1443 } else {
1444 /*
1445 * For write commands, we have transmitted the 4-byte header
1446 * plus the variable-length payload.
1447 */
1448 count = 4 + packet.payload_length;
1449 }
1450
1451 return count;
1452}
1453
1454static int tegra_dsi_ganged_setup(struct tegra_dsi *dsi)
1455{
1456 struct clk *parent;
1457 int err;
1458
1459 /* make sure both DSI controllers share the same PLL */
1460 parent = clk_get_parent(dsi->slave->clk);
1461 if (!parent)
1462 return -EINVAL;
1463
1464 err = clk_set_parent(parent, dsi->clk_parent);
1465 if (err < 0)
1466 return err;
1467
1468 return 0;
1469}
1470
1471static int tegra_dsi_host_attach(struct mipi_dsi_host *host,
1472 struct mipi_dsi_device *device)
1473{
1474 struct tegra_dsi *dsi = host_to_tegra(host);
1475
1476 dsi->flags = device->mode_flags;
1477 dsi->format = device->format;
1478 dsi->lanes = device->lanes;
1479
1480 if (dsi->slave) {
1481 int err;
1482
1483 dev_dbg(dsi->dev, "attaching dual-channel device %s\n",
1484 dev_name(&device->dev));
1485
1486 err = tegra_dsi_ganged_setup(dsi);
1487 if (err < 0) {
1488 dev_err(dsi->dev, "failed to set up ganged mode: %d\n",
1489 err);
1490 return err;
1491 }
1492 }
1493
1494 /*
1495 * Slaves don't have a panel associated with them, so they provide
1496 * merely the second channel.
1497 */
1498 if (!dsi->master) {
1499 struct tegra_output *output = &dsi->output;
1500
1501 output->panel = of_drm_find_panel(device->dev.of_node);
1502 if (IS_ERR(output->panel))
1503 output->panel = NULL;
1504
1505 if (output->panel && output->connector.dev)
1506 drm_helper_hpd_irq_event(output->connector.dev);
1507 }
1508
1509 return 0;
1510}
1511
1512static int tegra_dsi_host_detach(struct mipi_dsi_host *host,
1513 struct mipi_dsi_device *device)
1514{
1515 struct tegra_dsi *dsi = host_to_tegra(host);
1516 struct tegra_output *output = &dsi->output;
1517
1518 if (output->panel && &device->dev == output->panel->dev) {
1519 output->panel = NULL;
1520
1521 if (output->connector.dev)
1522 drm_helper_hpd_irq_event(output->connector.dev);
1523 }
1524
1525 return 0;
1526}
1527
1528static const struct mipi_dsi_host_ops tegra_dsi_host_ops = {
1529 .attach = tegra_dsi_host_attach,
1530 .detach = tegra_dsi_host_detach,
1531 .transfer = tegra_dsi_host_transfer,
1532};
1533
1534static int tegra_dsi_ganged_probe(struct tegra_dsi *dsi)
1535{
1536 struct device_node *np;
1537
1538 np = of_parse_phandle(dsi->dev->of_node, "nvidia,ganged-mode", 0);
1539 if (np) {
1540 struct platform_device *gangster = of_find_device_by_node(np);
1541 of_node_put(np);
1542 if (!gangster)
1543 return -EPROBE_DEFER;
1544
1545 dsi->slave = platform_get_drvdata(gangster);
1546 put_device(&gangster->dev);
1547 if (!dsi->slave)
1548 return -EPROBE_DEFER;
1549
1550 dsi->slave->master = dsi;
1551 }
1552
1553 return 0;
1554}
1555
1556static int tegra_dsi_probe(struct platform_device *pdev)
1557{
1558 struct tegra_dsi *dsi;
1559 int err;
1560
1561 dsi = devm_kzalloc(&pdev->dev, sizeof(*dsi), GFP_KERNEL);
1562 if (!dsi)
1563 return -ENOMEM;
1564
1565 dsi->output.dev = dsi->dev = &pdev->dev;
1566 dsi->video_fifo_depth = 1920;
1567 dsi->host_fifo_depth = 64;
1568
1569 err = tegra_dsi_ganged_probe(dsi);
1570 if (err < 0)
1571 return err;
1572
1573 err = tegra_output_probe(&dsi->output);
1574 if (err < 0)
1575 return err;
1576
1577 dsi->output.connector.polled = DRM_CONNECTOR_POLL_HPD;
1578
1579 /*
1580 * Assume these values by default. When a DSI peripheral driver
1581 * attaches to the DSI host, the parameters will be taken from
1582 * the attached device.
1583 */
1584 dsi->flags = MIPI_DSI_MODE_VIDEO;
1585 dsi->format = MIPI_DSI_FMT_RGB888;
1586 dsi->lanes = 4;
1587
1588 if (!pdev->dev.pm_domain) {
1589 dsi->rst = devm_reset_control_get(&pdev->dev, "dsi");
1590 if (IS_ERR(dsi->rst)) {
1591 err = PTR_ERR(dsi->rst);
1592 goto remove;
1593 }
1594 }
1595
1596 dsi->clk = devm_clk_get(&pdev->dev, NULL);
1597 if (IS_ERR(dsi->clk)) {
1598 err = dev_err_probe(&pdev->dev, PTR_ERR(dsi->clk),
1599 "cannot get DSI clock\n");
1600 goto remove;
1601 }
1602
1603 dsi->clk_lp = devm_clk_get(&pdev->dev, "lp");
1604 if (IS_ERR(dsi->clk_lp)) {
1605 err = dev_err_probe(&pdev->dev, PTR_ERR(dsi->clk_lp),
1606 "cannot get low-power clock\n");
1607 goto remove;
1608 }
1609
1610 dsi->clk_parent = devm_clk_get(&pdev->dev, "parent");
1611 if (IS_ERR(dsi->clk_parent)) {
1612 err = dev_err_probe(&pdev->dev, PTR_ERR(dsi->clk_parent),
1613 "cannot get parent clock\n");
1614 goto remove;
1615 }
1616
1617 dsi->vdd = devm_regulator_get(&pdev->dev, "avdd-dsi-csi");
1618 if (IS_ERR(dsi->vdd)) {
1619 err = dev_err_probe(&pdev->dev, PTR_ERR(dsi->vdd),
1620 "cannot get VDD supply\n");
1621 goto remove;
1622 }
1623
1624 err = tegra_dsi_setup_clocks(dsi);
1625 if (err < 0) {
1626 dev_err(&pdev->dev, "cannot setup clocks\n");
1627 goto remove;
1628 }
1629
1630 dsi->regs = devm_platform_ioremap_resource(pdev, 0);
1631 if (IS_ERR(dsi->regs)) {
1632 err = PTR_ERR(dsi->regs);
1633 goto remove;
1634 }
1635
1636 dsi->mipi = tegra_mipi_request(&pdev->dev, pdev->dev.of_node);
1637 if (IS_ERR(dsi->mipi)) {
1638 err = PTR_ERR(dsi->mipi);
1639 goto remove;
1640 }
1641
1642 dsi->host.ops = &tegra_dsi_host_ops;
1643 dsi->host.dev = &pdev->dev;
1644
1645 err = mipi_dsi_host_register(&dsi->host);
1646 if (err < 0) {
1647 dev_err(&pdev->dev, "failed to register DSI host: %d\n", err);
1648 goto mipi_free;
1649 }
1650
1651 platform_set_drvdata(pdev, dsi);
1652 pm_runtime_enable(&pdev->dev);
1653
1654 INIT_LIST_HEAD(&dsi->client.list);
1655 dsi->client.ops = &dsi_client_ops;
1656 dsi->client.dev = &pdev->dev;
1657
1658 err = host1x_client_register(&dsi->client);
1659 if (err < 0) {
1660 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
1661 err);
1662 goto unregister;
1663 }
1664
1665 return 0;
1666
1667unregister:
1668 pm_runtime_disable(&pdev->dev);
1669 mipi_dsi_host_unregister(&dsi->host);
1670mipi_free:
1671 tegra_mipi_free(dsi->mipi);
1672remove:
1673 tegra_output_remove(&dsi->output);
1674 return err;
1675}
1676
1677static void tegra_dsi_remove(struct platform_device *pdev)
1678{
1679 struct tegra_dsi *dsi = platform_get_drvdata(pdev);
1680
1681 pm_runtime_disable(&pdev->dev);
1682
1683 host1x_client_unregister(&dsi->client);
1684
1685 tegra_output_remove(&dsi->output);
1686
1687 mipi_dsi_host_unregister(&dsi->host);
1688 tegra_mipi_free(dsi->mipi);
1689}
1690
1691static const struct of_device_id tegra_dsi_of_match[] = {
1692 { .compatible = "nvidia,tegra210-dsi", },
1693 { .compatible = "nvidia,tegra132-dsi", },
1694 { .compatible = "nvidia,tegra124-dsi", },
1695 { .compatible = "nvidia,tegra114-dsi", },
1696 { },
1697};
1698MODULE_DEVICE_TABLE(of, tegra_dsi_of_match);
1699
1700struct platform_driver tegra_dsi_driver = {
1701 .driver = {
1702 .name = "tegra-dsi",
1703 .of_match_table = tegra_dsi_of_match,
1704 },
1705 .probe = tegra_dsi_probe,
1706 .remove = tegra_dsi_remove,
1707};