Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
4 * Author: Tomi Valkeinen <tomi.valkeinen@ti.com>
5 */
6
7#ifndef __TIDSS_DISPC_H__
8#define __TIDSS_DISPC_H__
9
10#include <drm/drm_color_mgmt.h>
11
12#include "tidss_drv.h"
13
14struct dispc_device;
15
16struct drm_crtc_state;
17struct drm_plane_state;
18
19enum tidss_gamma_type { TIDSS_GAMMA_8BIT, TIDSS_GAMMA_10BIT };
20
21struct tidss_vp_feat {
22 struct tidss_vp_color_feat {
23 u32 gamma_size;
24 enum tidss_gamma_type gamma_type;
25 bool has_ctm;
26 } color;
27};
28
29struct tidss_plane_feat {
30 struct tidss_plane_color_feat {
31 u32 encodings;
32 u32 ranges;
33 enum drm_color_encoding default_encoding;
34 enum drm_color_range default_range;
35 } color;
36 struct tidss_plane_blend_feat {
37 bool global_alpha;
38 } blend;
39};
40
41struct dispc_features_scaling {
42 u32 in_width_max_5tap_rgb;
43 u32 in_width_max_3tap_rgb;
44 u32 in_width_max_5tap_yuv;
45 u32 in_width_max_3tap_yuv;
46 u32 upscale_limit;
47 u32 downscale_limit_5tap;
48 u32 downscale_limit_3tap;
49 u32 xinc_max;
50};
51
52struct dispc_vid_info {
53 const char *name; /* Should match dt reg names */
54 u32 hw_id;
55 bool is_lite;
56};
57
58struct dispc_errata {
59 bool i2000; /* DSS Does Not Support YUV Pixel Data Formats */
60};
61
62enum dispc_vp_bus_type {
63 DISPC_VP_DPI, /* DPI output */
64 DISPC_VP_OLDI_AM65X, /* OLDI (LVDS) output for AM65x DSS */
65 DISPC_VP_INTERNAL, /* SoC internal routing */
66 DISPC_VP_TIED_OFF, /* Tied off / Unavailable */
67 DISPC_VP_MAX_BUS_TYPE,
68};
69
70enum dispc_dss_subrevision {
71 DISPC_K2G,
72 DISPC_AM625,
73 DISPC_AM62L,
74 DISPC_AM62A7,
75 DISPC_AM65X,
76 DISPC_J721E,
77};
78
79struct dispc_features {
80 struct dispc_features_scaling scaling;
81
82 enum dispc_dss_subrevision subrev;
83
84 const char *common;
85 const u16 *common_regs;
86 u32 num_vps;
87 const char *vp_name[TIDSS_MAX_PORTS]; /* Should match dt reg names */
88 const char *ovr_name[TIDSS_MAX_PORTS]; /* Should match dt reg names */
89 const char *vpclk_name[TIDSS_MAX_PORTS]; /* Should match dt clk names */
90 const enum dispc_vp_bus_type vp_bus_type[TIDSS_MAX_PORTS];
91 struct tidss_vp_feat vp_feat;
92 u32 num_vids;
93 struct dispc_vid_info vid_info[TIDSS_MAX_PLANES];
94 u32 vid_order[TIDSS_MAX_PLANES];
95};
96
97extern const struct dispc_features dispc_k2g_feats;
98extern const struct dispc_features dispc_am625_feats;
99extern const struct dispc_features dispc_am62a7_feats;
100extern const struct dispc_features dispc_am62l_feats;
101extern const struct dispc_features dispc_am65x_feats;
102extern const struct dispc_features dispc_j721e_feats;
103
104int tidss_configure_oldi(struct tidss_device *tidss, u32 hw_videoport,
105 u32 oldi_cfg);
106void tidss_disable_oldi(struct tidss_device *tidss, u32 hw_videoport);
107unsigned int dispc_pclk_diff(unsigned long rate, unsigned long real_rate);
108
109void dispc_set_irqenable(struct dispc_device *dispc, dispc_irq_t mask);
110dispc_irq_t dispc_read_and_clear_irqstatus(struct dispc_device *dispc);
111
112void dispc_ovr_set_plane(struct dispc_device *dispc, u32 hw_plane,
113 u32 hw_videoport, u32 x, u32 y, u32 layer);
114void dispc_ovr_enable_layer(struct dispc_device *dispc,
115 u32 hw_videoport, u32 layer, bool enable);
116
117void dispc_vp_prepare(struct dispc_device *dispc, u32 hw_videoport,
118 const struct drm_crtc_state *state);
119void dispc_vp_enable(struct dispc_device *dispc, u32 hw_videoport);
120void dispc_vp_disable(struct dispc_device *dispc, u32 hw_videoport);
121void dispc_vp_unprepare(struct dispc_device *dispc, u32 hw_videoport);
122bool dispc_vp_go_busy(struct dispc_device *dispc, u32 hw_videoport);
123void dispc_vp_go(struct dispc_device *dispc, u32 hw_videoport);
124int dispc_vp_bus_check(struct dispc_device *dispc, u32 hw_videoport,
125 const struct drm_crtc_state *state);
126enum drm_mode_status dispc_vp_mode_valid(struct dispc_device *dispc,
127 u32 hw_videoport,
128 const struct drm_display_mode *mode);
129int dispc_vp_enable_clk(struct dispc_device *dispc, u32 hw_videoport);
130void dispc_vp_disable_clk(struct dispc_device *dispc, u32 hw_videoport);
131int dispc_vp_set_clk_rate(struct dispc_device *dispc, u32 hw_videoport,
132 unsigned long rate);
133void dispc_vp_setup(struct dispc_device *dispc, u32 hw_videoport,
134 const struct drm_crtc_state *state, bool newmodeset);
135
136int dispc_runtime_suspend(struct dispc_device *dispc);
137int dispc_runtime_resume(struct dispc_device *dispc);
138
139int dispc_plane_check(struct dispc_device *dispc, u32 hw_plane,
140 const struct drm_plane_state *state,
141 u32 hw_videoport);
142void dispc_plane_setup(struct dispc_device *dispc, u32 hw_plane,
143 const struct drm_plane_state *state,
144 u32 hw_videoport);
145void dispc_plane_enable(struct dispc_device *dispc, u32 hw_plane, bool enable);
146const u32 *dispc_plane_formats(struct dispc_device *dispc, unsigned int *len);
147
148int dispc_init(struct tidss_device *tidss);
149void dispc_remove(struct tidss_device *tidss);
150
151#endif