Linux kernel mirror (for testing)
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linux
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2012 Texas Instruments
4 * Author: Rob Clark <robdclark@gmail.com>
5 */
6
7/* LCDC DRM driver, based on da8xx-fb */
8
9#include <linux/mod_devicetable.h>
10#include <linux/pinctrl/consumer.h>
11#include <linux/platform_device.h>
12#include <linux/pm_runtime.h>
13
14#include <drm/clients/drm_client_setup.h>
15#include <drm/drm_atomic_helper.h>
16#include <drm/drm_debugfs.h>
17#include <drm/drm_drv.h>
18#include <drm/drm_fbdev_dma.h>
19#include <drm/drm_fourcc.h>
20#include <drm/drm_gem_dma_helper.h>
21#include <drm/drm_gem_framebuffer_helper.h>
22#include <drm/drm_mm.h>
23#include <drm/drm_module.h>
24#include <drm/drm_probe_helper.h>
25#include <drm/drm_vblank.h>
26
27
28#include "tilcdc_drv.h"
29#include "tilcdc_encoder.h"
30#include "tilcdc_regs.h"
31
32enum tilcdc_variant {
33 AM33XX_TILCDC,
34 DA850_TILCDC,
35};
36
37static const u32 tilcdc_rev1_formats[] = { DRM_FORMAT_RGB565 };
38
39static const u32 tilcdc_straight_formats[] = { DRM_FORMAT_RGB565,
40 DRM_FORMAT_BGR888,
41 DRM_FORMAT_XBGR8888 };
42
43static const u32 tilcdc_crossed_formats[] = { DRM_FORMAT_BGR565,
44 DRM_FORMAT_RGB888,
45 DRM_FORMAT_XRGB8888 };
46
47static const u32 tilcdc_legacy_formats[] = { DRM_FORMAT_RGB565,
48 DRM_FORMAT_RGB888,
49 DRM_FORMAT_XRGB8888 };
50
51static int tilcdc_atomic_check(struct drm_device *dev,
52 struct drm_atomic_state *state)
53{
54 int ret;
55
56 ret = drm_atomic_helper_check_modeset(dev, state);
57 if (ret)
58 return ret;
59
60 ret = drm_atomic_helper_check_planes(dev, state);
61 if (ret)
62 return ret;
63
64 /*
65 * tilcdc ->atomic_check can update ->mode_changed if pixel format
66 * changes, hence will we check modeset changes again.
67 */
68 ret = drm_atomic_helper_check_modeset(dev, state);
69 if (ret)
70 return ret;
71
72 return ret;
73}
74
75static const struct drm_mode_config_funcs mode_config_funcs = {
76 .fb_create = drm_gem_fb_create,
77 .atomic_check = tilcdc_atomic_check,
78 .atomic_commit = drm_atomic_helper_commit,
79};
80
81static void modeset_init(struct drm_device *dev)
82{
83 struct tilcdc_drm_private *priv = ddev_to_tilcdc_priv(dev);
84
85 dev->mode_config.min_width = 0;
86 dev->mode_config.min_height = 0;
87 dev->mode_config.max_width = priv->max_width;
88 dev->mode_config.max_height = 2048;
89 dev->mode_config.funcs = &mode_config_funcs;
90}
91
92#ifdef CONFIG_CPU_FREQ
93static int cpufreq_transition(struct notifier_block *nb,
94 unsigned long val, void *data)
95{
96 struct tilcdc_drm_private *priv = container_of(nb,
97 struct tilcdc_drm_private, freq_transition);
98
99 if (val == CPUFREQ_POSTCHANGE)
100 tilcdc_crtc_update_clk(priv->crtc);
101
102 return 0;
103}
104#endif
105
106static irqreturn_t tilcdc_irq(int irq, void *arg)
107{
108 struct drm_device *dev = arg;
109 struct tilcdc_drm_private *priv = ddev_to_tilcdc_priv(dev);
110
111 return tilcdc_crtc_irq(priv->crtc);
112}
113
114static int tilcdc_irq_install(struct drm_device *dev, unsigned int irq)
115{
116 struct tilcdc_drm_private *priv = ddev_to_tilcdc_priv(dev);
117 int ret;
118
119 ret = request_irq(irq, tilcdc_irq, 0, dev->driver->name, dev);
120 if (ret)
121 return ret;
122
123 priv->irq_enabled = true;
124
125 return 0;
126}
127
128static void tilcdc_irq_uninstall(struct drm_device *dev)
129{
130 struct tilcdc_drm_private *priv = ddev_to_tilcdc_priv(dev);
131
132 if (!priv->irq_enabled)
133 return;
134
135 free_irq(priv->irq, dev);
136 priv->irq_enabled = false;
137}
138
139/*
140 * DRM operations:
141 */
142
143#if defined(CONFIG_DEBUG_FS)
144static const struct {
145 const char *name;
146 uint8_t rev;
147 uint8_t save;
148 uint32_t reg;
149} registers[] = {
150#define REG(rev, save, reg) { #reg, rev, save, reg }
151 /* exists in revision 1: */
152 REG(1, false, LCDC_PID_REG),
153 REG(1, true, LCDC_CTRL_REG),
154 REG(1, false, LCDC_STAT_REG),
155 REG(1, true, LCDC_RASTER_CTRL_REG),
156 REG(1, true, LCDC_RASTER_TIMING_0_REG),
157 REG(1, true, LCDC_RASTER_TIMING_1_REG),
158 REG(1, true, LCDC_RASTER_TIMING_2_REG),
159 REG(1, true, LCDC_DMA_CTRL_REG),
160 REG(1, true, LCDC_DMA_FB_BASE_ADDR_0_REG),
161 REG(1, true, LCDC_DMA_FB_CEILING_ADDR_0_REG),
162 REG(1, true, LCDC_DMA_FB_BASE_ADDR_1_REG),
163 REG(1, true, LCDC_DMA_FB_CEILING_ADDR_1_REG),
164 /* new in revision 2: */
165 REG(2, false, LCDC_RAW_STAT_REG),
166 REG(2, false, LCDC_MASKED_STAT_REG),
167 REG(2, true, LCDC_INT_ENABLE_SET_REG),
168 REG(2, false, LCDC_INT_ENABLE_CLR_REG),
169 REG(2, false, LCDC_END_OF_INT_IND_REG),
170 REG(2, true, LCDC_CLK_ENABLE_REG),
171#undef REG
172};
173
174static int tilcdc_regs_show(struct seq_file *m, void *arg)
175{
176 struct drm_info_node *node = (struct drm_info_node *) m->private;
177 struct drm_device *dev = node->minor->dev;
178 struct tilcdc_drm_private *priv = ddev_to_tilcdc_priv(dev);
179 unsigned i;
180
181 pm_runtime_get_sync(dev->dev);
182
183 seq_printf(m, "revision: %d\n", priv->rev);
184
185 for (i = 0; i < ARRAY_SIZE(registers); i++)
186 if (priv->rev >= registers[i].rev)
187 seq_printf(m, "%s:\t %08x\n", registers[i].name,
188 tilcdc_read(dev, registers[i].reg));
189
190 pm_runtime_put_sync(dev->dev);
191
192 return 0;
193}
194
195static int tilcdc_mm_show(struct seq_file *m, void *arg)
196{
197 struct drm_info_node *node = (struct drm_info_node *) m->private;
198 struct drm_device *dev = node->minor->dev;
199 struct drm_printer p = drm_seq_file_printer(m);
200 drm_mm_print(&dev->vma_offset_manager->vm_addr_space_mm, &p);
201 return 0;
202}
203
204static struct drm_info_list tilcdc_debugfs_list[] = {
205 { "regs", tilcdc_regs_show, 0, NULL },
206 { "mm", tilcdc_mm_show, 0, NULL },
207};
208
209static void tilcdc_debugfs_init(struct drm_minor *minor)
210{
211 drm_debugfs_create_files(tilcdc_debugfs_list,
212 ARRAY_SIZE(tilcdc_debugfs_list),
213 minor->debugfs_root, minor);
214}
215#endif
216
217DEFINE_DRM_GEM_DMA_FOPS(fops);
218
219static const struct drm_driver tilcdc_driver = {
220 .driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
221 DRM_GEM_DMA_DRIVER_OPS,
222 DRM_FBDEV_DMA_DRIVER_OPS,
223#ifdef CONFIG_DEBUG_FS
224 .debugfs_init = tilcdc_debugfs_init,
225#endif
226 .fops = &fops,
227 .name = "tilcdc",
228 .desc = "TI LCD Controller DRM",
229 .major = 1,
230 .minor = 0,
231};
232
233/*
234 * Power management:
235 */
236
237static int tilcdc_pm_suspend(struct device *dev)
238{
239 struct drm_device *ddev = dev_get_drvdata(dev);
240 int ret = 0;
241
242 ret = drm_mode_config_helper_suspend(ddev);
243
244 /* Select sleep pin state */
245 pinctrl_pm_select_sleep_state(dev);
246
247 return ret;
248}
249
250static int tilcdc_pm_resume(struct device *dev)
251{
252 struct drm_device *ddev = dev_get_drvdata(dev);
253
254 /* Select default pin state */
255 pinctrl_pm_select_default_state(dev);
256 return drm_mode_config_helper_resume(ddev);
257}
258
259static DEFINE_SIMPLE_DEV_PM_OPS(tilcdc_pm_ops,
260 tilcdc_pm_suspend, tilcdc_pm_resume);
261
262static int tilcdc_pdev_probe(struct platform_device *pdev)
263{
264 struct device_node *node = pdev->dev.of_node;
265 struct tilcdc_drm_private *priv;
266 struct device *dev = &pdev->dev;
267 enum tilcdc_variant variant;
268 struct drm_device *ddev;
269 u32 bpp = 0;
270 int ret;
271
272 priv = devm_drm_dev_alloc(dev, &tilcdc_driver,
273 struct tilcdc_drm_private, ddev);
274 if (IS_ERR(priv))
275 return PTR_ERR(priv);
276
277 variant = (uintptr_t)of_device_get_match_data(dev);
278
279 platform_set_drvdata(pdev, priv);
280 ddev = &priv->ddev;
281 ret = drmm_mode_config_init(ddev);
282 if (ret)
283 return ret;
284
285 priv->wq = alloc_ordered_workqueue("tilcdc", 0);
286 if (!priv->wq)
287 return -ENOMEM;
288
289 priv->mmio = devm_platform_ioremap_resource(pdev, 0);
290 if (IS_ERR(priv->mmio)) {
291 drm_err(ddev, "failed to request / ioremap\n");
292 ret = PTR_ERR(priv->mmio);
293 goto free_wq;
294 }
295
296 priv->clk = clk_get(dev, "fck");
297 if (IS_ERR(priv->clk)) {
298 drm_err(ddev, "failed to get functional clock\n");
299 ret = -ENODEV;
300 goto free_wq;
301 }
302
303 pm_runtime_enable(dev);
304
305 /* Determine LCD IP Version */
306 pm_runtime_get_sync(dev);
307 switch (tilcdc_read(ddev, LCDC_PID_REG)) {
308 case 0x4c100102:
309 priv->rev = 1;
310 break;
311 case 0x4f200800:
312 case 0x4f201000:
313 priv->rev = 2;
314 break;
315 default:
316 drm_warn(ddev, "Unknown PID Reg value 0x%08x, "
317 "defaulting to LCD revision 1\n",
318 tilcdc_read(ddev, LCDC_PID_REG));
319 priv->rev = 1;
320 break;
321 }
322
323 pm_runtime_put_sync(dev);
324
325 if (priv->rev == 1) {
326 DBG("Revision 1 LCDC supports only RGB565 format");
327 priv->pixelformats = tilcdc_rev1_formats;
328 priv->num_pixelformats = ARRAY_SIZE(tilcdc_rev1_formats);
329 bpp = 16;
330 } else {
331 const char *str = "\0";
332
333 of_property_read_string(node, "blue-and-red-wiring", &str);
334 if (0 == strcmp(str, "crossed")) {
335 DBG("Configured for crossed blue and red wires");
336 priv->pixelformats = tilcdc_crossed_formats;
337 priv->num_pixelformats =
338 ARRAY_SIZE(tilcdc_crossed_formats);
339 bpp = 32; /* Choose bpp with RGB support for fbdef */
340 } else if (0 == strcmp(str, "straight")) {
341 DBG("Configured for straight blue and red wires");
342 priv->pixelformats = tilcdc_straight_formats;
343 priv->num_pixelformats =
344 ARRAY_SIZE(tilcdc_straight_formats);
345 bpp = 16; /* Choose bpp with RGB support for fbdef */
346 } else {
347 DBG("Blue and red wiring '%s' unknown, use legacy mode",
348 str);
349 priv->pixelformats = tilcdc_legacy_formats;
350 priv->num_pixelformats =
351 ARRAY_SIZE(tilcdc_legacy_formats);
352 bpp = 16; /* This is just a guess */
353 }
354 }
355
356 if (of_property_read_u32(node, "max-bandwidth", &priv->max_bandwidth))
357 priv->max_bandwidth = TILCDC_DEFAULT_MAX_BANDWIDTH;
358
359 DBG("Maximum Bandwidth Value %d", priv->max_bandwidth);
360
361 if (of_property_read_u32(node, "max-width", &priv->max_width)) {
362 if (priv->rev == 1)
363 priv->max_width = TILCDC_DEFAULT_MAX_WIDTH_V1;
364 else
365 priv->max_width = TILCDC_DEFAULT_MAX_WIDTH_V2;
366 }
367
368 DBG("Maximum Horizontal Pixel Width Value %dpixels", priv->max_width);
369
370 if (of_property_read_u32(node, "max-pixelclock",
371 &priv->max_pixelclock))
372 priv->max_pixelclock = TILCDC_DEFAULT_MAX_PIXELCLOCK;
373
374 DBG("Maximum Pixel Clock Value %dKHz", priv->max_pixelclock);
375
376 if (variant == DA850_TILCDC)
377 priv->fifo_th = 16;
378 else
379 priv->fifo_th = 8;
380
381 ret = tilcdc_crtc_create(ddev);
382 if (ret < 0) {
383 drm_err(ddev, "failed to create crtc\n");
384 goto disable_pm;
385 }
386 modeset_init(ddev);
387
388#ifdef CONFIG_CPU_FREQ
389 priv->freq_transition.notifier_call = cpufreq_transition;
390 ret = cpufreq_register_notifier(&priv->freq_transition,
391 CPUFREQ_TRANSITION_NOTIFIER);
392 if (ret) {
393 drm_err(ddev, "failed to register cpufreq notifier\n");
394 priv->freq_transition.notifier_call = NULL;
395 goto disable_pm;
396 }
397#endif
398
399 ret = tilcdc_encoder_create(ddev);
400 if (ret)
401 goto unregister_cpufreq_notif;
402
403 if (!priv->connector) {
404 drm_err(ddev, "no encoders/connectors found\n");
405 ret = -EPROBE_DEFER;
406 goto unregister_cpufreq_notif;
407 }
408
409 ret = drm_vblank_init(ddev, 1);
410 if (ret < 0) {
411 drm_err(ddev, "failed to initialize vblank\n");
412 goto unregister_cpufreq_notif;
413 }
414
415 ret = platform_get_irq(pdev, 0);
416 if (ret < 0)
417 goto unregister_cpufreq_notif;
418 priv->irq = ret;
419
420 ret = tilcdc_irq_install(ddev, priv->irq);
421 if (ret < 0) {
422 drm_err(ddev, "failed to install IRQ handler\n");
423 goto unregister_cpufreq_notif;
424 }
425
426 drm_mode_config_reset(ddev);
427
428 drm_kms_helper_poll_init(ddev);
429
430 ret = drm_dev_register(ddev, 0);
431 if (ret)
432 goto stop_poll;
433
434 drm_client_setup_with_color_mode(ddev, bpp);
435
436 return 0;
437
438stop_poll:
439 drm_kms_helper_poll_fini(ddev);
440 tilcdc_irq_uninstall(ddev);
441unregister_cpufreq_notif:
442#ifdef CONFIG_CPU_FREQ
443 cpufreq_unregister_notifier(&priv->freq_transition,
444 CPUFREQ_TRANSITION_NOTIFIER);
445#endif
446disable_pm:
447 pm_runtime_disable(dev);
448 clk_put(priv->clk);
449free_wq:
450 destroy_workqueue(priv->wq);
451
452 return ret;
453}
454
455static void tilcdc_pdev_remove(struct platform_device *pdev)
456{
457 struct tilcdc_drm_private *priv = platform_get_drvdata(pdev);
458 struct drm_device *ddev = &priv->ddev;
459
460 drm_dev_unregister(ddev);
461 drm_kms_helper_poll_fini(ddev);
462 tilcdc_irq_uninstall(ddev);
463#ifdef CONFIG_CPU_FREQ
464 cpufreq_unregister_notifier(&priv->freq_transition,
465 CPUFREQ_TRANSITION_NOTIFIER);
466#endif
467 pm_runtime_disable(&pdev->dev);
468 clk_put(priv->clk);
469 destroy_workqueue(priv->wq);
470}
471
472static void tilcdc_pdev_shutdown(struct platform_device *pdev)
473{
474 struct tilcdc_drm_private *priv = platform_get_drvdata(pdev);
475 struct drm_device *ddev = &priv->ddev;
476
477 drm_atomic_helper_shutdown(ddev);
478}
479
480static const struct of_device_id tilcdc_of_match[] = {
481 { .compatible = "ti,am33xx-tilcdc", .data = (void *)AM33XX_TILCDC},
482 { .compatible = "ti,da850-tilcdc", .data = (void *)DA850_TILCDC},
483 { },
484};
485MODULE_DEVICE_TABLE(of, tilcdc_of_match);
486
487static struct platform_driver tilcdc_platform_driver = {
488 .probe = tilcdc_pdev_probe,
489 .remove = tilcdc_pdev_remove,
490 .shutdown = tilcdc_pdev_shutdown,
491 .driver = {
492 .name = "tilcdc",
493 .pm = pm_sleep_ptr(&tilcdc_pm_ops),
494 .of_match_table = tilcdc_of_match,
495 },
496};
497
498drm_module_platform_driver(tilcdc_platform_driver);
499
500MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
501MODULE_DESCRIPTION("TI LCD Controller DRM Driver");
502MODULE_LICENSE("GPL");