Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1// SPDX-License-Identifier: GPL-2.0 or MIT
2
3// We don't expect that all the registers and fields will be used, even in the
4// future.
5//
6// Nevertheless, it is useful to have most of them defined, like the C driver
7// does.
8#![allow(dead_code)]
9
10use kernel::{
11 bits::bit_u32,
12 device::{
13 Bound,
14 Device, //
15 },
16 devres::Devres,
17 io::Io,
18 prelude::*, //
19};
20
21use crate::driver::IoMem;
22
23/// Represents a register in the Register Set
24///
25/// TODO: Replace this with the Nova `register!()` macro when it is available.
26/// In particular, this will automatically give us 64bit register reads and
27/// writes.
28pub(crate) struct Register<const OFFSET: usize>;
29
30impl<const OFFSET: usize> Register<OFFSET> {
31 #[inline]
32 pub(crate) fn read(&self, dev: &Device<Bound>, iomem: &Devres<IoMem>) -> Result<u32> {
33 let value = (*iomem).access(dev)?.read32(OFFSET);
34 Ok(value)
35 }
36
37 #[inline]
38 pub(crate) fn write(&self, dev: &Device<Bound>, iomem: &Devres<IoMem>, value: u32) -> Result {
39 (*iomem).access(dev)?.write32(value, OFFSET);
40 Ok(())
41 }
42}
43
44pub(crate) const GPU_ID: Register<0x0> = Register;
45pub(crate) const GPU_L2_FEATURES: Register<0x4> = Register;
46pub(crate) const GPU_CORE_FEATURES: Register<0x8> = Register;
47pub(crate) const GPU_CSF_ID: Register<0x1c> = Register;
48pub(crate) const GPU_REVID: Register<0x280> = Register;
49pub(crate) const GPU_TILER_FEATURES: Register<0xc> = Register;
50pub(crate) const GPU_MEM_FEATURES: Register<0x10> = Register;
51pub(crate) const GPU_MMU_FEATURES: Register<0x14> = Register;
52pub(crate) const GPU_AS_PRESENT: Register<0x18> = Register;
53pub(crate) const GPU_IRQ_RAWSTAT: Register<0x20> = Register;
54
55pub(crate) const GPU_IRQ_RAWSTAT_FAULT: u32 = bit_u32(0);
56pub(crate) const GPU_IRQ_RAWSTAT_PROTECTED_FAULT: u32 = bit_u32(1);
57pub(crate) const GPU_IRQ_RAWSTAT_RESET_COMPLETED: u32 = bit_u32(8);
58pub(crate) const GPU_IRQ_RAWSTAT_POWER_CHANGED_SINGLE: u32 = bit_u32(9);
59pub(crate) const GPU_IRQ_RAWSTAT_POWER_CHANGED_ALL: u32 = bit_u32(10);
60pub(crate) const GPU_IRQ_RAWSTAT_CLEAN_CACHES_COMPLETED: u32 = bit_u32(17);
61pub(crate) const GPU_IRQ_RAWSTAT_DOORBELL_STATUS: u32 = bit_u32(18);
62pub(crate) const GPU_IRQ_RAWSTAT_MCU_STATUS: u32 = bit_u32(19);
63
64pub(crate) const GPU_IRQ_CLEAR: Register<0x24> = Register;
65pub(crate) const GPU_IRQ_MASK: Register<0x28> = Register;
66pub(crate) const GPU_IRQ_STAT: Register<0x2c> = Register;
67pub(crate) const GPU_CMD: Register<0x30> = Register;
68pub(crate) const GPU_CMD_SOFT_RESET: u32 = 1 | (1 << 8);
69pub(crate) const GPU_CMD_HARD_RESET: u32 = 1 | (2 << 8);
70pub(crate) const GPU_THREAD_FEATURES: Register<0xac> = Register;
71pub(crate) const GPU_THREAD_MAX_THREADS: Register<0xa0> = Register;
72pub(crate) const GPU_THREAD_MAX_WORKGROUP_SIZE: Register<0xa4> = Register;
73pub(crate) const GPU_THREAD_MAX_BARRIER_SIZE: Register<0xa8> = Register;
74pub(crate) const GPU_TEXTURE_FEATURES0: Register<0xb0> = Register;
75pub(crate) const GPU_SHADER_PRESENT_LO: Register<0x100> = Register;
76pub(crate) const GPU_SHADER_PRESENT_HI: Register<0x104> = Register;
77pub(crate) const GPU_TILER_PRESENT_LO: Register<0x110> = Register;
78pub(crate) const GPU_TILER_PRESENT_HI: Register<0x114> = Register;
79pub(crate) const GPU_L2_PRESENT_LO: Register<0x120> = Register;
80pub(crate) const GPU_L2_PRESENT_HI: Register<0x124> = Register;
81pub(crate) const L2_READY_LO: Register<0x160> = Register;
82pub(crate) const L2_READY_HI: Register<0x164> = Register;
83pub(crate) const L2_PWRON_LO: Register<0x1a0> = Register;
84pub(crate) const L2_PWRON_HI: Register<0x1a4> = Register;
85pub(crate) const L2_PWRTRANS_LO: Register<0x220> = Register;
86pub(crate) const L2_PWRTRANS_HI: Register<0x204> = Register;
87pub(crate) const L2_PWRACTIVE_LO: Register<0x260> = Register;
88pub(crate) const L2_PWRACTIVE_HI: Register<0x264> = Register;
89
90pub(crate) const MCU_CONTROL: Register<0x700> = Register;
91pub(crate) const MCU_CONTROL_ENABLE: u32 = 1;
92pub(crate) const MCU_CONTROL_AUTO: u32 = 2;
93pub(crate) const MCU_CONTROL_DISABLE: u32 = 0;
94
95pub(crate) const MCU_STATUS: Register<0x704> = Register;
96pub(crate) const MCU_STATUS_DISABLED: u32 = 0;
97pub(crate) const MCU_STATUS_ENABLED: u32 = 1;
98pub(crate) const MCU_STATUS_HALT: u32 = 2;
99pub(crate) const MCU_STATUS_FATAL: u32 = 3;
100
101pub(crate) const GPU_COHERENCY_FEATURES: Register<0x300> = Register;
102
103pub(crate) const JOB_IRQ_RAWSTAT: Register<0x1000> = Register;
104pub(crate) const JOB_IRQ_CLEAR: Register<0x1004> = Register;
105pub(crate) const JOB_IRQ_MASK: Register<0x1008> = Register;
106pub(crate) const JOB_IRQ_STAT: Register<0x100c> = Register;
107
108pub(crate) const JOB_IRQ_GLOBAL_IF: u32 = bit_u32(31);
109
110pub(crate) const MMU_IRQ_RAWSTAT: Register<0x2000> = Register;
111pub(crate) const MMU_IRQ_CLEAR: Register<0x2004> = Register;
112pub(crate) const MMU_IRQ_MASK: Register<0x2008> = Register;
113pub(crate) const MMU_IRQ_STAT: Register<0x200c> = Register;