Linux kernel mirror (for testing)
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linux
1// SPDX-License-Identifier: GPL-2.0+
2/* Copyright (C) 2014-2018 Broadcom */
3
4/**
5 * DOC: Broadcom V3D Graphics Driver
6 *
7 * This driver supports the Broadcom V3D 3.3 and 4.1 OpenGL ES GPUs.
8 * For V3D 2.x support, see the VC4 driver.
9 *
10 * The V3D GPU includes a tiled render (composed of a bin and render
11 * pipelines), the TFU (texture formatting unit), and the CSD (compute
12 * shader dispatch).
13 */
14
15#include <linux/clk.h>
16#include <linux/device.h>
17#include <linux/dma-mapping.h>
18#include <linux/io.h>
19#include <linux/module.h>
20#include <linux/of.h>
21#include <linux/of_platform.h>
22#include <linux/platform_device.h>
23#include <linux/sched/clock.h>
24#include <linux/reset.h>
25
26#include <drm/drm_drv.h>
27#include <drm/drm_managed.h>
28#include <drm/drm_print.h>
29#include <uapi/drm/v3d_drm.h>
30
31#include "v3d_drv.h"
32#include "v3d_regs.h"
33
34#define DRIVER_NAME "v3d"
35#define DRIVER_DESC "Broadcom V3D graphics"
36#define DRIVER_MAJOR 1
37#define DRIVER_MINOR 0
38#define DRIVER_PATCHLEVEL 0
39
40/* Only expose the `super_pages` modparam if THP is enabled. */
41#ifdef CONFIG_TRANSPARENT_HUGEPAGE
42bool super_pages = true;
43module_param_named(super_pages, super_pages, bool, 0400);
44MODULE_PARM_DESC(super_pages, "Enable/Disable Super Pages support.");
45#endif
46
47static int v3d_get_param_ioctl(struct drm_device *dev, void *data,
48 struct drm_file *file_priv)
49{
50 struct v3d_file_priv *v3d_priv = file_priv->driver_priv;
51 struct v3d_dev *v3d = to_v3d_dev(dev);
52 struct drm_v3d_get_param *args = data;
53 static const u32 reg_map[] = {
54 [DRM_V3D_PARAM_V3D_UIFCFG] = V3D_HUB_UIFCFG,
55 [DRM_V3D_PARAM_V3D_HUB_IDENT1] = V3D_HUB_IDENT1,
56 [DRM_V3D_PARAM_V3D_HUB_IDENT2] = V3D_HUB_IDENT2,
57 [DRM_V3D_PARAM_V3D_HUB_IDENT3] = V3D_HUB_IDENT3,
58 [DRM_V3D_PARAM_V3D_CORE0_IDENT0] = V3D_CTL_IDENT0,
59 [DRM_V3D_PARAM_V3D_CORE0_IDENT1] = V3D_CTL_IDENT1,
60 [DRM_V3D_PARAM_V3D_CORE0_IDENT2] = V3D_CTL_IDENT2,
61 };
62
63 if (args->pad != 0)
64 return -EINVAL;
65
66 /* Note that DRM_V3D_PARAM_V3D_CORE0_IDENT0 is 0, so we need
67 * to explicitly allow it in the "the register in our
68 * parameter map" check.
69 */
70 if (args->param < ARRAY_SIZE(reg_map) &&
71 (reg_map[args->param] ||
72 args->param == DRM_V3D_PARAM_V3D_CORE0_IDENT0)) {
73 u32 offset = reg_map[args->param];
74
75 if (args->value != 0)
76 return -EINVAL;
77
78 if (args->param >= DRM_V3D_PARAM_V3D_CORE0_IDENT0 &&
79 args->param <= DRM_V3D_PARAM_V3D_CORE0_IDENT2) {
80 args->value = V3D_CORE_READ(0, offset);
81 } else {
82 args->value = V3D_READ(offset);
83 }
84 return 0;
85 }
86
87 switch (args->param) {
88 case DRM_V3D_PARAM_SUPPORTS_TFU:
89 args->value = 1;
90 return 0;
91 case DRM_V3D_PARAM_SUPPORTS_CSD:
92 args->value = v3d_has_csd(v3d);
93 return 0;
94 case DRM_V3D_PARAM_SUPPORTS_CACHE_FLUSH:
95 args->value = 1;
96 return 0;
97 case DRM_V3D_PARAM_SUPPORTS_PERFMON:
98 args->value = (v3d->ver >= V3D_GEN_41);
99 return 0;
100 case DRM_V3D_PARAM_SUPPORTS_MULTISYNC_EXT:
101 args->value = 1;
102 return 0;
103 case DRM_V3D_PARAM_SUPPORTS_CPU_QUEUE:
104 args->value = 1;
105 return 0;
106 case DRM_V3D_PARAM_MAX_PERF_COUNTERS:
107 args->value = v3d->perfmon_info.max_counters;
108 return 0;
109 case DRM_V3D_PARAM_SUPPORTS_SUPER_PAGES:
110 args->value = !!drm_gem_get_huge_mnt(dev);
111 return 0;
112 case DRM_V3D_PARAM_GLOBAL_RESET_COUNTER:
113 args->value = atomic_read(&v3d->reset_counter);
114 return 0;
115 case DRM_V3D_PARAM_CONTEXT_RESET_COUNTER:
116 args->value = 0;
117 for (enum v3d_queue q = 0; q < V3D_MAX_QUEUES; q++)
118 args->value += atomic_read(&v3d_priv->stats[q]->reset_counter);
119 return 0;
120 default:
121 drm_dbg(dev, "Unknown parameter %d\n", args->param);
122 return -EINVAL;
123 }
124}
125
126static int
127v3d_open(struct drm_device *dev, struct drm_file *file)
128{
129 struct v3d_dev *v3d = to_v3d_dev(dev);
130 struct v3d_file_priv *v3d_priv;
131 struct drm_gpu_scheduler *sched;
132 int i, ret;
133
134 v3d_priv = kzalloc_obj(*v3d_priv);
135 if (!v3d_priv)
136 return -ENOMEM;
137
138 v3d_priv->v3d = v3d;
139
140 for (i = 0; i < V3D_MAX_QUEUES; i++) {
141 v3d_priv->stats[i] = v3d_stats_alloc();
142 if (!v3d_priv->stats[i]) {
143 ret = -ENOMEM;
144 goto err_stats;
145 }
146
147 sched = &v3d->queue[i].sched;
148 ret = drm_sched_entity_init(&v3d_priv->sched_entity[i],
149 DRM_SCHED_PRIORITY_NORMAL, &sched,
150 1, NULL);
151 if (ret)
152 goto err_sched;
153 }
154
155 v3d_perfmon_open_file(v3d_priv);
156 file->driver_priv = v3d_priv;
157
158 return 0;
159
160err_sched:
161 v3d_stats_put(v3d_priv->stats[i]);
162err_stats:
163 for (i--; i >= 0; i--) {
164 drm_sched_entity_destroy(&v3d_priv->sched_entity[i]);
165 v3d_stats_put(v3d_priv->stats[i]);
166 }
167 kfree(v3d_priv);
168 return ret;
169}
170
171static void
172v3d_postclose(struct drm_device *dev, struct drm_file *file)
173{
174 struct v3d_file_priv *v3d_priv = file->driver_priv;
175 enum v3d_queue q;
176
177 for (q = 0; q < V3D_MAX_QUEUES; q++) {
178 drm_sched_entity_destroy(&v3d_priv->sched_entity[q]);
179 v3d_stats_put(v3d_priv->stats[q]);
180 }
181
182 v3d_perfmon_close_file(v3d_priv);
183 kfree(v3d_priv);
184}
185
186void v3d_get_stats(const struct v3d_stats *stats, u64 timestamp,
187 u64 *active_runtime, u64 *jobs_completed)
188{
189 unsigned int seq;
190
191 do {
192 seq = raw_read_seqcount_begin(&stats->lock);
193 *active_runtime = stats->enabled_ns;
194 if (stats->start_ns)
195 *active_runtime += timestamp - stats->start_ns;
196 *jobs_completed = stats->jobs_completed;
197 } while (read_seqcount_retry(&stats->lock, seq));
198}
199
200static void v3d_show_fdinfo(struct drm_printer *p, struct drm_file *file)
201{
202 struct v3d_file_priv *file_priv = file->driver_priv;
203 u64 timestamp = local_clock();
204 enum v3d_queue queue;
205
206 for (queue = 0; queue < V3D_MAX_QUEUES; queue++) {
207 struct v3d_stats *stats = file_priv->stats[queue];
208 u64 active_runtime, jobs_completed;
209
210 v3d_get_stats(stats, timestamp, &active_runtime, &jobs_completed);
211
212 /* Note that, in case of a GPU reset, the time spent during an
213 * attempt of executing the job is not computed in the runtime.
214 */
215 drm_printf(p, "drm-engine-%s: \t%llu ns\n",
216 v3d_queue_to_string(queue), active_runtime);
217
218 /* Note that we only count jobs that completed. Therefore, jobs
219 * that were resubmitted due to a GPU reset are not computed.
220 */
221 drm_printf(p, "v3d-jobs-%s: \t%llu jobs\n",
222 v3d_queue_to_string(queue), jobs_completed);
223 }
224
225 drm_show_memory_stats(p, file);
226}
227
228static const struct file_operations v3d_drm_fops = {
229 .owner = THIS_MODULE,
230 DRM_GEM_FOPS,
231 .show_fdinfo = drm_show_fdinfo,
232};
233
234/* DRM_AUTH is required on SUBMIT_CL for now, while we don't have GMP
235 * protection between clients. Note that render nodes would be
236 * able to submit CLs that could access BOs from clients authenticated
237 * with the master node. The TFU doesn't use the GMP, so it would
238 * need to stay DRM_AUTH until we do buffer size/offset validation.
239 */
240static const struct drm_ioctl_desc v3d_drm_ioctls[] = {
241 DRM_IOCTL_DEF_DRV(V3D_SUBMIT_CL, v3d_submit_cl_ioctl, DRM_RENDER_ALLOW | DRM_AUTH),
242 DRM_IOCTL_DEF_DRV(V3D_WAIT_BO, v3d_wait_bo_ioctl, DRM_RENDER_ALLOW),
243 DRM_IOCTL_DEF_DRV(V3D_CREATE_BO, v3d_create_bo_ioctl, DRM_RENDER_ALLOW),
244 DRM_IOCTL_DEF_DRV(V3D_MMAP_BO, v3d_mmap_bo_ioctl, DRM_RENDER_ALLOW),
245 DRM_IOCTL_DEF_DRV(V3D_GET_PARAM, v3d_get_param_ioctl, DRM_RENDER_ALLOW),
246 DRM_IOCTL_DEF_DRV(V3D_GET_BO_OFFSET, v3d_get_bo_offset_ioctl, DRM_RENDER_ALLOW),
247 DRM_IOCTL_DEF_DRV(V3D_SUBMIT_TFU, v3d_submit_tfu_ioctl, DRM_RENDER_ALLOW | DRM_AUTH),
248 DRM_IOCTL_DEF_DRV(V3D_SUBMIT_CSD, v3d_submit_csd_ioctl, DRM_RENDER_ALLOW | DRM_AUTH),
249 DRM_IOCTL_DEF_DRV(V3D_PERFMON_CREATE, v3d_perfmon_create_ioctl, DRM_RENDER_ALLOW),
250 DRM_IOCTL_DEF_DRV(V3D_PERFMON_DESTROY, v3d_perfmon_destroy_ioctl, DRM_RENDER_ALLOW),
251 DRM_IOCTL_DEF_DRV(V3D_PERFMON_GET_VALUES, v3d_perfmon_get_values_ioctl, DRM_RENDER_ALLOW),
252 DRM_IOCTL_DEF_DRV(V3D_SUBMIT_CPU, v3d_submit_cpu_ioctl, DRM_RENDER_ALLOW | DRM_AUTH),
253 DRM_IOCTL_DEF_DRV(V3D_PERFMON_GET_COUNTER, v3d_perfmon_get_counter_ioctl, DRM_RENDER_ALLOW),
254 DRM_IOCTL_DEF_DRV(V3D_PERFMON_SET_GLOBAL, v3d_perfmon_set_global_ioctl, DRM_RENDER_ALLOW),
255};
256
257static const struct drm_driver v3d_drm_driver = {
258 .driver_features = (DRIVER_GEM |
259 DRIVER_RENDER |
260 DRIVER_SYNCOBJ),
261
262 .open = v3d_open,
263 .postclose = v3d_postclose,
264
265#if defined(CONFIG_DEBUG_FS)
266 .debugfs_init = v3d_debugfs_init,
267#endif
268
269 .gem_create_object = v3d_create_object,
270 .gem_prime_import_sg_table = v3d_prime_import_sg_table,
271
272 .ioctls = v3d_drm_ioctls,
273 .num_ioctls = ARRAY_SIZE(v3d_drm_ioctls),
274 .fops = &v3d_drm_fops,
275 .show_fdinfo = v3d_show_fdinfo,
276
277 .name = DRIVER_NAME,
278 .desc = DRIVER_DESC,
279 .major = DRIVER_MAJOR,
280 .minor = DRIVER_MINOR,
281 .patchlevel = DRIVER_PATCHLEVEL,
282};
283
284static const struct of_device_id v3d_of_match[] = {
285 { .compatible = "brcm,2711-v3d", .data = (void *)V3D_GEN_42 },
286 { .compatible = "brcm,2712-v3d", .data = (void *)V3D_GEN_71 },
287 { .compatible = "brcm,7268-v3d", .data = (void *)V3D_GEN_33 },
288 { .compatible = "brcm,7278-v3d", .data = (void *)V3D_GEN_41 },
289 {},
290};
291MODULE_DEVICE_TABLE(of, v3d_of_match);
292
293static void
294v3d_idle_sms(struct v3d_dev *v3d)
295{
296 if (v3d->ver < V3D_GEN_71)
297 return;
298
299 V3D_SMS_WRITE(V3D_SMS_TEE_CS, V3D_SMS_CLEAR_POWER_OFF);
300
301 if (wait_for((V3D_GET_FIELD(V3D_SMS_READ(V3D_SMS_TEE_CS),
302 V3D_SMS_STATE) == V3D_SMS_IDLE), 100)) {
303 drm_err(&v3d->drm, "Failed to power up SMS\n");
304 }
305
306 v3d_reset_sms(v3d);
307}
308
309static void
310v3d_power_off_sms(struct v3d_dev *v3d)
311{
312 if (v3d->ver < V3D_GEN_71)
313 return;
314
315 V3D_SMS_WRITE(V3D_SMS_TEE_CS, V3D_SMS_POWER_OFF);
316
317 if (wait_for((V3D_GET_FIELD(V3D_SMS_READ(V3D_SMS_TEE_CS),
318 V3D_SMS_STATE) == V3D_SMS_POWER_OFF_STATE), 100)) {
319 drm_err(&v3d->drm, "Failed to power off SMS\n");
320 }
321}
322
323static int
324map_regs(struct v3d_dev *v3d, void __iomem **regs, const char *name)
325{
326 *regs = devm_platform_ioremap_resource_byname(v3d_to_pdev(v3d), name);
327 return PTR_ERR_OR_ZERO(*regs);
328}
329
330static int v3d_platform_drm_probe(struct platform_device *pdev)
331{
332 struct device *dev = &pdev->dev;
333 struct drm_device *drm;
334 struct v3d_dev *v3d;
335 enum v3d_gen gen;
336 int ret;
337 u32 mmu_debug;
338 u32 ident1, ident3;
339 u64 mask;
340
341 v3d = devm_drm_dev_alloc(dev, &v3d_drm_driver, struct v3d_dev, drm);
342 if (IS_ERR(v3d))
343 return PTR_ERR(v3d);
344
345 drm = &v3d->drm;
346
347 platform_set_drvdata(pdev, drm);
348
349 gen = (uintptr_t)of_device_get_match_data(dev);
350 v3d->ver = gen;
351
352 ret = map_regs(v3d, &v3d->hub_regs, "hub");
353 if (ret)
354 return ret;
355
356 ret = map_regs(v3d, &v3d->core_regs[0], "core0");
357 if (ret)
358 return ret;
359
360 if (v3d->ver >= V3D_GEN_71) {
361 ret = map_regs(v3d, &v3d->sms_regs, "sms");
362 if (ret)
363 return ret;
364 }
365
366 v3d->clk = devm_clk_get_optional(dev, NULL);
367 if (IS_ERR(v3d->clk))
368 return dev_err_probe(dev, PTR_ERR(v3d->clk), "Failed to get V3D clock\n");
369
370 ret = clk_prepare_enable(v3d->clk);
371 if (ret) {
372 dev_err(&pdev->dev, "Couldn't enable the V3D clock\n");
373 return ret;
374 }
375
376 v3d_idle_sms(v3d);
377
378 mmu_debug = V3D_READ(V3D_MMU_DEBUG_INFO);
379 mask = DMA_BIT_MASK(30 + V3D_GET_FIELD(mmu_debug, V3D_MMU_PA_WIDTH));
380 ret = dma_set_mask_and_coherent(dev, mask);
381 if (ret)
382 goto clk_disable;
383
384 dma_set_max_seg_size(&pdev->dev, UINT_MAX);
385
386 v3d->va_width = 30 + V3D_GET_FIELD(mmu_debug, V3D_MMU_VA_WIDTH);
387
388 ident1 = V3D_READ(V3D_HUB_IDENT1);
389 v3d->ver = (V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_TVER) * 10 +
390 V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_REV));
391 /* Make sure that the V3D tech version retrieved from the HW is equal
392 * to the one advertised by the device tree.
393 */
394 WARN_ON(v3d->ver != gen);
395
396 v3d->cores = V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_NCORES);
397 WARN_ON(v3d->cores > 1); /* multicore not yet implemented */
398
399 ident3 = V3D_READ(V3D_HUB_IDENT3);
400 v3d->rev = V3D_GET_FIELD(ident3, V3D_HUB_IDENT3_IPREV);
401
402 v3d_perfmon_init(v3d);
403
404 v3d->reset = devm_reset_control_get_exclusive(dev, NULL);
405 if (IS_ERR(v3d->reset)) {
406 ret = PTR_ERR(v3d->reset);
407
408 if (ret == -EPROBE_DEFER)
409 goto clk_disable;
410
411 v3d->reset = NULL;
412 ret = map_regs(v3d, &v3d->bridge_regs, "bridge");
413 if (ret) {
414 dev_err(dev,
415 "Failed to get reset control or bridge regs\n");
416 goto clk_disable;
417 }
418 }
419
420 if (v3d->ver < V3D_GEN_41) {
421 ret = map_regs(v3d, &v3d->gca_regs, "gca");
422 if (ret)
423 goto clk_disable;
424 }
425
426 v3d->mmu_scratch = dma_alloc_wc(dev, 4096, &v3d->mmu_scratch_paddr,
427 GFP_KERNEL | __GFP_NOWARN | __GFP_ZERO);
428 if (!v3d->mmu_scratch) {
429 dev_err(dev, "Failed to allocate MMU scratch page\n");
430 ret = -ENOMEM;
431 goto clk_disable;
432 }
433
434 ret = v3d_gem_init(drm);
435 if (ret)
436 goto dma_free;
437
438 ret = v3d_irq_init(v3d);
439 if (ret)
440 goto gem_destroy;
441
442 ret = drm_dev_register(drm, 0);
443 if (ret)
444 goto irq_disable;
445
446 ret = v3d_sysfs_init(dev);
447 if (ret)
448 goto drm_unregister;
449
450 return 0;
451
452drm_unregister:
453 drm_dev_unregister(drm);
454irq_disable:
455 v3d_irq_disable(v3d);
456gem_destroy:
457 v3d_gem_destroy(drm);
458dma_free:
459 dma_free_wc(dev, 4096, v3d->mmu_scratch, v3d->mmu_scratch_paddr);
460clk_disable:
461 clk_disable_unprepare(v3d->clk);
462 return ret;
463}
464
465static void v3d_platform_drm_remove(struct platform_device *pdev)
466{
467 struct drm_device *drm = platform_get_drvdata(pdev);
468 struct v3d_dev *v3d = to_v3d_dev(drm);
469 struct device *dev = &pdev->dev;
470
471 v3d_sysfs_destroy(dev);
472
473 drm_dev_unregister(drm);
474
475 v3d_gem_destroy(drm);
476
477 dma_free_wc(v3d->drm.dev, 4096, v3d->mmu_scratch,
478 v3d->mmu_scratch_paddr);
479
480 v3d_power_off_sms(v3d);
481
482 clk_disable_unprepare(v3d->clk);
483}
484
485static struct platform_driver v3d_platform_driver = {
486 .probe = v3d_platform_drm_probe,
487 .remove = v3d_platform_drm_remove,
488 .driver = {
489 .name = "v3d",
490 .of_match_table = v3d_of_match,
491 },
492};
493
494module_platform_driver(v3d_platform_driver);
495
496MODULE_ALIAS("platform:v3d-drm");
497MODULE_DESCRIPTION("Broadcom V3D DRM Driver");
498MODULE_AUTHOR("Eric Anholt <eric@anholt.net>");
499MODULE_LICENSE("GPL v2");