Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Register constants and other forward declarations needed by the bma400
4 * sources.
5 *
6 * Copyright 2019 Dan Robertson <dan@dlrobertson.com>
7 */
8
9#ifndef _BMA400_H_
10#define _BMA400_H_
11
12#include <linux/bits.h>
13#include <linux/regmap.h>
14
15/*
16 * Read-Only Registers
17 */
18
19/* Chip ID of BMA 400 devices found in the chip ID register. */
20#define BMA400_ID_REG_VAL 0x90
21
22/* Status and ID registers */
23#define BMA400_CHIP_ID_REG 0x00
24#define BMA400_ERR_REG 0x02
25#define BMA400_STATUS_REG 0x03
26
27/* Acceleration registers */
28#define BMA400_ACC_X_LSB_REG 0x04
29#define BMA400_ACC_X_MSB_REG 0x05
30#define BMA400_ACC_Y_LSB_REG 0x06
31#define BMA400_ACC_Y_MSB_REG 0x07
32#define BMA400_ACC_Z_LSB_REG 0x08
33#define BMA400_ACC_Z_MSB_REG 0x09
34
35/* Sensor time registers */
36#define BMA400_SENSOR_TIME0_REG 0x0a
37#define BMA400_SENSOR_TIME1_REG 0x0b
38#define BMA400_SENSOR_TIME2_REG 0x0c
39
40/* Event and interrupt registers */
41#define BMA400_EVENT_REG 0x0d
42
43#define BMA400_INT_STAT0_REG 0x0e
44#define BMA400_INT_STAT0_GEN1_MASK BIT(2)
45#define BMA400_INT_STAT0_GEN2_MASK BIT(3)
46#define BMA400_INT_STAT0_DRDY_MASK BIT(7)
47
48#define BMA400_INT_STAT1_REG 0x0f
49#define BMA400_INT_STAT1_STEP_INT_MASK GENMASK(9, 8)
50#define BMA400_INT_STAT1_S_TAP_MASK BIT(10)
51#define BMA400_INT_STAT1_D_TAP_MASK BIT(11)
52
53#define BMA400_INT_STAT2_REG 0x10
54
55/* Bit present in all INT_STAT registers */
56#define BMA400_INT_STAT_ENG_OVRRUN_MASK BIT(4)
57
58/* Temperature register */
59#define BMA400_TEMP_DATA_REG 0x11
60
61/* FIFO length and data registers */
62#define BMA400_FIFO_LENGTH0_REG 0x12
63#define BMA400_FIFO_LENGTH1_REG 0x13
64#define BMA400_FIFO_DATA_REG 0x14
65
66/* Step count registers */
67#define BMA400_STEP_CNT0_REG 0x15
68#define BMA400_STEP_CNT1_REG 0x16
69#define BMA400_STEP_CNT3_REG 0x17
70#define BMA400_STEP_STAT_REG 0x18
71#define BMA400_STEP_RAW_LEN 0x03
72
73/*
74 * Read-write configuration registers
75 */
76#define BMA400_ACC_CONFIG0_REG 0x19
77#define BMA400_ACC_CONFIG0_LP_OSR_MASK GENMASK(6, 5)
78
79#define BMA400_ACC_CONFIG1_REG 0x1a
80#define BMA400_ACC_CONFIG1_ODR_MASK GENMASK(3, 0)
81#define BMA400_ACC_CONFIG1_ODR_MIN_RAW 0x05
82#define BMA400_ACC_CONFIG1_ODR_LP_RAW 0x06
83#define BMA400_ACC_CONFIG1_ODR_MAX_RAW 0x0b
84#define BMA400_ACC_CONFIG1_ODR_MAX_HZ 800
85#define BMA400_ACC_CONFIG1_ODR_MIN_WHOLE_HZ 25
86#define BMA400_ACC_CONFIG1_ODR_MIN_HZ 12
87#define BMA400_ACC_CONFIG1_NP_OSR_MASK GENMASK(5, 4)
88#define BMA400_ACC_CONFIG1_ACC_RANGE_MASK GENMASK(7, 6)
89
90#define BMA400_ACC_CONFIG2_REG 0x1b
91
92/* Interrupt registers */
93#define BMA400_INT_CONFIG0_REG 0x1f
94#define BMA400_INT_CONFIG0_GEN1_MASK BIT(2)
95#define BMA400_INT_CONFIG0_GEN2_MASK BIT(3)
96#define BMA400_INT_CONFIG0_DRDY_MASK BIT(7)
97
98enum bma400_generic_intr {
99 BMA400_GEN1_INTR = 0x1,
100 BMA400_GEN2_INTR = 0x2,
101};
102
103#define BMA400_INT_CONFIG1_REG 0x20
104#define BMA400_INT_CONFIG1_STEP_INT_MASK BIT(0)
105#define BMA400_INT_CONFIG1_S_TAP_MASK BIT(2)
106#define BMA400_INT_CONFIG1_D_TAP_MASK BIT(3)
107
108#define BMA400_INT1_MAP_REG 0x21
109#define BMA400_INT12_MAP_REG 0x23
110#define BMA400_INT_IO_CTRL_REG 0x24
111
112#define BMA400_TWO_BITS_MASK GENMASK(1, 0)
113
114/* Generic interrupts register */
115#define BMA400_GENINT_CONFIG_REG_BASE 0x3f
116#define BMA400_NUM_GENINT_CONFIG_REGS 11
117#define BMA400_GENINT_CONFIG_REG(gen_intr, config_idx) \
118 (BMA400_GENINT_CONFIG_REG_BASE + \
119 (gen_intr - 1) * BMA400_NUM_GENINT_CONFIG_REGS + \
120 (config_idx))
121#define BMA400_GENINT_CONFIG0_HYST_MASK GENMASK(1, 0)
122#define BMA400_GENINT_CONFIG0_REF_UPD_MODE_MASK GENMASK(3, 2)
123#define BMA400_GENINT_CONFIG0_DATA_SRC_MASK BIT(4)
124#define BMA400_GENINT_CONFIG0_X_EN_MASK BIT(5)
125#define BMA400_GENINT_CONFIG0_Y_EN_MASK BIT(6)
126#define BMA400_GENINT_CONFIG0_Z_EN_MASK BIT(7)
127
128enum bma400_accel_data_src {
129 ACCEL_FILT1 = 0x0,
130 ACCEL_FILT2 = 0x1,
131};
132
133enum bma400_ref_updt_mode {
134 BMA400_REF_MANUAL_UPDT_MODE = 0x0,
135 BMA400_REF_ONETIME_UPDT_MODE = 0x1,
136 BMA400_REF_EVERYTIME_UPDT_MODE = 0x2,
137 BMA400_REF_EVERYTIME_LP_UPDT_MODE = 0x3,
138};
139
140#define BMA400_GEN_CONFIG1_OFF 0x01
141#define BMA400_GENINT_CONFIG1_AXES_COMB_MASK BIT(0)
142#define BMA400_GENINT_CONFIG1_DETCT_CRIT_MASK BIT(1)
143
144enum bma400_genintr_acceleval_axescomb {
145 BMA400_EVAL_X_OR_Y_OR_Z = 0x0,
146 BMA400_EVAL_X_AND_Y_AND_Z = 0x1,
147};
148
149enum bma400_detect_criterion {
150 BMA400_DETECT_INACTIVITY = 0x0,
151 BMA400_DETECT_ACTIVITY = 0x1,
152};
153
154/* TAP config registers */
155#define BMA400_TAP_CONFIG_REG 0x57
156#define BMA400_TAP_CONFIG_SEN_MASK GENMASK(2, 0)
157
158#define BMA400_TAP_CONFIG1_REG 0x58
159#define BMA400_TAP_CONFIG1_TICSTH_MASK GENMASK(1, 0)
160#define BMA400_TAP_CONFIG1_QUIET_MASK GENMASK(3, 2)
161#define BMA400_TAP_CONFIG1_QUIETDT_MASK GENMASK(5, 4)
162#define BMA400_TAP_TIM_LIST_LEN 4
163
164#define BMA400_CMD_REG 0x7e
165/*
166 * BMA400_SCALE_MIN macro value represents m/s^2 for 1 LSB before
167 * converting to micro values for +-2g range.
168 *
169 * For +-2g - 1 LSB = 0.976562 milli g = 0.009576 m/s^2
170 * For +-4g - 1 LSB = 1.953125 milli g = 0.019153 m/s^2
171 * For +-16g - 1 LSB = 7.8125 milli g = 0.076614 m/s^2
172 *
173 * The raw value which is used to select the different ranges is determined
174 * by the first bit set position from the scale value, so BMA400_SCALE_MIN
175 * should be odd.
176 *
177 * Scale values for +-2g, +-4g, +-8g and +-16g are populated into bma400_scales
178 * array by left shifting BMA400_SCALE_MIN.
179 * e.g.:
180 * To select +-2g = 9577 << 0 = raw value to write is 0.
181 * To select +-8g = 9577 << 2 = raw value to write is 2.
182 * To select +-16g = 9577 << 3 = raw value to write is 3.
183 */
184#define BMA400_ACC_SCALE_MIN 9577
185#define BMA400_ACC_SCALE_MAX 76617
186
187extern const struct regmap_config bma400_regmap_config;
188
189int bma400_probe(struct device *dev, struct regmap *regmap, int irq,
190 const char *name);
191
192#endif