Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Analog devices AD5360, AD5361, AD5362, AD5363, AD5370, AD5371, AD5373
4 * multi-channel Digital to Analog Converters driver
5 *
6 * Copyright 2011 Analog Devices Inc.
7 */
8
9#include <linux/device.h>
10#include <linux/err.h>
11#include <linux/module.h>
12#include <linux/kernel.h>
13#include <linux/spi/spi.h>
14#include <linux/slab.h>
15#include <linux/sysfs.h>
16#include <linux/regulator/consumer.h>
17
18#include <linux/iio/iio.h>
19#include <linux/iio/sysfs.h>
20
21#define AD5360_CMD(x) ((x) << 22)
22#define AD5360_ADDR(x) ((x) << 16)
23
24#define AD5360_READBACK_TYPE(x) ((x) << 13)
25#define AD5360_READBACK_ADDR(x) ((x) << 7)
26
27#define AD5360_CHAN_ADDR(chan) ((chan) + 0x8)
28
29#define AD5360_CMD_WRITE_DATA 0x3
30#define AD5360_CMD_WRITE_OFFSET 0x2
31#define AD5360_CMD_WRITE_GAIN 0x1
32#define AD5360_CMD_SPECIAL_FUNCTION 0x0
33
34/* Special function register addresses */
35#define AD5360_REG_SF_NOP 0x0
36#define AD5360_REG_SF_CTRL 0x1
37#define AD5360_REG_SF_OFS(x) (0x2 + (x))
38#define AD5360_REG_SF_READBACK 0x5
39
40#define AD5360_SF_CTRL_PWR_DOWN BIT(0)
41
42#define AD5360_READBACK_X1A 0x0
43#define AD5360_READBACK_X1B 0x1
44#define AD5360_READBACK_OFFSET 0x2
45#define AD5360_READBACK_GAIN 0x3
46#define AD5360_READBACK_SF 0x4
47
48
49/**
50 * struct ad5360_chip_info - chip specific information
51 * @channel_template: channel specification template
52 * @num_channels: number of channels
53 * @channels_per_group: number of channels per group
54 * @num_vrefs: number of vref supplies for the chip
55*/
56
57struct ad5360_chip_info {
58 struct iio_chan_spec channel_template;
59 unsigned int num_channels;
60 unsigned int channels_per_group;
61 unsigned int num_vrefs;
62};
63
64/**
65 * struct ad5360_state - driver instance specific data
66 * @spi: spi_device
67 * @chip_info: chip model specific constants, available modes etc
68 * @vref_reg: vref supply regulators
69 * @ctrl: control register cache
70 * @lock: lock to protect the data buffer during SPI ops
71 * @data: spi transfer buffers
72 */
73
74struct ad5360_state {
75 struct spi_device *spi;
76 const struct ad5360_chip_info *chip_info;
77 struct regulator_bulk_data vref_reg[3];
78 unsigned int ctrl;
79 struct mutex lock;
80
81 /*
82 * DMA (thus cache coherency maintenance) may require the
83 * transfer buffers to live in their own cache lines.
84 */
85 union {
86 __be32 d32;
87 u8 d8[4];
88 } data[2] __aligned(IIO_DMA_MINALIGN);
89};
90
91enum ad5360_type {
92 ID_AD5360,
93 ID_AD5361,
94 ID_AD5362,
95 ID_AD5363,
96 ID_AD5370,
97 ID_AD5371,
98 ID_AD5372,
99 ID_AD5373,
100};
101
102#define AD5360_CHANNEL(bits) { \
103 .type = IIO_VOLTAGE, \
104 .indexed = 1, \
105 .output = 1, \
106 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
107 BIT(IIO_CHAN_INFO_SCALE) | \
108 BIT(IIO_CHAN_INFO_OFFSET) | \
109 BIT(IIO_CHAN_INFO_CALIBSCALE) | \
110 BIT(IIO_CHAN_INFO_CALIBBIAS), \
111 .scan_type = { \
112 .sign = 'u', \
113 .realbits = (bits), \
114 .storagebits = 16, \
115 .shift = 16 - (bits), \
116 }, \
117}
118
119static const struct ad5360_chip_info ad5360_chip_info_tbl[] = {
120 [ID_AD5360] = {
121 .channel_template = AD5360_CHANNEL(16),
122 .num_channels = 16,
123 .channels_per_group = 8,
124 .num_vrefs = 2,
125 },
126 [ID_AD5361] = {
127 .channel_template = AD5360_CHANNEL(14),
128 .num_channels = 16,
129 .channels_per_group = 8,
130 .num_vrefs = 2,
131 },
132 [ID_AD5362] = {
133 .channel_template = AD5360_CHANNEL(16),
134 .num_channels = 8,
135 .channels_per_group = 4,
136 .num_vrefs = 2,
137 },
138 [ID_AD5363] = {
139 .channel_template = AD5360_CHANNEL(14),
140 .num_channels = 8,
141 .channels_per_group = 4,
142 .num_vrefs = 2,
143 },
144 [ID_AD5370] = {
145 .channel_template = AD5360_CHANNEL(16),
146 .num_channels = 40,
147 .channels_per_group = 8,
148 .num_vrefs = 2,
149 },
150 [ID_AD5371] = {
151 .channel_template = AD5360_CHANNEL(14),
152 .num_channels = 40,
153 .channels_per_group = 8,
154 .num_vrefs = 3,
155 },
156 [ID_AD5372] = {
157 .channel_template = AD5360_CHANNEL(16),
158 .num_channels = 32,
159 .channels_per_group = 8,
160 .num_vrefs = 2,
161 },
162 [ID_AD5373] = {
163 .channel_template = AD5360_CHANNEL(14),
164 .num_channels = 32,
165 .channels_per_group = 8,
166 .num_vrefs = 2,
167 },
168};
169
170static unsigned int ad5360_get_channel_vref_index(struct ad5360_state *st,
171 unsigned int channel)
172{
173 unsigned int i;
174
175 /* The first groups have their own vref, while the remaining groups
176 * share the last vref */
177 i = channel / st->chip_info->channels_per_group;
178 if (i >= st->chip_info->num_vrefs)
179 i = st->chip_info->num_vrefs - 1;
180
181 return i;
182}
183
184static int ad5360_get_channel_vref(struct ad5360_state *st,
185 unsigned int channel)
186{
187 unsigned int i = ad5360_get_channel_vref_index(st, channel);
188
189 return regulator_get_voltage(st->vref_reg[i].consumer);
190}
191
192
193static int ad5360_write_unlocked(struct iio_dev *indio_dev,
194 unsigned int cmd, unsigned int addr, unsigned int val,
195 unsigned int shift)
196{
197 struct ad5360_state *st = iio_priv(indio_dev);
198
199 val <<= shift;
200 val |= AD5360_CMD(cmd) | AD5360_ADDR(addr);
201 st->data[0].d32 = cpu_to_be32(val);
202
203 return spi_write(st->spi, &st->data[0].d8[1], 3);
204}
205
206static int ad5360_write(struct iio_dev *indio_dev, unsigned int cmd,
207 unsigned int addr, unsigned int val, unsigned int shift)
208{
209 struct ad5360_state *st = iio_priv(indio_dev);
210
211 guard(mutex)(&st->lock);
212 return ad5360_write_unlocked(indio_dev, cmd, addr, val, shift);
213}
214
215static int ad5360_read(struct iio_dev *indio_dev, unsigned int type,
216 unsigned int addr)
217{
218 struct ad5360_state *st = iio_priv(indio_dev);
219 int ret;
220 struct spi_transfer t[] = {
221 {
222 .tx_buf = &st->data[0].d8[1],
223 .len = 3,
224 .cs_change = 1,
225 }, {
226 .rx_buf = &st->data[1].d8[1],
227 .len = 3,
228 },
229 };
230
231 guard(mutex)(&st->lock);
232
233 st->data[0].d32 = cpu_to_be32(AD5360_CMD(AD5360_CMD_SPECIAL_FUNCTION) |
234 AD5360_ADDR(AD5360_REG_SF_READBACK) |
235 AD5360_READBACK_TYPE(type) |
236 AD5360_READBACK_ADDR(addr));
237
238 ret = spi_sync_transfer(st->spi, t, ARRAY_SIZE(t));
239 if (ret < 0)
240 return ret;
241
242 return be32_to_cpu(st->data[1].d32) & 0xffff;
243}
244
245static ssize_t ad5360_read_dac_powerdown(struct device *dev,
246 struct device_attribute *attr,
247 char *buf)
248{
249 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
250 struct ad5360_state *st = iio_priv(indio_dev);
251
252 return sysfs_emit(buf, "%d\n", (bool)(st->ctrl & AD5360_SF_CTRL_PWR_DOWN));
253}
254
255static int ad5360_update_ctrl(struct iio_dev *indio_dev, unsigned int set,
256 unsigned int clr)
257{
258 struct ad5360_state *st = iio_priv(indio_dev);
259
260 guard(mutex)(&st->lock);
261
262 st->ctrl |= set;
263 st->ctrl &= ~clr;
264
265 return ad5360_write_unlocked(indio_dev, AD5360_CMD_SPECIAL_FUNCTION,
266 AD5360_REG_SF_CTRL, st->ctrl, 0);
267}
268
269static ssize_t ad5360_write_dac_powerdown(struct device *dev,
270 struct device_attribute *attr, const char *buf, size_t len)
271{
272 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
273 bool pwr_down;
274 int ret;
275
276 ret = kstrtobool(buf, &pwr_down);
277 if (ret)
278 return ret;
279
280 if (pwr_down)
281 ret = ad5360_update_ctrl(indio_dev, AD5360_SF_CTRL_PWR_DOWN, 0);
282 else
283 ret = ad5360_update_ctrl(indio_dev, 0, AD5360_SF_CTRL_PWR_DOWN);
284
285 return ret ? ret : len;
286}
287
288static IIO_DEVICE_ATTR(out_voltage_powerdown,
289 S_IRUGO | S_IWUSR,
290 ad5360_read_dac_powerdown,
291 ad5360_write_dac_powerdown, 0);
292
293static struct attribute *ad5360_attributes[] = {
294 &iio_dev_attr_out_voltage_powerdown.dev_attr.attr,
295 NULL,
296};
297
298static const struct attribute_group ad5360_attribute_group = {
299 .attrs = ad5360_attributes,
300};
301
302static int ad5360_write_raw(struct iio_dev *indio_dev,
303 struct iio_chan_spec const *chan,
304 int val,
305 int val2,
306 long mask)
307{
308 struct ad5360_state *st = iio_priv(indio_dev);
309 int max_val = (1 << chan->scan_type.realbits);
310 unsigned int ofs_index;
311
312 switch (mask) {
313 case IIO_CHAN_INFO_RAW:
314 if (val >= max_val || val < 0)
315 return -EINVAL;
316
317 return ad5360_write(indio_dev, AD5360_CMD_WRITE_DATA,
318 chan->address, val, chan->scan_type.shift);
319
320 case IIO_CHAN_INFO_CALIBBIAS:
321 if (val >= max_val || val < 0)
322 return -EINVAL;
323
324 return ad5360_write(indio_dev, AD5360_CMD_WRITE_OFFSET,
325 chan->address, val, chan->scan_type.shift);
326
327 case IIO_CHAN_INFO_CALIBSCALE:
328 if (val >= max_val || val < 0)
329 return -EINVAL;
330
331 return ad5360_write(indio_dev, AD5360_CMD_WRITE_GAIN,
332 chan->address, val, chan->scan_type.shift);
333
334 case IIO_CHAN_INFO_OFFSET:
335 if (val <= -max_val || val > 0)
336 return -EINVAL;
337
338 val = -val;
339
340 /* offset is supposed to have the same scale as raw, but it
341 * is always 14bits wide, so on a chip where the raw value has
342 * more bits, we need to shift offset. */
343 val >>= (chan->scan_type.realbits - 14);
344
345 /* There is one DAC offset register per vref. Changing one
346 * channels offset will also change the offset for all other
347 * channels which share the same vref supply. */
348 ofs_index = ad5360_get_channel_vref_index(st, chan->channel);
349 return ad5360_write(indio_dev, AD5360_CMD_SPECIAL_FUNCTION,
350 AD5360_REG_SF_OFS(ofs_index), val, 0);
351 default:
352 break;
353 }
354
355 return -EINVAL;
356}
357
358static int ad5360_read_raw(struct iio_dev *indio_dev,
359 struct iio_chan_spec const *chan,
360 int *val,
361 int *val2,
362 long m)
363{
364 struct ad5360_state *st = iio_priv(indio_dev);
365 unsigned int ofs_index;
366 int scale_uv;
367 int ret;
368
369 switch (m) {
370 case IIO_CHAN_INFO_RAW:
371 ret = ad5360_read(indio_dev, AD5360_READBACK_X1A,
372 chan->address);
373 if (ret < 0)
374 return ret;
375 *val = ret >> chan->scan_type.shift;
376 return IIO_VAL_INT;
377 case IIO_CHAN_INFO_SCALE:
378 scale_uv = ad5360_get_channel_vref(st, chan->channel);
379 if (scale_uv < 0)
380 return scale_uv;
381
382 /* vout = 4 * vref * dac_code */
383 *val = scale_uv * 4 / 1000;
384 *val2 = chan->scan_type.realbits;
385 return IIO_VAL_FRACTIONAL_LOG2;
386 case IIO_CHAN_INFO_CALIBBIAS:
387 ret = ad5360_read(indio_dev, AD5360_READBACK_OFFSET,
388 chan->address);
389 if (ret < 0)
390 return ret;
391 *val = ret;
392 return IIO_VAL_INT;
393 case IIO_CHAN_INFO_CALIBSCALE:
394 ret = ad5360_read(indio_dev, AD5360_READBACK_GAIN,
395 chan->address);
396 if (ret < 0)
397 return ret;
398 *val = ret;
399 return IIO_VAL_INT;
400 case IIO_CHAN_INFO_OFFSET:
401 ofs_index = ad5360_get_channel_vref_index(st, chan->channel);
402 ret = ad5360_read(indio_dev, AD5360_READBACK_SF,
403 AD5360_REG_SF_OFS(ofs_index));
404 if (ret < 0)
405 return ret;
406
407 ret <<= (chan->scan_type.realbits - 14);
408 *val = -ret;
409 return IIO_VAL_INT;
410 }
411
412 return -EINVAL;
413}
414
415static const struct iio_info ad5360_info = {
416 .read_raw = ad5360_read_raw,
417 .write_raw = ad5360_write_raw,
418 .attrs = &ad5360_attribute_group,
419};
420
421static const char * const ad5360_vref_name[] = {
422 "vref0", "vref1", "vref2"
423};
424
425static int ad5360_alloc_channels(struct iio_dev *indio_dev)
426{
427 struct ad5360_state *st = iio_priv(indio_dev);
428 struct iio_chan_spec *channels;
429 unsigned int i;
430
431 channels = kzalloc_objs(struct iio_chan_spec,
432 st->chip_info->num_channels);
433
434 if (!channels)
435 return -ENOMEM;
436
437 for (i = 0; i < st->chip_info->num_channels; ++i) {
438 channels[i] = st->chip_info->channel_template;
439 channels[i].channel = i;
440 channels[i].address = AD5360_CHAN_ADDR(i);
441 }
442
443 indio_dev->channels = channels;
444
445 return 0;
446}
447
448static int ad5360_probe(struct spi_device *spi)
449{
450 enum ad5360_type type = spi_get_device_id(spi)->driver_data;
451 struct iio_dev *indio_dev;
452 struct ad5360_state *st;
453 unsigned int i;
454 int ret;
455
456 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
457 if (indio_dev == NULL) {
458 dev_err(&spi->dev, "Failed to allocate iio device\n");
459 return -ENOMEM;
460 }
461
462 st = iio_priv(indio_dev);
463 spi_set_drvdata(spi, indio_dev);
464
465 st->chip_info = &ad5360_chip_info_tbl[type];
466 st->spi = spi;
467
468 indio_dev->name = spi_get_device_id(spi)->name;
469 indio_dev->info = &ad5360_info;
470 indio_dev->modes = INDIO_DIRECT_MODE;
471 indio_dev->num_channels = st->chip_info->num_channels;
472
473 mutex_init(&st->lock);
474
475 ret = ad5360_alloc_channels(indio_dev);
476 if (ret) {
477 dev_err(&spi->dev, "Failed to allocate channel spec: %d\n", ret);
478 return ret;
479 }
480
481 for (i = 0; i < st->chip_info->num_vrefs; ++i)
482 st->vref_reg[i].supply = ad5360_vref_name[i];
483
484 ret = devm_regulator_bulk_get(&st->spi->dev, st->chip_info->num_vrefs,
485 st->vref_reg);
486 if (ret) {
487 dev_err(&spi->dev, "Failed to request vref regulators: %d\n", ret);
488 goto error_free_channels;
489 }
490
491 ret = regulator_bulk_enable(st->chip_info->num_vrefs, st->vref_reg);
492 if (ret) {
493 dev_err(&spi->dev, "Failed to enable vref regulators: %d\n", ret);
494 goto error_free_channels;
495 }
496
497 ret = iio_device_register(indio_dev);
498 if (ret) {
499 dev_err(&spi->dev, "Failed to register iio device: %d\n", ret);
500 goto error_disable_reg;
501 }
502
503 return 0;
504
505error_disable_reg:
506 regulator_bulk_disable(st->chip_info->num_vrefs, st->vref_reg);
507error_free_channels:
508 kfree(indio_dev->channels);
509
510 return ret;
511}
512
513static void ad5360_remove(struct spi_device *spi)
514{
515 struct iio_dev *indio_dev = spi_get_drvdata(spi);
516 struct ad5360_state *st = iio_priv(indio_dev);
517
518 iio_device_unregister(indio_dev);
519
520 kfree(indio_dev->channels);
521
522 regulator_bulk_disable(st->chip_info->num_vrefs, st->vref_reg);
523}
524
525static const struct spi_device_id ad5360_ids[] = {
526 { "ad5360", ID_AD5360 },
527 { "ad5361", ID_AD5361 },
528 { "ad5362", ID_AD5362 },
529 { "ad5363", ID_AD5363 },
530 { "ad5370", ID_AD5370 },
531 { "ad5371", ID_AD5371 },
532 { "ad5372", ID_AD5372 },
533 { "ad5373", ID_AD5373 },
534 { }
535};
536MODULE_DEVICE_TABLE(spi, ad5360_ids);
537
538static struct spi_driver ad5360_driver = {
539 .driver = {
540 .name = "ad5360",
541 },
542 .probe = ad5360_probe,
543 .remove = ad5360_remove,
544 .id_table = ad5360_ids,
545};
546module_spi_driver(ad5360_driver);
547
548MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
549MODULE_DESCRIPTION("Analog Devices AD5360/61/62/63/70/71/72/73 DAC");
550MODULE_LICENSE("GPL v2");