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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * MPU3050 gyroscope driver
4 *
5 * Copyright (C) 2016 Linaro Ltd.
6 * Author: Linus Walleij <linus.walleij@linaro.org>
7 *
8 * Based on the input subsystem driver, Copyright (C) 2011 Wistron Co.Ltd
9 * Joseph Lai <joseph_lai@wistron.com> and trimmed down by
10 * Alan Cox <alan@linux.intel.com> in turn based on bma023.c.
11 * Device behaviour based on a misc driver posted by Nathan Royer in 2011.
12 *
13 * TODO: add support for setting up the low pass 3dB frequency.
14 */
15
16#include <linux/bitfield.h>
17#include <linux/bitops.h>
18#include <linux/delay.h>
19#include <linux/err.h>
20#include <linux/iio/buffer.h>
21#include <linux/iio/iio.h>
22#include <linux/iio/sysfs.h>
23#include <linux/iio/trigger.h>
24#include <linux/iio/trigger_consumer.h>
25#include <linux/iio/triggered_buffer.h>
26#include <linux/interrupt.h>
27#include <linux/module.h>
28#include <linux/pm_runtime.h>
29#include <linux/property.h>
30#include <linux/random.h>
31#include <linux/slab.h>
32
33#include "mpu3050.h"
34
35#define MPU3050_CHIP_ID 0x68
36#define MPU3050_CHIP_ID_MASK 0x7E
37
38/*
39 * Register map: anything suffixed *_H is a big-endian high byte and always
40 * followed by the corresponding low byte (*_L) even though these are not
41 * explicitly included in the register definitions.
42 */
43#define MPU3050_CHIP_ID_REG 0x00
44#define MPU3050_PRODUCT_ID_REG 0x01
45#define MPU3050_XG_OFFS_TC 0x05
46#define MPU3050_YG_OFFS_TC 0x08
47#define MPU3050_ZG_OFFS_TC 0x0B
48#define MPU3050_X_OFFS_USR_H 0x0C
49#define MPU3050_Y_OFFS_USR_H 0x0E
50#define MPU3050_Z_OFFS_USR_H 0x10
51#define MPU3050_FIFO_EN 0x12
52#define MPU3050_AUX_VDDIO 0x13
53#define MPU3050_SLV_ADDR 0x14
54#define MPU3050_SMPLRT_DIV 0x15
55#define MPU3050_DLPF_FS_SYNC 0x16
56#define MPU3050_INT_CFG 0x17
57#define MPU3050_AUX_ADDR 0x18
58#define MPU3050_INT_STATUS 0x1A
59#define MPU3050_TEMP_H 0x1B
60#define MPU3050_XOUT_H 0x1D
61#define MPU3050_YOUT_H 0x1F
62#define MPU3050_ZOUT_H 0x21
63#define MPU3050_DMP_CFG1 0x35
64#define MPU3050_DMP_CFG2 0x36
65#define MPU3050_BANK_SEL 0x37
66#define MPU3050_MEM_START_ADDR 0x38
67#define MPU3050_MEM_R_W 0x39
68#define MPU3050_FIFO_COUNT_H 0x3A
69#define MPU3050_FIFO_R 0x3C
70#define MPU3050_USR_CTRL 0x3D
71#define MPU3050_PWR_MGM 0x3E
72
73/* MPU memory bank read options */
74#define MPU3050_MEM_PRFTCH BIT(5)
75#define MPU3050_MEM_USER_BANK BIT(4)
76/* Bits 8-11 select memory bank */
77#define MPU3050_MEM_RAM_BANK_0 0
78#define MPU3050_MEM_RAM_BANK_1 1
79#define MPU3050_MEM_RAM_BANK_2 2
80#define MPU3050_MEM_RAM_BANK_3 3
81#define MPU3050_MEM_OTP_BANK_0 4
82
83#define MPU3050_AXIS_REGS(axis) (MPU3050_XOUT_H + (axis * 2))
84
85/* Register bits */
86
87/* FIFO Enable */
88#define MPU3050_FIFO_EN_FOOTER BIT(0)
89#define MPU3050_FIFO_EN_AUX_ZOUT BIT(1)
90#define MPU3050_FIFO_EN_AUX_YOUT BIT(2)
91#define MPU3050_FIFO_EN_AUX_XOUT BIT(3)
92#define MPU3050_FIFO_EN_GYRO_ZOUT BIT(4)
93#define MPU3050_FIFO_EN_GYRO_YOUT BIT(5)
94#define MPU3050_FIFO_EN_GYRO_XOUT BIT(6)
95#define MPU3050_FIFO_EN_TEMP_OUT BIT(7)
96
97/*
98 * Digital Low Pass filter (DLPF)
99 * Full Scale (FS)
100 * and Synchronization
101 */
102#define MPU3050_EXT_SYNC_NONE 0x00
103#define MPU3050_EXT_SYNC_TEMP 0x20
104#define MPU3050_EXT_SYNC_GYROX 0x40
105#define MPU3050_EXT_SYNC_GYROY 0x60
106#define MPU3050_EXT_SYNC_GYROZ 0x80
107#define MPU3050_EXT_SYNC_ACCELX 0xA0
108#define MPU3050_EXT_SYNC_ACCELY 0xC0
109#define MPU3050_EXT_SYNC_ACCELZ 0xE0
110#define MPU3050_EXT_SYNC_MASK 0xE0
111#define MPU3050_EXT_SYNC_SHIFT 5
112
113#define MPU3050_FS_250DPS 0x00
114#define MPU3050_FS_500DPS 0x08
115#define MPU3050_FS_1000DPS 0x10
116#define MPU3050_FS_2000DPS 0x18
117#define MPU3050_FS_MASK 0x18
118#define MPU3050_FS_SHIFT 3
119
120#define MPU3050_DLPF_CFG_256HZ_NOLPF2 0x00
121#define MPU3050_DLPF_CFG_188HZ 0x01
122#define MPU3050_DLPF_CFG_98HZ 0x02
123#define MPU3050_DLPF_CFG_42HZ 0x03
124#define MPU3050_DLPF_CFG_20HZ 0x04
125#define MPU3050_DLPF_CFG_10HZ 0x05
126#define MPU3050_DLPF_CFG_5HZ 0x06
127#define MPU3050_DLPF_CFG_2100HZ_NOLPF 0x07
128#define MPU3050_DLPF_CFG_MASK 0x07
129#define MPU3050_DLPF_CFG_SHIFT 0
130
131/* Interrupt config */
132#define MPU3050_INT_RAW_RDY_EN BIT(0)
133#define MPU3050_INT_DMP_DONE_EN BIT(1)
134#define MPU3050_INT_MPU_RDY_EN BIT(2)
135#define MPU3050_INT_ANYRD_2CLEAR BIT(4)
136#define MPU3050_INT_LATCH_EN BIT(5)
137#define MPU3050_INT_OPEN BIT(6)
138#define MPU3050_INT_ACTL BIT(7)
139/* Interrupt status */
140#define MPU3050_INT_STATUS_RAW_RDY BIT(0)
141#define MPU3050_INT_STATUS_DMP_DONE BIT(1)
142#define MPU3050_INT_STATUS_MPU_RDY BIT(2)
143#define MPU3050_INT_STATUS_FIFO_OVFLW BIT(7)
144/* USR_CTRL */
145#define MPU3050_USR_CTRL_FIFO_EN BIT(6)
146#define MPU3050_USR_CTRL_AUX_IF_EN BIT(5)
147#define MPU3050_USR_CTRL_AUX_IF_RST BIT(3)
148#define MPU3050_USR_CTRL_FIFO_RST BIT(1)
149#define MPU3050_USR_CTRL_GYRO_RST BIT(0)
150/* PWR_MGM */
151#define MPU3050_PWR_MGM_PLL_X 0x01
152#define MPU3050_PWR_MGM_PLL_Y 0x02
153#define MPU3050_PWR_MGM_PLL_Z 0x03
154#define MPU3050_PWR_MGM_CLKSEL_MASK 0x07
155#define MPU3050_PWR_MGM_STBY_ZG BIT(3)
156#define MPU3050_PWR_MGM_STBY_YG BIT(4)
157#define MPU3050_PWR_MGM_STBY_XG BIT(5)
158#define MPU3050_PWR_MGM_SLEEP BIT(6)
159#define MPU3050_PWR_MGM_RESET BIT(7)
160#define MPU3050_PWR_MGM_MASK 0xff
161
162/*
163 * Fullscale precision is (for finest precision) +/- 250 deg/s, so the full
164 * scale is actually 500 deg/s. All 16 bits are then used to cover this scale,
165 * in two's complement.
166 */
167static unsigned int mpu3050_fs_precision[] = {
168 IIO_DEGREE_TO_RAD(250),
169 IIO_DEGREE_TO_RAD(500),
170 IIO_DEGREE_TO_RAD(1000),
171 IIO_DEGREE_TO_RAD(2000)
172};
173
174/*
175 * Regulator names
176 */
177static const char mpu3050_reg_vdd[] = "vdd";
178static const char mpu3050_reg_vlogic[] = "vlogic";
179
180static unsigned int mpu3050_get_freq(struct mpu3050 *mpu3050)
181{
182 unsigned int freq;
183
184 if (mpu3050->lpf == MPU3050_DLPF_CFG_256HZ_NOLPF2)
185 freq = 8000;
186 else
187 freq = 1000;
188 freq /= (mpu3050->divisor + 1);
189
190 return freq;
191}
192
193static int mpu3050_start_sampling(struct mpu3050 *mpu3050)
194{
195 __be16 raw_val[3];
196 int ret;
197 int i;
198
199 /* Reset */
200 ret = regmap_set_bits(mpu3050->map, MPU3050_PWR_MGM,
201 MPU3050_PWR_MGM_RESET);
202 if (ret)
203 return ret;
204
205 /* Turn on the Z-axis PLL */
206 ret = regmap_update_bits(mpu3050->map, MPU3050_PWR_MGM,
207 MPU3050_PWR_MGM_CLKSEL_MASK,
208 MPU3050_PWR_MGM_PLL_Z);
209 if (ret)
210 return ret;
211
212 /* Write calibration offset registers */
213 for (i = 0; i < 3; i++)
214 raw_val[i] = cpu_to_be16(mpu3050->calibration[i]);
215
216 ret = regmap_bulk_write(mpu3050->map, MPU3050_X_OFFS_USR_H, raw_val,
217 sizeof(raw_val));
218 if (ret)
219 return ret;
220
221 /* Set low pass filter (sample rate), sync and full scale */
222 ret = regmap_write(mpu3050->map, MPU3050_DLPF_FS_SYNC,
223 MPU3050_EXT_SYNC_NONE << MPU3050_EXT_SYNC_SHIFT |
224 mpu3050->fullscale << MPU3050_FS_SHIFT |
225 mpu3050->lpf << MPU3050_DLPF_CFG_SHIFT);
226 if (ret)
227 return ret;
228
229 /* Set up sampling frequency */
230 ret = regmap_write(mpu3050->map, MPU3050_SMPLRT_DIV, mpu3050->divisor);
231 if (ret)
232 return ret;
233
234 /*
235 * Max 50 ms start-up time after setting DLPF_FS_SYNC
236 * according to the data sheet, then wait for the next sample
237 * at this frequency T = 1000/f ms.
238 */
239 msleep(50 + 1000 / mpu3050_get_freq(mpu3050));
240
241 return 0;
242}
243
244static int mpu3050_set_8khz_samplerate(struct mpu3050 *mpu3050)
245{
246 int ret;
247 u8 divisor;
248 enum mpu3050_lpf lpf;
249
250 lpf = mpu3050->lpf;
251 divisor = mpu3050->divisor;
252
253 mpu3050->lpf = LPF_256_HZ_NOLPF; /* 8 kHz base frequency */
254 mpu3050->divisor = 0; /* Divide by 1 */
255 ret = mpu3050_start_sampling(mpu3050);
256
257 mpu3050->lpf = lpf;
258 mpu3050->divisor = divisor;
259
260 return ret;
261}
262
263static int mpu3050_read_raw(struct iio_dev *indio_dev,
264 struct iio_chan_spec const *chan,
265 int *val, int *val2,
266 long mask)
267{
268 struct mpu3050 *mpu3050 = iio_priv(indio_dev);
269 int ret;
270 __be16 raw_val;
271
272 switch (mask) {
273 case IIO_CHAN_INFO_OFFSET:
274 switch (chan->type) {
275 case IIO_TEMP:
276 /*
277 * The temperature scaling is (x+23000)/280 Celsius
278 * for the "best fit straight line" temperature range
279 * of -30C..85C. The 23000 includes room temperature
280 * offset of +35C, 280 is the precision scale and x is
281 * the 16-bit signed integer reported by hardware.
282 *
283 * Temperature value itself represents temperature of
284 * the sensor die.
285 */
286 *val = 23000;
287 return IIO_VAL_INT;
288 default:
289 return -EINVAL;
290 }
291 case IIO_CHAN_INFO_CALIBBIAS:
292 switch (chan->type) {
293 case IIO_ANGL_VEL:
294 *val = mpu3050->calibration[chan->scan_index-1];
295 return IIO_VAL_INT;
296 default:
297 return -EINVAL;
298 }
299 case IIO_CHAN_INFO_SAMP_FREQ:
300 *val = mpu3050_get_freq(mpu3050);
301 return IIO_VAL_INT;
302 case IIO_CHAN_INFO_SCALE:
303 switch (chan->type) {
304 case IIO_TEMP:
305 /* Millidegrees, see about temperature scaling above */
306 *val = 1000;
307 *val2 = 280;
308 return IIO_VAL_FRACTIONAL;
309 case IIO_ANGL_VEL:
310 /*
311 * Convert to the corresponding full scale in
312 * radians. All 16 bits are used with sign to
313 * span the available scale: to account for the one
314 * missing value if we multiply by 1/S16_MAX, instead
315 * multiply with 2/U16_MAX.
316 */
317 *val = mpu3050_fs_precision[mpu3050->fullscale] * 2;
318 *val2 = U16_MAX;
319 return IIO_VAL_FRACTIONAL;
320 default:
321 return -EINVAL;
322 }
323 case IIO_CHAN_INFO_RAW:
324 /* Resume device */
325 ret = pm_runtime_resume_and_get(mpu3050->dev);
326 if (ret)
327 return ret;
328 mutex_lock(&mpu3050->lock);
329
330 ret = mpu3050_set_8khz_samplerate(mpu3050);
331 if (ret)
332 goto out_read_raw_unlock;
333
334 switch (chan->type) {
335 case IIO_TEMP:
336 ret = regmap_bulk_read(mpu3050->map, MPU3050_TEMP_H,
337 &raw_val, sizeof(raw_val));
338 if (ret) {
339 dev_err(mpu3050->dev,
340 "error reading temperature\n");
341 goto out_read_raw_unlock;
342 }
343
344 *val = (s16)be16_to_cpu(raw_val);
345 ret = IIO_VAL_INT;
346
347 goto out_read_raw_unlock;
348 case IIO_ANGL_VEL:
349 ret = regmap_bulk_read(mpu3050->map,
350 MPU3050_AXIS_REGS(chan->scan_index-1),
351 &raw_val,
352 sizeof(raw_val));
353 if (ret) {
354 dev_err(mpu3050->dev,
355 "error reading axis data\n");
356 goto out_read_raw_unlock;
357 }
358
359 *val = be16_to_cpu(raw_val);
360 ret = IIO_VAL_INT;
361
362 goto out_read_raw_unlock;
363 default:
364 ret = -EINVAL;
365 goto out_read_raw_unlock;
366 }
367 default:
368 break;
369 }
370
371 return -EINVAL;
372
373out_read_raw_unlock:
374 mutex_unlock(&mpu3050->lock);
375 pm_runtime_put_autosuspend(mpu3050->dev);
376
377 return ret;
378}
379
380static int mpu3050_write_raw(struct iio_dev *indio_dev,
381 const struct iio_chan_spec *chan,
382 int val, int val2, long mask)
383{
384 struct mpu3050 *mpu3050 = iio_priv(indio_dev);
385 /*
386 * Couldn't figure out a way to precalculate these at compile time.
387 */
388 unsigned int fs250 =
389 DIV_ROUND_CLOSEST(mpu3050_fs_precision[0] * 1000000 * 2,
390 U16_MAX);
391 unsigned int fs500 =
392 DIV_ROUND_CLOSEST(mpu3050_fs_precision[1] * 1000000 * 2,
393 U16_MAX);
394 unsigned int fs1000 =
395 DIV_ROUND_CLOSEST(mpu3050_fs_precision[2] * 1000000 * 2,
396 U16_MAX);
397 unsigned int fs2000 =
398 DIV_ROUND_CLOSEST(mpu3050_fs_precision[3] * 1000000 * 2,
399 U16_MAX);
400
401 switch (mask) {
402 case IIO_CHAN_INFO_CALIBBIAS:
403 if (chan->type != IIO_ANGL_VEL)
404 return -EINVAL;
405 mpu3050->calibration[chan->scan_index-1] = val;
406 return 0;
407 case IIO_CHAN_INFO_SAMP_FREQ:
408 /*
409 * The max samplerate is 8000 Hz, the minimum
410 * 1000 / 256 ~= 4 Hz
411 */
412 if (val < 4 || val > 8000)
413 return -EINVAL;
414
415 /*
416 * Above 1000 Hz we must turn off the digital low pass filter
417 * so we get a base frequency of 8kHz to the divider
418 */
419 if (val > 1000) {
420 mpu3050->lpf = LPF_256_HZ_NOLPF;
421 mpu3050->divisor = DIV_ROUND_CLOSEST(8000, val) - 1;
422 return 0;
423 }
424
425 mpu3050->lpf = LPF_188_HZ;
426 mpu3050->divisor = DIV_ROUND_CLOSEST(1000, val) - 1;
427 return 0;
428 case IIO_CHAN_INFO_SCALE:
429 if (chan->type != IIO_ANGL_VEL)
430 return -EINVAL;
431 /*
432 * We support +/-250, +/-500, +/-1000 and +/2000 deg/s
433 * which means we need to round to the closest radians
434 * which will be roughly +/-4.3, +/-8.7, +/-17.5, +/-35
435 * rad/s. The scale is then for the 16 bits used to cover
436 * it 2/(2^16) of that.
437 */
438
439 /* Just too large, set the max range */
440 if (val != 0) {
441 mpu3050->fullscale = FS_2000_DPS;
442 return 0;
443 }
444
445 /*
446 * Now we're dealing with fractions below zero in millirad/s
447 * do some integer interpolation and match with the closest
448 * fullscale in the table.
449 */
450 if (val2 <= fs250 ||
451 val2 < ((fs500 + fs250) / 2))
452 mpu3050->fullscale = FS_250_DPS;
453 else if (val2 <= fs500 ||
454 val2 < ((fs1000 + fs500) / 2))
455 mpu3050->fullscale = FS_500_DPS;
456 else if (val2 <= fs1000 ||
457 val2 < ((fs2000 + fs1000) / 2))
458 mpu3050->fullscale = FS_1000_DPS;
459 else
460 /* Catch-all */
461 mpu3050->fullscale = FS_2000_DPS;
462 return 0;
463 default:
464 break;
465 }
466
467 return -EINVAL;
468}
469
470static irqreturn_t mpu3050_trigger_handler(int irq, void *p)
471{
472 const struct iio_poll_func *pf = p;
473 struct iio_dev *indio_dev = pf->indio_dev;
474 struct mpu3050 *mpu3050 = iio_priv(indio_dev);
475 int ret;
476 struct {
477 __be16 chans[4];
478 aligned_s64 timestamp;
479 } scan;
480 s64 timestamp;
481 unsigned int datums_from_fifo = 0;
482
483 /*
484 * If we're using the hardware trigger, get the precise timestamp from
485 * the top half of the threaded IRQ handler. Otherwise get the
486 * timestamp here so it will be close in time to the actual values
487 * read from the registers.
488 */
489 if (iio_trigger_using_own(indio_dev))
490 timestamp = mpu3050->hw_timestamp;
491 else
492 timestamp = iio_get_time_ns(indio_dev);
493
494 mutex_lock(&mpu3050->lock);
495
496 /* Using the hardware IRQ trigger? Check the buffer then. */
497 if (mpu3050->hw_irq_trigger) {
498 __be16 raw_fifocnt;
499 u16 fifocnt;
500 /* X, Y, Z + temperature */
501 unsigned int bytes_per_datum = 8;
502 bool fifo_overflow = false;
503
504 ret = regmap_bulk_read(mpu3050->map,
505 MPU3050_FIFO_COUNT_H,
506 &raw_fifocnt,
507 sizeof(raw_fifocnt));
508 if (ret)
509 goto out_trigger_unlock;
510 fifocnt = be16_to_cpu(raw_fifocnt);
511
512 if (fifocnt == 512) {
513 dev_info(mpu3050->dev,
514 "FIFO overflow! Emptying and resetting FIFO\n");
515 fifo_overflow = true;
516 /* Reset and enable the FIFO */
517 ret = regmap_set_bits(mpu3050->map, MPU3050_USR_CTRL,
518 MPU3050_USR_CTRL_FIFO_EN |
519 MPU3050_USR_CTRL_FIFO_RST);
520 if (ret) {
521 dev_info(mpu3050->dev, "error resetting FIFO\n");
522 goto out_trigger_unlock;
523 }
524 mpu3050->pending_fifo_footer = false;
525 }
526
527 if (fifocnt)
528 dev_dbg(mpu3050->dev,
529 "%d bytes in the FIFO\n",
530 fifocnt);
531
532 while (!fifo_overflow && fifocnt > bytes_per_datum) {
533 unsigned int toread;
534 unsigned int offset;
535 __be16 fifo_values[5];
536
537 /*
538 * If there is a FIFO footer in the pipe, first clear
539 * that out. This follows the complex algorithm in the
540 * datasheet that states that you may never leave the
541 * FIFO empty after the first reading: you have to
542 * always leave two footer bytes in it. The footer is
543 * in practice just two zero bytes.
544 */
545 if (mpu3050->pending_fifo_footer) {
546 toread = bytes_per_datum + 2;
547 offset = 0;
548 } else {
549 toread = bytes_per_datum;
550 offset = 1;
551 /* Put in some dummy value */
552 fifo_values[0] = cpu_to_be16(0xAAAA);
553 }
554
555 ret = regmap_bulk_read(mpu3050->map,
556 MPU3050_FIFO_R,
557 &fifo_values[offset],
558 toread);
559 if (ret)
560 goto out_trigger_unlock;
561
562 dev_dbg(mpu3050->dev,
563 "%04x %04x %04x %04x %04x\n",
564 fifo_values[0],
565 fifo_values[1],
566 fifo_values[2],
567 fifo_values[3],
568 fifo_values[4]);
569
570 /* Index past the footer (fifo_values[0]) and push */
571 iio_push_to_buffers_with_ts_unaligned(indio_dev,
572 &fifo_values[1],
573 sizeof(__be16) * 4,
574 timestamp);
575
576 fifocnt -= toread;
577 datums_from_fifo++;
578 mpu3050->pending_fifo_footer = true;
579
580 /*
581 * If we're emptying the FIFO, just make sure to
582 * check if something new appeared.
583 */
584 if (fifocnt < bytes_per_datum) {
585 ret = regmap_bulk_read(mpu3050->map,
586 MPU3050_FIFO_COUNT_H,
587 &raw_fifocnt,
588 sizeof(raw_fifocnt));
589 if (ret)
590 goto out_trigger_unlock;
591 fifocnt = be16_to_cpu(raw_fifocnt);
592 }
593
594 if (fifocnt < bytes_per_datum)
595 dev_dbg(mpu3050->dev,
596 "%d bytes left in the FIFO\n",
597 fifocnt);
598
599 /*
600 * At this point, the timestamp that triggered the
601 * hardware interrupt is no longer valid for what
602 * we are reading (the interrupt likely fired for
603 * the value on the top of the FIFO), so set the
604 * timestamp to zero and let userspace deal with it.
605 */
606 timestamp = 0;
607 }
608 }
609
610 /*
611 * If we picked some datums from the FIFO that's enough, else
612 * fall through and just read from the current value registers.
613 * This happens in two cases:
614 *
615 * - We are using some other trigger (external, like an HRTimer)
616 * than the sensor's own sample generator. In this case the
617 * sensor is just set to the max sampling frequency and we give
618 * the trigger a copy of the latest value every time we get here.
619 *
620 * - The hardware trigger is active but unused and we actually use
621 * another trigger which calls here with a frequency higher
622 * than what the device provides data. We will then just read
623 * duplicate values directly from the hardware registers.
624 */
625 if (datums_from_fifo) {
626 dev_dbg(mpu3050->dev,
627 "read %d datums from the FIFO\n",
628 datums_from_fifo);
629 goto out_trigger_unlock;
630 }
631
632 ret = regmap_bulk_read(mpu3050->map, MPU3050_TEMP_H, scan.chans,
633 sizeof(scan.chans));
634 if (ret) {
635 dev_err(mpu3050->dev,
636 "error reading axis data\n");
637 goto out_trigger_unlock;
638 }
639
640 iio_push_to_buffers_with_timestamp(indio_dev, &scan, timestamp);
641
642out_trigger_unlock:
643 mutex_unlock(&mpu3050->lock);
644 iio_trigger_notify_done(indio_dev->trig);
645
646 return IRQ_HANDLED;
647}
648
649static int mpu3050_buffer_preenable(struct iio_dev *indio_dev)
650{
651 struct mpu3050 *mpu3050 = iio_priv(indio_dev);
652 int ret;
653
654 ret = pm_runtime_resume_and_get(mpu3050->dev);
655 if (ret)
656 return ret;
657
658 /* Unless we have OUR trigger active, run at full speed */
659 if (!mpu3050->hw_irq_trigger) {
660 ret = mpu3050_set_8khz_samplerate(mpu3050);
661 if (ret)
662 pm_runtime_put_autosuspend(mpu3050->dev);
663 }
664
665 return ret;
666}
667
668static int mpu3050_buffer_postdisable(struct iio_dev *indio_dev)
669{
670 struct mpu3050 *mpu3050 = iio_priv(indio_dev);
671
672 pm_runtime_put_autosuspend(mpu3050->dev);
673
674 return 0;
675}
676
677static const struct iio_buffer_setup_ops mpu3050_buffer_setup_ops = {
678 .preenable = mpu3050_buffer_preenable,
679 .postdisable = mpu3050_buffer_postdisable,
680};
681
682static const struct iio_mount_matrix *
683mpu3050_get_mount_matrix(const struct iio_dev *indio_dev,
684 const struct iio_chan_spec *chan)
685{
686 struct mpu3050 *mpu3050 = iio_priv(indio_dev);
687
688 return &mpu3050->orientation;
689}
690
691static const struct iio_chan_spec_ext_info mpu3050_ext_info[] = {
692 IIO_MOUNT_MATRIX(IIO_SHARED_BY_TYPE, mpu3050_get_mount_matrix),
693 { }
694};
695
696#define MPU3050_AXIS_CHANNEL(axis, index) \
697 { \
698 .type = IIO_ANGL_VEL, \
699 .modified = 1, \
700 .channel2 = IIO_MOD_##axis, \
701 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
702 BIT(IIO_CHAN_INFO_CALIBBIAS), \
703 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
704 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),\
705 .ext_info = mpu3050_ext_info, \
706 .scan_index = index, \
707 .scan_type = { \
708 .sign = 's', \
709 .realbits = 16, \
710 .storagebits = 16, \
711 .endianness = IIO_BE, \
712 }, \
713 }
714
715static const struct iio_chan_spec mpu3050_channels[] = {
716 {
717 .type = IIO_TEMP,
718 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
719 BIT(IIO_CHAN_INFO_SCALE) |
720 BIT(IIO_CHAN_INFO_OFFSET),
721 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),
722 .scan_index = 0,
723 .scan_type = {
724 .sign = 's',
725 .realbits = 16,
726 .storagebits = 16,
727 .endianness = IIO_BE,
728 },
729 },
730 MPU3050_AXIS_CHANNEL(X, 1),
731 MPU3050_AXIS_CHANNEL(Y, 2),
732 MPU3050_AXIS_CHANNEL(Z, 3),
733 IIO_CHAN_SOFT_TIMESTAMP(4),
734};
735
736/* Four channels apart from timestamp, scan mask = 0x0f */
737static const unsigned long mpu3050_scan_masks[] = { 0xf, 0 };
738
739/*
740 * These are just the hardcoded factors resulting from the more elaborate
741 * calculations done with fractions in the scale raw get/set functions.
742 */
743static IIO_CONST_ATTR(anglevel_scale_available,
744 "0.000122070 "
745 "0.000274658 "
746 "0.000518798 "
747 "0.001068115");
748
749static struct attribute *mpu3050_attributes[] = {
750 &iio_const_attr_anglevel_scale_available.dev_attr.attr,
751 NULL,
752};
753
754static const struct attribute_group mpu3050_attribute_group = {
755 .attrs = mpu3050_attributes,
756};
757
758static const struct iio_info mpu3050_info = {
759 .read_raw = mpu3050_read_raw,
760 .write_raw = mpu3050_write_raw,
761 .attrs = &mpu3050_attribute_group,
762};
763
764/**
765 * mpu3050_read_mem() - read MPU-3050 internal memory
766 * @mpu3050: device to read from
767 * @bank: target bank
768 * @addr: target address
769 * @len: number of bytes
770 * @buf: the buffer to store the read bytes in
771 */
772static int mpu3050_read_mem(struct mpu3050 *mpu3050,
773 u8 bank,
774 u8 addr,
775 u8 len,
776 u8 *buf)
777{
778 int ret;
779
780 ret = regmap_write(mpu3050->map,
781 MPU3050_BANK_SEL,
782 bank);
783 if (ret)
784 return ret;
785
786 ret = regmap_write(mpu3050->map,
787 MPU3050_MEM_START_ADDR,
788 addr);
789 if (ret)
790 return ret;
791
792 return regmap_bulk_read(mpu3050->map,
793 MPU3050_MEM_R_W,
794 buf,
795 len);
796}
797
798static int mpu3050_hw_init(struct mpu3050 *mpu3050)
799{
800 int ret;
801 __le64 otp_le;
802 u64 otp;
803
804 /* Reset */
805 ret = regmap_set_bits(mpu3050->map, MPU3050_PWR_MGM,
806 MPU3050_PWR_MGM_RESET);
807 if (ret)
808 return ret;
809
810 /* Turn on the PLL */
811 ret = regmap_update_bits(mpu3050->map,
812 MPU3050_PWR_MGM,
813 MPU3050_PWR_MGM_CLKSEL_MASK,
814 MPU3050_PWR_MGM_PLL_Z);
815 if (ret)
816 return ret;
817
818 /* Disable IRQs */
819 ret = regmap_write(mpu3050->map,
820 MPU3050_INT_CFG,
821 0);
822 if (ret)
823 return ret;
824
825 /* Read out the 8 bytes of OTP (one-time-programmable) memory */
826 ret = mpu3050_read_mem(mpu3050,
827 (MPU3050_MEM_PRFTCH |
828 MPU3050_MEM_USER_BANK |
829 MPU3050_MEM_OTP_BANK_0),
830 0,
831 sizeof(otp_le),
832 (u8 *)&otp_le);
833 if (ret)
834 return ret;
835
836 /* This is device-unique data so it goes into the entropy pool */
837 add_device_randomness(&otp_le, sizeof(otp_le));
838
839 otp = le64_to_cpu(otp_le);
840
841 dev_info(mpu3050->dev,
842 "die ID: %04llX, wafer ID: %02llX, A lot ID: %04llX, "
843 "W lot ID: %03llX, WP ID: %01llX, rev ID: %02llX\n",
844 /* Die ID, bits 0-12 */
845 FIELD_GET(GENMASK_ULL(12, 0), otp),
846 /* Wafer ID, bits 13-17 */
847 FIELD_GET(GENMASK_ULL(17, 13), otp),
848 /* A lot ID, bits 18-33 */
849 FIELD_GET(GENMASK_ULL(33, 18), otp),
850 /* W lot ID, bits 34-45 */
851 FIELD_GET(GENMASK_ULL(45, 34), otp),
852 /* WP ID, bits 47-49 */
853 FIELD_GET(GENMASK_ULL(49, 47), otp),
854 /* rev ID, bits 50-55 */
855 FIELD_GET(GENMASK_ULL(55, 50), otp));
856
857 return 0;
858}
859
860static int mpu3050_power_up(struct mpu3050 *mpu3050)
861{
862 int ret;
863
864 ret = regulator_bulk_enable(ARRAY_SIZE(mpu3050->regs), mpu3050->regs);
865 if (ret) {
866 dev_err(mpu3050->dev, "cannot enable regulators\n");
867 return ret;
868 }
869 /*
870 * 20-100 ms start-up time for register read/write according to
871 * the datasheet, be on the safe side and wait 200 ms.
872 */
873 msleep(200);
874
875 /* Take device out of sleep mode */
876 ret = regmap_clear_bits(mpu3050->map, MPU3050_PWR_MGM,
877 MPU3050_PWR_MGM_SLEEP);
878 if (ret) {
879 regulator_bulk_disable(ARRAY_SIZE(mpu3050->regs), mpu3050->regs);
880 dev_err(mpu3050->dev, "error setting power mode\n");
881 return ret;
882 }
883 usleep_range(10000, 20000);
884
885 return 0;
886}
887
888static int mpu3050_power_down(struct mpu3050 *mpu3050)
889{
890 int ret;
891
892 /*
893 * Put MPU-3050 into sleep mode before cutting regulators.
894 * This is important, because we may not be the sole user
895 * of the regulator so the power may stay on after this, and
896 * then we would be wasting power unless we go to sleep mode
897 * first.
898 */
899 ret = regmap_set_bits(mpu3050->map, MPU3050_PWR_MGM,
900 MPU3050_PWR_MGM_SLEEP);
901 if (ret)
902 dev_err(mpu3050->dev, "error putting to sleep\n");
903
904 ret = regulator_bulk_disable(ARRAY_SIZE(mpu3050->regs), mpu3050->regs);
905 if (ret)
906 dev_err(mpu3050->dev, "error disabling regulators\n");
907
908 return 0;
909}
910
911static irqreturn_t mpu3050_irq_handler(int irq, void *p)
912{
913 struct iio_trigger *trig = p;
914 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
915 struct mpu3050 *mpu3050 = iio_priv(indio_dev);
916
917 if (!mpu3050->hw_irq_trigger)
918 return IRQ_NONE;
919
920 /* Get the time stamp as close in time as possible */
921 mpu3050->hw_timestamp = iio_get_time_ns(indio_dev);
922
923 return IRQ_WAKE_THREAD;
924}
925
926static irqreturn_t mpu3050_irq_thread(int irq, void *p)
927{
928 struct iio_trigger *trig = p;
929 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
930 struct mpu3050 *mpu3050 = iio_priv(indio_dev);
931 unsigned int val;
932 int ret;
933
934 /* ACK IRQ and check if it was from us */
935 ret = regmap_read(mpu3050->map, MPU3050_INT_STATUS, &val);
936 if (ret) {
937 dev_err(mpu3050->dev, "error reading IRQ status\n");
938 return IRQ_HANDLED;
939 }
940 if (!(val & MPU3050_INT_STATUS_RAW_RDY))
941 return IRQ_NONE;
942
943 iio_trigger_poll_nested(p);
944
945 return IRQ_HANDLED;
946}
947
948/**
949 * mpu3050_drdy_trigger_set_state() - set data ready interrupt state
950 * @trig: trigger instance
951 * @enable: true if trigger should be enabled, false to disable
952 */
953static int mpu3050_drdy_trigger_set_state(struct iio_trigger *trig,
954 bool enable)
955{
956 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
957 struct mpu3050 *mpu3050 = iio_priv(indio_dev);
958 unsigned int val;
959 int ret;
960
961 /* Disabling trigger: disable interrupt and return */
962 if (!enable) {
963 /* Disable all interrupts */
964 ret = regmap_write(mpu3050->map,
965 MPU3050_INT_CFG,
966 0);
967 if (ret)
968 dev_err(mpu3050->dev, "error disabling IRQ\n");
969
970 /* Clear IRQ flag */
971 ret = regmap_read(mpu3050->map, MPU3050_INT_STATUS, &val);
972 if (ret)
973 dev_err(mpu3050->dev, "error clearing IRQ status\n");
974
975 /* Disable all things in the FIFO and reset it */
976 ret = regmap_write(mpu3050->map, MPU3050_FIFO_EN, 0);
977 if (ret)
978 dev_err(mpu3050->dev, "error disabling FIFO\n");
979
980 ret = regmap_write(mpu3050->map, MPU3050_USR_CTRL,
981 MPU3050_USR_CTRL_FIFO_RST);
982 if (ret)
983 dev_err(mpu3050->dev, "error resetting FIFO\n");
984
985 pm_runtime_put_autosuspend(mpu3050->dev);
986 mpu3050->hw_irq_trigger = false;
987
988 return 0;
989 } else {
990 /* Else we're enabling the trigger from this point */
991 pm_runtime_get_sync(mpu3050->dev);
992 mpu3050->hw_irq_trigger = true;
993
994 /* Disable all things in the FIFO */
995 ret = regmap_write(mpu3050->map, MPU3050_FIFO_EN, 0);
996 if (ret)
997 return ret;
998
999 /* Reset and enable the FIFO */
1000 ret = regmap_set_bits(mpu3050->map, MPU3050_USR_CTRL,
1001 MPU3050_USR_CTRL_FIFO_EN |
1002 MPU3050_USR_CTRL_FIFO_RST);
1003 if (ret)
1004 return ret;
1005
1006 mpu3050->pending_fifo_footer = false;
1007
1008 /* Turn on the FIFO for temp+X+Y+Z */
1009 ret = regmap_write(mpu3050->map, MPU3050_FIFO_EN,
1010 MPU3050_FIFO_EN_TEMP_OUT |
1011 MPU3050_FIFO_EN_GYRO_XOUT |
1012 MPU3050_FIFO_EN_GYRO_YOUT |
1013 MPU3050_FIFO_EN_GYRO_ZOUT |
1014 MPU3050_FIFO_EN_FOOTER);
1015 if (ret)
1016 return ret;
1017
1018 /* Configure the sample engine */
1019 ret = mpu3050_start_sampling(mpu3050);
1020 if (ret)
1021 return ret;
1022
1023 /* Clear IRQ flag */
1024 ret = regmap_read(mpu3050->map, MPU3050_INT_STATUS, &val);
1025 if (ret)
1026 dev_err(mpu3050->dev, "error clearing IRQ status\n");
1027
1028 /* Give us interrupts whenever there is new data ready */
1029 val = MPU3050_INT_RAW_RDY_EN;
1030
1031 if (mpu3050->irq_actl)
1032 val |= MPU3050_INT_ACTL;
1033 if (mpu3050->irq_latch)
1034 val |= MPU3050_INT_LATCH_EN;
1035 if (mpu3050->irq_opendrain)
1036 val |= MPU3050_INT_OPEN;
1037
1038 ret = regmap_write(mpu3050->map, MPU3050_INT_CFG, val);
1039 if (ret)
1040 return ret;
1041 }
1042
1043 return 0;
1044}
1045
1046static const struct iio_trigger_ops mpu3050_trigger_ops = {
1047 .set_trigger_state = mpu3050_drdy_trigger_set_state,
1048};
1049
1050static int mpu3050_trigger_probe(struct iio_dev *indio_dev, int irq)
1051{
1052 struct mpu3050 *mpu3050 = iio_priv(indio_dev);
1053 struct device *dev = mpu3050->dev;
1054 unsigned long irq_trig;
1055 int ret;
1056
1057 mpu3050->trig = devm_iio_trigger_alloc(&indio_dev->dev,
1058 "%s-dev%d",
1059 indio_dev->name,
1060 iio_device_id(indio_dev));
1061 if (!mpu3050->trig)
1062 return -ENOMEM;
1063
1064 /* Check if IRQ is open drain */
1065 mpu3050->irq_opendrain = device_property_read_bool(dev, "drive-open-drain");
1066
1067 /*
1068 * Configure the interrupt generator hardware to supply whatever
1069 * the interrupt is configured for, edges low/high level low/high,
1070 * we can provide it all.
1071 */
1072 irq_trig = irq_get_trigger_type(irq);
1073 switch (irq_trig) {
1074 case IRQF_TRIGGER_RISING:
1075 dev_info(&indio_dev->dev,
1076 "pulse interrupts on the rising edge\n");
1077 break;
1078 case IRQF_TRIGGER_FALLING:
1079 mpu3050->irq_actl = true;
1080 dev_info(&indio_dev->dev,
1081 "pulse interrupts on the falling edge\n");
1082 break;
1083 case IRQF_TRIGGER_HIGH:
1084 mpu3050->irq_latch = true;
1085 dev_info(&indio_dev->dev,
1086 "interrupts active high level\n");
1087 /*
1088 * With level IRQs, we mask the IRQ until it is processed,
1089 * but with edge IRQs (pulses) we can queue several interrupts
1090 * in the top half.
1091 */
1092 irq_trig |= IRQF_ONESHOT;
1093 break;
1094 case IRQF_TRIGGER_LOW:
1095 mpu3050->irq_latch = true;
1096 mpu3050->irq_actl = true;
1097 irq_trig |= IRQF_ONESHOT;
1098 dev_info(&indio_dev->dev,
1099 "interrupts active low level\n");
1100 break;
1101 default:
1102 /* This is the most preferred mode, if possible */
1103 dev_err(&indio_dev->dev,
1104 "unsupported IRQ trigger specified (%lx), enforce "
1105 "rising edge\n", irq_trig);
1106 irq_trig = IRQF_TRIGGER_RISING;
1107 break;
1108 }
1109
1110 /* An open drain line can be shared with several devices */
1111 if (mpu3050->irq_opendrain)
1112 irq_trig |= IRQF_SHARED;
1113
1114 ret = request_threaded_irq(irq,
1115 mpu3050_irq_handler,
1116 mpu3050_irq_thread,
1117 irq_trig,
1118 mpu3050->trig->name,
1119 mpu3050->trig);
1120 if (ret) {
1121 dev_err(dev, "can't get IRQ %d, error %d\n", irq, ret);
1122 return ret;
1123 }
1124
1125 mpu3050->irq = irq;
1126 mpu3050->trig->dev.parent = dev;
1127 mpu3050->trig->ops = &mpu3050_trigger_ops;
1128 iio_trigger_set_drvdata(mpu3050->trig, indio_dev);
1129
1130 ret = iio_trigger_register(mpu3050->trig);
1131 if (ret)
1132 goto err_iio_trigger;
1133
1134 indio_dev->trig = iio_trigger_get(mpu3050->trig);
1135
1136 return 0;
1137
1138err_iio_trigger:
1139 free_irq(mpu3050->irq, mpu3050->trig);
1140
1141 return ret;
1142}
1143
1144int mpu3050_common_probe(struct device *dev,
1145 struct regmap *map,
1146 int irq,
1147 const char *name)
1148{
1149 struct iio_dev *indio_dev;
1150 struct mpu3050 *mpu3050;
1151 unsigned int val;
1152 int ret;
1153
1154 indio_dev = devm_iio_device_alloc(dev, sizeof(*mpu3050));
1155 if (!indio_dev)
1156 return -ENOMEM;
1157 mpu3050 = iio_priv(indio_dev);
1158
1159 mpu3050->dev = dev;
1160 mpu3050->map = map;
1161 mutex_init(&mpu3050->lock);
1162 /* Default fullscale: 2000 degrees per second */
1163 mpu3050->fullscale = FS_2000_DPS;
1164 /* 1 kHz, divide by 100, default frequency = 10 Hz */
1165 mpu3050->lpf = MPU3050_DLPF_CFG_188HZ;
1166 mpu3050->divisor = 99;
1167
1168 /* Read the mounting matrix, if present */
1169 ret = iio_read_mount_matrix(dev, &mpu3050->orientation);
1170 if (ret)
1171 return ret;
1172
1173 /* Fetch and turn on regulators */
1174 mpu3050->regs[0].supply = mpu3050_reg_vdd;
1175 mpu3050->regs[1].supply = mpu3050_reg_vlogic;
1176 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(mpu3050->regs),
1177 mpu3050->regs);
1178 if (ret)
1179 return dev_err_probe(dev, ret, "Cannot get regulators\n");
1180
1181 ret = mpu3050_power_up(mpu3050);
1182 if (ret)
1183 return ret;
1184
1185 ret = regmap_read(map, MPU3050_CHIP_ID_REG, &val);
1186 if (ret) {
1187 dev_err(dev, "could not read device ID\n");
1188 ret = -ENODEV;
1189
1190 goto err_power_down;
1191 }
1192
1193 if ((val & MPU3050_CHIP_ID_MASK) != MPU3050_CHIP_ID) {
1194 dev_err(dev, "unsupported chip id %02x\n",
1195 (u8)(val & MPU3050_CHIP_ID_MASK));
1196 ret = -ENODEV;
1197 goto err_power_down;
1198 }
1199
1200 ret = regmap_read(map, MPU3050_PRODUCT_ID_REG, &val);
1201 if (ret) {
1202 dev_err(dev, "could not read device ID\n");
1203 ret = -ENODEV;
1204
1205 goto err_power_down;
1206 }
1207 dev_info(dev, "found MPU-3050 part no: %d, version: %d\n",
1208 ((val >> 4) & 0xf), (val & 0xf));
1209
1210 ret = mpu3050_hw_init(mpu3050);
1211 if (ret)
1212 goto err_power_down;
1213
1214 indio_dev->channels = mpu3050_channels;
1215 indio_dev->num_channels = ARRAY_SIZE(mpu3050_channels);
1216 indio_dev->info = &mpu3050_info;
1217 indio_dev->available_scan_masks = mpu3050_scan_masks;
1218 indio_dev->modes = INDIO_DIRECT_MODE;
1219 indio_dev->name = name;
1220
1221 ret = iio_triggered_buffer_setup(indio_dev, iio_pollfunc_store_time,
1222 mpu3050_trigger_handler,
1223 &mpu3050_buffer_setup_ops);
1224 if (ret) {
1225 dev_err(dev, "triggered buffer setup failed\n");
1226 goto err_power_down;
1227 }
1228
1229 dev_set_drvdata(dev, indio_dev);
1230
1231 /* Check if we have an assigned IRQ to use as trigger */
1232 if (irq) {
1233 ret = mpu3050_trigger_probe(indio_dev, irq);
1234 if (ret)
1235 dev_err(dev, "failed to register trigger\n");
1236 }
1237
1238 /* Enable runtime PM */
1239 pm_runtime_get_noresume(dev);
1240 pm_runtime_set_active(dev);
1241 pm_runtime_enable(dev);
1242 /*
1243 * Set autosuspend to two orders of magnitude larger than the
1244 * start-up time. 100ms start-up time means 10000ms autosuspend,
1245 * i.e. 10 seconds.
1246 */
1247 pm_runtime_set_autosuspend_delay(dev, 10000);
1248 pm_runtime_use_autosuspend(dev);
1249 pm_runtime_put(dev);
1250
1251 ret = iio_device_register(indio_dev);
1252 if (ret) {
1253 dev_err(dev, "device register failed\n");
1254 goto err_iio_device_register;
1255 }
1256
1257 return 0;
1258
1259err_iio_device_register:
1260 pm_runtime_get_sync(dev);
1261 pm_runtime_put_noidle(dev);
1262 pm_runtime_disable(dev);
1263 if (irq)
1264 free_irq(mpu3050->irq, mpu3050->trig);
1265 iio_triggered_buffer_cleanup(indio_dev);
1266err_power_down:
1267 mpu3050_power_down(mpu3050);
1268
1269 return ret;
1270}
1271
1272void mpu3050_common_remove(struct device *dev)
1273{
1274 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1275 struct mpu3050 *mpu3050 = iio_priv(indio_dev);
1276
1277 iio_device_unregister(indio_dev);
1278 pm_runtime_get_sync(dev);
1279 pm_runtime_put_noidle(dev);
1280 pm_runtime_disable(dev);
1281 if (mpu3050->irq)
1282 free_irq(mpu3050->irq, mpu3050->trig);
1283 iio_triggered_buffer_cleanup(indio_dev);
1284 mpu3050_power_down(mpu3050);
1285}
1286
1287static int mpu3050_runtime_suspend(struct device *dev)
1288{
1289 return mpu3050_power_down(iio_priv(dev_get_drvdata(dev)));
1290}
1291
1292static int mpu3050_runtime_resume(struct device *dev)
1293{
1294 return mpu3050_power_up(iio_priv(dev_get_drvdata(dev)));
1295}
1296
1297DEFINE_RUNTIME_DEV_PM_OPS(mpu3050_dev_pm_ops, mpu3050_runtime_suspend,
1298 mpu3050_runtime_resume, NULL);
1299MODULE_AUTHOR("Linus Walleij");
1300MODULE_DESCRIPTION("MPU3050 gyroscope driver");
1301MODULE_LICENSE("GPL");