Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2025, Qualcomm Innovation Center, Inc. All rights reserved.
4 *
5 */
6
7#include <linux/device.h>
8#include <linux/interconnect.h>
9#include <linux/interconnect-provider.h>
10#include <linux/module.h>
11#include <linux/of_platform.h>
12#include <linux/property.h>
13#include <dt-bindings/interconnect/qcom,glymur-rpmh.h>
14
15#include "bcm-voter.h"
16#include "icc-rpmh.h"
17
18static struct qcom_icc_node qup0_core_slave = {
19 .name = "qup0_core_slave",
20 .channels = 1,
21 .buswidth = 4,
22};
23
24static struct qcom_icc_node qup1_core_slave = {
25 .name = "qup1_core_slave",
26 .channels = 1,
27 .buswidth = 4,
28};
29
30static struct qcom_icc_node qup2_core_slave = {
31 .name = "qup2_core_slave",
32 .channels = 1,
33 .buswidth = 4,
34};
35
36static struct qcom_icc_node qhs_ahb2phy0 = {
37 .name = "qhs_ahb2phy0",
38 .channels = 1,
39 .buswidth = 4,
40};
41
42static struct qcom_icc_node qhs_ahb2phy1 = {
43 .name = "qhs_ahb2phy1",
44 .channels = 1,
45 .buswidth = 4,
46};
47
48static struct qcom_icc_node qhs_ahb2phy2 = {
49 .name = "qhs_ahb2phy2",
50 .channels = 1,
51 .buswidth = 4,
52};
53
54static struct qcom_icc_node qhs_ahb2phy3 = {
55 .name = "qhs_ahb2phy3",
56 .channels = 1,
57 .buswidth = 4,
58};
59
60static struct qcom_icc_node qhs_av1_enc_cfg = {
61 .name = "qhs_av1_enc_cfg",
62 .channels = 1,
63 .buswidth = 4,
64};
65
66static struct qcom_icc_node qhs_camera_cfg = {
67 .name = "qhs_camera_cfg",
68 .channels = 1,
69 .buswidth = 4,
70};
71
72static struct qcom_icc_node qhs_clk_ctl = {
73 .name = "qhs_clk_ctl",
74 .channels = 1,
75 .buswidth = 4,
76};
77
78static struct qcom_icc_node qhs_crypto0_cfg = {
79 .name = "qhs_crypto0_cfg",
80 .channels = 1,
81 .buswidth = 4,
82};
83
84static struct qcom_icc_node qhs_display_cfg = {
85 .name = "qhs_display_cfg",
86 .channels = 1,
87 .buswidth = 4,
88};
89
90static struct qcom_icc_node qhs_gpuss_cfg = {
91 .name = "qhs_gpuss_cfg",
92 .channels = 1,
93 .buswidth = 8,
94};
95
96static struct qcom_icc_node qhs_imem_cfg = {
97 .name = "qhs_imem_cfg",
98 .channels = 1,
99 .buswidth = 4,
100};
101
102static struct qcom_icc_node qhs_pcie0_cfg = {
103 .name = "qhs_pcie0_cfg",
104 .channels = 1,
105 .buswidth = 4,
106};
107
108static struct qcom_icc_node qhs_pcie1_cfg = {
109 .name = "qhs_pcie1_cfg",
110 .channels = 1,
111 .buswidth = 4,
112};
113
114static struct qcom_icc_node qhs_pcie2_cfg = {
115 .name = "qhs_pcie2_cfg",
116 .channels = 1,
117 .buswidth = 4,
118};
119
120static struct qcom_icc_node qhs_pcie3a_cfg = {
121 .name = "qhs_pcie3a_cfg",
122 .channels = 1,
123 .buswidth = 4,
124};
125
126static struct qcom_icc_node qhs_pcie3b_cfg = {
127 .name = "qhs_pcie3b_cfg",
128 .channels = 1,
129 .buswidth = 4,
130};
131
132static struct qcom_icc_node qhs_pcie4_cfg = {
133 .name = "qhs_pcie4_cfg",
134 .channels = 1,
135 .buswidth = 4,
136};
137
138static struct qcom_icc_node qhs_pcie5_cfg = {
139 .name = "qhs_pcie5_cfg",
140 .channels = 1,
141 .buswidth = 4,
142};
143
144static struct qcom_icc_node qhs_pcie6_cfg = {
145 .name = "qhs_pcie6_cfg",
146 .channels = 1,
147 .buswidth = 4,
148};
149
150static struct qcom_icc_node qhs_pcie_rscc = {
151 .name = "qhs_pcie_rscc",
152 .channels = 1,
153 .buswidth = 4,
154};
155
156static struct qcom_icc_node qhs_pdm = {
157 .name = "qhs_pdm",
158 .channels = 1,
159 .buswidth = 4,
160};
161
162static struct qcom_icc_node qhs_prng = {
163 .name = "qhs_prng",
164 .channels = 1,
165 .buswidth = 4,
166};
167
168static struct qcom_icc_node qhs_qdss_cfg = {
169 .name = "qhs_qdss_cfg",
170 .channels = 1,
171 .buswidth = 4,
172};
173
174static struct qcom_icc_node qhs_qspi = {
175 .name = "qhs_qspi",
176 .channels = 1,
177 .buswidth = 4,
178};
179
180static struct qcom_icc_node qhs_qup0 = {
181 .name = "qhs_qup0",
182 .channels = 1,
183 .buswidth = 4,
184};
185
186static struct qcom_icc_node qhs_qup1 = {
187 .name = "qhs_qup1",
188 .channels = 1,
189 .buswidth = 4,
190};
191
192static struct qcom_icc_node qhs_qup2 = {
193 .name = "qhs_qup2",
194 .channels = 1,
195 .buswidth = 4,
196};
197
198static struct qcom_icc_node qhs_sdc2 = {
199 .name = "qhs_sdc2",
200 .channels = 1,
201 .buswidth = 4,
202};
203
204static struct qcom_icc_node qhs_sdc4 = {
205 .name = "qhs_sdc4",
206 .channels = 1,
207 .buswidth = 4,
208};
209
210static struct qcom_icc_node qhs_smmuv3_cfg = {
211 .name = "qhs_smmuv3_cfg",
212 .channels = 1,
213 .buswidth = 8,
214};
215
216static struct qcom_icc_node qhs_tcsr = {
217 .name = "qhs_tcsr",
218 .channels = 1,
219 .buswidth = 4,
220};
221
222static struct qcom_icc_node qhs_tlmm = {
223 .name = "qhs_tlmm",
224 .channels = 1,
225 .buswidth = 4,
226};
227
228static struct qcom_icc_node qhs_ufs_mem_cfg = {
229 .name = "qhs_ufs_mem_cfg",
230 .channels = 1,
231 .buswidth = 4,
232};
233
234static struct qcom_icc_node qhs_usb2_0_cfg = {
235 .name = "qhs_usb2_0_cfg",
236 .channels = 1,
237 .buswidth = 4,
238};
239
240static struct qcom_icc_node qhs_usb3_0_cfg = {
241 .name = "qhs_usb3_0_cfg",
242 .channels = 1,
243 .buswidth = 4,
244};
245
246static struct qcom_icc_node qhs_usb3_1_cfg = {
247 .name = "qhs_usb3_1_cfg",
248 .channels = 1,
249 .buswidth = 4,
250};
251
252static struct qcom_icc_node qhs_usb3_2_cfg = {
253 .name = "qhs_usb3_2_cfg",
254 .channels = 1,
255 .buswidth = 4,
256};
257
258static struct qcom_icc_node qhs_usb3_mp_cfg = {
259 .name = "qhs_usb3_mp_cfg",
260 .channels = 1,
261 .buswidth = 4,
262};
263
264static struct qcom_icc_node qhs_usb4_0_cfg = {
265 .name = "qhs_usb4_0_cfg",
266 .channels = 1,
267 .buswidth = 4,
268};
269
270static struct qcom_icc_node qhs_usb4_1_cfg = {
271 .name = "qhs_usb4_1_cfg",
272 .channels = 1,
273 .buswidth = 4,
274};
275
276static struct qcom_icc_node qhs_usb4_2_cfg = {
277 .name = "qhs_usb4_2_cfg",
278 .channels = 1,
279 .buswidth = 4,
280};
281
282static struct qcom_icc_node qhs_venus_cfg = {
283 .name = "qhs_venus_cfg",
284 .channels = 1,
285 .buswidth = 4,
286};
287
288static struct qcom_icc_node qss_lpass_qtb_cfg = {
289 .name = "qss_lpass_qtb_cfg",
290 .channels = 1,
291 .buswidth = 4,
292};
293
294static struct qcom_icc_node qss_nsp_qtb_cfg = {
295 .name = "qss_nsp_qtb_cfg",
296 .channels = 1,
297 .buswidth = 4,
298};
299
300static struct qcom_icc_node xs_qdss_stm = {
301 .name = "xs_qdss_stm",
302 .channels = 1,
303 .buswidth = 4,
304};
305
306static struct qcom_icc_node xs_sys_tcu_cfg = {
307 .name = "xs_sys_tcu_cfg",
308 .channels = 1,
309 .buswidth = 8,
310};
311
312static struct qcom_icc_node qhs_aoss = {
313 .name = "qhs_aoss",
314 .channels = 1,
315 .buswidth = 4,
316};
317
318static struct qcom_icc_node qhs_ipc_router = {
319 .name = "qhs_ipc_router",
320 .channels = 1,
321 .buswidth = 4,
322};
323
324static struct qcom_icc_node qhs_soccp = {
325 .name = "qhs_soccp",
326 .channels = 1,
327 .buswidth = 4,
328};
329
330static struct qcom_icc_node qhs_tme_cfg = {
331 .name = "qhs_tme_cfg",
332 .channels = 1,
333 .buswidth = 4,
334};
335
336static struct qcom_icc_node qns_apss = {
337 .name = "qns_apss",
338 .channels = 1,
339 .buswidth = 8,
340};
341
342static struct qcom_icc_node qxs_boot_imem = {
343 .name = "qxs_boot_imem",
344 .channels = 1,
345 .buswidth = 16,
346};
347
348static struct qcom_icc_node qxs_imem = {
349 .name = "qxs_imem",
350 .channels = 1,
351 .buswidth = 8,
352};
353
354static struct qcom_icc_node ebi = {
355 .name = "ebi",
356 .channels = 12,
357 .buswidth = 4,
358};
359
360static struct qcom_icc_node srvc_mnoc = {
361 .name = "srvc_mnoc",
362 .channels = 1,
363 .buswidth = 4,
364};
365
366static struct qcom_icc_node srvc_nsinoc = {
367 .name = "srvc_nsinoc",
368 .channels = 1,
369 .buswidth = 4,
370};
371
372static struct qcom_icc_node srvc_pcie_east_aggre_noc = {
373 .name = "srvc_pcie_east_aggre_noc",
374 .channels = 1,
375 .buswidth = 4,
376};
377
378static struct qcom_icc_node qhs_hscnoc_pcie_east_ms_mpu_cfg = {
379 .name = "qhs_hscnoc_pcie_east_ms_mpu_cfg",
380 .channels = 1,
381 .buswidth = 4,
382};
383
384static struct qcom_icc_node srvc_pcie_east = {
385 .name = "srvc_pcie_east",
386 .channels = 1,
387 .buswidth = 4,
388};
389
390static struct qcom_icc_node xs_pcie_0 = {
391 .name = "xs_pcie_0",
392 .channels = 1,
393 .buswidth = 16,
394};
395
396static struct qcom_icc_node xs_pcie_1 = {
397 .name = "xs_pcie_1",
398 .channels = 1,
399 .buswidth = 32,
400};
401
402static struct qcom_icc_node xs_pcie_5 = {
403 .name = "xs_pcie_5",
404 .channels = 1,
405 .buswidth = 32,
406};
407
408static struct qcom_icc_node srvc_pcie_west_aggre_noc = {
409 .name = "srvc_pcie_west_aggre_noc",
410 .channels = 1,
411 .buswidth = 4,
412};
413
414static struct qcom_icc_node qhs_hscnoc_pcie_west_ms_mpu_cfg = {
415 .name = "qhs_hscnoc_pcie_west_ms_mpu_cfg",
416 .channels = 1,
417 .buswidth = 4,
418};
419
420static struct qcom_icc_node srvc_pcie_west = {
421 .name = "srvc_pcie_west",
422 .channels = 1,
423 .buswidth = 4,
424};
425
426static struct qcom_icc_node xs_pcie_2 = {
427 .name = "xs_pcie_2",
428 .channels = 1,
429 .buswidth = 16,
430};
431
432static struct qcom_icc_node xs_pcie_3a = {
433 .name = "xs_pcie_3a",
434 .channels = 1,
435 .buswidth = 64,
436};
437
438static struct qcom_icc_node xs_pcie_3b = {
439 .name = "xs_pcie_3b",
440 .channels = 1,
441 .buswidth = 32,
442};
443
444static struct qcom_icc_node xs_pcie_4 = {
445 .name = "xs_pcie_4",
446 .channels = 1,
447 .buswidth = 16,
448};
449
450static struct qcom_icc_node xs_pcie_6 = {
451 .name = "xs_pcie_6",
452 .channels = 1,
453 .buswidth = 16,
454};
455
456static struct qcom_icc_node qup0_core_master = {
457 .name = "qup0_core_master",
458 .channels = 1,
459 .buswidth = 4,
460 .num_links = 1,
461 .link_nodes = { &qup0_core_slave },
462};
463
464static struct qcom_icc_node qup1_core_master = {
465 .name = "qup1_core_master",
466 .channels = 1,
467 .buswidth = 4,
468 .num_links = 1,
469 .link_nodes = { &qup1_core_slave },
470};
471
472static struct qcom_icc_node qup2_core_master = {
473 .name = "qup2_core_master",
474 .channels = 1,
475 .buswidth = 4,
476 .num_links = 1,
477 .link_nodes = { &qup2_core_slave },
478};
479
480static struct qcom_icc_node llcc_mc = {
481 .name = "llcc_mc",
482 .channels = 12,
483 .buswidth = 4,
484 .num_links = 1,
485 .link_nodes = { &ebi },
486};
487
488static struct qcom_icc_node qsm_mnoc_cfg = {
489 .name = "qsm_mnoc_cfg",
490 .channels = 1,
491 .buswidth = 4,
492 .num_links = 1,
493 .link_nodes = { &srvc_mnoc },
494};
495
496static struct qcom_icc_node qsm_pcie_east_anoc_cfg = {
497 .name = "qsm_pcie_east_anoc_cfg",
498 .channels = 1,
499 .buswidth = 4,
500 .num_links = 1,
501 .link_nodes = { &srvc_pcie_east_aggre_noc },
502};
503
504static struct qcom_icc_node qnm_hscnoc_pcie_east = {
505 .name = "qnm_hscnoc_pcie_east",
506 .channels = 1,
507 .buswidth = 32,
508 .num_links = 3,
509 .link_nodes = { &xs_pcie_0, &xs_pcie_1,
510 &xs_pcie_5 },
511};
512
513static struct qcom_icc_node qsm_cnoc_pcie_east_slave_cfg = {
514 .name = "qsm_cnoc_pcie_east_slave_cfg",
515 .channels = 1,
516 .buswidth = 4,
517 .num_links = 2,
518 .link_nodes = { &qhs_hscnoc_pcie_east_ms_mpu_cfg,
519 &srvc_pcie_east },
520};
521
522static struct qcom_icc_node qsm_pcie_west_anoc_cfg = {
523 .name = "qsm_pcie_west_anoc_cfg",
524 .channels = 1,
525 .buswidth = 4,
526 .num_links = 1,
527 .link_nodes = { &srvc_pcie_west_aggre_noc },
528};
529
530static struct qcom_icc_node qnm_hscnoc_pcie_west = {
531 .name = "qnm_hscnoc_pcie_west",
532 .channels = 1,
533 .buswidth = 32,
534 .num_links = 5,
535 .link_nodes = { &xs_pcie_2, &xs_pcie_3a,
536 &xs_pcie_3b, &xs_pcie_4,
537 &xs_pcie_6 },
538};
539
540static struct qcom_icc_node qsm_cnoc_pcie_west_slave_cfg = {
541 .name = "qsm_cnoc_pcie_west_slave_cfg",
542 .channels = 1,
543 .buswidth = 4,
544 .num_links = 2,
545 .link_nodes = { &qhs_hscnoc_pcie_west_ms_mpu_cfg,
546 &srvc_pcie_west },
547};
548
549static struct qcom_icc_node qss_cnoc_pcie_slave_east_cfg = {
550 .name = "qss_cnoc_pcie_slave_east_cfg",
551 .channels = 1,
552 .buswidth = 4,
553 .num_links = 1,
554 .link_nodes = { &qsm_cnoc_pcie_east_slave_cfg },
555};
556
557static struct qcom_icc_node qss_cnoc_pcie_slave_west_cfg = {
558 .name = "qss_cnoc_pcie_slave_west_cfg",
559 .channels = 1,
560 .buswidth = 4,
561 .num_links = 1,
562 .link_nodes = { &qsm_cnoc_pcie_west_slave_cfg },
563};
564
565static struct qcom_icc_node qss_mnoc_cfg = {
566 .name = "qss_mnoc_cfg",
567 .channels = 1,
568 .buswidth = 4,
569 .num_links = 1,
570 .link_nodes = { &qsm_mnoc_cfg },
571};
572
573static struct qcom_icc_node qss_pcie_east_anoc_cfg = {
574 .name = "qss_pcie_east_anoc_cfg",
575 .channels = 1,
576 .buswidth = 4,
577 .num_links = 1,
578 .link_nodes = { &qsm_pcie_east_anoc_cfg },
579};
580
581static struct qcom_icc_node qss_pcie_west_anoc_cfg = {
582 .name = "qss_pcie_west_anoc_cfg",
583 .channels = 1,
584 .buswidth = 4,
585 .num_links = 1,
586 .link_nodes = { &qsm_pcie_west_anoc_cfg },
587};
588
589static struct qcom_icc_node qns_llcc = {
590 .name = "qns_llcc",
591 .channels = 12,
592 .buswidth = 16,
593 .num_links = 1,
594 .link_nodes = { &llcc_mc },
595};
596
597static struct qcom_icc_node qns_pcie_east = {
598 .name = "qns_pcie_east",
599 .channels = 1,
600 .buswidth = 32,
601 .num_links = 1,
602 .link_nodes = { &qnm_hscnoc_pcie_east },
603};
604
605static struct qcom_icc_node qns_pcie_west = {
606 .name = "qns_pcie_west",
607 .channels = 1,
608 .buswidth = 32,
609 .num_links = 1,
610 .link_nodes = { &qnm_hscnoc_pcie_west },
611};
612
613static struct qcom_icc_node qsm_cfg = {
614 .name = "qsm_cfg",
615 .channels = 1,
616 .buswidth = 4,
617 .num_links = 51,
618 .link_nodes = { &qhs_ahb2phy0, &qhs_ahb2phy1,
619 &qhs_ahb2phy2, &qhs_ahb2phy3,
620 &qhs_av1_enc_cfg, &qhs_camera_cfg,
621 &qhs_clk_ctl, &qhs_crypto0_cfg,
622 &qhs_display_cfg, &qhs_gpuss_cfg,
623 &qhs_imem_cfg, &qhs_pcie0_cfg,
624 &qhs_pcie1_cfg, &qhs_pcie2_cfg,
625 &qhs_pcie3a_cfg, &qhs_pcie3b_cfg,
626 &qhs_pcie4_cfg, &qhs_pcie5_cfg,
627 &qhs_pcie6_cfg, &qhs_pcie_rscc,
628 &qhs_pdm, &qhs_prng,
629 &qhs_qdss_cfg, &qhs_qspi,
630 &qhs_qup0, &qhs_qup1,
631 &qhs_qup2, &qhs_sdc2,
632 &qhs_sdc4, &qhs_smmuv3_cfg,
633 &qhs_tcsr, &qhs_tlmm,
634 &qhs_ufs_mem_cfg, &qhs_usb2_0_cfg,
635 &qhs_usb3_0_cfg, &qhs_usb3_1_cfg,
636 &qhs_usb3_2_cfg, &qhs_usb3_mp_cfg,
637 &qhs_usb4_0_cfg, &qhs_usb4_1_cfg,
638 &qhs_usb4_2_cfg, &qhs_venus_cfg,
639 &qss_cnoc_pcie_slave_east_cfg, &qss_cnoc_pcie_slave_west_cfg,
640 &qss_lpass_qtb_cfg, &qss_mnoc_cfg,
641 &qss_nsp_qtb_cfg, &qss_pcie_east_anoc_cfg,
642 &qss_pcie_west_anoc_cfg, &xs_qdss_stm,
643 &xs_sys_tcu_cfg },
644};
645
646static struct qcom_icc_node xm_gic = {
647 .name = "xm_gic",
648 .channels = 1,
649 .buswidth = 8,
650 .qosbox = &(const struct qcom_icc_qosbox) {
651 .num_ports = 1,
652 .port_offsets = { 0x33000 },
653 .prio = 0,
654 .urg_fwd = 1,
655 .prio_fwd_disable = 0,
656 },
657 .num_links = 1,
658 .link_nodes = { &qns_llcc },
659};
660
661static struct qcom_icc_node qss_cfg = {
662 .name = "qss_cfg",
663 .channels = 1,
664 .buswidth = 4,
665 .num_links = 1,
666 .link_nodes = { &qsm_cfg },
667};
668
669static struct qcom_icc_node qnm_hscnoc_cnoc = {
670 .name = "qnm_hscnoc_cnoc",
671 .channels = 1,
672 .buswidth = 16,
673 .num_links = 8,
674 .link_nodes = { &qhs_aoss, &qhs_ipc_router,
675 &qhs_soccp, &qhs_tme_cfg,
676 &qns_apss, &qss_cfg,
677 &qxs_boot_imem, &qxs_imem },
678};
679
680static struct qcom_icc_node qns_hscnoc_cnoc = {
681 .name = "qns_hscnoc_cnoc",
682 .channels = 1,
683 .buswidth = 16,
684 .num_links = 1,
685 .link_nodes = { &qnm_hscnoc_cnoc },
686};
687
688static struct qcom_icc_node alm_gpu_tcu = {
689 .name = "alm_gpu_tcu",
690 .channels = 1,
691 .buswidth = 8,
692 .qosbox = &(const struct qcom_icc_qosbox) {
693 .num_ports = 1,
694 .port_offsets = { 0x933000 },
695 .prio = 1,
696 .urg_fwd = 0,
697 .prio_fwd_disable = 1,
698 },
699 .num_links = 2,
700 .link_nodes = { &qns_hscnoc_cnoc, &qns_llcc },
701};
702
703static struct qcom_icc_node alm_pcie_qtc = {
704 .name = "alm_pcie_qtc",
705 .channels = 1,
706 .buswidth = 8,
707 .qosbox = &(const struct qcom_icc_qosbox) {
708 .num_ports = 1,
709 .port_offsets = { 0x51f000 },
710 .prio = 3,
711 .urg_fwd = 0,
712 .prio_fwd_disable = 1,
713 },
714 .num_links = 2,
715 .link_nodes = { &qns_hscnoc_cnoc, &qns_llcc },
716};
717
718static struct qcom_icc_node alm_sys_tcu = {
719 .name = "alm_sys_tcu",
720 .channels = 1,
721 .buswidth = 8,
722 .qosbox = &(const struct qcom_icc_qosbox) {
723 .num_ports = 1,
724 .port_offsets = { 0x51f080 },
725 .prio = 6,
726 .urg_fwd = 0,
727 .prio_fwd_disable = 1,
728 },
729 .num_links = 2,
730 .link_nodes = { &qns_hscnoc_cnoc, &qns_llcc },
731};
732
733static struct qcom_icc_node chm_apps = {
734 .name = "chm_apps",
735 .channels = 6,
736 .buswidth = 32,
737 .num_links = 4,
738 .link_nodes = { &qns_hscnoc_cnoc, &qns_llcc,
739 &qns_pcie_east, &qns_pcie_west },
740};
741
742static struct qcom_icc_node qnm_aggre_noc_east = {
743 .name = "qnm_aggre_noc_east",
744 .channels = 1,
745 .buswidth = 32,
746 .qosbox = &(const struct qcom_icc_qosbox) {
747 .num_ports = 1,
748 .port_offsets = { 0x934000 },
749 .prio = 2,
750 .urg_fwd = 1,
751 .prio_fwd_disable = 1,
752 },
753 .num_links = 4,
754 .link_nodes = { &qns_hscnoc_cnoc, &qns_llcc,
755 &qns_pcie_east, &qns_pcie_west },
756};
757
758static struct qcom_icc_node qnm_gpu = {
759 .name = "qnm_gpu",
760 .channels = 4,
761 .buswidth = 32,
762 .qosbox = &(const struct qcom_icc_qosbox) {
763 .num_ports = 4,
764 .port_offsets = { 0x935000, 0x936000, 0x937000, 0x938000 },
765 .prio = 0,
766 .urg_fwd = 1,
767 .prio_fwd_disable = 1,
768 },
769 .num_links = 4,
770 .link_nodes = { &qns_hscnoc_cnoc, &qns_llcc,
771 &qns_pcie_east, &qns_pcie_west },
772};
773
774static struct qcom_icc_node qnm_lpass = {
775 .name = "qnm_lpass",
776 .channels = 1,
777 .buswidth = 16,
778 .qosbox = &(const struct qcom_icc_qosbox) {
779 .num_ports = 1,
780 .port_offsets = { 0x939000 },
781 .prio = 0,
782 .urg_fwd = 1,
783 .prio_fwd_disable = 0,
784 },
785 .num_links = 4,
786 .link_nodes = { &qns_hscnoc_cnoc, &qns_llcc,
787 &qns_pcie_east, &qns_pcie_west },
788};
789
790static struct qcom_icc_node qnm_mnoc_hf = {
791 .name = "qnm_mnoc_hf",
792 .channels = 2,
793 .buswidth = 32,
794 .qosbox = &(const struct qcom_icc_qosbox) {
795 .num_ports = 2,
796 .port_offsets = { 0x721000, 0x721080 },
797 .prio = 0,
798 .urg_fwd = 1,
799 .prio_fwd_disable = 0,
800 },
801 .num_links = 4,
802 .link_nodes = { &qns_hscnoc_cnoc, &qns_llcc,
803 &qns_pcie_east, &qns_pcie_west },
804};
805
806static struct qcom_icc_node qnm_mnoc_sf = {
807 .name = "qnm_mnoc_sf",
808 .channels = 2,
809 .buswidth = 32,
810 .qosbox = &(const struct qcom_icc_qosbox) {
811 .num_ports = 2,
812 .port_offsets = { 0x721100, 0x721180 },
813 .prio = 0,
814 .urg_fwd = 1,
815 .prio_fwd_disable = 0,
816 },
817 .num_links = 4,
818 .link_nodes = { &qns_hscnoc_cnoc, &qns_llcc,
819 &qns_pcie_east, &qns_pcie_west },
820};
821
822static struct qcom_icc_node qnm_nsp_noc = {
823 .name = "qnm_nsp_noc",
824 .channels = 4,
825 .buswidth = 32,
826 .qosbox = &(const struct qcom_icc_qosbox) {
827 .num_ports = 4,
828 .port_offsets = { 0x816000, 0x816080, 0x816100, 0x816180 },
829 .prio = 0,
830 .urg_fwd = 1,
831 .prio_fwd_disable = 1,
832 },
833 .num_links = 4,
834 .link_nodes = { &qns_hscnoc_cnoc, &qns_llcc,
835 &qns_pcie_east, &qns_pcie_west },
836};
837
838static struct qcom_icc_node qnm_pcie_east = {
839 .name = "qnm_pcie_east",
840 .channels = 1,
841 .buswidth = 32,
842 .qosbox = &(const struct qcom_icc_qosbox) {
843 .num_ports = 1,
844 .port_offsets = { 0x93a000 },
845 .prio = 2,
846 .urg_fwd = 1,
847 .prio_fwd_disable = 1,
848 },
849 .num_links = 2,
850 .link_nodes = { &qns_hscnoc_cnoc, &qns_llcc },
851};
852
853static struct qcom_icc_node qnm_pcie_west = {
854 .name = "qnm_pcie_west",
855 .channels = 1,
856 .buswidth = 64,
857 .qosbox = &(const struct qcom_icc_qosbox) {
858 .num_ports = 1,
859 .port_offsets = { 0x721200 },
860 .prio = 2,
861 .urg_fwd = 1,
862 .prio_fwd_disable = 1,
863 },
864 .num_links = 2,
865 .link_nodes = { &qns_hscnoc_cnoc, &qns_llcc },
866};
867
868static struct qcom_icc_node qnm_snoc_sf = {
869 .name = "qnm_snoc_sf",
870 .channels = 1,
871 .buswidth = 64,
872 .qosbox = &(const struct qcom_icc_qosbox) {
873 .num_ports = 1,
874 .port_offsets = { 0x51f100 },
875 .prio = 2,
876 .urg_fwd = 1,
877 .prio_fwd_disable = 1,
878 },
879 .num_links = 4,
880 .link_nodes = { &qns_hscnoc_cnoc, &qns_llcc,
881 &qns_pcie_east, &qns_pcie_west },
882};
883
884static struct qcom_icc_node qxm_wlan_q6 = {
885 .name = "qxm_wlan_q6",
886 .channels = 1,
887 .buswidth = 8,
888 .num_links = 4,
889 .link_nodes = { &qns_hscnoc_cnoc, &qns_llcc,
890 &qns_pcie_east, &qns_pcie_west },
891};
892
893static struct qcom_icc_node qns_a4noc_hscnoc = {
894 .name = "qns_a4noc_hscnoc",
895 .channels = 1,
896 .buswidth = 32,
897 .num_links = 1,
898 .link_nodes = { &qnm_aggre_noc_east },
899};
900
901static struct qcom_icc_node qns_lpass_ag_noc_gemnoc = {
902 .name = "qns_lpass_ag_noc_gemnoc",
903 .channels = 1,
904 .buswidth = 16,
905 .num_links = 1,
906 .link_nodes = { &qnm_lpass },
907};
908
909static struct qcom_icc_node qns_mem_noc_hf = {
910 .name = "qns_mem_noc_hf",
911 .channels = 2,
912 .buswidth = 32,
913 .num_links = 1,
914 .link_nodes = { &qnm_mnoc_hf },
915};
916
917static struct qcom_icc_node qns_mem_noc_sf = {
918 .name = "qns_mem_noc_sf",
919 .channels = 2,
920 .buswidth = 32,
921 .num_links = 1,
922 .link_nodes = { &qnm_mnoc_sf },
923};
924
925static struct qcom_icc_node qns_nsp_hscnoc = {
926 .name = "qns_nsp_hscnoc",
927 .channels = 4,
928 .buswidth = 32,
929 .num_links = 1,
930 .link_nodes = { &qnm_nsp_noc },
931};
932
933static struct qcom_icc_node qns_pcie_east_mem_noc = {
934 .name = "qns_pcie_east_mem_noc",
935 .channels = 1,
936 .buswidth = 32,
937 .num_links = 1,
938 .link_nodes = { &qnm_pcie_east },
939};
940
941static struct qcom_icc_node qns_pcie_west_mem_noc = {
942 .name = "qns_pcie_west_mem_noc",
943 .channels = 1,
944 .buswidth = 64,
945 .num_links = 1,
946 .link_nodes = { &qnm_pcie_west },
947};
948
949static struct qcom_icc_node qns_gemnoc_sf = {
950 .name = "qns_gemnoc_sf",
951 .channels = 1,
952 .buswidth = 64,
953 .num_links = 1,
954 .link_nodes = { &qnm_snoc_sf },
955};
956
957static struct qcom_icc_node xm_usb3_0 = {
958 .name = "xm_usb3_0",
959 .channels = 1,
960 .buswidth = 8,
961 .qosbox = &(const struct qcom_icc_qosbox) {
962 .num_ports = 1,
963 .port_offsets = { 0xa000 },
964 .prio = 0,
965 .urg_fwd = 0,
966 .prio_fwd_disable = 1,
967 },
968 .num_links = 1,
969 .link_nodes = { &qns_a4noc_hscnoc },
970};
971
972static struct qcom_icc_node xm_usb3_1 = {
973 .name = "xm_usb3_1",
974 .channels = 1,
975 .buswidth = 8,
976 .qosbox = &(const struct qcom_icc_qosbox) {
977 .num_ports = 1,
978 .port_offsets = { 0xb000 },
979 .prio = 0,
980 .urg_fwd = 0,
981 .prio_fwd_disable = 1,
982 },
983 .num_links = 1,
984 .link_nodes = { &qns_a4noc_hscnoc },
985};
986
987static struct qcom_icc_node xm_usb4_0 = {
988 .name = "xm_usb4_0",
989 .channels = 1,
990 .buswidth = 16,
991 .qosbox = &(const struct qcom_icc_qosbox) {
992 .num_ports = 1,
993 .port_offsets = { 0xc000 },
994 .prio = 0,
995 .urg_fwd = 0,
996 .prio_fwd_disable = 1,
997 },
998 .num_links = 1,
999 .link_nodes = { &qns_a4noc_hscnoc },
1000};
1001
1002static struct qcom_icc_node xm_usb4_1 = {
1003 .name = "xm_usb4_1",
1004 .channels = 1,
1005 .buswidth = 32,
1006 .qosbox = &(const struct qcom_icc_qosbox) {
1007 .num_ports = 1,
1008 .port_offsets = { 0xd000 },
1009 .prio = 0,
1010 .urg_fwd = 0,
1011 .prio_fwd_disable = 1,
1012 },
1013 .num_links = 1,
1014 .link_nodes = { &qns_a4noc_hscnoc },
1015};
1016
1017static struct qcom_icc_node qnm_lpiaon_noc = {
1018 .name = "qnm_lpiaon_noc",
1019 .channels = 1,
1020 .buswidth = 16,
1021 .num_links = 1,
1022 .link_nodes = { &qns_lpass_ag_noc_gemnoc },
1023};
1024
1025static struct qcom_icc_node qnm_av1_enc = {
1026 .name = "qnm_av1_enc",
1027 .channels = 1,
1028 .buswidth = 32,
1029 .qosbox = &(const struct qcom_icc_qosbox) {
1030 .num_ports = 1,
1031 .port_offsets = { 0x30000 },
1032 .prio = 4,
1033 .urg_fwd = 1,
1034 .prio_fwd_disable = 1,
1035 },
1036 .num_links = 1,
1037 .link_nodes = { &qns_mem_noc_sf },
1038};
1039
1040static struct qcom_icc_node qnm_camnoc_hf = {
1041 .name = "qnm_camnoc_hf",
1042 .channels = 2,
1043 .buswidth = 32,
1044 .qosbox = &(const struct qcom_icc_qosbox) {
1045 .num_ports = 2,
1046 .port_offsets = { 0x29000, 0x2a000 },
1047 .prio = 0,
1048 .urg_fwd = 1,
1049 .prio_fwd_disable = 0,
1050 },
1051 .num_links = 1,
1052 .link_nodes = { &qns_mem_noc_hf },
1053};
1054
1055static struct qcom_icc_node qnm_camnoc_icp = {
1056 .name = "qnm_camnoc_icp",
1057 .channels = 1,
1058 .buswidth = 8,
1059 .qosbox = &(const struct qcom_icc_qosbox) {
1060 .num_ports = 1,
1061 .port_offsets = { 0x2b000 },
1062 .prio = 4,
1063 .urg_fwd = 1,
1064 .prio_fwd_disable = 1,
1065 },
1066 .num_links = 1,
1067 .link_nodes = { &qns_mem_noc_sf },
1068};
1069
1070static struct qcom_icc_node qnm_camnoc_sf = {
1071 .name = "qnm_camnoc_sf",
1072 .channels = 2,
1073 .buswidth = 32,
1074 .qosbox = &(const struct qcom_icc_qosbox) {
1075 .num_ports = 2,
1076 .port_offsets = { 0x2c000, 0x2d000 },
1077 .prio = 0,
1078 .urg_fwd = 1,
1079 .prio_fwd_disable = 0,
1080 },
1081 .num_links = 1,
1082 .link_nodes = { &qns_mem_noc_sf },
1083};
1084
1085static struct qcom_icc_node qnm_eva = {
1086 .name = "qnm_eva",
1087 .channels = 1,
1088 .buswidth = 32,
1089 .qosbox = &(const struct qcom_icc_qosbox) {
1090 .num_ports = 1,
1091 .port_offsets = { 0x34000 },
1092 .prio = 0,
1093 .urg_fwd = 1,
1094 .prio_fwd_disable = 0,
1095 },
1096 .num_links = 1,
1097 .link_nodes = { &qns_mem_noc_sf },
1098};
1099
1100static struct qcom_icc_node qnm_mdp = {
1101 .name = "qnm_mdp",
1102 .channels = 2,
1103 .buswidth = 32,
1104 .qosbox = &(const struct qcom_icc_qosbox) {
1105 .num_ports = 2,
1106 .port_offsets = { 0x2e000, 0x2f000 },
1107 .prio = 0,
1108 .urg_fwd = 1,
1109 .prio_fwd_disable = 0,
1110 },
1111 .num_links = 1,
1112 .link_nodes = { &qns_mem_noc_hf },
1113};
1114
1115static struct qcom_icc_node qnm_vapss_hcp = {
1116 .name = "qnm_vapss_hcp",
1117 .channels = 1,
1118 .buswidth = 32,
1119 .num_links = 1,
1120 .link_nodes = { &qns_mem_noc_sf },
1121};
1122
1123static struct qcom_icc_node qnm_video = {
1124 .name = "qnm_video",
1125 .channels = 4,
1126 .buswidth = 32,
1127 .qosbox = &(const struct qcom_icc_qosbox) {
1128 .num_ports = 4,
1129 .port_offsets = { 0x31000, 0x32000, 0x37000, 0x38000 },
1130 .prio = 0,
1131 .urg_fwd = 1,
1132 .prio_fwd_disable = 0,
1133 },
1134 .num_links = 1,
1135 .link_nodes = { &qns_mem_noc_sf },
1136};
1137
1138static struct qcom_icc_node qnm_video_cv_cpu = {
1139 .name = "qnm_video_cv_cpu",
1140 .channels = 1,
1141 .buswidth = 8,
1142 .qosbox = &(const struct qcom_icc_qosbox) {
1143 .num_ports = 1,
1144 .port_offsets = { 0x33000 },
1145 .prio = 4,
1146 .urg_fwd = 1,
1147 .prio_fwd_disable = 1,
1148 },
1149 .num_links = 1,
1150 .link_nodes = { &qns_mem_noc_sf },
1151};
1152
1153static struct qcom_icc_node qnm_video_v_cpu = {
1154 .name = "qnm_video_v_cpu",
1155 .channels = 1,
1156 .buswidth = 8,
1157 .qosbox = &(const struct qcom_icc_qosbox) {
1158 .num_ports = 1,
1159 .port_offsets = { 0x35000 },
1160 .prio = 4,
1161 .urg_fwd = 1,
1162 .prio_fwd_disable = 1,
1163 },
1164 .num_links = 1,
1165 .link_nodes = { &qns_mem_noc_sf },
1166};
1167
1168static struct qcom_icc_node qnm_nsp = {
1169 .name = "qnm_nsp",
1170 .channels = 4,
1171 .buswidth = 32,
1172 .num_links = 1,
1173 .link_nodes = { &qns_nsp_hscnoc },
1174};
1175
1176static struct qcom_icc_node xm_pcie_0 = {
1177 .name = "xm_pcie_0",
1178 .channels = 1,
1179 .buswidth = 16,
1180 .qosbox = &(const struct qcom_icc_qosbox) {
1181 .num_ports = 1,
1182 .port_offsets = { 0xb000 },
1183 .prio = 2,
1184 .urg_fwd = 0,
1185 .prio_fwd_disable = 0,
1186 },
1187 .num_links = 1,
1188 .link_nodes = { &qns_pcie_east_mem_noc },
1189};
1190
1191static struct qcom_icc_node xm_pcie_1 = {
1192 .name = "xm_pcie_1",
1193 .channels = 1,
1194 .buswidth = 32,
1195 .qosbox = &(const struct qcom_icc_qosbox) {
1196 .num_ports = 1,
1197 .port_offsets = { 0xc000 },
1198 .prio = 2,
1199 .urg_fwd = 0,
1200 .prio_fwd_disable = 0,
1201 },
1202 .num_links = 1,
1203 .link_nodes = { &qns_pcie_east_mem_noc },
1204};
1205
1206static struct qcom_icc_node xm_pcie_5 = {
1207 .name = "xm_pcie_5",
1208 .channels = 1,
1209 .buswidth = 32,
1210 .qosbox = &(const struct qcom_icc_qosbox) {
1211 .num_ports = 1,
1212 .port_offsets = { 0xd000 },
1213 .prio = 2,
1214 .urg_fwd = 0,
1215 .prio_fwd_disable = 0,
1216 },
1217 .num_links = 1,
1218 .link_nodes = { &qns_pcie_east_mem_noc },
1219};
1220
1221static struct qcom_icc_node xm_pcie_2 = {
1222 .name = "xm_pcie_2",
1223 .channels = 1,
1224 .buswidth = 16,
1225 .qosbox = &(const struct qcom_icc_qosbox) {
1226 .num_ports = 1,
1227 .port_offsets = { 0xd000 },
1228 .prio = 2,
1229 .urg_fwd = 0,
1230 .prio_fwd_disable = 0,
1231 },
1232 .num_links = 1,
1233 .link_nodes = { &qns_pcie_west_mem_noc },
1234};
1235
1236static struct qcom_icc_node xm_pcie_3a = {
1237 .name = "xm_pcie_3a",
1238 .channels = 1,
1239 .buswidth = 64,
1240 .qosbox = &(const struct qcom_icc_qosbox) {
1241 .num_ports = 1,
1242 .port_offsets = { 0xd200 },
1243 .prio = 2,
1244 .urg_fwd = 0,
1245 .prio_fwd_disable = 0,
1246 },
1247 .num_links = 1,
1248 .link_nodes = { &qns_pcie_west_mem_noc },
1249};
1250
1251static struct qcom_icc_node xm_pcie_3b = {
1252 .name = "xm_pcie_3b",
1253 .channels = 1,
1254 .buswidth = 32,
1255 .qosbox = &(const struct qcom_icc_qosbox) {
1256 .num_ports = 1,
1257 .port_offsets = { 0xd400 },
1258 .prio = 2,
1259 .urg_fwd = 0,
1260 .prio_fwd_disable = 0,
1261 },
1262 .num_links = 1,
1263 .link_nodes = { &qns_pcie_west_mem_noc },
1264};
1265
1266static struct qcom_icc_node xm_pcie_4 = {
1267 .name = "xm_pcie_4",
1268 .channels = 1,
1269 .buswidth = 16,
1270 .qosbox = &(const struct qcom_icc_qosbox) {
1271 .num_ports = 1,
1272 .port_offsets = { 0xd600 },
1273 .prio = 2,
1274 .urg_fwd = 0,
1275 .prio_fwd_disable = 0,
1276 },
1277 .num_links = 1,
1278 .link_nodes = { &qns_pcie_west_mem_noc },
1279};
1280
1281static struct qcom_icc_node xm_pcie_6 = {
1282 .name = "xm_pcie_6",
1283 .channels = 1,
1284 .buswidth = 16,
1285 .qosbox = &(const struct qcom_icc_qosbox) {
1286 .num_ports = 1,
1287 .port_offsets = { 0xd800 },
1288 .prio = 2,
1289 .urg_fwd = 0,
1290 .prio_fwd_disable = 0,
1291 },
1292 .num_links = 1,
1293 .link_nodes = { &qns_pcie_west_mem_noc },
1294};
1295
1296static struct qcom_icc_node qnm_aggre1_noc = {
1297 .name = "qnm_aggre1_noc",
1298 .channels = 1,
1299 .buswidth = 16,
1300 .num_links = 1,
1301 .link_nodes = { &qns_gemnoc_sf },
1302};
1303
1304static struct qcom_icc_node qnm_aggre2_noc = {
1305 .name = "qnm_aggre2_noc",
1306 .channels = 1,
1307 .buswidth = 16,
1308 .num_links = 1,
1309 .link_nodes = { &qns_gemnoc_sf },
1310};
1311
1312static struct qcom_icc_node qnm_aggre3_noc = {
1313 .name = "qnm_aggre3_noc",
1314 .channels = 1,
1315 .buswidth = 32,
1316 .num_links = 1,
1317 .link_nodes = { &qns_gemnoc_sf },
1318};
1319
1320static struct qcom_icc_node qnm_nsi_noc = {
1321 .name = "qnm_nsi_noc",
1322 .channels = 1,
1323 .buswidth = 8,
1324 .qosbox = &(const struct qcom_icc_qosbox) {
1325 .num_ports = 1,
1326 .port_offsets = { 0x1c000 },
1327 .prio = 0,
1328 .urg_fwd = 0,
1329 .prio_fwd_disable = 1,
1330 },
1331 .num_links = 1,
1332 .link_nodes = { &qns_gemnoc_sf },
1333};
1334
1335static struct qcom_icc_node qnm_oobmss = {
1336 .name = "qnm_oobmss",
1337 .channels = 1,
1338 .buswidth = 16,
1339 .qosbox = &(const struct qcom_icc_qosbox) {
1340 .num_ports = 1,
1341 .port_offsets = { 0x1b000 },
1342 .prio = 0,
1343 .urg_fwd = 0,
1344 .prio_fwd_disable = 1,
1345 },
1346 .num_links = 1,
1347 .link_nodes = { &qns_gemnoc_sf },
1348};
1349
1350static struct qcom_icc_node qns_a1noc_snoc = {
1351 .name = "qns_a1noc_snoc",
1352 .channels = 1,
1353 .buswidth = 16,
1354 .num_links = 1,
1355 .link_nodes = { &qnm_aggre1_noc },
1356};
1357
1358static struct qcom_icc_node qns_a2noc_snoc = {
1359 .name = "qns_a2noc_snoc",
1360 .channels = 1,
1361 .buswidth = 16,
1362 .num_links = 1,
1363 .link_nodes = { &qnm_aggre2_noc },
1364};
1365
1366static struct qcom_icc_node qns_a3noc_snoc = {
1367 .name = "qns_a3noc_snoc",
1368 .channels = 1,
1369 .buswidth = 32,
1370 .num_links = 1,
1371 .link_nodes = { &qnm_aggre3_noc },
1372};
1373
1374static struct qcom_icc_node qns_lpass_aggnoc = {
1375 .name = "qns_lpass_aggnoc",
1376 .channels = 1,
1377 .buswidth = 16,
1378 .num_links = 1,
1379 .link_nodes = { &qnm_lpiaon_noc },
1380};
1381
1382static struct qcom_icc_node qns_system_noc = {
1383 .name = "qns_system_noc",
1384 .channels = 1,
1385 .buswidth = 8,
1386 .num_links = 1,
1387 .link_nodes = { &qnm_nsi_noc },
1388};
1389
1390static struct qcom_icc_node qns_oobmss_snoc = {
1391 .name = "qns_oobmss_snoc",
1392 .channels = 1,
1393 .buswidth = 16,
1394 .num_links = 1,
1395 .link_nodes = { &qnm_oobmss },
1396};
1397
1398static struct qcom_icc_node qxm_crypto = {
1399 .name = "qxm_crypto",
1400 .channels = 1,
1401 .buswidth = 8,
1402 .qosbox = &(const struct qcom_icc_qosbox) {
1403 .num_ports = 1,
1404 .port_offsets = { 0xb000 },
1405 .prio = 0,
1406 .urg_fwd = 1,
1407 .prio_fwd_disable = 1,
1408 },
1409 .num_links = 1,
1410 .link_nodes = { &qns_a1noc_snoc },
1411};
1412
1413static struct qcom_icc_node qxm_soccp = {
1414 .name = "qxm_soccp",
1415 .channels = 1,
1416 .buswidth = 8,
1417 .qosbox = &(const struct qcom_icc_qosbox) {
1418 .num_ports = 1,
1419 .port_offsets = { 0xe000 },
1420 .prio = 0,
1421 .urg_fwd = 1,
1422 .prio_fwd_disable = 1,
1423 },
1424 .num_links = 1,
1425 .link_nodes = { &qns_a1noc_snoc },
1426};
1427
1428static struct qcom_icc_node xm_qdss_etr_0 = {
1429 .name = "xm_qdss_etr_0",
1430 .channels = 1,
1431 .buswidth = 8,
1432 .qosbox = &(const struct qcom_icc_qosbox) {
1433 .num_ports = 1,
1434 .port_offsets = { 0xc000 },
1435 .prio = 0,
1436 .urg_fwd = 0,
1437 .prio_fwd_disable = 1,
1438 },
1439 .num_links = 1,
1440 .link_nodes = { &qns_a1noc_snoc },
1441};
1442
1443static struct qcom_icc_node xm_qdss_etr_1 = {
1444 .name = "xm_qdss_etr_1",
1445 .channels = 1,
1446 .buswidth = 8,
1447 .qosbox = &(const struct qcom_icc_qosbox) {
1448 .num_ports = 1,
1449 .port_offsets = { 0xd000 },
1450 .prio = 0,
1451 .urg_fwd = 0,
1452 .prio_fwd_disable = 1,
1453 },
1454 .num_links = 1,
1455 .link_nodes = { &qns_a1noc_snoc },
1456};
1457
1458static struct qcom_icc_node xm_ufs_mem = {
1459 .name = "xm_ufs_mem",
1460 .channels = 1,
1461 .buswidth = 16,
1462 .qosbox = &(const struct qcom_icc_qosbox) {
1463 .num_ports = 1,
1464 .port_offsets = { 0xa000 },
1465 .prio = 0,
1466 .urg_fwd = 0,
1467 .prio_fwd_disable = 1,
1468 },
1469 .num_links = 1,
1470 .link_nodes = { &qns_a2noc_snoc },
1471};
1472
1473static struct qcom_icc_node xm_usb3_2 = {
1474 .name = "xm_usb3_2",
1475 .channels = 1,
1476 .buswidth = 8,
1477 .qosbox = &(const struct qcom_icc_qosbox) {
1478 .num_ports = 1,
1479 .port_offsets = { 0x8000 },
1480 .prio = 0,
1481 .urg_fwd = 0,
1482 .prio_fwd_disable = 1,
1483 },
1484 .num_links = 1,
1485 .link_nodes = { &qns_a2noc_snoc },
1486};
1487
1488static struct qcom_icc_node xm_usb4_2 = {
1489 .name = "xm_usb4_2",
1490 .channels = 1,
1491 .buswidth = 16,
1492 .qosbox = &(const struct qcom_icc_qosbox) {
1493 .num_ports = 1,
1494 .port_offsets = { 0x9000 },
1495 .prio = 0,
1496 .urg_fwd = 0,
1497 .prio_fwd_disable = 1,
1498 },
1499 .num_links = 1,
1500 .link_nodes = { &qns_a2noc_snoc },
1501};
1502
1503static struct qcom_icc_node qhm_qspi = {
1504 .name = "qhm_qspi",
1505 .channels = 1,
1506 .buswidth = 4,
1507 .qosbox = &(const struct qcom_icc_qosbox) {
1508 .num_ports = 1,
1509 .port_offsets = { 0x10000 },
1510 .prio = 0,
1511 .urg_fwd = 0,
1512 .prio_fwd_disable = 1,
1513 },
1514 .num_links = 1,
1515 .link_nodes = { &qns_a3noc_snoc },
1516};
1517
1518static struct qcom_icc_node qhm_qup0 = {
1519 .name = "qhm_qup0",
1520 .channels = 1,
1521 .buswidth = 4,
1522 .qosbox = &(const struct qcom_icc_qosbox) {
1523 .num_ports = 1,
1524 .port_offsets = { 0x11000 },
1525 .prio = 0,
1526 .urg_fwd = 0,
1527 .prio_fwd_disable = 1,
1528 },
1529 .num_links = 1,
1530 .link_nodes = { &qns_a3noc_snoc },
1531};
1532
1533static struct qcom_icc_node qhm_qup1 = {
1534 .name = "qhm_qup1",
1535 .channels = 1,
1536 .buswidth = 4,
1537 .qosbox = &(const struct qcom_icc_qosbox) {
1538 .num_ports = 1,
1539 .port_offsets = { 0x12000 },
1540 .prio = 0,
1541 .urg_fwd = 0,
1542 .prio_fwd_disable = 1,
1543 },
1544 .num_links = 1,
1545 .link_nodes = { &qns_a3noc_snoc },
1546};
1547
1548static struct qcom_icc_node qhm_qup2 = {
1549 .name = "qhm_qup2",
1550 .channels = 1,
1551 .buswidth = 4,
1552 .qosbox = &(const struct qcom_icc_qosbox) {
1553 .num_ports = 1,
1554 .port_offsets = { 0x13000 },
1555 .prio = 0,
1556 .urg_fwd = 0,
1557 .prio_fwd_disable = 1,
1558 },
1559 .num_links = 1,
1560 .link_nodes = { &qns_a3noc_snoc },
1561};
1562
1563static struct qcom_icc_node qxm_sp = {
1564 .name = "qxm_sp",
1565 .channels = 1,
1566 .buswidth = 8,
1567 .num_links = 1,
1568 .link_nodes = { &qns_a3noc_snoc },
1569};
1570
1571static struct qcom_icc_node xm_sdc2 = {
1572 .name = "xm_sdc2",
1573 .channels = 1,
1574 .buswidth = 8,
1575 .qosbox = &(const struct qcom_icc_qosbox) {
1576 .num_ports = 1,
1577 .port_offsets = { 0x18000 },
1578 .prio = 0,
1579 .urg_fwd = 0,
1580 .prio_fwd_disable = 1,
1581 },
1582 .num_links = 1,
1583 .link_nodes = { &qns_a3noc_snoc },
1584};
1585
1586static struct qcom_icc_node xm_sdc4 = {
1587 .name = "xm_sdc4",
1588 .channels = 1,
1589 .buswidth = 8,
1590 .qosbox = &(const struct qcom_icc_qosbox) {
1591 .num_ports = 1,
1592 .port_offsets = { 0x14000 },
1593 .prio = 0,
1594 .urg_fwd = 0,
1595 .prio_fwd_disable = 1,
1596 },
1597 .num_links = 1,
1598 .link_nodes = { &qns_a3noc_snoc },
1599};
1600
1601static struct qcom_icc_node xm_usb2_0 = {
1602 .name = "xm_usb2_0",
1603 .channels = 1,
1604 .buswidth = 8,
1605 .qosbox = &(const struct qcom_icc_qosbox) {
1606 .num_ports = 1,
1607 .port_offsets = { 0x15000 },
1608 .prio = 0,
1609 .urg_fwd = 0,
1610 .prio_fwd_disable = 1,
1611 },
1612 .num_links = 1,
1613 .link_nodes = { &qns_a3noc_snoc },
1614};
1615
1616static struct qcom_icc_node xm_usb3_mp = {
1617 .name = "xm_usb3_mp",
1618 .channels = 1,
1619 .buswidth = 16,
1620 .qosbox = &(const struct qcom_icc_qosbox) {
1621 .num_ports = 1,
1622 .port_offsets = { 0x16000 },
1623 .prio = 0,
1624 .urg_fwd = 0,
1625 .prio_fwd_disable = 1,
1626 },
1627 .num_links = 1,
1628 .link_nodes = { &qns_a3noc_snoc },
1629};
1630
1631static struct qcom_icc_node qnm_lpass_lpinoc = {
1632 .name = "qnm_lpass_lpinoc",
1633 .channels = 1,
1634 .buswidth = 16,
1635 .num_links = 1,
1636 .link_nodes = { &qns_lpass_aggnoc },
1637};
1638
1639static struct qcom_icc_node xm_cpucp = {
1640 .name = "xm_cpucp",
1641 .channels = 1,
1642 .buswidth = 8,
1643 .num_links = 2,
1644 .link_nodes = { &qns_system_noc, &srvc_nsinoc },
1645};
1646
1647static struct qcom_icc_node xm_mem_sp = {
1648 .name = "xm_mem_sp",
1649 .channels = 1,
1650 .buswidth = 8,
1651 .num_links = 1,
1652 .link_nodes = { &qns_oobmss_snoc },
1653};
1654
1655static struct qcom_icc_node qns_lpi_aon_noc = {
1656 .name = "qns_lpi_aon_noc",
1657 .channels = 1,
1658 .buswidth = 16,
1659 .num_links = 1,
1660 .link_nodes = { &qnm_lpass_lpinoc },
1661};
1662
1663static struct qcom_icc_node qnm_lpinoc_dsp_qns4m = {
1664 .name = "qnm_lpinoc_dsp_qns4m",
1665 .channels = 1,
1666 .buswidth = 16,
1667 .num_links = 1,
1668 .link_nodes = { &qns_lpi_aon_noc },
1669};
1670
1671static struct qcom_icc_bcm bcm_acv = {
1672 .name = "ACV",
1673 .enable_mask = BIT(3),
1674 .num_nodes = 1,
1675 .nodes = { &ebi },
1676};
1677
1678static struct qcom_icc_bcm bcm_ce0 = {
1679 .name = "CE0",
1680 .num_nodes = 1,
1681 .nodes = { &qxm_crypto },
1682};
1683
1684static struct qcom_icc_bcm bcm_cn0 = {
1685 .name = "CN0",
1686 .keepalive = true,
1687 .enable_mask = BIT(0),
1688 .num_nodes = 60,
1689 .nodes = { &qsm_cfg, &qhs_ahb2phy0,
1690 &qhs_ahb2phy1, &qhs_ahb2phy2,
1691 &qhs_ahb2phy3, &qhs_av1_enc_cfg,
1692 &qhs_camera_cfg, &qhs_clk_ctl,
1693 &qhs_crypto0_cfg, &qhs_gpuss_cfg,
1694 &qhs_imem_cfg, &qhs_pcie0_cfg,
1695 &qhs_pcie1_cfg, &qhs_pcie2_cfg,
1696 &qhs_pcie3a_cfg, &qhs_pcie3b_cfg,
1697 &qhs_pcie4_cfg, &qhs_pcie5_cfg,
1698 &qhs_pcie6_cfg, &qhs_pcie_rscc,
1699 &qhs_pdm, &qhs_prng,
1700 &qhs_qdss_cfg, &qhs_qspi,
1701 &qhs_qup0, &qhs_qup1,
1702 &qhs_qup2, &qhs_sdc2,
1703 &qhs_sdc4, &qhs_smmuv3_cfg,
1704 &qhs_tcsr, &qhs_tlmm,
1705 &qhs_ufs_mem_cfg, &qhs_usb2_0_cfg,
1706 &qhs_usb3_0_cfg, &qhs_usb3_1_cfg,
1707 &qhs_usb3_2_cfg, &qhs_usb3_mp_cfg,
1708 &qhs_usb4_0_cfg, &qhs_usb4_1_cfg,
1709 &qhs_usb4_2_cfg, &qhs_venus_cfg,
1710 &qss_cnoc_pcie_slave_east_cfg, &qss_cnoc_pcie_slave_west_cfg,
1711 &qss_lpass_qtb_cfg, &qss_mnoc_cfg,
1712 &qss_nsp_qtb_cfg, &qss_pcie_east_anoc_cfg,
1713 &qss_pcie_west_anoc_cfg, &xs_qdss_stm,
1714 &xs_sys_tcu_cfg, &qnm_hscnoc_cnoc,
1715 &qhs_aoss, &qhs_ipc_router,
1716 &qhs_soccp, &qhs_tme_cfg,
1717 &qns_apss, &qss_cfg,
1718 &qxs_boot_imem, &qxs_imem },
1719};
1720
1721static struct qcom_icc_bcm bcm_cn1 = {
1722 .name = "CN1",
1723 .num_nodes = 1,
1724 .nodes = { &qhs_display_cfg },
1725};
1726
1727static struct qcom_icc_bcm bcm_co0 = {
1728 .name = "CO0",
1729 .enable_mask = BIT(0),
1730 .num_nodes = 2,
1731 .nodes = { &qnm_nsp, &qns_nsp_hscnoc },
1732};
1733
1734static struct qcom_icc_bcm bcm_lp0 = {
1735 .name = "LP0",
1736 .num_nodes = 2,
1737 .nodes = { &qnm_lpass_lpinoc, &qns_lpass_aggnoc },
1738};
1739
1740static struct qcom_icc_bcm bcm_mc0 = {
1741 .name = "MC0",
1742 .keepalive = true,
1743 .num_nodes = 1,
1744 .nodes = { &ebi },
1745};
1746
1747static struct qcom_icc_bcm bcm_mm0 = {
1748 .name = "MM0",
1749 .num_nodes = 1,
1750 .nodes = { &qns_mem_noc_hf },
1751};
1752
1753static struct qcom_icc_bcm bcm_mm1 = {
1754 .name = "MM1",
1755 .enable_mask = BIT(0),
1756 .num_nodes = 11,
1757 .nodes = { &qnm_av1_enc, &qnm_camnoc_hf,
1758 &qnm_camnoc_icp, &qnm_camnoc_sf,
1759 &qnm_eva, &qnm_mdp,
1760 &qnm_vapss_hcp, &qnm_video,
1761 &qnm_video_cv_cpu, &qnm_video_v_cpu,
1762 &qns_mem_noc_sf },
1763};
1764
1765static struct qcom_icc_bcm bcm_qup0 = {
1766 .name = "QUP0",
1767 .vote_scale = 1,
1768 .keepalive = true,
1769 .num_nodes = 1,
1770 .nodes = { &qup0_core_slave },
1771};
1772
1773static struct qcom_icc_bcm bcm_qup1 = {
1774 .name = "QUP1",
1775 .vote_scale = 1,
1776 .keepalive = true,
1777 .num_nodes = 1,
1778 .nodes = { &qup1_core_slave },
1779};
1780
1781static struct qcom_icc_bcm bcm_qup2 = {
1782 .name = "QUP2",
1783 .vote_scale = 1,
1784 .keepalive = true,
1785 .num_nodes = 1,
1786 .nodes = { &qup2_core_slave },
1787};
1788
1789static struct qcom_icc_bcm bcm_sh0 = {
1790 .name = "SH0",
1791 .keepalive = true,
1792 .num_nodes = 1,
1793 .nodes = { &qns_llcc },
1794};
1795
1796static struct qcom_icc_bcm bcm_sh1 = {
1797 .name = "SH1",
1798 .enable_mask = BIT(0),
1799 .num_nodes = 18,
1800 .nodes = { &alm_gpu_tcu, &alm_pcie_qtc,
1801 &alm_sys_tcu, &chm_apps,
1802 &qnm_aggre_noc_east, &qnm_gpu,
1803 &qnm_lpass, &qnm_mnoc_hf,
1804 &qnm_mnoc_sf, &qnm_nsp_noc,
1805 &qnm_pcie_east, &qnm_pcie_west,
1806 &qnm_snoc_sf, &qxm_wlan_q6,
1807 &xm_gic, &qns_hscnoc_cnoc,
1808 &qns_pcie_east, &qns_pcie_west },
1809};
1810
1811static struct qcom_icc_bcm bcm_sn0 = {
1812 .name = "SN0",
1813 .keepalive = true,
1814 .num_nodes = 1,
1815 .nodes = { &qns_gemnoc_sf },
1816};
1817
1818static struct qcom_icc_bcm bcm_sn1 = {
1819 .name = "SN1",
1820 .enable_mask = BIT(0),
1821 .num_nodes = 1,
1822 .nodes = { &qnm_oobmss },
1823};
1824
1825static struct qcom_icc_bcm bcm_sn2 = {
1826 .name = "SN2",
1827 .num_nodes = 1,
1828 .nodes = { &qnm_aggre1_noc },
1829};
1830
1831static struct qcom_icc_bcm bcm_sn3 = {
1832 .name = "SN3",
1833 .num_nodes = 1,
1834 .nodes = { &qnm_aggre2_noc },
1835};
1836
1837static struct qcom_icc_bcm bcm_sn4 = {
1838 .name = "SN4",
1839 .num_nodes = 1,
1840 .nodes = { &qnm_aggre3_noc },
1841};
1842
1843static struct qcom_icc_bcm bcm_sn5 = {
1844 .name = "SN5",
1845 .num_nodes = 1,
1846 .nodes = { &qns_a4noc_hscnoc },
1847};
1848
1849static struct qcom_icc_bcm bcm_sn6 = {
1850 .name = "SN6",
1851 .num_nodes = 4,
1852 .nodes = { &qns_pcie_east_mem_noc, &qnm_hscnoc_pcie_east,
1853 &qns_pcie_west_mem_noc, &qnm_hscnoc_pcie_west },
1854};
1855
1856static struct qcom_icc_bcm * const aggre1_noc_bcms[] = {
1857 &bcm_ce0,
1858};
1859
1860static struct qcom_icc_node * const aggre1_noc_nodes[] = {
1861 [MASTER_CRYPTO] = &qxm_crypto,
1862 [MASTER_SOCCP_PROC] = &qxm_soccp,
1863 [MASTER_QDSS_ETR] = &xm_qdss_etr_0,
1864 [MASTER_QDSS_ETR_1] = &xm_qdss_etr_1,
1865 [SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc,
1866};
1867
1868static const struct regmap_config glymur_aggre1_noc_regmap_config = {
1869 .reg_bits = 32,
1870 .reg_stride = 4,
1871 .val_bits = 32,
1872 .max_register = 0x14400,
1873 .fast_io = true,
1874};
1875
1876static const struct qcom_icc_desc glymur_aggre1_noc = {
1877 .config = &glymur_aggre1_noc_regmap_config,
1878 .nodes = aggre1_noc_nodes,
1879 .num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
1880 .bcms = aggre1_noc_bcms,
1881 .num_bcms = ARRAY_SIZE(aggre1_noc_bcms),
1882};
1883
1884static struct qcom_icc_node * const aggre2_noc_nodes[] = {
1885 [MASTER_UFS_MEM] = &xm_ufs_mem,
1886 [MASTER_USB3_2] = &xm_usb3_2,
1887 [MASTER_USB4_2] = &xm_usb4_2,
1888 [SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc,
1889};
1890
1891static const struct regmap_config glymur_aggre2_noc_regmap_config = {
1892 .reg_bits = 32,
1893 .reg_stride = 4,
1894 .val_bits = 32,
1895 .max_register = 0x14400,
1896 .fast_io = true,
1897};
1898
1899static const struct qcom_icc_desc glymur_aggre2_noc = {
1900 .config = &glymur_aggre2_noc_regmap_config,
1901 .nodes = aggre2_noc_nodes,
1902 .num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
1903 .qos_requires_clocks = true,
1904};
1905
1906static struct qcom_icc_node * const aggre3_noc_nodes[] = {
1907 [MASTER_QSPI_0] = &qhm_qspi,
1908 [MASTER_QUP_0] = &qhm_qup0,
1909 [MASTER_QUP_1] = &qhm_qup1,
1910 [MASTER_QUP_2] = &qhm_qup2,
1911 [MASTER_SP] = &qxm_sp,
1912 [MASTER_SDCC_2] = &xm_sdc2,
1913 [MASTER_SDCC_4] = &xm_sdc4,
1914 [MASTER_USB2] = &xm_usb2_0,
1915 [MASTER_USB3_MP] = &xm_usb3_mp,
1916 [SLAVE_A3NOC_SNOC] = &qns_a3noc_snoc,
1917};
1918
1919static const struct regmap_config glymur_aggre3_noc_regmap_config = {
1920 .reg_bits = 32,
1921 .reg_stride = 4,
1922 .val_bits = 32,
1923 .max_register = 0x1d400,
1924 .fast_io = true,
1925};
1926
1927static const struct qcom_icc_desc glymur_aggre3_noc = {
1928 .config = &glymur_aggre3_noc_regmap_config,
1929 .nodes = aggre3_noc_nodes,
1930 .num_nodes = ARRAY_SIZE(aggre3_noc_nodes),
1931};
1932
1933static struct qcom_icc_bcm * const aggre4_noc_bcms[] = {
1934 &bcm_sn5,
1935};
1936
1937static struct qcom_icc_node * const aggre4_noc_nodes[] = {
1938 [MASTER_USB3_0] = &xm_usb3_0,
1939 [MASTER_USB3_1] = &xm_usb3_1,
1940 [MASTER_USB4_0] = &xm_usb4_0,
1941 [MASTER_USB4_1] = &xm_usb4_1,
1942 [SLAVE_A4NOC_HSCNOC] = &qns_a4noc_hscnoc,
1943};
1944
1945static const struct regmap_config glymur_aggre4_noc_regmap_config = {
1946 .reg_bits = 32,
1947 .reg_stride = 4,
1948 .val_bits = 32,
1949 .max_register = 0x14400,
1950 .fast_io = true,
1951};
1952
1953static const struct qcom_icc_desc glymur_aggre4_noc = {
1954 .config = &glymur_aggre4_noc_regmap_config,
1955 .nodes = aggre4_noc_nodes,
1956 .num_nodes = ARRAY_SIZE(aggre4_noc_nodes),
1957 .bcms = aggre4_noc_bcms,
1958 .num_bcms = ARRAY_SIZE(aggre4_noc_bcms),
1959 .qos_requires_clocks = true,
1960};
1961
1962static struct qcom_icc_bcm * const clk_virt_bcms[] = {
1963 &bcm_qup0,
1964 &bcm_qup1,
1965 &bcm_qup2,
1966};
1967
1968static struct qcom_icc_node * const clk_virt_nodes[] = {
1969 [MASTER_QUP_CORE_0] = &qup0_core_master,
1970 [MASTER_QUP_CORE_1] = &qup1_core_master,
1971 [MASTER_QUP_CORE_2] = &qup2_core_master,
1972 [SLAVE_QUP_CORE_0] = &qup0_core_slave,
1973 [SLAVE_QUP_CORE_1] = &qup1_core_slave,
1974 [SLAVE_QUP_CORE_2] = &qup2_core_slave,
1975};
1976
1977static const struct qcom_icc_desc glymur_clk_virt = {
1978 .nodes = clk_virt_nodes,
1979 .num_nodes = ARRAY_SIZE(clk_virt_nodes),
1980 .bcms = clk_virt_bcms,
1981 .num_bcms = ARRAY_SIZE(clk_virt_bcms),
1982};
1983
1984static struct qcom_icc_bcm * const cnoc_cfg_bcms[] = {
1985 &bcm_cn0,
1986 &bcm_cn1,
1987};
1988
1989static struct qcom_icc_node *cnoc_cfg_nodes[] = {
1990 [MASTER_CNOC_CFG] = &qsm_cfg,
1991 [SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy0,
1992 [SLAVE_AHB2PHY_NORTH] = &qhs_ahb2phy1,
1993 [SLAVE_AHB2PHY_2] = &qhs_ahb2phy2,
1994 [SLAVE_AHB2PHY_3] = &qhs_ahb2phy3,
1995 [SLAVE_AV1_ENC_CFG] = &qhs_av1_enc_cfg,
1996 [SLAVE_CAMERA_CFG] = &qhs_camera_cfg,
1997 [SLAVE_CLK_CTL] = &qhs_clk_ctl,
1998 [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg,
1999 [SLAVE_DISPLAY_CFG] = &qhs_display_cfg,
2000 [SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg,
2001 [SLAVE_IMEM_CFG] = &qhs_imem_cfg,
2002 [SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg,
2003 [SLAVE_PCIE_1_CFG] = &qhs_pcie1_cfg,
2004 [SLAVE_PCIE_2_CFG] = &qhs_pcie2_cfg,
2005 [SLAVE_PCIE_3A_CFG] = &qhs_pcie3a_cfg,
2006 [SLAVE_PCIE_3B_CFG] = &qhs_pcie3b_cfg,
2007 [SLAVE_PCIE_4_CFG] = &qhs_pcie4_cfg,
2008 [SLAVE_PCIE_5_CFG] = &qhs_pcie5_cfg,
2009 [SLAVE_PCIE_6_CFG] = &qhs_pcie6_cfg,
2010 [SLAVE_PCIE_RSCC] = &qhs_pcie_rscc,
2011 [SLAVE_PDM] = &qhs_pdm,
2012 [SLAVE_PRNG] = &qhs_prng,
2013 [SLAVE_QDSS_CFG] = &qhs_qdss_cfg,
2014 [SLAVE_QSPI_0] = &qhs_qspi,
2015 [SLAVE_QUP_0] = &qhs_qup0,
2016 [SLAVE_QUP_1] = &qhs_qup1,
2017 [SLAVE_QUP_2] = &qhs_qup2,
2018 [SLAVE_SDCC_2] = &qhs_sdc2,
2019 [SLAVE_SDCC_4] = &qhs_sdc4,
2020 [SLAVE_SMMUV3_CFG] = &qhs_smmuv3_cfg,
2021 [SLAVE_TCSR] = &qhs_tcsr,
2022 [SLAVE_TLMM] = &qhs_tlmm,
2023 [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg,
2024 [SLAVE_USB2] = &qhs_usb2_0_cfg,
2025 [SLAVE_USB3_0] = &qhs_usb3_0_cfg,
2026 [SLAVE_USB3_1] = &qhs_usb3_1_cfg,
2027 [SLAVE_USB3_2] = &qhs_usb3_2_cfg,
2028 [SLAVE_USB3_MP] = &qhs_usb3_mp_cfg,
2029 [SLAVE_USB4_0] = &qhs_usb4_0_cfg,
2030 [SLAVE_USB4_1] = &qhs_usb4_1_cfg,
2031 [SLAVE_USB4_2] = &qhs_usb4_2_cfg,
2032 [SLAVE_VENUS_CFG] = &qhs_venus_cfg,
2033 [SLAVE_CNOC_PCIE_SLAVE_EAST_CFG] = &qss_cnoc_pcie_slave_east_cfg,
2034 [SLAVE_CNOC_PCIE_SLAVE_WEST_CFG] = &qss_cnoc_pcie_slave_west_cfg,
2035 [SLAVE_LPASS_QTB_CFG] = &qss_lpass_qtb_cfg,
2036 [SLAVE_CNOC_MNOC_CFG] = &qss_mnoc_cfg,
2037 [SLAVE_NSP_QTB_CFG] = &qss_nsp_qtb_cfg,
2038 [SLAVE_PCIE_EAST_ANOC_CFG] = &qss_pcie_east_anoc_cfg,
2039 [SLAVE_PCIE_WEST_ANOC_CFG] = &qss_pcie_west_anoc_cfg,
2040 [SLAVE_QDSS_STM] = &xs_qdss_stm,
2041 [SLAVE_TCU] = &xs_sys_tcu_cfg,
2042};
2043
2044static const struct regmap_config glymur_cnoc_cfg_regmap_config = {
2045 .reg_bits = 32,
2046 .reg_stride = 4,
2047 .val_bits = 32,
2048 .max_register = 0x6600,
2049 .fast_io = true,
2050};
2051
2052static const struct qcom_icc_desc glymur_cnoc_cfg = {
2053 .config = &glymur_cnoc_cfg_regmap_config,
2054 .nodes = cnoc_cfg_nodes,
2055 .num_nodes = ARRAY_SIZE(cnoc_cfg_nodes),
2056 .bcms = cnoc_cfg_bcms,
2057 .num_bcms = ARRAY_SIZE(cnoc_cfg_bcms),
2058};
2059
2060static struct qcom_icc_bcm * const cnoc_main_bcms[] = {
2061 &bcm_cn0,
2062};
2063
2064static struct qcom_icc_node * const cnoc_main_nodes[] = {
2065 [MASTER_HSCNOC_CNOC] = &qnm_hscnoc_cnoc,
2066 [SLAVE_AOSS] = &qhs_aoss,
2067 [SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router,
2068 [SLAVE_SOCCP] = &qhs_soccp,
2069 [SLAVE_TME_CFG] = &qhs_tme_cfg,
2070 [SLAVE_APPSS] = &qns_apss,
2071 [SLAVE_CNOC_CFG] = &qss_cfg,
2072 [SLAVE_BOOT_IMEM] = &qxs_boot_imem,
2073 [SLAVE_IMEM] = &qxs_imem,
2074};
2075
2076static const struct regmap_config glymur_cnoc_main_regmap_config = {
2077 .reg_bits = 32,
2078 .reg_stride = 4,
2079 .val_bits = 32,
2080 .max_register = 0x17080,
2081 .fast_io = true,
2082};
2083
2084static const struct qcom_icc_desc glymur_cnoc_main = {
2085 .config = &glymur_cnoc_main_regmap_config,
2086 .nodes = cnoc_main_nodes,
2087 .num_nodes = ARRAY_SIZE(cnoc_main_nodes),
2088 .bcms = cnoc_main_bcms,
2089 .num_bcms = ARRAY_SIZE(cnoc_main_bcms),
2090};
2091
2092static struct qcom_icc_bcm * const hscnoc_bcms[] = {
2093 &bcm_sh0,
2094 &bcm_sh1,
2095};
2096
2097static struct qcom_icc_node *hscnoc_nodes[] = {
2098 [MASTER_GPU_TCU] = &alm_gpu_tcu,
2099 [MASTER_PCIE_TCU] = &alm_pcie_qtc,
2100 [MASTER_SYS_TCU] = &alm_sys_tcu,
2101 [MASTER_APPSS_PROC] = &chm_apps,
2102 [MASTER_AGGRE_NOC_EAST] = &qnm_aggre_noc_east,
2103 [MASTER_GFX3D] = &qnm_gpu,
2104 [MASTER_LPASS_GEM_NOC] = &qnm_lpass,
2105 [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf,
2106 [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf,
2107 [MASTER_COMPUTE_NOC] = &qnm_nsp_noc,
2108 [MASTER_PCIE_EAST] = &qnm_pcie_east,
2109 [MASTER_PCIE_WEST] = &qnm_pcie_west,
2110 [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf,
2111 [MASTER_WLAN_Q6] = &qxm_wlan_q6,
2112 [MASTER_GIC] = &xm_gic,
2113 [SLAVE_HSCNOC_CNOC] = &qns_hscnoc_cnoc,
2114 [SLAVE_LLCC] = &qns_llcc,
2115 [SLAVE_PCIE_EAST] = &qns_pcie_east,
2116 [SLAVE_PCIE_WEST] = &qns_pcie_west,
2117};
2118
2119static const struct regmap_config glymur_hscnoc_regmap_config = {
2120 .reg_bits = 32,
2121 .reg_stride = 4,
2122 .val_bits = 32,
2123 .max_register = 0x93a080,
2124 .fast_io = true,
2125};
2126
2127static const struct qcom_icc_desc glymur_hscnoc = {
2128 .config = &glymur_hscnoc_regmap_config,
2129 .nodes = hscnoc_nodes,
2130 .num_nodes = ARRAY_SIZE(hscnoc_nodes),
2131 .bcms = hscnoc_bcms,
2132 .num_bcms = ARRAY_SIZE(hscnoc_bcms),
2133};
2134
2135static struct qcom_icc_node * const lpass_ag_noc_nodes[] = {
2136 [MASTER_LPIAON_NOC] = &qnm_lpiaon_noc,
2137 [SLAVE_LPASS_GEM_NOC] = &qns_lpass_ag_noc_gemnoc,
2138};
2139
2140static const struct regmap_config glymur_lpass_ag_noc_regmap_config = {
2141 .reg_bits = 32,
2142 .reg_stride = 4,
2143 .val_bits = 32,
2144 .max_register = 0xe080,
2145 .fast_io = true,
2146};
2147
2148static const struct qcom_icc_desc glymur_lpass_ag_noc = {
2149 .config = &glymur_lpass_ag_noc_regmap_config,
2150 .nodes = lpass_ag_noc_nodes,
2151 .num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes),
2152};
2153
2154static struct qcom_icc_bcm * const lpass_lpiaon_noc_bcms[] = {
2155 &bcm_lp0,
2156};
2157
2158static struct qcom_icc_node * const lpass_lpiaon_noc_nodes[] = {
2159 [MASTER_LPASS_LPINOC] = &qnm_lpass_lpinoc,
2160 [SLAVE_LPIAON_NOC_LPASS_AG_NOC] = &qns_lpass_aggnoc,
2161};
2162
2163static const struct regmap_config glymur_lpass_lpiaon_noc_regmap_config = {
2164 .reg_bits = 32,
2165 .reg_stride = 4,
2166 .val_bits = 32,
2167 .max_register = 0x19080,
2168 .fast_io = true,
2169};
2170
2171static const struct qcom_icc_desc glymur_lpass_lpiaon_noc = {
2172 .config = &glymur_lpass_lpiaon_noc_regmap_config,
2173 .nodes = lpass_lpiaon_noc_nodes,
2174 .num_nodes = ARRAY_SIZE(lpass_lpiaon_noc_nodes),
2175 .bcms = lpass_lpiaon_noc_bcms,
2176 .num_bcms = ARRAY_SIZE(lpass_lpiaon_noc_bcms),
2177};
2178
2179static struct qcom_icc_node * const lpass_lpicx_noc_nodes[] = {
2180 [MASTER_LPASS_PROC] = &qnm_lpinoc_dsp_qns4m,
2181 [SLAVE_LPICX_NOC_LPIAON_NOC] = &qns_lpi_aon_noc,
2182};
2183
2184static const struct regmap_config glymur_lpass_lpicx_noc_regmap_config = {
2185 .reg_bits = 32,
2186 .reg_stride = 4,
2187 .val_bits = 32,
2188 .max_register = 0x44080,
2189 .fast_io = true,
2190};
2191
2192static const struct qcom_icc_desc glymur_lpass_lpicx_noc = {
2193 .config = &glymur_lpass_lpicx_noc_regmap_config,
2194 .nodes = lpass_lpicx_noc_nodes,
2195 .num_nodes = ARRAY_SIZE(lpass_lpicx_noc_nodes),
2196};
2197
2198static struct qcom_icc_bcm * const mc_virt_bcms[] = {
2199 &bcm_acv,
2200 &bcm_mc0,
2201};
2202
2203static struct qcom_icc_node * const mc_virt_nodes[] = {
2204 [MASTER_LLCC] = &llcc_mc,
2205 [SLAVE_EBI1] = &ebi,
2206};
2207
2208static const struct qcom_icc_desc glymur_mc_virt = {
2209 .nodes = mc_virt_nodes,
2210 .num_nodes = ARRAY_SIZE(mc_virt_nodes),
2211 .bcms = mc_virt_bcms,
2212 .num_bcms = ARRAY_SIZE(mc_virt_bcms),
2213};
2214
2215static struct qcom_icc_bcm * const mmss_noc_bcms[] = {
2216 &bcm_mm0,
2217 &bcm_mm1,
2218};
2219
2220static struct qcom_icc_node * const mmss_noc_nodes[] = {
2221 [MASTER_AV1_ENC] = &qnm_av1_enc,
2222 [MASTER_CAMNOC_HF] = &qnm_camnoc_hf,
2223 [MASTER_CAMNOC_ICP] = &qnm_camnoc_icp,
2224 [MASTER_CAMNOC_SF] = &qnm_camnoc_sf,
2225 [MASTER_EVA] = &qnm_eva,
2226 [MASTER_MDP] = &qnm_mdp,
2227 [MASTER_CDSP_HCP] = &qnm_vapss_hcp,
2228 [MASTER_VIDEO] = &qnm_video,
2229 [MASTER_VIDEO_CV_PROC] = &qnm_video_cv_cpu,
2230 [MASTER_VIDEO_V_PROC] = &qnm_video_v_cpu,
2231 [MASTER_CNOC_MNOC_CFG] = &qsm_mnoc_cfg,
2232 [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf,
2233 [SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf,
2234 [SLAVE_SERVICE_MNOC] = &srvc_mnoc,
2235};
2236
2237static const struct regmap_config glymur_mmss_noc_regmap_config = {
2238 .reg_bits = 32,
2239 .reg_stride = 4,
2240 .val_bits = 32,
2241 .max_register = 0x5b800,
2242 .fast_io = true,
2243};
2244
2245static const struct qcom_icc_desc glymur_mmss_noc = {
2246 .config = &glymur_mmss_noc_regmap_config,
2247 .nodes = mmss_noc_nodes,
2248 .num_nodes = ARRAY_SIZE(mmss_noc_nodes),
2249 .bcms = mmss_noc_bcms,
2250 .num_bcms = ARRAY_SIZE(mmss_noc_bcms),
2251};
2252
2253static struct qcom_icc_node * const nsinoc_nodes[] = {
2254 [MASTER_CPUCP] = &xm_cpucp,
2255 [SLAVE_NSINOC_SYSTEM_NOC] = &qns_system_noc,
2256 [SLAVE_SERVICE_NSINOC] = &srvc_nsinoc,
2257};
2258
2259static const struct regmap_config glymur_nsinoc_regmap_config = {
2260 .reg_bits = 32,
2261 .reg_stride = 4,
2262 .val_bits = 32,
2263 .max_register = 0x14080,
2264 .fast_io = true,
2265};
2266
2267static const struct qcom_icc_desc glymur_nsinoc = {
2268 .config = &glymur_nsinoc_regmap_config,
2269 .nodes = nsinoc_nodes,
2270 .num_nodes = ARRAY_SIZE(nsinoc_nodes),
2271};
2272
2273static struct qcom_icc_bcm * const nsp_noc_bcms[] = {
2274 &bcm_co0,
2275};
2276
2277static struct qcom_icc_node * const nsp_noc_nodes[] = {
2278 [MASTER_CDSP_PROC] = &qnm_nsp,
2279 [SLAVE_NSP0_HSC_NOC] = &qns_nsp_hscnoc,
2280};
2281
2282static const struct regmap_config glymur_nsp_noc_regmap_config = {
2283 .reg_bits = 32,
2284 .reg_stride = 4,
2285 .val_bits = 32,
2286 .max_register = 0x21280,
2287 .fast_io = true,
2288};
2289
2290static const struct qcom_icc_desc glymur_nsp_noc = {
2291 .config = &glymur_nsp_noc_regmap_config,
2292 .nodes = nsp_noc_nodes,
2293 .num_nodes = ARRAY_SIZE(nsp_noc_nodes),
2294 .bcms = nsp_noc_bcms,
2295 .num_bcms = ARRAY_SIZE(nsp_noc_bcms),
2296};
2297
2298static struct qcom_icc_node * const oobm_ss_noc_nodes[] = {
2299 [MASTER_OOBMSS_SP_PROC] = &xm_mem_sp,
2300 [SLAVE_OOBMSS_SNOC] = &qns_oobmss_snoc,
2301};
2302
2303static const struct regmap_config glymur_oobm_ss_noc_regmap_config = {
2304 .reg_bits = 32,
2305 .reg_stride = 4,
2306 .val_bits = 32,
2307 .max_register = 0x1e080,
2308 .fast_io = true,
2309};
2310
2311static const struct qcom_icc_desc glymur_oobm_ss_noc = {
2312 .config = &glymur_oobm_ss_noc_regmap_config,
2313 .nodes = oobm_ss_noc_nodes,
2314 .num_nodes = ARRAY_SIZE(oobm_ss_noc_nodes),
2315};
2316
2317static struct qcom_icc_bcm * const pcie_east_anoc_bcms[] = {
2318 &bcm_sn6,
2319};
2320
2321static struct qcom_icc_node * const pcie_east_anoc_nodes[] = {
2322 [MASTER_PCIE_EAST_ANOC_CFG] = &qsm_pcie_east_anoc_cfg,
2323 [MASTER_PCIE_0] = &xm_pcie_0,
2324 [MASTER_PCIE_1] = &xm_pcie_1,
2325 [MASTER_PCIE_5] = &xm_pcie_5,
2326 [SLAVE_PCIE_EAST_MEM_NOC] = &qns_pcie_east_mem_noc,
2327 [SLAVE_SERVICE_PCIE_EAST_AGGRE_NOC] = &srvc_pcie_east_aggre_noc,
2328};
2329
2330static const struct regmap_config glymur_pcie_east_anoc_regmap_config = {
2331 .reg_bits = 32,
2332 .reg_stride = 4,
2333 .val_bits = 32,
2334 .max_register = 0xf300,
2335 .fast_io = true,
2336};
2337
2338static const struct qcom_icc_desc glymur_pcie_east_anoc = {
2339 .config = &glymur_pcie_east_anoc_regmap_config,
2340 .nodes = pcie_east_anoc_nodes,
2341 .num_nodes = ARRAY_SIZE(pcie_east_anoc_nodes),
2342 .bcms = pcie_east_anoc_bcms,
2343 .num_bcms = ARRAY_SIZE(pcie_east_anoc_bcms),
2344 .qos_requires_clocks = true,
2345};
2346
2347static struct qcom_icc_bcm * const pcie_east_slv_noc_bcms[] = {
2348 &bcm_sn6,
2349};
2350
2351static struct qcom_icc_node * const pcie_east_slv_noc_nodes[] = {
2352 [MASTER_HSCNOC_PCIE_EAST] = &qnm_hscnoc_pcie_east,
2353 [MASTER_CNOC_PCIE_EAST_SLAVE_CFG] = &qsm_cnoc_pcie_east_slave_cfg,
2354 [SLAVE_HSCNOC_PCIE_EAST_MS_MPU_CFG] = &qhs_hscnoc_pcie_east_ms_mpu_cfg,
2355 [SLAVE_SERVICE_PCIE_EAST] = &srvc_pcie_east,
2356 [SLAVE_PCIE_0] = &xs_pcie_0,
2357 [SLAVE_PCIE_1] = &xs_pcie_1,
2358 [SLAVE_PCIE_5] = &xs_pcie_5,
2359};
2360
2361static const struct regmap_config glymur_pcie_east_slv_noc_regmap_config = {
2362 .reg_bits = 32,
2363 .reg_stride = 4,
2364 .val_bits = 32,
2365 .max_register = 0xe080,
2366 .fast_io = true,
2367};
2368
2369static const struct qcom_icc_desc glymur_pcie_east_slv_noc = {
2370 .config = &glymur_pcie_east_slv_noc_regmap_config,
2371 .nodes = pcie_east_slv_noc_nodes,
2372 .num_nodes = ARRAY_SIZE(pcie_east_slv_noc_nodes),
2373 .bcms = pcie_east_slv_noc_bcms,
2374 .num_bcms = ARRAY_SIZE(pcie_east_slv_noc_bcms),
2375};
2376
2377static struct qcom_icc_bcm * const pcie_west_anoc_bcms[] = {
2378 &bcm_sn6,
2379};
2380
2381static struct qcom_icc_node *pcie_west_anoc_nodes[] = {
2382 [MASTER_PCIE_WEST_ANOC_CFG] = &qsm_pcie_west_anoc_cfg,
2383 [MASTER_PCIE_2] = &xm_pcie_2,
2384 [MASTER_PCIE_3A] = &xm_pcie_3a,
2385 [MASTER_PCIE_3B] = &xm_pcie_3b,
2386 [MASTER_PCIE_4] = &xm_pcie_4,
2387 [MASTER_PCIE_6] = &xm_pcie_6,
2388 [SLAVE_PCIE_WEST_MEM_NOC] = &qns_pcie_west_mem_noc,
2389 [SLAVE_SERVICE_PCIE_WEST_AGGRE_NOC] = &srvc_pcie_west_aggre_noc,
2390};
2391
2392static const struct regmap_config glymur_pcie_west_anoc_regmap_config = {
2393 .reg_bits = 32,
2394 .reg_stride = 4,
2395 .val_bits = 32,
2396 .max_register = 0xf580,
2397 .fast_io = true,
2398};
2399
2400static const struct qcom_icc_desc glymur_pcie_west_anoc = {
2401 .config = &glymur_pcie_west_anoc_regmap_config,
2402 .nodes = pcie_west_anoc_nodes,
2403 .num_nodes = ARRAY_SIZE(pcie_west_anoc_nodes),
2404 .bcms = pcie_west_anoc_bcms,
2405 .num_bcms = ARRAY_SIZE(pcie_west_anoc_bcms),
2406 .qos_requires_clocks = true,
2407};
2408
2409static struct qcom_icc_bcm * const pcie_west_slv_noc_bcms[] = {
2410 &bcm_sn6,
2411};
2412
2413static struct qcom_icc_node *pcie_west_slv_noc_nodes[] = {
2414 [MASTER_HSCNOC_PCIE_WEST] = &qnm_hscnoc_pcie_west,
2415 [MASTER_CNOC_PCIE_WEST_SLAVE_CFG] = &qsm_cnoc_pcie_west_slave_cfg,
2416 [SLAVE_HSCNOC_PCIE_WEST_MS_MPU_CFG] = &qhs_hscnoc_pcie_west_ms_mpu_cfg,
2417 [SLAVE_SERVICE_PCIE_WEST] = &srvc_pcie_west,
2418 [SLAVE_PCIE_2] = &xs_pcie_2,
2419 [SLAVE_PCIE_3A] = &xs_pcie_3a,
2420 [SLAVE_PCIE_3B] = &xs_pcie_3b,
2421 [SLAVE_PCIE_4] = &xs_pcie_4,
2422 [SLAVE_PCIE_6] = &xs_pcie_6,
2423};
2424
2425static const struct regmap_config glymur_pcie_west_slv_noc_regmap_config = {
2426 .reg_bits = 32,
2427 .reg_stride = 4,
2428 .val_bits = 32,
2429 .max_register = 0xf180,
2430 .fast_io = true,
2431};
2432
2433static const struct qcom_icc_desc glymur_pcie_west_slv_noc = {
2434 .config = &glymur_pcie_west_slv_noc_regmap_config,
2435 .nodes = pcie_west_slv_noc_nodes,
2436 .num_nodes = ARRAY_SIZE(pcie_west_slv_noc_nodes),
2437 .bcms = pcie_west_slv_noc_bcms,
2438 .num_bcms = ARRAY_SIZE(pcie_west_slv_noc_bcms),
2439};
2440
2441static struct qcom_icc_bcm * const system_noc_bcms[] = {
2442 &bcm_sn0,
2443 &bcm_sn1,
2444 &bcm_sn2,
2445 &bcm_sn3,
2446 &bcm_sn4,
2447};
2448
2449static struct qcom_icc_node * const system_noc_nodes[] = {
2450 [MASTER_A1NOC_SNOC] = &qnm_aggre1_noc,
2451 [MASTER_A2NOC_SNOC] = &qnm_aggre2_noc,
2452 [MASTER_A3NOC_SNOC] = &qnm_aggre3_noc,
2453 [MASTER_NSINOC_SNOC] = &qnm_nsi_noc,
2454 [MASTER_OOBMSS] = &qnm_oobmss,
2455 [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf,
2456};
2457
2458static const struct regmap_config glymur_system_noc_regmap_config = {
2459 .reg_bits = 32,
2460 .reg_stride = 4,
2461 .val_bits = 32,
2462 .max_register = 0x1c080,
2463 .fast_io = true,
2464};
2465
2466static const struct qcom_icc_desc glymur_system_noc = {
2467 .config = &glymur_system_noc_regmap_config,
2468 .nodes = system_noc_nodes,
2469 .num_nodes = ARRAY_SIZE(system_noc_nodes),
2470 .bcms = system_noc_bcms,
2471 .num_bcms = ARRAY_SIZE(system_noc_bcms),
2472};
2473
2474static int glymur_qnoc_probe(struct platform_device *pdev)
2475{
2476 if (device_is_compatible(&pdev->dev, "qcom,mahua-mc-virt")) {
2477 llcc_mc.channels = 8;
2478 ebi.channels = 8;
2479 } else if (device_is_compatible(&pdev->dev, "qcom,mahua-hscnoc")) {
2480 qns_llcc.channels = 8;
2481 chm_apps.channels = 4;
2482 qnm_pcie_west.buswidth = 32;
2483 hscnoc_nodes[MASTER_WLAN_Q6] = NULL;
2484 } else if (device_is_compatible(&pdev->dev, "qcom,mahua-pcie-west-anoc")) {
2485 qns_pcie_west_mem_noc.buswidth = 32;
2486 pcie_west_anoc_nodes[MASTER_PCIE_3A] = NULL;
2487 } else if (device_is_compatible(&pdev->dev, "qcom,mahua-cnoc-cfg")) {
2488 cnoc_cfg_nodes[SLAVE_PCIE_3A_CFG] = NULL;
2489 } else if (device_is_compatible(&pdev->dev, "qcom,mahua-pcie-west-slv-noc")) {
2490 pcie_west_slv_noc_nodes[SLAVE_PCIE_3A] = NULL;
2491 }
2492
2493 return qcom_icc_rpmh_probe(pdev);
2494}
2495
2496static const struct of_device_id qnoc_of_match[] = {
2497 { .compatible = "qcom,glymur-aggre1-noc", .data = &glymur_aggre1_noc},
2498 { .compatible = "qcom,glymur-aggre2-noc", .data = &glymur_aggre2_noc},
2499 { .compatible = "qcom,glymur-aggre3-noc", .data = &glymur_aggre3_noc},
2500 { .compatible = "qcom,glymur-aggre4-noc", .data = &glymur_aggre4_noc},
2501 { .compatible = "qcom,glymur-clk-virt", .data = &glymur_clk_virt},
2502 { .compatible = "qcom,glymur-cnoc-cfg", .data = &glymur_cnoc_cfg},
2503 { .compatible = "qcom,mahua-cnoc-cfg", .data = &glymur_cnoc_cfg},
2504 { .compatible = "qcom,glymur-cnoc-main", .data = &glymur_cnoc_main},
2505 { .compatible = "qcom,glymur-hscnoc", .data = &glymur_hscnoc},
2506 { .compatible = "qcom,mahua-hscnoc", .data = &glymur_hscnoc},
2507 { .compatible = "qcom,glymur-lpass-ag-noc", .data = &glymur_lpass_ag_noc},
2508 { .compatible = "qcom,glymur-lpass-lpiaon-noc", .data = &glymur_lpass_lpiaon_noc},
2509 { .compatible = "qcom,glymur-lpass-lpicx-noc", .data = &glymur_lpass_lpicx_noc},
2510 { .compatible = "qcom,glymur-mc-virt", .data = &glymur_mc_virt},
2511 { .compatible = "qcom,mahua-mc-virt", .data = &glymur_mc_virt},
2512 { .compatible = "qcom,glymur-mmss-noc", .data = &glymur_mmss_noc},
2513 { .compatible = "qcom,glymur-nsinoc", .data = &glymur_nsinoc},
2514 { .compatible = "qcom,glymur-nsp-noc", .data = &glymur_nsp_noc},
2515 { .compatible = "qcom,glymur-oobm-ss-noc", .data = &glymur_oobm_ss_noc},
2516 { .compatible = "qcom,glymur-pcie-east-anoc", .data = &glymur_pcie_east_anoc},
2517 { .compatible = "qcom,glymur-pcie-east-slv-noc", .data = &glymur_pcie_east_slv_noc},
2518 { .compatible = "qcom,glymur-pcie-west-anoc", .data = &glymur_pcie_west_anoc},
2519 { .compatible = "qcom,mahua-pcie-west-anoc", .data = &glymur_pcie_west_anoc},
2520 { .compatible = "qcom,glymur-pcie-west-slv-noc", .data = &glymur_pcie_west_slv_noc},
2521 { .compatible = "qcom,mahua-pcie-west-slv-noc", .data = &glymur_pcie_west_slv_noc},
2522 { .compatible = "qcom,glymur-system-noc", .data = &glymur_system_noc},
2523 { }
2524};
2525MODULE_DEVICE_TABLE(of, qnoc_of_match);
2526
2527static struct platform_driver qnoc_driver = {
2528 .probe = glymur_qnoc_probe,
2529 .remove = qcom_icc_rpmh_remove,
2530 .driver = {
2531 .name = "qnoc-glymur",
2532 .of_match_table = qnoc_of_match,
2533 .sync_state = icc_sync_state,
2534 },
2535};
2536
2537static int __init qnoc_driver_init(void)
2538{
2539 return platform_driver_register(&qnoc_driver);
2540}
2541core_initcall(qnoc_driver_init);
2542
2543static void __exit qnoc_driver_exit(void)
2544{
2545 platform_driver_unregister(&qnoc_driver);
2546}
2547module_exit(qnoc_driver_exit);
2548
2549MODULE_DESCRIPTION("Glymur NoC driver");
2550MODULE_LICENSE("GPL");