Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
4 *
5 */
6
7#include <linux/device.h>
8#include <linux/interconnect.h>
9#include <linux/interconnect-provider.h>
10#include <linux/module.h>
11#include <linux/of_platform.h>
12#include <dt-bindings/interconnect/qcom,qcs615-rpmh.h>
13
14#include "bcm-voter.h"
15#include "icc-rpmh.h"
16
17static struct qcom_icc_node qhm_a1noc_cfg;
18static struct qcom_icc_node qhm_qdss_bam;
19static struct qcom_icc_node qhm_qspi;
20static struct qcom_icc_node qhm_qup0;
21static struct qcom_icc_node qhm_qup1;
22static struct qcom_icc_node qnm_cnoc;
23static struct qcom_icc_node qxm_crypto;
24static struct qcom_icc_node qxm_ipa;
25static struct qcom_icc_node xm_emac_avb;
26static struct qcom_icc_node xm_pcie;
27static struct qcom_icc_node xm_qdss_etr;
28static struct qcom_icc_node xm_sdc1;
29static struct qcom_icc_node xm_sdc2;
30static struct qcom_icc_node xm_ufs_mem;
31static struct qcom_icc_node xm_usb2;
32static struct qcom_icc_node xm_usb3_0;
33static struct qcom_icc_node qxm_camnoc_hf0_uncomp;
34static struct qcom_icc_node qxm_camnoc_hf1_uncomp;
35static struct qcom_icc_node qxm_camnoc_sf_uncomp;
36static struct qcom_icc_node qhm_spdm;
37static struct qcom_icc_node qnm_snoc;
38static struct qcom_icc_node xm_qdss_dap;
39static struct qcom_icc_node qhm_cnoc;
40static struct qcom_icc_node acm_apps;
41static struct qcom_icc_node acm_gpu_tcu;
42static struct qcom_icc_node acm_sys_tcu;
43static struct qcom_icc_node qhm_gemnoc_cfg;
44static struct qcom_icc_node qnm_gpu;
45static struct qcom_icc_node qnm_mnoc_hf;
46static struct qcom_icc_node qnm_mnoc_sf;
47static struct qcom_icc_node qnm_snoc_gc;
48static struct qcom_icc_node qnm_snoc_sf;
49static struct qcom_icc_node llcc_mc;
50static struct qcom_icc_node qhm_mnoc_cfg;
51static struct qcom_icc_node qxm_camnoc_hf0;
52static struct qcom_icc_node qxm_camnoc_hf1;
53static struct qcom_icc_node qxm_camnoc_sf;
54static struct qcom_icc_node qxm_mdp0;
55static struct qcom_icc_node qxm_rot;
56static struct qcom_icc_node qxm_venus0;
57static struct qcom_icc_node qxm_venus_arm9;
58static struct qcom_icc_node qhm_snoc_cfg;
59static struct qcom_icc_node qnm_aggre1_noc;
60static struct qcom_icc_node qnm_gemnoc;
61static struct qcom_icc_node qnm_gemnoc_pcie;
62static struct qcom_icc_node qnm_lpass_anoc;
63static struct qcom_icc_node qnm_pcie_anoc;
64static struct qcom_icc_node qxm_pimem;
65static struct qcom_icc_node xm_gic;
66static struct qcom_icc_node qns_a1noc_snoc;
67static struct qcom_icc_node qns_lpass_snoc;
68static struct qcom_icc_node qns_pcie_snoc;
69static struct qcom_icc_node srvc_aggre2_noc;
70static struct qcom_icc_node qns_camnoc_uncomp;
71static struct qcom_icc_node qhs_a1_noc_cfg;
72static struct qcom_icc_node qhs_ahb2phy_east;
73static struct qcom_icc_node qhs_ahb2phy_west;
74static struct qcom_icc_node qhs_aop;
75static struct qcom_icc_node qhs_aoss;
76static struct qcom_icc_node qhs_camera_cfg;
77static struct qcom_icc_node qhs_clk_ctl;
78static struct qcom_icc_node qhs_cpr_cx;
79static struct qcom_icc_node qhs_cpr_mx;
80static struct qcom_icc_node qhs_crypto0_cfg;
81static struct qcom_icc_node qhs_ddrss_cfg;
82static struct qcom_icc_node qhs_display_cfg;
83static struct qcom_icc_node qhs_emac_avb_cfg;
84static struct qcom_icc_node qhs_glm;
85static struct qcom_icc_node qhs_gpuss_cfg;
86static struct qcom_icc_node qhs_imem_cfg;
87static struct qcom_icc_node qhs_ipa;
88static struct qcom_icc_node qhs_mnoc_cfg;
89static struct qcom_icc_node qhs_pcie_config;
90static struct qcom_icc_node qhs_pimem_cfg;
91static struct qcom_icc_node qhs_prng;
92static struct qcom_icc_node qhs_qdss_cfg;
93static struct qcom_icc_node qhs_qspi;
94static struct qcom_icc_node qhs_qup0;
95static struct qcom_icc_node qhs_qup1;
96static struct qcom_icc_node qhs_sdc1;
97static struct qcom_icc_node qhs_sdc2;
98static struct qcom_icc_node qhs_snoc_cfg;
99static struct qcom_icc_node qhs_spdm;
100static struct qcom_icc_node qhs_tcsr;
101static struct qcom_icc_node qhs_tlmm_east;
102static struct qcom_icc_node qhs_tlmm_south;
103static struct qcom_icc_node qhs_tlmm_west;
104static struct qcom_icc_node qhs_ufs_mem_cfg;
105static struct qcom_icc_node qhs_usb2;
106static struct qcom_icc_node qhs_usb3;
107static struct qcom_icc_node qhs_venus_cfg;
108static struct qcom_icc_node qhs_vsense_ctrl_cfg;
109static struct qcom_icc_node qns_cnoc_a2noc;
110static struct qcom_icc_node srvc_cnoc;
111static struct qcom_icc_node qhs_dc_noc_gemnoc;
112static struct qcom_icc_node qhs_llcc;
113static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg;
114static struct qcom_icc_node qns_gem_noc_snoc;
115static struct qcom_icc_node qns_llcc;
116static struct qcom_icc_node qns_sys_pcie;
117static struct qcom_icc_node srvc_gemnoc;
118static struct qcom_icc_node ebi;
119static struct qcom_icc_node qns2_mem_noc;
120static struct qcom_icc_node qns_mem_noc_hf;
121static struct qcom_icc_node srvc_mnoc;
122static struct qcom_icc_node qhs_apss;
123static struct qcom_icc_node qns_cnoc;
124static struct qcom_icc_node qns_gemnoc_sf;
125static struct qcom_icc_node qns_memnoc_gc;
126static struct qcom_icc_node qxs_imem;
127static struct qcom_icc_node qxs_pimem;
128static struct qcom_icc_node srvc_snoc;
129static struct qcom_icc_node xs_pcie;
130static struct qcom_icc_node xs_qdss_stm;
131static struct qcom_icc_node xs_sys_tcu_cfg;
132
133static struct qcom_icc_node qhm_a1noc_cfg = {
134 .name = "qhm_a1noc_cfg",
135 .channels = 1,
136 .buswidth = 4,
137 .num_links = 1,
138 .link_nodes = { &srvc_aggre2_noc },
139};
140
141static struct qcom_icc_node qhm_qdss_bam = {
142 .name = "qhm_qdss_bam",
143 .channels = 1,
144 .buswidth = 4,
145 .qosbox = &(const struct qcom_icc_qosbox) {
146 .num_ports = 1,
147 .port_offsets = { 0xc000 },
148 .prio = 2,
149 .urg_fwd = 0,
150 },
151 .num_links = 1,
152 .link_nodes = { &qns_a1noc_snoc },
153};
154
155static struct qcom_icc_node qhm_qspi = {
156 .name = "qhm_qspi",
157 .channels = 1,
158 .buswidth = 4,
159 .qosbox = &(const struct qcom_icc_qosbox) {
160 .num_ports = 1,
161 .port_offsets = { 0x17000 },
162 .prio = 2,
163 .urg_fwd = 0,
164 },
165 .num_links = 1,
166 .link_nodes = { &qns_a1noc_snoc },
167};
168
169static struct qcom_icc_node qhm_qup0 = {
170 .name = "qhm_qup0",
171 .channels = 1,
172 .buswidth = 4,
173 .qosbox = &(const struct qcom_icc_qosbox) {
174 .num_ports = 1,
175 .port_offsets = { 0x10000 },
176 .prio = 2,
177 .urg_fwd = 0,
178 },
179 .num_links = 1,
180 .link_nodes = { &qns_a1noc_snoc },
181};
182
183static struct qcom_icc_node qhm_qup1 = {
184 .name = "qhm_qup1",
185 .channels = 1,
186 .buswidth = 4,
187 .qosbox = &(const struct qcom_icc_qosbox) {
188 .num_ports = 1,
189 .port_offsets = { 0x12000 },
190 .prio = 2,
191 .urg_fwd = 0,
192 },
193 .num_links = 1,
194 .link_nodes = { &qns_a1noc_snoc },
195};
196
197static struct qcom_icc_node qnm_cnoc = {
198 .name = "qnm_cnoc",
199 .channels = 1,
200 .buswidth = 8,
201 .qosbox = &(const struct qcom_icc_qosbox) {
202 .num_ports = 1,
203 .port_offsets = { 0x4000 },
204 .prio = 2,
205 .urg_fwd = 1,
206 },
207 .num_links = 1,
208 .link_nodes = { &qns_a1noc_snoc },
209};
210
211static struct qcom_icc_node qxm_crypto = {
212 .name = "qxm_crypto",
213 .channels = 1,
214 .buswidth = 8,
215 .qosbox = &(const struct qcom_icc_qosbox) {
216 .num_ports = 1,
217 .port_offsets = { 0x5000 },
218 .prio = 2,
219 .urg_fwd = 1,
220 },
221 .num_links = 1,
222 .link_nodes = { &qns_a1noc_snoc },
223};
224
225static struct qcom_icc_node qxm_ipa = {
226 .name = "qxm_ipa",
227 .channels = 1,
228 .buswidth = 8,
229 .qosbox = &(const struct qcom_icc_qosbox) {
230 .num_ports = 1,
231 .port_offsets = { 0x6000 },
232 .prio = 2,
233 .urg_fwd = 1,
234 },
235 .num_links = 1,
236 .link_nodes = { &qns_lpass_snoc },
237};
238
239static struct qcom_icc_node xm_emac_avb = {
240 .name = "xm_emac_avb",
241 .channels = 1,
242 .buswidth = 8,
243 .qosbox = &(const struct qcom_icc_qosbox) {
244 .num_ports = 1,
245 .port_offsets = { 0xa000 },
246 .prio = 2,
247 .urg_fwd = 0,
248 },
249 .num_links = 1,
250 .link_nodes = { &qns_a1noc_snoc },
251};
252
253static struct qcom_icc_node xm_pcie = {
254 .name = "xm_pcie",
255 .channels = 1,
256 .buswidth = 8,
257 .qosbox = &(const struct qcom_icc_qosbox) {
258 .num_ports = 1,
259 .port_offsets = { 0x13000 },
260 .prio = 0,
261 .urg_fwd = 0,
262 },
263 .num_links = 1,
264 .link_nodes = { &qns_pcie_snoc },
265};
266
267static struct qcom_icc_node xm_qdss_etr = {
268 .name = "xm_qdss_etr",
269 .channels = 1,
270 .buswidth = 8,
271 .qosbox = &(const struct qcom_icc_qosbox) {
272 .num_ports = 1,
273 .port_offsets = { 0xb000 },
274 .prio = 2,
275 .urg_fwd = 0,
276 },
277 .num_links = 1,
278 .link_nodes = { &qns_a1noc_snoc },
279};
280
281static struct qcom_icc_node xm_sdc1 = {
282 .name = "xm_sdc1",
283 .channels = 1,
284 .buswidth = 8,
285 .qosbox = &(const struct qcom_icc_qosbox) {
286 .num_ports = 1,
287 .port_offsets = { 0xe000 },
288 .prio = 2,
289 .urg_fwd = 0,
290 },
291 .num_links = 1,
292 .link_nodes = { &qns_a1noc_snoc },
293};
294
295static struct qcom_icc_node xm_sdc2 = {
296 .name = "xm_sdc2",
297 .channels = 1,
298 .buswidth = 8,
299 .qosbox = &(const struct qcom_icc_qosbox) {
300 .num_ports = 1,
301 .port_offsets = { 0x16000 },
302 .prio = 2,
303 .urg_fwd = 0,
304 },
305 .num_links = 1,
306 .link_nodes = { &qns_a1noc_snoc },
307};
308
309static struct qcom_icc_node xm_ufs_mem = {
310 .name = "xm_ufs_mem",
311 .channels = 1,
312 .buswidth = 8,
313 .qosbox = &(const struct qcom_icc_qosbox) {
314 .num_ports = 1,
315 .port_offsets = { 0x11000 },
316 .prio = 2,
317 .urg_fwd = 0,
318 },
319 .num_links = 1,
320 .link_nodes = { &qns_a1noc_snoc },
321};
322
323static struct qcom_icc_node xm_usb2 = {
324 .name = "xm_usb2",
325 .channels = 1,
326 .buswidth = 8,
327 .qosbox = &(const struct qcom_icc_qosbox) {
328 .num_ports = 1,
329 .port_offsets = { 0x15000 },
330 .prio = 2,
331 .urg_fwd = 0,
332 },
333 .num_links = 1,
334 .link_nodes = { &qns_a1noc_snoc },
335};
336
337static struct qcom_icc_node xm_usb3_0 = {
338 .name = "xm_usb3_0",
339 .channels = 1,
340 .buswidth = 8,
341 .qosbox = &(const struct qcom_icc_qosbox) {
342 .num_ports = 1,
343 .port_offsets = { 0xd000 },
344 .prio = 2,
345 .urg_fwd = 0,
346 },
347 .num_links = 1,
348 .link_nodes = { &qns_a1noc_snoc },
349};
350
351static struct qcom_icc_node qxm_camnoc_hf0_uncomp = {
352 .name = "qxm_camnoc_hf0_uncomp",
353 .channels = 1,
354 .buswidth = 32,
355 .num_links = 1,
356 .link_nodes = { &qns_camnoc_uncomp },
357};
358
359static struct qcom_icc_node qxm_camnoc_hf1_uncomp = {
360 .name = "qxm_camnoc_hf1_uncomp",
361 .channels = 1,
362 .buswidth = 32,
363 .num_links = 1,
364 .link_nodes = { &qns_camnoc_uncomp },
365};
366
367static struct qcom_icc_node qxm_camnoc_sf_uncomp = {
368 .name = "qxm_camnoc_sf_uncomp",
369 .channels = 1,
370 .buswidth = 32,
371 .num_links = 1,
372 .link_nodes = { &qns_camnoc_uncomp },
373};
374
375static struct qcom_icc_node qhm_spdm = {
376 .name = "qhm_spdm",
377 .channels = 1,
378 .buswidth = 4,
379 .num_links = 1,
380 .link_nodes = { &qns_cnoc_a2noc },
381};
382
383static struct qcom_icc_node qnm_snoc = {
384 .name = "qnm_snoc",
385 .channels = 1,
386 .buswidth = 8,
387 .num_links = 39,
388 .link_nodes = { &qhs_a1_noc_cfg, &qhs_ahb2phy_east,
389 &qhs_ahb2phy_west, &qhs_aop,
390 &qhs_aoss, &qhs_camera_cfg,
391 &qhs_clk_ctl, &qhs_cpr_cx,
392 &qhs_cpr_mx, &qhs_crypto0_cfg,
393 &qhs_ddrss_cfg, &qhs_display_cfg,
394 &qhs_emac_avb_cfg, &qhs_glm,
395 &qhs_gpuss_cfg, &qhs_imem_cfg,
396 &qhs_ipa, &qhs_mnoc_cfg,
397 &qhs_pcie_config, &qhs_pimem_cfg,
398 &qhs_prng, &qhs_qdss_cfg,
399 &qhs_qspi, &qhs_qup0,
400 &qhs_qup1, &qhs_sdc1,
401 &qhs_sdc2, &qhs_snoc_cfg,
402 &qhs_spdm, &qhs_tcsr,
403 &qhs_tlmm_east, &qhs_tlmm_south,
404 &qhs_tlmm_west, &qhs_ufs_mem_cfg,
405 &qhs_usb2, &qhs_usb3,
406 &qhs_venus_cfg, &qhs_vsense_ctrl_cfg,
407 &srvc_cnoc },
408};
409
410static struct qcom_icc_node xm_qdss_dap = {
411 .name = "xm_qdss_dap",
412 .channels = 1,
413 .buswidth = 8,
414 .num_links = 40,
415 .link_nodes = { &qhs_a1_noc_cfg, &qhs_ahb2phy_east,
416 &qhs_ahb2phy_west, &qhs_aop,
417 &qhs_aoss, &qhs_camera_cfg,
418 &qhs_clk_ctl, &qhs_cpr_cx,
419 &qhs_cpr_mx, &qhs_crypto0_cfg,
420 &qhs_ddrss_cfg, &qhs_display_cfg,
421 &qhs_emac_avb_cfg, &qhs_glm,
422 &qhs_gpuss_cfg, &qhs_imem_cfg,
423 &qhs_ipa, &qhs_mnoc_cfg,
424 &qhs_pcie_config, &qhs_pimem_cfg,
425 &qhs_prng, &qhs_qdss_cfg,
426 &qhs_qspi, &qhs_qup0,
427 &qhs_qup1, &qhs_sdc1,
428 &qhs_sdc2, &qhs_snoc_cfg,
429 &qhs_spdm, &qhs_tcsr,
430 &qhs_tlmm_east, &qhs_tlmm_south,
431 &qhs_tlmm_west, &qhs_ufs_mem_cfg,
432 &qhs_usb2, &qhs_usb3,
433 &qhs_venus_cfg, &qhs_vsense_ctrl_cfg,
434 &qns_cnoc_a2noc, &srvc_cnoc },
435};
436
437static struct qcom_icc_node qhm_cnoc = {
438 .name = "qhm_cnoc",
439 .channels = 1,
440 .buswidth = 4,
441 .num_links = 2,
442 .link_nodes = { &qhs_dc_noc_gemnoc, &qhs_llcc },
443};
444
445static struct qcom_icc_node acm_apps = {
446 .name = "acm_apps",
447 .channels = 1,
448 .buswidth = 16,
449 .qosbox = &(const struct qcom_icc_qosbox) {
450 .num_ports = 2,
451 .port_offsets = { 0x2e000, 0x2e100 },
452 .prio = 0,
453 .urg_fwd = 1,
454 },
455 .num_links = 3,
456 .link_nodes = { &qns_gem_noc_snoc, &qns_llcc,
457 &qns_sys_pcie },
458};
459
460static struct qcom_icc_node acm_gpu_tcu = {
461 .name = "acm_gpu_tcu",
462 .channels = 1,
463 .buswidth = 8,
464 .qosbox = &(const struct qcom_icc_qosbox) {
465 .num_ports = 1,
466 .port_offsets = { 0x36000 },
467 .prio = 6,
468 .urg_fwd = 0,
469 },
470 .num_links = 2,
471 .link_nodes = { &qns_gem_noc_snoc, &qns_llcc },
472};
473
474static struct qcom_icc_node acm_sys_tcu = {
475 .name = "acm_sys_tcu",
476 .channels = 1,
477 .buswidth = 8,
478 .qosbox = &(const struct qcom_icc_qosbox) {
479 .num_ports = 1,
480 .port_offsets = { 0x37000 },
481 .prio = 6,
482 .urg_fwd = 0,
483 },
484 .num_links = 2,
485 .link_nodes = { &qns_gem_noc_snoc, &qns_llcc },
486};
487
488static struct qcom_icc_node qhm_gemnoc_cfg = {
489 .name = "qhm_gemnoc_cfg",
490 .channels = 1,
491 .buswidth = 4,
492 .num_links = 2,
493 .link_nodes = { &qhs_mdsp_ms_mpu_cfg, &srvc_gemnoc },
494};
495
496static struct qcom_icc_node qnm_gpu = {
497 .name = "qnm_gpu",
498 .channels = 2,
499 .buswidth = 32,
500 .qosbox = &(const struct qcom_icc_qosbox) {
501 .num_ports = 2,
502 .port_offsets = { 0x34000, 0x34080 },
503 .prio = 0,
504 .urg_fwd = 1,
505 },
506 .num_links = 2,
507 .link_nodes = { &qns_gem_noc_snoc, &qns_llcc },
508};
509
510static struct qcom_icc_node qnm_mnoc_hf = {
511 .name = "qnm_mnoc_hf",
512 .channels = 1,
513 .buswidth = 32,
514 .qosbox = &(const struct qcom_icc_qosbox) {
515 .num_ports = 1,
516 .port_offsets = { 0x2f000 },
517 .prio = 0,
518 .urg_fwd = 1,
519 },
520 .num_links = 1,
521 .link_nodes = { &qns_llcc },
522};
523
524static struct qcom_icc_node qnm_mnoc_sf = {
525 .name = "qnm_mnoc_sf",
526 .channels = 1,
527 .buswidth = 32,
528 .qosbox = &(const struct qcom_icc_qosbox) {
529 .num_ports = 1,
530 .port_offsets = { 0x35000 },
531 .prio = 0,
532 .urg_fwd = 1,
533 },
534 .num_links = 2,
535 .link_nodes = { &qns_gem_noc_snoc, &qns_llcc },
536};
537
538static struct qcom_icc_node qnm_snoc_gc = {
539 .name = "qnm_snoc_gc",
540 .channels = 1,
541 .buswidth = 8,
542 .qosbox = &(const struct qcom_icc_qosbox) {
543 .num_ports = 1,
544 .port_offsets = { 0x31000 },
545 .prio = 0,
546 .urg_fwd = 1,
547 },
548 .num_links = 1,
549 .link_nodes = { &qns_llcc },
550};
551
552static struct qcom_icc_node qnm_snoc_sf = {
553 .name = "qnm_snoc_sf",
554 .channels = 1,
555 .buswidth = 16,
556 .qosbox = &(const struct qcom_icc_qosbox) {
557 .num_ports = 1,
558 .port_offsets = { 0x30000 },
559 .prio = 0,
560 .urg_fwd = 1,
561 },
562 .num_links = 1,
563 .link_nodes = { &qns_llcc },
564};
565
566static struct qcom_icc_node llcc_mc = {
567 .name = "llcc_mc",
568 .channels = 2,
569 .buswidth = 4,
570 .num_links = 1,
571 .link_nodes = { &ebi },
572};
573
574static struct qcom_icc_node qhm_mnoc_cfg = {
575 .name = "qhm_mnoc_cfg",
576 .channels = 1,
577 .buswidth = 4,
578 .num_links = 1,
579 .link_nodes = { &srvc_mnoc },
580};
581
582static struct qcom_icc_node qxm_camnoc_hf0 = {
583 .name = "qxm_camnoc_hf0",
584 .channels = 1,
585 .buswidth = 32,
586 .qosbox = &(const struct qcom_icc_qosbox) {
587 .num_ports = 1,
588 .port_offsets = { 0xa000 },
589 .prio = 0,
590 .urg_fwd = 1,
591 },
592 .num_links = 1,
593 .link_nodes = { &qns_mem_noc_hf },
594};
595
596static struct qcom_icc_node qxm_camnoc_hf1 = {
597 .name = "qxm_camnoc_hf1",
598 .channels = 1,
599 .buswidth = 32,
600 .qosbox = &(const struct qcom_icc_qosbox) {
601 .num_ports = 1,
602 .port_offsets = { 0xb000 },
603 .prio = 0,
604 .urg_fwd = 1,
605 },
606 .num_links = 1,
607 .link_nodes = { &qns_mem_noc_hf },
608};
609
610static struct qcom_icc_node qxm_camnoc_sf = {
611 .name = "qxm_camnoc_sf",
612 .channels = 1,
613 .buswidth = 32,
614 .qosbox = &(const struct qcom_icc_qosbox) {
615 .num_ports = 1,
616 .port_offsets = { 0x9000 },
617 .prio = 0,
618 .urg_fwd = 1,
619 },
620 .num_links = 1,
621 .link_nodes = { &qns2_mem_noc },
622};
623
624static struct qcom_icc_node qxm_mdp0 = {
625 .name = "qxm_mdp0",
626 .channels = 1,
627 .buswidth = 32,
628 .qosbox = &(const struct qcom_icc_qosbox) {
629 .num_ports = 1,
630 .port_offsets = { 0xc000 },
631 .prio = 0,
632 .urg_fwd = 1,
633 },
634 .num_links = 1,
635 .link_nodes = { &qns_mem_noc_hf },
636};
637
638static struct qcom_icc_node qxm_rot = {
639 .name = "qxm_rot",
640 .channels = 1,
641 .buswidth = 32,
642 .qosbox = &(const struct qcom_icc_qosbox) {
643 .num_ports = 1,
644 .port_offsets = { 0xe000 },
645 .prio = 0,
646 .urg_fwd = 1,
647 },
648 .num_links = 1,
649 .link_nodes = { &qns2_mem_noc },
650};
651
652static struct qcom_icc_node qxm_venus0 = {
653 .name = "qxm_venus0",
654 .channels = 1,
655 .buswidth = 32,
656 .qosbox = &(const struct qcom_icc_qosbox) {
657 .num_ports = 1,
658 .port_offsets = { 0xf000 },
659 .prio = 0,
660 .urg_fwd = 1,
661 },
662 .num_links = 1,
663 .link_nodes = { &qns2_mem_noc },
664};
665
666static struct qcom_icc_node qxm_venus_arm9 = {
667 .name = "qxm_venus_arm9",
668 .channels = 1,
669 .buswidth = 8,
670 .qosbox = &(const struct qcom_icc_qosbox) {
671 .num_ports = 1,
672 .port_offsets = { 0x11000 },
673 .prio = 0,
674 .urg_fwd = 1,
675 },
676 .num_links = 1,
677 .link_nodes = { &qns2_mem_noc },
678};
679
680static struct qcom_icc_node qhm_snoc_cfg = {
681 .name = "qhm_snoc_cfg",
682 .channels = 1,
683 .buswidth = 4,
684 .num_links = 1,
685 .link_nodes = { &srvc_snoc },
686};
687
688static struct qcom_icc_node qnm_aggre1_noc = {
689 .name = "qnm_aggre1_noc",
690 .channels = 1,
691 .buswidth = 16,
692 .num_links = 8,
693 .link_nodes = { &qhs_apss, &qns_cnoc,
694 &qns_gemnoc_sf, &qxs_imem,
695 &qxs_pimem, &xs_pcie,
696 &xs_qdss_stm, &xs_sys_tcu_cfg },
697};
698
699static struct qcom_icc_node qnm_gemnoc = {
700 .name = "qnm_gemnoc",
701 .channels = 1,
702 .buswidth = 8,
703 .num_links = 6,
704 .link_nodes = { &qhs_apss, &qns_cnoc,
705 &qxs_imem, &qxs_pimem,
706 &xs_qdss_stm, &xs_sys_tcu_cfg },
707};
708
709static struct qcom_icc_node qnm_gemnoc_pcie = {
710 .name = "qnm_gemnoc_pcie",
711 .channels = 1,
712 .buswidth = 8,
713 .num_links = 1,
714 .link_nodes = { &xs_pcie },
715};
716
717static struct qcom_icc_node qnm_lpass_anoc = {
718 .name = "qnm_lpass_anoc",
719 .channels = 1,
720 .buswidth = 8,
721 .num_links = 7,
722 .link_nodes = { &qhs_apss, &qns_cnoc,
723 &qns_gemnoc_sf, &qxs_imem,
724 &qxs_pimem, &xs_pcie,
725 &xs_qdss_stm },
726};
727
728static struct qcom_icc_node qnm_pcie_anoc = {
729 .name = "qnm_pcie_anoc",
730 .channels = 1,
731 .buswidth = 8,
732 .num_links = 5,
733 .link_nodes = { &qhs_apss, &qns_cnoc,
734 &qns_gemnoc_sf, &qxs_imem,
735 &xs_qdss_stm },
736};
737
738static struct qcom_icc_node qxm_pimem = {
739 .name = "qxm_pimem",
740 .channels = 1,
741 .buswidth = 8,
742 .qosbox = &(const struct qcom_icc_qosbox) {
743 .num_ports = 1,
744 .port_offsets = { 0xc000 },
745 .prio = 2,
746 .urg_fwd = 1,
747 },
748 .num_links = 2,
749 .link_nodes = { &qns_memnoc_gc, &qxs_imem },
750};
751
752static struct qcom_icc_node xm_gic = {
753 .name = "xm_gic",
754 .channels = 1,
755 .buswidth = 8,
756 .qosbox = &(const struct qcom_icc_qosbox) {
757 .num_ports = 1,
758 .port_offsets = { 0xd000 },
759 .prio = 2,
760 .urg_fwd = 1,
761 },
762 .num_links = 2,
763 .link_nodes = { &qns_memnoc_gc, &qxs_imem },
764};
765
766static struct qcom_icc_node qns_a1noc_snoc = {
767 .name = "qns_a1noc_snoc",
768 .channels = 1,
769 .buswidth = 16,
770 .num_links = 1,
771 .link_nodes = { &qnm_aggre1_noc },
772};
773
774static struct qcom_icc_node qns_lpass_snoc = {
775 .name = "qns_lpass_snoc",
776 .channels = 1,
777 .buswidth = 8,
778 .num_links = 1,
779 .link_nodes = { &qnm_lpass_anoc },
780};
781
782static struct qcom_icc_node qns_pcie_snoc = {
783 .name = "qns_pcie_snoc",
784 .channels = 1,
785 .buswidth = 8,
786 .num_links = 1,
787 .link_nodes = { &qnm_pcie_anoc },
788};
789
790static struct qcom_icc_node srvc_aggre2_noc = {
791 .name = "srvc_aggre2_noc",
792 .channels = 1,
793 .buswidth = 4,
794};
795
796static struct qcom_icc_node qns_camnoc_uncomp = {
797 .name = "qns_camnoc_uncomp",
798 .channels = 1,
799 .buswidth = 32,
800};
801
802static struct qcom_icc_node qhs_a1_noc_cfg = {
803 .name = "qhs_a1_noc_cfg",
804 .channels = 1,
805 .buswidth = 4,
806 .num_links = 1,
807 .link_nodes = { &qhm_a1noc_cfg },
808};
809
810static struct qcom_icc_node qhs_ahb2phy_east = {
811 .name = "qhs_ahb2phy_east",
812 .channels = 1,
813 .buswidth = 4,
814};
815
816static struct qcom_icc_node qhs_ahb2phy_west = {
817 .name = "qhs_ahb2phy_west",
818 .channels = 1,
819 .buswidth = 4,
820};
821
822static struct qcom_icc_node qhs_aop = {
823 .name = "qhs_aop",
824 .channels = 1,
825 .buswidth = 4,
826};
827
828static struct qcom_icc_node qhs_aoss = {
829 .name = "qhs_aoss",
830 .channels = 1,
831 .buswidth = 4,
832};
833
834static struct qcom_icc_node qhs_camera_cfg = {
835 .name = "qhs_camera_cfg",
836 .channels = 1,
837 .buswidth = 4,
838};
839
840static struct qcom_icc_node qhs_clk_ctl = {
841 .name = "qhs_clk_ctl",
842 .channels = 1,
843 .buswidth = 4,
844};
845
846static struct qcom_icc_node qhs_cpr_cx = {
847 .name = "qhs_cpr_cx",
848 .channels = 1,
849 .buswidth = 4,
850};
851
852static struct qcom_icc_node qhs_cpr_mx = {
853 .name = "qhs_cpr_mx",
854 .channels = 1,
855 .buswidth = 4,
856};
857
858static struct qcom_icc_node qhs_crypto0_cfg = {
859 .name = "qhs_crypto0_cfg",
860 .channels = 1,
861 .buswidth = 4,
862};
863
864static struct qcom_icc_node qhs_ddrss_cfg = {
865 .name = "qhs_ddrss_cfg",
866 .channels = 1,
867 .buswidth = 4,
868 .num_links = 1,
869 .link_nodes = { &qhm_cnoc },
870};
871
872static struct qcom_icc_node qhs_display_cfg = {
873 .name = "qhs_display_cfg",
874 .channels = 1,
875 .buswidth = 4,
876};
877
878static struct qcom_icc_node qhs_emac_avb_cfg = {
879 .name = "qhs_emac_avb_cfg",
880 .channels = 1,
881 .buswidth = 4,
882};
883
884static struct qcom_icc_node qhs_glm = {
885 .name = "qhs_glm",
886 .channels = 1,
887 .buswidth = 4,
888};
889
890static struct qcom_icc_node qhs_gpuss_cfg = {
891 .name = "qhs_gpuss_cfg",
892 .channels = 1,
893 .buswidth = 8,
894};
895
896static struct qcom_icc_node qhs_imem_cfg = {
897 .name = "qhs_imem_cfg",
898 .channels = 1,
899 .buswidth = 4,
900};
901
902static struct qcom_icc_node qhs_ipa = {
903 .name = "qhs_ipa",
904 .channels = 1,
905 .buswidth = 4,
906};
907
908static struct qcom_icc_node qhs_mnoc_cfg = {
909 .name = "qhs_mnoc_cfg",
910 .channels = 1,
911 .buswidth = 4,
912 .num_links = 1,
913 .link_nodes = { &qhm_mnoc_cfg },
914};
915
916static struct qcom_icc_node qhs_pcie_config = {
917 .name = "qhs_pcie_config",
918 .channels = 1,
919 .buswidth = 4,
920};
921
922static struct qcom_icc_node qhs_pimem_cfg = {
923 .name = "qhs_pimem_cfg",
924 .channels = 1,
925 .buswidth = 4,
926};
927
928static struct qcom_icc_node qhs_prng = {
929 .name = "qhs_prng",
930 .channels = 1,
931 .buswidth = 4,
932};
933
934static struct qcom_icc_node qhs_qdss_cfg = {
935 .name = "qhs_qdss_cfg",
936 .channels = 1,
937 .buswidth = 4,
938};
939
940static struct qcom_icc_node qhs_qspi = {
941 .name = "qhs_qspi",
942 .channels = 1,
943 .buswidth = 4,
944};
945
946static struct qcom_icc_node qhs_qup0 = {
947 .name = "qhs_qup0",
948 .channels = 1,
949 .buswidth = 4,
950};
951
952static struct qcom_icc_node qhs_qup1 = {
953 .name = "qhs_qup1",
954 .channels = 1,
955 .buswidth = 4,
956};
957
958static struct qcom_icc_node qhs_sdc1 = {
959 .name = "qhs_sdc1",
960 .channels = 1,
961 .buswidth = 4,
962};
963
964static struct qcom_icc_node qhs_sdc2 = {
965 .name = "qhs_sdc2",
966 .channels = 1,
967 .buswidth = 4,
968};
969
970static struct qcom_icc_node qhs_snoc_cfg = {
971 .name = "qhs_snoc_cfg",
972 .channels = 1,
973 .buswidth = 4,
974 .num_links = 1,
975 .link_nodes = { &qhm_snoc_cfg },
976};
977
978static struct qcom_icc_node qhs_spdm = {
979 .name = "qhs_spdm",
980 .channels = 1,
981 .buswidth = 4,
982};
983
984static struct qcom_icc_node qhs_tcsr = {
985 .name = "qhs_tcsr",
986 .channels = 1,
987 .buswidth = 4,
988};
989
990static struct qcom_icc_node qhs_tlmm_east = {
991 .name = "qhs_tlmm_east",
992 .channels = 1,
993 .buswidth = 4,
994};
995
996static struct qcom_icc_node qhs_tlmm_south = {
997 .name = "qhs_tlmm_south",
998 .channels = 1,
999 .buswidth = 4,
1000};
1001
1002static struct qcom_icc_node qhs_tlmm_west = {
1003 .name = "qhs_tlmm_west",
1004 .channels = 1,
1005 .buswidth = 4,
1006};
1007
1008static struct qcom_icc_node qhs_ufs_mem_cfg = {
1009 .name = "qhs_ufs_mem_cfg",
1010 .channels = 1,
1011 .buswidth = 4,
1012};
1013
1014static struct qcom_icc_node qhs_usb2 = {
1015 .name = "qhs_usb2",
1016 .channels = 1,
1017 .buswidth = 4,
1018};
1019
1020static struct qcom_icc_node qhs_usb3 = {
1021 .name = "qhs_usb3",
1022 .channels = 1,
1023 .buswidth = 4,
1024};
1025
1026static struct qcom_icc_node qhs_venus_cfg = {
1027 .name = "qhs_venus_cfg",
1028 .channels = 1,
1029 .buswidth = 4,
1030};
1031
1032static struct qcom_icc_node qhs_vsense_ctrl_cfg = {
1033 .name = "qhs_vsense_ctrl_cfg",
1034 .channels = 1,
1035 .buswidth = 4,
1036};
1037
1038static struct qcom_icc_node qns_cnoc_a2noc = {
1039 .name = "qns_cnoc_a2noc",
1040 .channels = 1,
1041 .buswidth = 8,
1042 .num_links = 1,
1043 .link_nodes = { &qnm_cnoc },
1044};
1045
1046static struct qcom_icc_node srvc_cnoc = {
1047 .name = "srvc_cnoc",
1048 .channels = 1,
1049 .buswidth = 4,
1050};
1051
1052static struct qcom_icc_node qhs_dc_noc_gemnoc = {
1053 .name = "qhs_dc_noc_gemnoc",
1054 .channels = 1,
1055 .buswidth = 4,
1056 .num_links = 1,
1057 .link_nodes = { &qhm_gemnoc_cfg },
1058};
1059
1060static struct qcom_icc_node qhs_llcc = {
1061 .name = "qhs_llcc",
1062 .channels = 1,
1063 .buswidth = 4,
1064};
1065
1066static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg = {
1067 .name = "qhs_mdsp_ms_mpu_cfg",
1068 .channels = 1,
1069 .buswidth = 4,
1070};
1071
1072static struct qcom_icc_node qns_gem_noc_snoc = {
1073 .name = "qns_gem_noc_snoc",
1074 .channels = 1,
1075 .buswidth = 8,
1076 .num_links = 1,
1077 .link_nodes = { &qnm_gemnoc },
1078};
1079
1080static struct qcom_icc_node qns_llcc = {
1081 .name = "qns_llcc",
1082 .channels = 1,
1083 .buswidth = 16,
1084 .num_links = 1,
1085 .link_nodes = { &llcc_mc },
1086};
1087
1088static struct qcom_icc_node qns_sys_pcie = {
1089 .name = "qns_sys_pcie",
1090 .channels = 1,
1091 .buswidth = 8,
1092 .num_links = 1,
1093 .link_nodes = { &qnm_gemnoc_pcie },
1094};
1095
1096static struct qcom_icc_node srvc_gemnoc = {
1097 .name = "srvc_gemnoc",
1098 .channels = 1,
1099 .buswidth = 4,
1100};
1101
1102static struct qcom_icc_node ebi = {
1103 .name = "ebi",
1104 .channels = 2,
1105 .buswidth = 4,
1106};
1107
1108static struct qcom_icc_node qns2_mem_noc = {
1109 .name = "qns2_mem_noc",
1110 .channels = 1,
1111 .buswidth = 32,
1112 .num_links = 1,
1113 .link_nodes = { &qnm_mnoc_sf },
1114};
1115
1116static struct qcom_icc_node qns_mem_noc_hf = {
1117 .name = "qns_mem_noc_hf",
1118 .channels = 1,
1119 .buswidth = 32,
1120 .num_links = 1,
1121 .link_nodes = { &qnm_mnoc_hf },
1122};
1123
1124static struct qcom_icc_node srvc_mnoc = {
1125 .name = "srvc_mnoc",
1126 .channels = 1,
1127 .buswidth = 4,
1128};
1129
1130static struct qcom_icc_node qhs_apss = {
1131 .name = "qhs_apss",
1132 .channels = 1,
1133 .buswidth = 8,
1134};
1135
1136static struct qcom_icc_node qns_cnoc = {
1137 .name = "qns_cnoc",
1138 .channels = 1,
1139 .buswidth = 8,
1140 .num_links = 1,
1141 .link_nodes = { &qnm_snoc },
1142};
1143
1144static struct qcom_icc_node qns_gemnoc_sf = {
1145 .name = "qns_gemnoc_sf",
1146 .channels = 1,
1147 .buswidth = 16,
1148 .num_links = 1,
1149 .link_nodes = { &qnm_snoc_sf },
1150};
1151
1152static struct qcom_icc_node qns_memnoc_gc = {
1153 .name = "qns_memnoc_gc",
1154 .channels = 1,
1155 .buswidth = 8,
1156 .num_links = 1,
1157 .link_nodes = { &qnm_snoc_gc },
1158};
1159
1160static struct qcom_icc_node qxs_imem = {
1161 .name = "qxs_imem",
1162 .channels = 1,
1163 .buswidth = 8,
1164};
1165
1166static struct qcom_icc_node qxs_pimem = {
1167 .name = "qxs_pimem",
1168 .channels = 1,
1169 .buswidth = 8,
1170};
1171
1172static struct qcom_icc_node srvc_snoc = {
1173 .name = "srvc_snoc",
1174 .channels = 1,
1175 .buswidth = 4,
1176};
1177
1178static struct qcom_icc_node xs_pcie = {
1179 .name = "xs_pcie",
1180 .channels = 1,
1181 .buswidth = 8,
1182};
1183
1184static struct qcom_icc_node xs_qdss_stm = {
1185 .name = "xs_qdss_stm",
1186 .channels = 1,
1187 .buswidth = 4,
1188};
1189
1190static struct qcom_icc_node xs_sys_tcu_cfg = {
1191 .name = "xs_sys_tcu_cfg",
1192 .channels = 1,
1193 .buswidth = 8,
1194};
1195
1196static struct qcom_icc_bcm bcm_acv = {
1197 .name = "ACV",
1198 .num_nodes = 1,
1199 .nodes = { &ebi },
1200};
1201
1202static struct qcom_icc_bcm bcm_ce0 = {
1203 .name = "CE0",
1204 .num_nodes = 1,
1205 .nodes = { &qxm_crypto },
1206};
1207
1208static struct qcom_icc_bcm bcm_cn0 = {
1209 .name = "CN0",
1210 .keepalive = true,
1211 .num_nodes = 37,
1212 .nodes = { &qhm_spdm, &qnm_snoc,
1213 &qhs_a1_noc_cfg, &qhs_aop,
1214 &qhs_aoss, &qhs_camera_cfg,
1215 &qhs_clk_ctl, &qhs_cpr_cx,
1216 &qhs_cpr_mx, &qhs_crypto0_cfg,
1217 &qhs_ddrss_cfg, &qhs_display_cfg,
1218 &qhs_emac_avb_cfg, &qhs_glm,
1219 &qhs_gpuss_cfg, &qhs_imem_cfg,
1220 &qhs_ipa, &qhs_mnoc_cfg,
1221 &qhs_pcie_config, &qhs_pimem_cfg,
1222 &qhs_prng, &qhs_qdss_cfg,
1223 &qhs_qup0, &qhs_qup1,
1224 &qhs_snoc_cfg, &qhs_spdm,
1225 &qhs_tcsr, &qhs_tlmm_east,
1226 &qhs_tlmm_south, &qhs_tlmm_west,
1227 &qhs_ufs_mem_cfg, &qhs_usb2,
1228 &qhs_usb3, &qhs_venus_cfg,
1229 &qhs_vsense_ctrl_cfg, &qns_cnoc_a2noc,
1230 &srvc_cnoc },
1231};
1232
1233static struct qcom_icc_bcm bcm_cn1 = {
1234 .name = "CN1",
1235 .num_nodes = 8,
1236 .nodes = { &qhm_qspi, &xm_sdc1,
1237 &xm_sdc2, &qhs_ahb2phy_east,
1238 &qhs_ahb2phy_west, &qhs_qspi,
1239 &qhs_sdc1, &qhs_sdc2 },
1240};
1241
1242static struct qcom_icc_bcm bcm_mc0 = {
1243 .name = "MC0",
1244 .keepalive = true,
1245 .num_nodes = 1,
1246 .nodes = { &ebi },
1247};
1248
1249static struct qcom_icc_bcm bcm_mm0 = {
1250 .name = "MM0",
1251 .keepalive = true,
1252 .num_nodes = 1,
1253 .nodes = { &qns_mem_noc_hf },
1254};
1255
1256static struct qcom_icc_bcm bcm_mm1 = {
1257 .name = "MM1",
1258 .num_nodes = 7,
1259 .nodes = { &qxm_camnoc_hf0_uncomp, &qxm_camnoc_hf1_uncomp,
1260 &qxm_camnoc_sf_uncomp, &qxm_camnoc_hf0,
1261 &qxm_camnoc_hf1, &qxm_mdp0,
1262 &qxm_rot },
1263};
1264
1265static struct qcom_icc_bcm bcm_mm2 = {
1266 .name = "MM2",
1267 .num_nodes = 2,
1268 .nodes = { &qxm_camnoc_sf, &qns2_mem_noc },
1269};
1270
1271static struct qcom_icc_bcm bcm_mm3 = {
1272 .name = "MM3",
1273 .num_nodes = 2,
1274 .nodes = { &qxm_venus0, &qxm_venus_arm9 },
1275};
1276
1277static struct qcom_icc_bcm bcm_qup0 = {
1278 .name = "QUP0",
1279 .keepalive = true,
1280 .vote_scale = 1,
1281 .num_nodes = 2,
1282 .nodes = { &qhm_qup0, &qhm_qup1 },
1283};
1284
1285static struct qcom_icc_bcm bcm_sh0 = {
1286 .name = "SH0",
1287 .keepalive = true,
1288 .num_nodes = 1,
1289 .nodes = { &qns_llcc },
1290};
1291
1292static struct qcom_icc_bcm bcm_sh2 = {
1293 .name = "SH2",
1294 .num_nodes = 1,
1295 .nodes = { &acm_apps },
1296};
1297
1298static struct qcom_icc_bcm bcm_sh3 = {
1299 .name = "SH3",
1300 .num_nodes = 1,
1301 .nodes = { &qns_gem_noc_snoc },
1302};
1303
1304static struct qcom_icc_bcm bcm_sn0 = {
1305 .name = "SN0",
1306 .keepalive = true,
1307 .num_nodes = 1,
1308 .nodes = { &qns_gemnoc_sf },
1309};
1310
1311static struct qcom_icc_bcm bcm_sn1 = {
1312 .name = "SN1",
1313 .num_nodes = 1,
1314 .nodes = { &qxs_imem },
1315};
1316
1317static struct qcom_icc_bcm bcm_sn2 = {
1318 .name = "SN2",
1319 .num_nodes = 1,
1320 .nodes = { &qns_memnoc_gc },
1321};
1322
1323static struct qcom_icc_bcm bcm_sn3 = {
1324 .name = "SN3",
1325 .num_nodes = 2,
1326 .nodes = { &srvc_aggre2_noc, &qns_cnoc },
1327};
1328
1329static struct qcom_icc_bcm bcm_sn4 = {
1330 .name = "SN4",
1331 .num_nodes = 1,
1332 .nodes = { &qxs_pimem },
1333};
1334
1335static struct qcom_icc_bcm bcm_sn5 = {
1336 .name = "SN5",
1337 .num_nodes = 1,
1338 .nodes = { &xs_qdss_stm },
1339};
1340
1341static struct qcom_icc_bcm bcm_sn8 = {
1342 .name = "SN8",
1343 .num_nodes = 2,
1344 .nodes = { &qnm_gemnoc_pcie, &xs_pcie },
1345};
1346
1347static struct qcom_icc_bcm bcm_sn9 = {
1348 .name = "SN9",
1349 .num_nodes = 1,
1350 .nodes = { &qnm_aggre1_noc },
1351};
1352
1353static struct qcom_icc_bcm bcm_sn12 = {
1354 .name = "SN12",
1355 .num_nodes = 2,
1356 .nodes = { &qxm_pimem, &xm_gic },
1357};
1358
1359static struct qcom_icc_bcm bcm_sn13 = {
1360 .name = "SN13",
1361 .num_nodes = 1,
1362 .nodes = { &qnm_lpass_anoc },
1363};
1364
1365static struct qcom_icc_bcm bcm_sn14 = {
1366 .name = "SN14",
1367 .num_nodes = 1,
1368 .nodes = { &qns_pcie_snoc },
1369};
1370
1371static struct qcom_icc_bcm bcm_sn15 = {
1372 .name = "SN15",
1373 .num_nodes = 1,
1374 .nodes = { &qnm_gemnoc },
1375};
1376
1377static struct qcom_icc_bcm * const aggre1_noc_bcms[] = {
1378 &bcm_ce0,
1379 &bcm_cn1,
1380 &bcm_qup0,
1381 &bcm_sn3,
1382 &bcm_sn14,
1383};
1384
1385static struct qcom_icc_node * const aggre1_noc_nodes[] = {
1386 [MASTER_A1NOC_CFG] = &qhm_a1noc_cfg,
1387 [MASTER_QDSS_BAM] = &qhm_qdss_bam,
1388 [MASTER_QSPI] = &qhm_qspi,
1389 [MASTER_QUP_0] = &qhm_qup0,
1390 [MASTER_BLSP_1] = &qhm_qup1,
1391 [MASTER_CNOC_A2NOC] = &qnm_cnoc,
1392 [MASTER_CRYPTO] = &qxm_crypto,
1393 [MASTER_IPA] = &qxm_ipa,
1394 [MASTER_EMAC_EVB] = &xm_emac_avb,
1395 [MASTER_PCIE] = &xm_pcie,
1396 [MASTER_QDSS_ETR] = &xm_qdss_etr,
1397 [MASTER_SDCC_1] = &xm_sdc1,
1398 [MASTER_SDCC_2] = &xm_sdc2,
1399 [MASTER_UFS_MEM] = &xm_ufs_mem,
1400 [MASTER_USB2] = &xm_usb2,
1401 [MASTER_USB3_0] = &xm_usb3_0,
1402 [SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc,
1403 [SLAVE_LPASS_SNOC] = &qns_lpass_snoc,
1404 [SLAVE_ANOC_PCIE_SNOC] = &qns_pcie_snoc,
1405 [SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc,
1406};
1407
1408static const struct regmap_config qcs615_aggre1_noc_regmap_config = {
1409 .reg_bits = 32,
1410 .reg_stride = 4,
1411 .val_bits = 32,
1412 .max_register = 0x3f200,
1413 .fast_io = true,
1414};
1415
1416static const struct qcom_icc_desc qcs615_aggre1_noc = {
1417 .config = &qcs615_aggre1_noc_regmap_config,
1418 .nodes = aggre1_noc_nodes,
1419 .num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
1420 .bcms = aggre1_noc_bcms,
1421 .num_bcms = ARRAY_SIZE(aggre1_noc_bcms),
1422 .qos_requires_clocks = true,
1423};
1424
1425static struct qcom_icc_bcm * const camnoc_virt_bcms[] = {
1426 &bcm_mm1,
1427};
1428
1429static struct qcom_icc_node * const camnoc_virt_nodes[] = {
1430 [MASTER_CAMNOC_HF0_UNCOMP] = &qxm_camnoc_hf0_uncomp,
1431 [MASTER_CAMNOC_HF1_UNCOMP] = &qxm_camnoc_hf1_uncomp,
1432 [MASTER_CAMNOC_SF_UNCOMP] = &qxm_camnoc_sf_uncomp,
1433 [SLAVE_CAMNOC_UNCOMP] = &qns_camnoc_uncomp,
1434};
1435
1436static const struct qcom_icc_desc qcs615_camnoc_virt = {
1437 .nodes = camnoc_virt_nodes,
1438 .num_nodes = ARRAY_SIZE(camnoc_virt_nodes),
1439 .bcms = camnoc_virt_bcms,
1440 .num_bcms = ARRAY_SIZE(camnoc_virt_bcms),
1441};
1442
1443static struct qcom_icc_bcm * const config_noc_bcms[] = {
1444 &bcm_cn0,
1445 &bcm_cn1,
1446};
1447
1448static struct qcom_icc_node * const config_noc_nodes[] = {
1449 [MASTER_SPDM] = &qhm_spdm,
1450 [MASTER_SNOC_CNOC] = &qnm_snoc,
1451 [MASTER_QDSS_DAP] = &xm_qdss_dap,
1452 [SLAVE_A1NOC_CFG] = &qhs_a1_noc_cfg,
1453 [SLAVE_AHB2PHY_EAST] = &qhs_ahb2phy_east,
1454 [SLAVE_AHB2PHY_WEST] = &qhs_ahb2phy_west,
1455 [SLAVE_AOP] = &qhs_aop,
1456 [SLAVE_AOSS] = &qhs_aoss,
1457 [SLAVE_CAMERA_CFG] = &qhs_camera_cfg,
1458 [SLAVE_CLK_CTL] = &qhs_clk_ctl,
1459 [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx,
1460 [SLAVE_RBCPR_MX_CFG] = &qhs_cpr_mx,
1461 [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg,
1462 [SLAVE_CNOC_DDRSS] = &qhs_ddrss_cfg,
1463 [SLAVE_DISPLAY_CFG] = &qhs_display_cfg,
1464 [SLAVE_EMAC_AVB_CFG] = &qhs_emac_avb_cfg,
1465 [SLAVE_GLM] = &qhs_glm,
1466 [SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg,
1467 [SLAVE_IMEM_CFG] = &qhs_imem_cfg,
1468 [SLAVE_IPA_CFG] = &qhs_ipa,
1469 [SLAVE_CNOC_MNOC_CFG] = &qhs_mnoc_cfg,
1470 [SLAVE_PCIE_CFG] = &qhs_pcie_config,
1471 [SLAVE_PIMEM_CFG] = &qhs_pimem_cfg,
1472 [SLAVE_PRNG] = &qhs_prng,
1473 [SLAVE_QDSS_CFG] = &qhs_qdss_cfg,
1474 [SLAVE_QSPI] = &qhs_qspi,
1475 [SLAVE_QUP_0] = &qhs_qup0,
1476 [SLAVE_QUP_1] = &qhs_qup1,
1477 [SLAVE_SDCC_1] = &qhs_sdc1,
1478 [SLAVE_SDCC_2] = &qhs_sdc2,
1479 [SLAVE_SNOC_CFG] = &qhs_snoc_cfg,
1480 [SLAVE_SPDM_WRAPPER] = &qhs_spdm,
1481 [SLAVE_TCSR] = &qhs_tcsr,
1482 [SLAVE_TLMM_EAST] = &qhs_tlmm_east,
1483 [SLAVE_TLMM_SOUTH] = &qhs_tlmm_south,
1484 [SLAVE_TLMM_WEST] = &qhs_tlmm_west,
1485 [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg,
1486 [SLAVE_USB2] = &qhs_usb2,
1487 [SLAVE_USB3] = &qhs_usb3,
1488 [SLAVE_VENUS_CFG] = &qhs_venus_cfg,
1489 [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg,
1490 [SLAVE_CNOC_A2NOC] = &qns_cnoc_a2noc,
1491 [SLAVE_SERVICE_CNOC] = &srvc_cnoc,
1492};
1493
1494static const struct regmap_config qcs615_config_noc_regmap_config = {
1495 .reg_bits = 32,
1496 .reg_stride = 4,
1497 .val_bits = 32,
1498 .max_register = 0x5080,
1499 .fast_io = true,
1500};
1501
1502static const struct qcom_icc_desc qcs615_config_noc = {
1503 .config = &qcs615_config_noc_regmap_config,
1504 .nodes = config_noc_nodes,
1505 .num_nodes = ARRAY_SIZE(config_noc_nodes),
1506 .bcms = config_noc_bcms,
1507 .num_bcms = ARRAY_SIZE(config_noc_bcms),
1508};
1509
1510static struct qcom_icc_node * const dc_noc_nodes[] = {
1511 [MASTER_CNOC_DC_NOC] = &qhm_cnoc,
1512 [SLAVE_DC_NOC_GEMNOC] = &qhs_dc_noc_gemnoc,
1513 [SLAVE_LLCC_CFG] = &qhs_llcc,
1514};
1515
1516static const struct regmap_config qcs615_dc_noc_regmap_config = {
1517 .reg_bits = 32,
1518 .reg_stride = 4,
1519 .val_bits = 32,
1520 .max_register = 0x3200,
1521 .fast_io = true,
1522};
1523
1524static const struct qcom_icc_desc qcs615_dc_noc = {
1525 .config = &qcs615_dc_noc_regmap_config,
1526 .nodes = dc_noc_nodes,
1527 .num_nodes = ARRAY_SIZE(dc_noc_nodes),
1528};
1529
1530static struct qcom_icc_bcm * const gem_noc_bcms[] = {
1531 &bcm_sh0,
1532 &bcm_sh2,
1533 &bcm_sh3,
1534 &bcm_mm1,
1535};
1536
1537static struct qcom_icc_node * const gem_noc_nodes[] = {
1538 [MASTER_APPSS_PROC] = &acm_apps,
1539 [MASTER_GPU_TCU] = &acm_gpu_tcu,
1540 [MASTER_SYS_TCU] = &acm_sys_tcu,
1541 [MASTER_GEM_NOC_CFG] = &qhm_gemnoc_cfg,
1542 [MASTER_GFX3D] = &qnm_gpu,
1543 [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf,
1544 [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf,
1545 [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc,
1546 [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf,
1547 [SLAVE_MSS_PROC_MS_MPU_CFG] = &qhs_mdsp_ms_mpu_cfg,
1548 [SLAVE_GEM_NOC_SNOC] = &qns_gem_noc_snoc,
1549 [SLAVE_LLCC] = &qns_llcc,
1550 [SLAVE_MEM_NOC_PCIE_SNOC] = &qns_sys_pcie,
1551 [SLAVE_SERVICE_GEM_NOC] = &srvc_gemnoc,
1552};
1553
1554static const struct regmap_config qcs615_gem_noc_regmap_config = {
1555 .reg_bits = 32,
1556 .reg_stride = 4,
1557 .val_bits = 32,
1558 .max_register = 0x3e200,
1559 .fast_io = true,
1560};
1561
1562static const struct qcom_icc_desc qcs615_gem_noc = {
1563 .config = &qcs615_gem_noc_regmap_config,
1564 .nodes = gem_noc_nodes,
1565 .num_nodes = ARRAY_SIZE(gem_noc_nodes),
1566 .bcms = gem_noc_bcms,
1567 .num_bcms = ARRAY_SIZE(gem_noc_bcms),
1568};
1569
1570static struct qcom_icc_bcm * const mc_virt_bcms[] = {
1571 &bcm_acv,
1572 &bcm_mc0,
1573};
1574
1575static struct qcom_icc_node * const mc_virt_nodes[] = {
1576 [MASTER_LLCC] = &llcc_mc,
1577 [SLAVE_EBI1] = &ebi,
1578};
1579
1580static const struct qcom_icc_desc qcs615_mc_virt = {
1581 .nodes = mc_virt_nodes,
1582 .num_nodes = ARRAY_SIZE(mc_virt_nodes),
1583 .bcms = mc_virt_bcms,
1584 .num_bcms = ARRAY_SIZE(mc_virt_bcms),
1585};
1586
1587static struct qcom_icc_bcm * const mmss_noc_bcms[] = {
1588 &bcm_mm0,
1589 &bcm_mm1,
1590 &bcm_mm2,
1591 &bcm_mm3,
1592};
1593
1594static struct qcom_icc_node * const mmss_noc_nodes[] = {
1595 [MASTER_CNOC_MNOC_CFG] = &qhm_mnoc_cfg,
1596 [MASTER_CAMNOC_HF0] = &qxm_camnoc_hf0,
1597 [MASTER_CAMNOC_HF1] = &qxm_camnoc_hf1,
1598 [MASTER_CAMNOC_SF] = &qxm_camnoc_sf,
1599 [MASTER_MDP0] = &qxm_mdp0,
1600 [MASTER_ROTATOR] = &qxm_rot,
1601 [MASTER_VIDEO_P0] = &qxm_venus0,
1602 [MASTER_VIDEO_PROC] = &qxm_venus_arm9,
1603 [SLAVE_MNOC_SF_MEM_NOC] = &qns2_mem_noc,
1604 [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf,
1605 [SLAVE_SERVICE_MNOC] = &srvc_mnoc,
1606};
1607
1608static const struct regmap_config qcs615_mmss_noc_regmap_config = {
1609 .reg_bits = 32,
1610 .reg_stride = 4,
1611 .val_bits = 32,
1612 .max_register = 0x1c100,
1613 .fast_io = true,
1614};
1615
1616static const struct qcom_icc_desc qcs615_mmss_noc = {
1617 .config = &qcs615_mmss_noc_regmap_config,
1618 .nodes = mmss_noc_nodes,
1619 .num_nodes = ARRAY_SIZE(mmss_noc_nodes),
1620 .bcms = mmss_noc_bcms,
1621 .num_bcms = ARRAY_SIZE(mmss_noc_bcms),
1622};
1623
1624static struct qcom_icc_bcm * const system_noc_bcms[] = {
1625 &bcm_sn0,
1626 &bcm_sn1,
1627 &bcm_sn2,
1628 &bcm_sn3,
1629 &bcm_sn4,
1630 &bcm_sn5,
1631 &bcm_sn8,
1632 &bcm_sn9,
1633 &bcm_sn12,
1634 &bcm_sn13,
1635 &bcm_sn15,
1636};
1637
1638static struct qcom_icc_node * const system_noc_nodes[] = {
1639 [MASTER_SNOC_CFG] = &qhm_snoc_cfg,
1640 [MASTER_A1NOC_SNOC] = &qnm_aggre1_noc,
1641 [MASTER_GEM_NOC_SNOC] = &qnm_gemnoc,
1642 [MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie,
1643 [MASTER_LPASS_ANOC] = &qnm_lpass_anoc,
1644 [MASTER_ANOC_PCIE_SNOC] = &qnm_pcie_anoc,
1645 [MASTER_PIMEM] = &qxm_pimem,
1646 [MASTER_GIC] = &xm_gic,
1647 [SLAVE_APPSS] = &qhs_apss,
1648 [SLAVE_SNOC_CNOC] = &qns_cnoc,
1649 [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf,
1650 [SLAVE_SNOC_MEM_NOC_GC] = &qns_memnoc_gc,
1651 [SLAVE_IMEM] = &qxs_imem,
1652 [SLAVE_PIMEM] = &qxs_pimem,
1653 [SLAVE_SERVICE_SNOC] = &srvc_snoc,
1654 [SLAVE_PCIE_0] = &xs_pcie,
1655 [SLAVE_QDSS_STM] = &xs_qdss_stm,
1656 [SLAVE_TCU] = &xs_sys_tcu_cfg,
1657};
1658
1659static const struct regmap_config qcs615_system_noc_regmap_config = {
1660 .reg_bits = 32,
1661 .reg_stride = 4,
1662 .val_bits = 32,
1663 .max_register = 0x1f300,
1664 .fast_io = true,
1665};
1666
1667static const struct qcom_icc_desc qcs615_system_noc = {
1668 .config = &qcs615_system_noc_regmap_config,
1669 .nodes = system_noc_nodes,
1670 .num_nodes = ARRAY_SIZE(system_noc_nodes),
1671 .bcms = system_noc_bcms,
1672 .num_bcms = ARRAY_SIZE(system_noc_bcms),
1673};
1674
1675static const struct of_device_id qnoc_of_match[] = {
1676 { .compatible = "qcom,qcs615-aggre1-noc",
1677 .data = &qcs615_aggre1_noc},
1678 { .compatible = "qcom,qcs615-camnoc-virt",
1679 .data = &qcs615_camnoc_virt},
1680 { .compatible = "qcom,qcs615-config-noc",
1681 .data = &qcs615_config_noc},
1682 { .compatible = "qcom,qcs615-dc-noc",
1683 .data = &qcs615_dc_noc},
1684 { .compatible = "qcom,qcs615-gem-noc",
1685 .data = &qcs615_gem_noc},
1686 { .compatible = "qcom,qcs615-mc-virt",
1687 .data = &qcs615_mc_virt},
1688 { .compatible = "qcom,qcs615-mmss-noc",
1689 .data = &qcs615_mmss_noc},
1690 { .compatible = "qcom,qcs615-system-noc",
1691 .data = &qcs615_system_noc},
1692 { }
1693};
1694MODULE_DEVICE_TABLE(of, qnoc_of_match);
1695
1696static struct platform_driver qnoc_driver = {
1697 .probe = qcom_icc_rpmh_probe,
1698 .remove = qcom_icc_rpmh_remove,
1699 .driver = {
1700 .name = "qnoc-qcs615",
1701 .of_match_table = qnoc_of_match,
1702 .sync_state = icc_sync_state,
1703 },
1704};
1705
1706static int __init qnoc_driver_init(void)
1707{
1708 return platform_driver_register(&qnoc_driver);
1709}
1710core_initcall(qnoc_driver_init);
1711
1712static void __exit qnoc_driver_exit(void)
1713{
1714 platform_driver_unregister(&qnoc_driver);
1715}
1716module_exit(qnoc_driver_exit);
1717
1718MODULE_DESCRIPTION("qcs615 NoC driver");
1719MODULE_LICENSE("GPL");