Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
4 *
5 */
6
7#include <linux/device.h>
8#include <linux/interconnect.h>
9#include <linux/interconnect-provider.h>
10#include <linux/module.h>
11#include <linux/of_platform.h>
12#include <dt-bindings/interconnect/qcom,qcs8300-rpmh.h>
13
14#include "bcm-voter.h"
15#include "icc-rpmh.h"
16
17static struct qcom_icc_node qxm_qup3;
18static struct qcom_icc_node xm_emac_0;
19static struct qcom_icc_node xm_sdc1;
20static struct qcom_icc_node xm_ufs_mem;
21static struct qcom_icc_node xm_usb2_2;
22static struct qcom_icc_node xm_usb3_0;
23static struct qcom_icc_node qhm_qdss_bam;
24static struct qcom_icc_node qhm_qup0;
25static struct qcom_icc_node qhm_qup1;
26static struct qcom_icc_node qnm_cnoc_datapath;
27static struct qcom_icc_node qxm_crypto_0;
28static struct qcom_icc_node qxm_crypto_1;
29static struct qcom_icc_node qxm_ipa;
30static struct qcom_icc_node xm_qdss_etr_0;
31static struct qcom_icc_node xm_qdss_etr_1;
32static struct qcom_icc_node qup0_core_master;
33static struct qcom_icc_node qup1_core_master;
34static struct qcom_icc_node qup3_core_master;
35static struct qcom_icc_node qnm_gemnoc_cnoc;
36static struct qcom_icc_node qnm_gemnoc_pcie;
37static struct qcom_icc_node qnm_cnoc_dc_noc;
38static struct qcom_icc_node alm_gpu_tcu;
39static struct qcom_icc_node alm_pcie_tcu;
40static struct qcom_icc_node alm_sys_tcu;
41static struct qcom_icc_node chm_apps;
42static struct qcom_icc_node qnm_cmpnoc0;
43static struct qcom_icc_node qnm_gemnoc_cfg;
44static struct qcom_icc_node qnm_gpdsp_sail;
45static struct qcom_icc_node qnm_gpu;
46static struct qcom_icc_node qnm_mnoc_hf;
47static struct qcom_icc_node qnm_mnoc_sf;
48static struct qcom_icc_node qnm_pcie;
49static struct qcom_icc_node qnm_snoc_gc;
50static struct qcom_icc_node qnm_snoc_sf;
51static struct qcom_icc_node qnm_sailss_md0;
52static struct qcom_icc_node qxm_dsp0;
53static struct qcom_icc_node qhm_config_noc;
54static struct qcom_icc_node qxm_lpass_dsp;
55static struct qcom_icc_node llcc_mc;
56static struct qcom_icc_node qnm_camnoc_hf;
57static struct qcom_icc_node qnm_camnoc_icp;
58static struct qcom_icc_node qnm_camnoc_sf;
59static struct qcom_icc_node qnm_mdp0_0;
60static struct qcom_icc_node qnm_mdp0_1;
61static struct qcom_icc_node qnm_mnoc_hf_cfg;
62static struct qcom_icc_node qnm_mnoc_sf_cfg;
63static struct qcom_icc_node qnm_video0;
64static struct qcom_icc_node qnm_video_cvp;
65static struct qcom_icc_node qnm_video_v_cpu;
66static struct qcom_icc_node qhm_nsp_noc_config;
67static struct qcom_icc_node qxm_nsp;
68static struct qcom_icc_node xm_pcie3_0;
69static struct qcom_icc_node xm_pcie3_1;
70static struct qcom_icc_node qhm_gic;
71static struct qcom_icc_node qnm_aggre1_noc;
72static struct qcom_icc_node qnm_aggre2_noc;
73static struct qcom_icc_node qnm_lpass_noc;
74static struct qcom_icc_node qnm_snoc_cfg;
75static struct qcom_icc_node qxm_pimem;
76static struct qcom_icc_node xm_gic;
77static struct qcom_icc_node qns_a1noc_snoc;
78static struct qcom_icc_node qns_a2noc_snoc;
79static struct qcom_icc_node qup0_core_slave;
80static struct qcom_icc_node qup1_core_slave;
81static struct qcom_icc_node qup3_core_slave;
82static struct qcom_icc_node qhs_ahb2phy2;
83static struct qcom_icc_node qhs_ahb2phy3;
84static struct qcom_icc_node qhs_anoc_throttle_cfg;
85static struct qcom_icc_node qhs_aoss;
86static struct qcom_icc_node qhs_apss;
87static struct qcom_icc_node qhs_boot_rom;
88static struct qcom_icc_node qhs_camera_cfg;
89static struct qcom_icc_node qhs_camera_nrt_throttle_cfg;
90static struct qcom_icc_node qhs_camera_rt_throttle_cfg;
91static struct qcom_icc_node qhs_clk_ctl;
92static struct qcom_icc_node qhs_compute0_cfg;
93static struct qcom_icc_node qhs_cpr_cx;
94static struct qcom_icc_node qhs_cpr_mmcx;
95static struct qcom_icc_node qhs_cpr_mx;
96static struct qcom_icc_node qhs_cpr_nspcx;
97static struct qcom_icc_node qhs_cpr_nsphmx;
98static struct qcom_icc_node qhs_crypto0_cfg;
99static struct qcom_icc_node qhs_cx_rdpm;
100static struct qcom_icc_node qhs_display0_cfg;
101static struct qcom_icc_node qhs_display0_rt_throttle_cfg;
102static struct qcom_icc_node qhs_emac0_cfg;
103static struct qcom_icc_node qhs_gp_dsp0_cfg;
104static struct qcom_icc_node qhs_gpdsp0_throttle_cfg;
105static struct qcom_icc_node qhs_gpu_tcu_throttle_cfg;
106static struct qcom_icc_node qhs_gpuss_cfg;
107static struct qcom_icc_node qhs_hwkm;
108static struct qcom_icc_node qhs_imem_cfg;
109static struct qcom_icc_node qhs_ipa;
110static struct qcom_icc_node qhs_ipc_router;
111static struct qcom_icc_node qhs_lpass_cfg;
112static struct qcom_icc_node qhs_lpass_throttle_cfg;
113static struct qcom_icc_node qhs_mx_rdpm;
114static struct qcom_icc_node qhs_mxc_rdpm;
115static struct qcom_icc_node qhs_pcie0_cfg;
116static struct qcom_icc_node qhs_pcie1_cfg;
117static struct qcom_icc_node qhs_pcie_tcu_throttle_cfg;
118static struct qcom_icc_node qhs_pcie_throttle_cfg;
119static struct qcom_icc_node qhs_pdm;
120static struct qcom_icc_node qhs_pimem_cfg;
121static struct qcom_icc_node qhs_pke_wrapper_cfg;
122static struct qcom_icc_node qhs_qdss_cfg;
123static struct qcom_icc_node qhs_qm_cfg;
124static struct qcom_icc_node qhs_qm_mpu_cfg;
125static struct qcom_icc_node qhs_qup0;
126static struct qcom_icc_node qhs_qup1;
127static struct qcom_icc_node qhs_qup3;
128static struct qcom_icc_node qhs_sail_throttle_cfg;
129static struct qcom_icc_node qhs_sdc1;
130static struct qcom_icc_node qhs_security;
131static struct qcom_icc_node qhs_snoc_throttle_cfg;
132static struct qcom_icc_node qhs_tcsr;
133static struct qcom_icc_node qhs_tlmm;
134static struct qcom_icc_node qhs_tsc_cfg;
135static struct qcom_icc_node qhs_ufs_mem_cfg;
136static struct qcom_icc_node qhs_usb2_0;
137static struct qcom_icc_node qhs_usb3_0;
138static struct qcom_icc_node qhs_venus_cfg;
139static struct qcom_icc_node qhs_venus_cvp_throttle_cfg;
140static struct qcom_icc_node qhs_venus_v_cpu_throttle_cfg;
141static struct qcom_icc_node qhs_venus_vcodec_throttle_cfg;
142static struct qcom_icc_node qns_ddrss_cfg;
143static struct qcom_icc_node qns_gpdsp_noc_cfg;
144static struct qcom_icc_node qns_mnoc_hf_cfg;
145static struct qcom_icc_node qns_mnoc_sf_cfg;
146static struct qcom_icc_node qns_pcie_anoc_cfg;
147static struct qcom_icc_node qns_snoc_cfg;
148static struct qcom_icc_node qxs_boot_imem;
149static struct qcom_icc_node qxs_imem;
150static struct qcom_icc_node qxs_pimem;
151static struct qcom_icc_node xs_pcie_0;
152static struct qcom_icc_node xs_pcie_1;
153static struct qcom_icc_node xs_qdss_stm;
154static struct qcom_icc_node xs_sys_tcu_cfg;
155static struct qcom_icc_node qhs_llcc;
156static struct qcom_icc_node qns_gemnoc;
157static struct qcom_icc_node qns_gem_noc_cnoc;
158static struct qcom_icc_node qns_llcc;
159static struct qcom_icc_node qns_pcie;
160static struct qcom_icc_node srvc_even_gemnoc;
161static struct qcom_icc_node srvc_odd_gemnoc;
162static struct qcom_icc_node srvc_sys_gemnoc;
163static struct qcom_icc_node srvc_sys_gemnoc_2;
164static struct qcom_icc_node qns_gp_dsp_sail_noc;
165static struct qcom_icc_node qhs_lpass_core;
166static struct qcom_icc_node qhs_lpass_lpi;
167static struct qcom_icc_node qhs_lpass_mpu;
168static struct qcom_icc_node qhs_lpass_top;
169static struct qcom_icc_node qns_sysnoc;
170static struct qcom_icc_node srvc_niu_aml_noc;
171static struct qcom_icc_node srvc_niu_lpass_agnoc;
172static struct qcom_icc_node ebi;
173static struct qcom_icc_node qns_mem_noc_hf;
174static struct qcom_icc_node qns_mem_noc_sf;
175static struct qcom_icc_node srvc_mnoc_hf;
176static struct qcom_icc_node srvc_mnoc_sf;
177static struct qcom_icc_node qns_hcp;
178static struct qcom_icc_node qns_nsp_gemnoc;
179static struct qcom_icc_node service_nsp_noc;
180static struct qcom_icc_node qns_pcie_mem_noc;
181static struct qcom_icc_node qns_gemnoc_gc;
182static struct qcom_icc_node qns_gemnoc_sf;
183static struct qcom_icc_node srvc_snoc;
184
185static struct qcom_icc_node qxm_qup3 = {
186 .name = "qxm_qup3",
187 .channels = 1,
188 .buswidth = 8,
189 .qosbox = &(const struct qcom_icc_qosbox) {
190 .num_ports = 1,
191 .port_offsets = { 0x11000 },
192 .prio_fwd_disable = 1,
193 .prio = 2,
194 .urg_fwd = 0,
195 },
196 .num_links = 1,
197 .link_nodes = { &qns_a1noc_snoc },
198};
199
200static struct qcom_icc_node xm_emac_0 = {
201 .name = "xm_emac_0",
202 .channels = 1,
203 .buswidth = 8,
204 .qosbox = &(const struct qcom_icc_qosbox) {
205 .num_ports = 1,
206 .port_offsets = { 0x12000 },
207 .prio_fwd_disable = 1,
208 .prio = 2,
209 .urg_fwd = 0,
210 },
211 .num_links = 1,
212 .link_nodes = { &qns_a1noc_snoc },
213};
214
215static struct qcom_icc_node xm_sdc1 = {
216 .name = "xm_sdc1",
217 .channels = 1,
218 .buswidth = 8,
219 .qosbox = &(const struct qcom_icc_qosbox) {
220 .num_ports = 1,
221 .port_offsets = { 0x14000 },
222 .prio_fwd_disable = 1,
223 .prio = 2,
224 .urg_fwd = 0,
225 },
226 .num_links = 1,
227 .link_nodes = { &qns_a1noc_snoc },
228};
229
230static struct qcom_icc_node xm_ufs_mem = {
231 .name = "xm_ufs_mem",
232 .channels = 1,
233 .buswidth = 8,
234 .qosbox = &(const struct qcom_icc_qosbox) {
235 .num_ports = 1,
236 .port_offsets = { 0x15000 },
237 .prio_fwd_disable = 1,
238 .prio = 2,
239 .urg_fwd = 0,
240 },
241 .num_links = 1,
242 .link_nodes = { &qns_a1noc_snoc },
243};
244
245static struct qcom_icc_node xm_usb2_2 = {
246 .name = "xm_usb2_2",
247 .channels = 1,
248 .buswidth = 8,
249 .qosbox = &(const struct qcom_icc_qosbox) {
250 .num_ports = 1,
251 .port_offsets = { 0x16000 },
252 .prio_fwd_disable = 1,
253 .prio = 2,
254 .urg_fwd = 0,
255 },
256 .num_links = 1,
257 .link_nodes = { &qns_a1noc_snoc },
258};
259
260static struct qcom_icc_node xm_usb3_0 = {
261 .name = "xm_usb3_0",
262 .channels = 1,
263 .buswidth = 8,
264 .qosbox = &(const struct qcom_icc_qosbox) {
265 .num_ports = 1,
266 .port_offsets = { 0x17000 },
267 .prio_fwd_disable = 1,
268 .prio = 2,
269 .urg_fwd = 0,
270 },
271 .num_links = 1,
272 .link_nodes = { &qns_a1noc_snoc },
273};
274
275static struct qcom_icc_node qhm_qdss_bam = {
276 .name = "qhm_qdss_bam",
277 .channels = 1,
278 .buswidth = 4,
279 .qosbox = &(const struct qcom_icc_qosbox) {
280 .num_ports = 1,
281 .port_offsets = { 0x14000 },
282 .prio_fwd_disable = 1,
283 .prio = 2,
284 .urg_fwd = 0,
285 },
286 .num_links = 1,
287 .link_nodes = { &qns_a2noc_snoc },
288};
289
290static struct qcom_icc_node qhm_qup0 = {
291 .name = "qhm_qup0",
292 .channels = 1,
293 .buswidth = 4,
294 .qosbox = &(const struct qcom_icc_qosbox) {
295 .num_ports = 1,
296 .port_offsets = { 0x17000 },
297 .prio_fwd_disable = 1,
298 .prio = 2,
299 .urg_fwd = 0,
300 },
301 .num_links = 1,
302 .link_nodes = { &qns_a2noc_snoc },
303};
304
305static struct qcom_icc_node qhm_qup1 = {
306 .name = "qhm_qup1",
307 .channels = 1,
308 .buswidth = 4,
309 .qosbox = &(const struct qcom_icc_qosbox) {
310 .num_ports = 1,
311 .port_offsets = { 0x12000 },
312 .prio_fwd_disable = 1,
313 .prio = 2,
314 .urg_fwd = 0,
315 },
316 .num_links = 1,
317 .link_nodes = { &qns_a2noc_snoc },
318};
319
320static struct qcom_icc_node qnm_cnoc_datapath = {
321 .name = "qnm_cnoc_datapath",
322 .channels = 1,
323 .buswidth = 8,
324 .qosbox = &(const struct qcom_icc_qosbox) {
325 .num_ports = 1,
326 .port_offsets = { 0x16000 },
327 .prio_fwd_disable = 1,
328 .prio = 2,
329 .urg_fwd = 0,
330 },
331 .num_links = 1,
332 .link_nodes = { &qns_a2noc_snoc },
333};
334
335static struct qcom_icc_node qxm_crypto_0 = {
336 .name = "qxm_crypto_0",
337 .channels = 1,
338 .buswidth = 8,
339 .qosbox = &(const struct qcom_icc_qosbox) {
340 .num_ports = 1,
341 .port_offsets = { 0x18000 },
342 .prio_fwd_disable = 1,
343 .prio = 2,
344 .urg_fwd = 0,
345 },
346 .num_links = 1,
347 .link_nodes = { &qns_a2noc_snoc },
348};
349
350static struct qcom_icc_node qxm_crypto_1 = {
351 .name = "qxm_crypto_1",
352 .channels = 1,
353 .buswidth = 8,
354 .qosbox = &(const struct qcom_icc_qosbox) {
355 .num_ports = 1,
356 .port_offsets = { 0x1a000 },
357 .prio_fwd_disable = 1,
358 .prio = 2,
359 .urg_fwd = 0,
360 },
361 .num_links = 1,
362 .link_nodes = { &qns_a2noc_snoc },
363};
364
365static struct qcom_icc_node qxm_ipa = {
366 .name = "qxm_ipa",
367 .channels = 1,
368 .buswidth = 8,
369 .qosbox = &(const struct qcom_icc_qosbox) {
370 .num_ports = 1,
371 .port_offsets = { 0x11000 },
372 .prio_fwd_disable = 1,
373 .prio = 2,
374 .urg_fwd = 0,
375 },
376 .num_links = 1,
377 .link_nodes = { &qns_a2noc_snoc },
378};
379
380static struct qcom_icc_node xm_qdss_etr_0 = {
381 .name = "xm_qdss_etr_0",
382 .channels = 1,
383 .buswidth = 8,
384 .qosbox = &(const struct qcom_icc_qosbox) {
385 .num_ports = 1,
386 .port_offsets = { 0x13000 },
387 .prio_fwd_disable = 1,
388 .prio = 2,
389 .urg_fwd = 0,
390 },
391 .num_links = 1,
392 .link_nodes = { &qns_a2noc_snoc },
393};
394
395static struct qcom_icc_node xm_qdss_etr_1 = {
396 .name = "xm_qdss_etr_1",
397 .channels = 1,
398 .buswidth = 8,
399 .qosbox = &(const struct qcom_icc_qosbox) {
400 .num_ports = 1,
401 .port_offsets = { 0x19000 },
402 .prio_fwd_disable = 1,
403 .prio = 2,
404 .urg_fwd = 0,
405 },
406 .num_links = 1,
407 .link_nodes = { &qns_a2noc_snoc },
408};
409
410static struct qcom_icc_node qup0_core_master = {
411 .name = "qup0_core_master",
412 .channels = 1,
413 .buswidth = 4,
414 .num_links = 1,
415 .link_nodes = { &qup0_core_slave },
416};
417
418static struct qcom_icc_node qup1_core_master = {
419 .name = "qup1_core_master",
420 .channels = 1,
421 .buswidth = 4,
422 .num_links = 1,
423 .link_nodes = { &qup1_core_slave },
424};
425
426static struct qcom_icc_node qup3_core_master = {
427 .name = "qup3_core_master",
428 .channels = 1,
429 .buswidth = 4,
430 .num_links = 1,
431 .link_nodes = { &qup3_core_slave },
432};
433
434static struct qcom_icc_node qnm_gemnoc_cnoc = {
435 .name = "qnm_gemnoc_cnoc",
436 .channels = 1,
437 .buswidth = 16,
438 .num_links = 71,
439 .link_nodes = { &qhs_ahb2phy2, &qhs_ahb2phy3,
440 &qhs_anoc_throttle_cfg, &qhs_aoss,
441 &qhs_apss, &qhs_boot_rom,
442 &qhs_camera_cfg, &qhs_camera_nrt_throttle_cfg,
443 &qhs_camera_rt_throttle_cfg, &qhs_clk_ctl,
444 &qhs_compute0_cfg, &qhs_cpr_cx,
445 &qhs_cpr_mmcx, &qhs_cpr_mx,
446 &qhs_cpr_nspcx, &qhs_cpr_nsphmx,
447 &qhs_crypto0_cfg, &qhs_cx_rdpm,
448 &qhs_display0_cfg, &qhs_display0_rt_throttle_cfg,
449 &qhs_emac0_cfg, &qhs_gp_dsp0_cfg,
450 &qhs_gpdsp0_throttle_cfg, &qhs_gpu_tcu_throttle_cfg,
451 &qhs_gpuss_cfg, &qhs_hwkm,
452 &qhs_imem_cfg, &qhs_ipa,
453 &qhs_ipc_router, &qhs_lpass_cfg,
454 &qhs_lpass_throttle_cfg, &qhs_mx_rdpm,
455 &qhs_mxc_rdpm, &qhs_pcie0_cfg,
456 &qhs_pcie1_cfg, &qhs_pcie_tcu_throttle_cfg,
457 &qhs_pcie_throttle_cfg, &qhs_pdm,
458 &qhs_pimem_cfg, &qhs_pke_wrapper_cfg,
459 &qhs_qdss_cfg, &qhs_qm_cfg,
460 &qhs_qm_mpu_cfg, &qhs_qup0,
461 &qhs_qup1, &qhs_qup3,
462 &qhs_sail_throttle_cfg, &qhs_sdc1,
463 &qhs_security, &qhs_snoc_throttle_cfg,
464 &qhs_tcsr, &qhs_tlmm,
465 &qhs_tsc_cfg, &qhs_ufs_mem_cfg,
466 &qhs_usb2_0, &qhs_usb3_0,
467 &qhs_venus_cfg, &qhs_venus_cvp_throttle_cfg,
468 &qhs_venus_v_cpu_throttle_cfg,
469 &qhs_venus_vcodec_throttle_cfg,
470 &qns_ddrss_cfg, &qns_gpdsp_noc_cfg,
471 &qns_mnoc_hf_cfg, &qns_mnoc_sf_cfg,
472 &qns_pcie_anoc_cfg, &qns_snoc_cfg,
473 &qxs_boot_imem, &qxs_imem,
474 &qxs_pimem, &xs_qdss_stm,
475 &xs_sys_tcu_cfg },
476};
477
478static struct qcom_icc_node qnm_gemnoc_pcie = {
479 .name = "qnm_gemnoc_pcie",
480 .channels = 1,
481 .buswidth = 16,
482 .num_links = 2,
483 .link_nodes = { &xs_pcie_0, &xs_pcie_1 },
484};
485
486static struct qcom_icc_node qnm_cnoc_dc_noc = {
487 .name = "qnm_cnoc_dc_noc",
488 .channels = 1,
489 .buswidth = 4,
490 .num_links = 2,
491 .link_nodes = { &qhs_llcc, &qns_gemnoc },
492};
493
494static struct qcom_icc_node alm_gpu_tcu = {
495 .name = "alm_gpu_tcu",
496 .channels = 1,
497 .buswidth = 8,
498 .qosbox = &(const struct qcom_icc_qosbox) {
499 .num_ports = 1,
500 .port_offsets = { 0xaf000 },
501 .prio_fwd_disable = 1,
502 .prio = 1,
503 .urg_fwd = 0,
504 },
505 .num_links = 2,
506 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
507};
508
509static struct qcom_icc_node alm_pcie_tcu = {
510 .name = "alm_pcie_tcu",
511 .channels = 1,
512 .buswidth = 8,
513 .qosbox = &(const struct qcom_icc_qosbox) {
514 .num_ports = 1,
515 .port_offsets = { 0xb0000 },
516 .prio_fwd_disable = 1,
517 .prio = 3,
518 .urg_fwd = 0,
519 },
520 .num_links = 2,
521 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
522};
523
524static struct qcom_icc_node alm_sys_tcu = {
525 .name = "alm_sys_tcu",
526 .channels = 1,
527 .buswidth = 8,
528 .qosbox = &(const struct qcom_icc_qosbox) {
529 .num_ports = 1,
530 .port_offsets = { 0xb1000 },
531 .prio_fwd_disable = 1,
532 .prio = 6,
533 .urg_fwd = 0,
534 },
535 .num_links = 2,
536 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
537};
538
539static struct qcom_icc_node chm_apps = {
540 .name = "chm_apps",
541 .channels = 4,
542 .buswidth = 32,
543 .num_links = 3,
544 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
545 &qns_pcie },
546};
547
548static struct qcom_icc_node qnm_cmpnoc0 = {
549 .name = "qnm_cmpnoc0",
550 .channels = 2,
551 .buswidth = 32,
552 .qosbox = &(const struct qcom_icc_qosbox) {
553 .num_ports = 2,
554 .port_offsets = { 0xf6000, 0xf7000 },
555 .prio_fwd_disable = 1,
556 .prio = 0,
557 .urg_fwd = 0,
558 },
559 .num_links = 2,
560 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
561};
562
563static struct qcom_icc_node qnm_gemnoc_cfg = {
564 .name = "qnm_gemnoc_cfg",
565 .channels = 1,
566 .buswidth = 4,
567 .num_links = 4,
568 .link_nodes = { &srvc_even_gemnoc, &srvc_odd_gemnoc,
569 &srvc_sys_gemnoc, &srvc_sys_gemnoc_2 },
570};
571
572static struct qcom_icc_node qnm_gpdsp_sail = {
573 .name = "qnm_gpdsp_sail",
574 .channels = 1,
575 .buswidth = 16,
576 .num_links = 2,
577 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
578};
579
580static struct qcom_icc_node qnm_gpu = {
581 .name = "qnm_gpu",
582 .channels = 2,
583 .buswidth = 32,
584 .qosbox = &(const struct qcom_icc_qosbox) {
585 .num_ports = 2,
586 .port_offsets = { 0xf0000, 0xf1000 },
587 .prio_fwd_disable = 1,
588 .prio = 0,
589 .urg_fwd = 0,
590 },
591 .num_links = 2,
592 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
593};
594
595static struct qcom_icc_node qnm_mnoc_hf = {
596 .name = "qnm_mnoc_hf",
597 .channels = 2,
598 .buswidth = 32,
599 .qosbox = &(const struct qcom_icc_qosbox) {
600 .num_ports = 2,
601 .port_offsets = { 0xf2000, 0xf3000 },
602 .prio_fwd_disable = 0,
603 .prio = 0,
604 .urg_fwd = 1,
605 },
606 .num_links = 2,
607 .link_nodes = { &qns_llcc, &qns_pcie },
608};
609
610static struct qcom_icc_node qnm_mnoc_sf = {
611 .name = "qnm_mnoc_sf",
612 .channels = 2,
613 .buswidth = 32,
614 .qosbox = &(const struct qcom_icc_qosbox) {
615 .num_ports = 2,
616 .port_offsets = { 0xf4000, 0xf5000 },
617 .prio_fwd_disable = 0,
618 .prio = 0,
619 .urg_fwd = 1,
620 },
621 .num_links = 3,
622 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
623 &qns_pcie },
624};
625
626static struct qcom_icc_node qnm_pcie = {
627 .name = "qnm_pcie",
628 .channels = 1,
629 .buswidth = 32,
630 .qosbox = &(const struct qcom_icc_qosbox) {
631 .num_ports = 1,
632 .port_offsets = { 0xb3000 },
633 .prio_fwd_disable = 1,
634 .prio = 2,
635 .urg_fwd = 0,
636 },
637 .num_links = 2,
638 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
639};
640
641static struct qcom_icc_node qnm_snoc_gc = {
642 .name = "qnm_snoc_gc",
643 .channels = 1,
644 .buswidth = 8,
645 .qosbox = &(const struct qcom_icc_qosbox) {
646 .num_ports = 1,
647 .port_offsets = { 0xb4000 },
648 .prio_fwd_disable = 0,
649 .prio = 0,
650 .urg_fwd = 1,
651 },
652 .num_links = 1,
653 .link_nodes = { &qns_llcc },
654};
655
656static struct qcom_icc_node qnm_snoc_sf = {
657 .name = "qnm_snoc_sf",
658 .channels = 1,
659 .buswidth = 16,
660 .qosbox = &(const struct qcom_icc_qosbox) {
661 .num_ports = 1,
662 .port_offsets = { 0xb5000 },
663 .prio_fwd_disable = 0,
664 .prio = 0,
665 .urg_fwd = 1,
666 },
667 .num_links = 3,
668 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
669 &qns_pcie },
670};
671
672static struct qcom_icc_node qnm_sailss_md0 = {
673 .name = "qnm_sailss_md0",
674 .channels = 1,
675 .buswidth = 16,
676 .num_links = 1,
677 .link_nodes = { &qns_gp_dsp_sail_noc },
678};
679
680static struct qcom_icc_node qxm_dsp0 = {
681 .name = "qxm_dsp0",
682 .channels = 1,
683 .buswidth = 16,
684 .num_links = 1,
685 .link_nodes = { &qns_gp_dsp_sail_noc },
686};
687
688static struct qcom_icc_node qhm_config_noc = {
689 .name = "qhm_config_noc",
690 .channels = 1,
691 .buswidth = 4,
692 .num_links = 6,
693 .link_nodes = { &qhs_lpass_core, &qhs_lpass_lpi,
694 &qhs_lpass_mpu, &qhs_lpass_top,
695 &srvc_niu_aml_noc, &srvc_niu_lpass_agnoc },
696};
697
698static struct qcom_icc_node qxm_lpass_dsp = {
699 .name = "qxm_lpass_dsp",
700 .channels = 1,
701 .buswidth = 8,
702 .num_links = 4,
703 .link_nodes = { &qhs_lpass_top, &qns_sysnoc,
704 &srvc_niu_aml_noc, &srvc_niu_lpass_agnoc },
705};
706
707static struct qcom_icc_node llcc_mc = {
708 .name = "llcc_mc",
709 .channels = 8,
710 .buswidth = 4,
711 .num_links = 1,
712 .link_nodes = { &ebi },
713};
714
715static struct qcom_icc_node qnm_camnoc_hf = {
716 .name = "qnm_camnoc_hf",
717 .channels = 1,
718 .buswidth = 32,
719 .qosbox = &(const struct qcom_icc_qosbox) {
720 .num_ports = 1,
721 .port_offsets = { 0xa000 },
722 .prio_fwd_disable = 0,
723 .prio = 0,
724 .urg_fwd = 1,
725 },
726 .num_links = 1,
727 .link_nodes = { &qns_mem_noc_hf },
728};
729
730static struct qcom_icc_node qnm_camnoc_icp = {
731 .name = "qnm_camnoc_icp",
732 .channels = 1,
733 .buswidth = 8,
734 .qosbox = &(const struct qcom_icc_qosbox) {
735 .num_ports = 1,
736 .port_offsets = { 0x2a000 },
737 .prio_fwd_disable = 0,
738 .prio = 0,
739 .urg_fwd = 1,
740 },
741 .num_links = 1,
742 .link_nodes = { &qns_mem_noc_sf },
743};
744
745static struct qcom_icc_node qnm_camnoc_sf = {
746 .name = "qnm_camnoc_sf",
747 .channels = 1,
748 .buswidth = 32,
749 .qosbox = &(const struct qcom_icc_qosbox) {
750 .num_ports = 1,
751 .port_offsets = { 0x2a080 },
752 .prio_fwd_disable = 0,
753 .prio = 0,
754 .urg_fwd = 1,
755 },
756 .num_links = 1,
757 .link_nodes = { &qns_mem_noc_sf },
758};
759
760static struct qcom_icc_node qnm_mdp0_0 = {
761 .name = "qnm_mdp0_0",
762 .channels = 1,
763 .buswidth = 32,
764 .qosbox = &(const struct qcom_icc_qosbox) {
765 .num_ports = 1,
766 .port_offsets = { 0xa080 },
767 .prio_fwd_disable = 0,
768 .prio = 0,
769 .urg_fwd = 1,
770 },
771 .num_links = 1,
772 .link_nodes = { &qns_mem_noc_hf },
773};
774
775static struct qcom_icc_node qnm_mdp0_1 = {
776 .name = "qnm_mdp0_1",
777 .channels = 1,
778 .buswidth = 32,
779 .qosbox = &(const struct qcom_icc_qosbox) {
780 .num_ports = 1,
781 .port_offsets = { 0xa180 },
782 .prio_fwd_disable = 0,
783 .prio = 0,
784 .urg_fwd = 1,
785 },
786 .num_links = 1,
787 .link_nodes = { &qns_mem_noc_hf },
788};
789
790static struct qcom_icc_node qnm_mnoc_hf_cfg = {
791 .name = "qnm_mnoc_hf_cfg",
792 .channels = 1,
793 .buswidth = 4,
794 .num_links = 1,
795 .link_nodes = { &srvc_mnoc_hf },
796};
797
798static struct qcom_icc_node qnm_mnoc_sf_cfg = {
799 .name = "qnm_mnoc_sf_cfg",
800 .channels = 1,
801 .buswidth = 4,
802 .num_links = 1,
803 .link_nodes = { &srvc_mnoc_sf },
804};
805
806static struct qcom_icc_node qnm_video0 = {
807 .name = "qnm_video0",
808 .channels = 1,
809 .buswidth = 32,
810 .qosbox = &(const struct qcom_icc_qosbox) {
811 .num_ports = 1,
812 .port_offsets = { 0x2a100 },
813 .prio_fwd_disable = 0,
814 .prio = 0,
815 .urg_fwd = 1,
816 },
817 .num_links = 1,
818 .link_nodes = { &qns_mem_noc_sf },
819};
820
821static struct qcom_icc_node qnm_video_cvp = {
822 .name = "qnm_video_cvp",
823 .channels = 1,
824 .buswidth = 32,
825 .qosbox = &(const struct qcom_icc_qosbox) {
826 .num_ports = 1,
827 .port_offsets = { 0x2a200 },
828 .prio_fwd_disable = 0,
829 .prio = 0,
830 .urg_fwd = 1,
831 },
832 .num_links = 1,
833 .link_nodes = { &qns_mem_noc_sf },
834};
835
836static struct qcom_icc_node qnm_video_v_cpu = {
837 .name = "qnm_video_v_cpu",
838 .channels = 1,
839 .buswidth = 8,
840 .qosbox = &(const struct qcom_icc_qosbox) {
841 .num_ports = 1,
842 .port_offsets = { 0x2a280 },
843 .prio_fwd_disable = 0,
844 .prio = 0,
845 .urg_fwd = 1,
846 },
847 .num_links = 1,
848 .link_nodes = { &qns_mem_noc_sf },
849};
850
851static struct qcom_icc_node qhm_nsp_noc_config = {
852 .name = "qhm_nsp_noc_config",
853 .channels = 1,
854 .buswidth = 4,
855 .num_links = 1,
856 .link_nodes = { &service_nsp_noc },
857};
858
859static struct qcom_icc_node qxm_nsp = {
860 .name = "qxm_nsp",
861 .channels = 2,
862 .buswidth = 32,
863 .num_links = 2,
864 .link_nodes = { &qns_hcp, &qns_nsp_gemnoc },
865};
866
867static struct qcom_icc_node xm_pcie3_0 = {
868 .name = "xm_pcie3_0",
869 .channels = 1,
870 .buswidth = 16,
871 .qosbox = &(const struct qcom_icc_qosbox) {
872 .num_ports = 1,
873 .port_offsets = { 0xb000 },
874 .prio_fwd_disable = 1,
875 .prio = 2,
876 .urg_fwd = 0,
877 },
878 .num_links = 1,
879 .link_nodes = { &qns_pcie_mem_noc },
880};
881
882static struct qcom_icc_node xm_pcie3_1 = {
883 .name = "xm_pcie3_1",
884 .channels = 1,
885 .buswidth = 32,
886 .qosbox = &(const struct qcom_icc_qosbox) {
887 .num_ports = 1,
888 .port_offsets = { 0xc000 },
889 .prio_fwd_disable = 1,
890 .prio = 2,
891 .urg_fwd = 0,
892 },
893 .num_links = 1,
894 .link_nodes = { &qns_pcie_mem_noc },
895};
896
897static struct qcom_icc_node qhm_gic = {
898 .name = "qhm_gic",
899 .channels = 1,
900 .buswidth = 4,
901 .qosbox = &(const struct qcom_icc_qosbox) {
902 .num_ports = 1,
903 .port_offsets = { 0x14000 },
904 .prio_fwd_disable = 1,
905 .prio = 2,
906 .urg_fwd = 0,
907 },
908 .num_links = 1,
909 .link_nodes = { &qns_gemnoc_sf },
910};
911
912static struct qcom_icc_node qnm_aggre1_noc = {
913 .name = "qnm_aggre1_noc",
914 .channels = 1,
915 .buswidth = 32,
916 .num_links = 1,
917 .link_nodes = { &qns_gemnoc_sf },
918};
919
920static struct qcom_icc_node qnm_aggre2_noc = {
921 .name = "qnm_aggre2_noc",
922 .channels = 1,
923 .buswidth = 16,
924 .num_links = 1,
925 .link_nodes = { &qns_gemnoc_sf },
926};
927
928static struct qcom_icc_node qnm_lpass_noc = {
929 .name = "qnm_lpass_noc",
930 .channels = 1,
931 .buswidth = 16,
932 .qosbox = &(const struct qcom_icc_qosbox) {
933 .num_ports = 1,
934 .port_offsets = { 0x12000 },
935 .prio_fwd_disable = 0,
936 .prio = 0,
937 .urg_fwd = 1,
938 },
939 .num_links = 1,
940 .link_nodes = { &qns_gemnoc_sf },
941};
942
943static struct qcom_icc_node qnm_snoc_cfg = {
944 .name = "qnm_snoc_cfg",
945 .channels = 1,
946 .buswidth = 4,
947 .num_links = 1,
948 .link_nodes = { &srvc_snoc },
949};
950
951static struct qcom_icc_node qxm_pimem = {
952 .name = "qxm_pimem",
953 .channels = 1,
954 .buswidth = 8,
955 .qosbox = &(const struct qcom_icc_qosbox) {
956 .num_ports = 1,
957 .port_offsets = { 0x13000 },
958 .prio_fwd_disable = 1,
959 .prio = 2,
960 .urg_fwd = 0,
961 },
962 .num_links = 1,
963 .link_nodes = { &qns_gemnoc_gc },
964};
965
966static struct qcom_icc_node xm_gic = {
967 .name = "xm_gic",
968 .channels = 1,
969 .buswidth = 8,
970 .qosbox = &(const struct qcom_icc_qosbox) {
971 .num_ports = 1,
972 .port_offsets = { 0x15000 },
973 .prio_fwd_disable = 1,
974 .prio = 2,
975 .urg_fwd = 0,
976 },
977 .num_links = 1,
978 .link_nodes = { &qns_gemnoc_gc },
979};
980
981static struct qcom_icc_node qns_a1noc_snoc = {
982 .name = "qns_a1noc_snoc",
983 .channels = 1,
984 .buswidth = 32,
985 .num_links = 1,
986 .link_nodes = { &qnm_aggre1_noc },
987};
988
989static struct qcom_icc_node qns_a2noc_snoc = {
990 .name = "qns_a2noc_snoc",
991 .channels = 1,
992 .buswidth = 16,
993 .num_links = 1,
994 .link_nodes = { &qnm_aggre2_noc },
995};
996
997static struct qcom_icc_node qup0_core_slave = {
998 .name = "qup0_core_slave",
999 .channels = 1,
1000 .buswidth = 4,
1001};
1002
1003static struct qcom_icc_node qup1_core_slave = {
1004 .name = "qup1_core_slave",
1005 .channels = 1,
1006 .buswidth = 4,
1007};
1008
1009static struct qcom_icc_node qup3_core_slave = {
1010 .name = "qup3_core_slave",
1011 .channels = 1,
1012 .buswidth = 4,
1013};
1014
1015static struct qcom_icc_node qhs_ahb2phy2 = {
1016 .name = "qhs_ahb2phy2",
1017 .channels = 1,
1018 .buswidth = 4,
1019};
1020
1021static struct qcom_icc_node qhs_ahb2phy3 = {
1022 .name = "qhs_ahb2phy3",
1023 .channels = 1,
1024 .buswidth = 4,
1025};
1026
1027static struct qcom_icc_node qhs_anoc_throttle_cfg = {
1028 .name = "qhs_anoc_throttle_cfg",
1029 .channels = 1,
1030 .buswidth = 4,
1031};
1032
1033static struct qcom_icc_node qhs_aoss = {
1034 .name = "qhs_aoss",
1035 .channels = 1,
1036 .buswidth = 4,
1037};
1038
1039static struct qcom_icc_node qhs_apss = {
1040 .name = "qhs_apss",
1041 .channels = 1,
1042 .buswidth = 8,
1043};
1044
1045static struct qcom_icc_node qhs_boot_rom = {
1046 .name = "qhs_boot_rom",
1047 .channels = 1,
1048 .buswidth = 4,
1049};
1050
1051static struct qcom_icc_node qhs_camera_cfg = {
1052 .name = "qhs_camera_cfg",
1053 .channels = 1,
1054 .buswidth = 4,
1055};
1056
1057static struct qcom_icc_node qhs_camera_nrt_throttle_cfg = {
1058 .name = "qhs_camera_nrt_throttle_cfg",
1059 .channels = 1,
1060 .buswidth = 4,
1061};
1062
1063static struct qcom_icc_node qhs_camera_rt_throttle_cfg = {
1064 .name = "qhs_camera_rt_throttle_cfg",
1065 .channels = 1,
1066 .buswidth = 4,
1067};
1068
1069static struct qcom_icc_node qhs_clk_ctl = {
1070 .name = "qhs_clk_ctl",
1071 .channels = 1,
1072 .buswidth = 4,
1073};
1074
1075static struct qcom_icc_node qhs_compute0_cfg = {
1076 .name = "qhs_compute0_cfg",
1077 .channels = 1,
1078 .buswidth = 4,
1079 .num_links = 1,
1080 .link_nodes = { &qhm_nsp_noc_config },
1081};
1082
1083static struct qcom_icc_node qhs_cpr_cx = {
1084 .name = "qhs_cpr_cx",
1085 .channels = 1,
1086 .buswidth = 4,
1087};
1088
1089static struct qcom_icc_node qhs_cpr_mmcx = {
1090 .name = "qhs_cpr_mmcx",
1091 .channels = 1,
1092 .buswidth = 4,
1093};
1094
1095static struct qcom_icc_node qhs_cpr_mx = {
1096 .name = "qhs_cpr_mx",
1097 .channels = 1,
1098 .buswidth = 4,
1099};
1100
1101static struct qcom_icc_node qhs_cpr_nspcx = {
1102 .name = "qhs_cpr_nspcx",
1103 .channels = 1,
1104 .buswidth = 4,
1105};
1106
1107static struct qcom_icc_node qhs_cpr_nsphmx = {
1108 .name = "qhs_cpr_nsphmx",
1109 .channels = 1,
1110 .buswidth = 4,
1111};
1112
1113static struct qcom_icc_node qhs_crypto0_cfg = {
1114 .name = "qhs_crypto0_cfg",
1115 .channels = 1,
1116 .buswidth = 4,
1117};
1118
1119static struct qcom_icc_node qhs_cx_rdpm = {
1120 .name = "qhs_cx_rdpm",
1121 .channels = 1,
1122 .buswidth = 4,
1123};
1124
1125static struct qcom_icc_node qhs_display0_cfg = {
1126 .name = "qhs_display0_cfg",
1127 .channels = 1,
1128 .buswidth = 4,
1129};
1130
1131static struct qcom_icc_node qhs_display0_rt_throttle_cfg = {
1132 .name = "qhs_display0_rt_throttle_cfg",
1133 .channels = 1,
1134 .buswidth = 4,
1135};
1136
1137static struct qcom_icc_node qhs_emac0_cfg = {
1138 .name = "qhs_emac0_cfg",
1139 .channels = 1,
1140 .buswidth = 4,
1141};
1142
1143static struct qcom_icc_node qhs_gp_dsp0_cfg = {
1144 .name = "qhs_gp_dsp0_cfg",
1145 .channels = 1,
1146 .buswidth = 4,
1147};
1148
1149static struct qcom_icc_node qhs_gpdsp0_throttle_cfg = {
1150 .name = "qhs_gpdsp0_throttle_cfg",
1151 .channels = 1,
1152 .buswidth = 4,
1153};
1154
1155static struct qcom_icc_node qhs_gpu_tcu_throttle_cfg = {
1156 .name = "qhs_gpu_tcu_throttle_cfg",
1157 .channels = 1,
1158 .buswidth = 4,
1159};
1160
1161static struct qcom_icc_node qhs_gpuss_cfg = {
1162 .name = "qhs_gpuss_cfg",
1163 .channels = 1,
1164 .buswidth = 8,
1165};
1166
1167static struct qcom_icc_node qhs_hwkm = {
1168 .name = "qhs_hwkm",
1169 .channels = 1,
1170 .buswidth = 4,
1171};
1172
1173static struct qcom_icc_node qhs_imem_cfg = {
1174 .name = "qhs_imem_cfg",
1175 .channels = 1,
1176 .buswidth = 4,
1177};
1178
1179static struct qcom_icc_node qhs_ipa = {
1180 .name = "qhs_ipa",
1181 .channels = 1,
1182 .buswidth = 4,
1183};
1184
1185static struct qcom_icc_node qhs_ipc_router = {
1186 .name = "qhs_ipc_router",
1187 .channels = 1,
1188 .buswidth = 4,
1189};
1190
1191static struct qcom_icc_node qhs_lpass_cfg = {
1192 .name = "qhs_lpass_cfg",
1193 .channels = 1,
1194 .buswidth = 4,
1195 .num_links = 1,
1196 .link_nodes = { &qhm_config_noc },
1197};
1198
1199static struct qcom_icc_node qhs_lpass_throttle_cfg = {
1200 .name = "qhs_lpass_throttle_cfg",
1201 .channels = 1,
1202 .buswidth = 4,
1203};
1204
1205static struct qcom_icc_node qhs_mx_rdpm = {
1206 .name = "qhs_mx_rdpm",
1207 .channels = 1,
1208 .buswidth = 4,
1209};
1210
1211static struct qcom_icc_node qhs_mxc_rdpm = {
1212 .name = "qhs_mxc_rdpm",
1213 .channels = 1,
1214 .buswidth = 4,
1215};
1216
1217static struct qcom_icc_node qhs_pcie0_cfg = {
1218 .name = "qhs_pcie0_cfg",
1219 .channels = 1,
1220 .buswidth = 4,
1221};
1222
1223static struct qcom_icc_node qhs_pcie1_cfg = {
1224 .name = "qhs_pcie1_cfg",
1225 .channels = 1,
1226 .buswidth = 4,
1227};
1228
1229static struct qcom_icc_node qhs_pcie_tcu_throttle_cfg = {
1230 .name = "qhs_pcie_tcu_throttle_cfg",
1231 .channels = 1,
1232 .buswidth = 4,
1233};
1234
1235static struct qcom_icc_node qhs_pcie_throttle_cfg = {
1236 .name = "qhs_pcie_throttle_cfg",
1237 .channels = 1,
1238 .buswidth = 4,
1239};
1240
1241static struct qcom_icc_node qhs_pdm = {
1242 .name = "qhs_pdm",
1243 .channels = 1,
1244 .buswidth = 4,
1245};
1246
1247static struct qcom_icc_node qhs_pimem_cfg = {
1248 .name = "qhs_pimem_cfg",
1249 .channels = 1,
1250 .buswidth = 4,
1251};
1252
1253static struct qcom_icc_node qhs_pke_wrapper_cfg = {
1254 .name = "qhs_pke_wrapper_cfg",
1255 .channels = 1,
1256 .buswidth = 4,
1257};
1258
1259static struct qcom_icc_node qhs_qdss_cfg = {
1260 .name = "qhs_qdss_cfg",
1261 .channels = 1,
1262 .buswidth = 4,
1263};
1264
1265static struct qcom_icc_node qhs_qm_cfg = {
1266 .name = "qhs_qm_cfg",
1267 .channels = 1,
1268 .buswidth = 4,
1269};
1270
1271static struct qcom_icc_node qhs_qm_mpu_cfg = {
1272 .name = "qhs_qm_mpu_cfg",
1273 .channels = 1,
1274 .buswidth = 4,
1275};
1276
1277static struct qcom_icc_node qhs_qup0 = {
1278 .name = "qhs_qup0",
1279 .channels = 1,
1280 .buswidth = 4,
1281};
1282
1283static struct qcom_icc_node qhs_qup1 = {
1284 .name = "qhs_qup1",
1285 .channels = 1,
1286 .buswidth = 4,
1287};
1288
1289static struct qcom_icc_node qhs_qup3 = {
1290 .name = "qhs_qup3",
1291 .channels = 1,
1292 .buswidth = 4,
1293};
1294
1295static struct qcom_icc_node qhs_sail_throttle_cfg = {
1296 .name = "qhs_sail_throttle_cfg",
1297 .channels = 1,
1298 .buswidth = 4,
1299};
1300
1301static struct qcom_icc_node qhs_sdc1 = {
1302 .name = "qhs_sdc1",
1303 .channels = 1,
1304 .buswidth = 4,
1305};
1306
1307static struct qcom_icc_node qhs_security = {
1308 .name = "qhs_security",
1309 .channels = 1,
1310 .buswidth = 4,
1311};
1312
1313static struct qcom_icc_node qhs_snoc_throttle_cfg = {
1314 .name = "qhs_snoc_throttle_cfg",
1315 .channels = 1,
1316 .buswidth = 4,
1317};
1318
1319static struct qcom_icc_node qhs_tcsr = {
1320 .name = "qhs_tcsr",
1321 .channels = 1,
1322 .buswidth = 4,
1323};
1324
1325static struct qcom_icc_node qhs_tlmm = {
1326 .name = "qhs_tlmm",
1327 .channels = 1,
1328 .buswidth = 4,
1329};
1330
1331static struct qcom_icc_node qhs_tsc_cfg = {
1332 .name = "qhs_tsc_cfg",
1333 .channels = 1,
1334 .buswidth = 4,
1335};
1336
1337static struct qcom_icc_node qhs_ufs_mem_cfg = {
1338 .name = "qhs_ufs_mem_cfg",
1339 .channels = 1,
1340 .buswidth = 4,
1341};
1342
1343static struct qcom_icc_node qhs_usb2_0 = {
1344 .name = "qhs_usb2_0",
1345 .channels = 1,
1346 .buswidth = 4,
1347};
1348
1349static struct qcom_icc_node qhs_usb3_0 = {
1350 .name = "qhs_usb3_0",
1351 .channels = 1,
1352 .buswidth = 4,
1353};
1354
1355static struct qcom_icc_node qhs_venus_cfg = {
1356 .name = "qhs_venus_cfg",
1357 .channels = 1,
1358 .buswidth = 4,
1359};
1360
1361static struct qcom_icc_node qhs_venus_cvp_throttle_cfg = {
1362 .name = "qhs_venus_cvp_throttle_cfg",
1363 .channels = 1,
1364 .buswidth = 4,
1365};
1366
1367static struct qcom_icc_node qhs_venus_v_cpu_throttle_cfg = {
1368 .name = "qhs_venus_v_cpu_throttle_cfg",
1369 .channels = 1,
1370 .buswidth = 4,
1371};
1372
1373static struct qcom_icc_node qhs_venus_vcodec_throttle_cfg = {
1374 .name = "qhs_venus_vcodec_throttle_cfg",
1375 .channels = 1,
1376 .buswidth = 4,
1377};
1378
1379static struct qcom_icc_node qns_ddrss_cfg = {
1380 .name = "qns_ddrss_cfg",
1381 .channels = 1,
1382 .buswidth = 4,
1383 .num_links = 1,
1384 .link_nodes = { &qnm_cnoc_dc_noc },
1385};
1386
1387static struct qcom_icc_node qns_gpdsp_noc_cfg = {
1388 .name = "qns_gpdsp_noc_cfg",
1389 .channels = 1,
1390 .buswidth = 4,
1391};
1392
1393static struct qcom_icc_node qns_mnoc_hf_cfg = {
1394 .name = "qns_mnoc_hf_cfg",
1395 .channels = 1,
1396 .buswidth = 4,
1397 .num_links = 1,
1398 .link_nodes = { &qnm_mnoc_hf_cfg },
1399};
1400
1401static struct qcom_icc_node qns_mnoc_sf_cfg = {
1402 .name = "qns_mnoc_sf_cfg",
1403 .channels = 1,
1404 .buswidth = 4,
1405 .num_links = 1,
1406 .link_nodes = { &qnm_mnoc_sf_cfg },
1407};
1408
1409static struct qcom_icc_node qns_pcie_anoc_cfg = {
1410 .name = "qns_pcie_anoc_cfg",
1411 .channels = 1,
1412 .buswidth = 4,
1413};
1414
1415static struct qcom_icc_node qns_snoc_cfg = {
1416 .name = "qns_snoc_cfg",
1417 .channels = 1,
1418 .buswidth = 4,
1419 .num_links = 1,
1420 .link_nodes = { &qnm_snoc_cfg },
1421};
1422
1423static struct qcom_icc_node qxs_boot_imem = {
1424 .name = "qxs_boot_imem",
1425 .channels = 1,
1426 .buswidth = 16,
1427};
1428
1429static struct qcom_icc_node qxs_imem = {
1430 .name = "qxs_imem",
1431 .channels = 1,
1432 .buswidth = 8,
1433};
1434
1435static struct qcom_icc_node qxs_pimem = {
1436 .name = "qxs_pimem",
1437 .channels = 1,
1438 .buswidth = 8,
1439};
1440
1441static struct qcom_icc_node xs_pcie_0 = {
1442 .name = "xs_pcie_0",
1443 .channels = 1,
1444 .buswidth = 16,
1445};
1446
1447static struct qcom_icc_node xs_pcie_1 = {
1448 .name = "xs_pcie_1",
1449 .channels = 1,
1450 .buswidth = 32,
1451};
1452
1453static struct qcom_icc_node xs_qdss_stm = {
1454 .name = "xs_qdss_stm",
1455 .channels = 1,
1456 .buswidth = 4,
1457};
1458
1459static struct qcom_icc_node xs_sys_tcu_cfg = {
1460 .name = "xs_sys_tcu_cfg",
1461 .channels = 1,
1462 .buswidth = 8,
1463};
1464
1465static struct qcom_icc_node qhs_llcc = {
1466 .name = "qhs_llcc",
1467 .channels = 1,
1468 .buswidth = 4,
1469};
1470
1471static struct qcom_icc_node qns_gemnoc = {
1472 .name = "qns_gemnoc",
1473 .channels = 1,
1474 .buswidth = 4,
1475 .num_links = 1,
1476 .link_nodes = { &qnm_gemnoc_cfg },
1477};
1478
1479static struct qcom_icc_node qns_gem_noc_cnoc = {
1480 .name = "qns_gem_noc_cnoc",
1481 .channels = 1,
1482 .buswidth = 16,
1483 .num_links = 1,
1484 .link_nodes = { &qnm_gemnoc_cnoc },
1485};
1486
1487static struct qcom_icc_node qns_llcc = {
1488 .name = "qns_llcc",
1489 .channels = 4,
1490 .buswidth = 16,
1491 .num_links = 1,
1492 .link_nodes = { &llcc_mc },
1493};
1494
1495static struct qcom_icc_node qns_pcie = {
1496 .name = "qns_pcie",
1497 .channels = 1,
1498 .buswidth = 16,
1499 .num_links = 1,
1500 .link_nodes = { &qnm_gemnoc_pcie },
1501};
1502
1503static struct qcom_icc_node srvc_even_gemnoc = {
1504 .name = "srvc_even_gemnoc",
1505 .channels = 1,
1506 .buswidth = 4,
1507};
1508
1509static struct qcom_icc_node srvc_odd_gemnoc = {
1510 .name = "srvc_odd_gemnoc",
1511 .channels = 1,
1512 .buswidth = 4,
1513};
1514
1515static struct qcom_icc_node srvc_sys_gemnoc = {
1516 .name = "srvc_sys_gemnoc",
1517 .channels = 1,
1518 .buswidth = 4,
1519};
1520
1521static struct qcom_icc_node srvc_sys_gemnoc_2 = {
1522 .name = "srvc_sys_gemnoc_2",
1523 .channels = 1,
1524 .buswidth = 4,
1525};
1526
1527static struct qcom_icc_node qns_gp_dsp_sail_noc = {
1528 .name = "qns_gp_dsp_sail_noc",
1529 .channels = 1,
1530 .buswidth = 16,
1531 .num_links = 1,
1532 .link_nodes = { &qnm_gpdsp_sail },
1533};
1534
1535static struct qcom_icc_node qhs_lpass_core = {
1536 .name = "qhs_lpass_core",
1537 .channels = 1,
1538 .buswidth = 4,
1539};
1540
1541static struct qcom_icc_node qhs_lpass_lpi = {
1542 .name = "qhs_lpass_lpi",
1543 .channels = 1,
1544 .buswidth = 4,
1545};
1546
1547static struct qcom_icc_node qhs_lpass_mpu = {
1548 .name = "qhs_lpass_mpu",
1549 .channels = 1,
1550 .buswidth = 4,
1551};
1552
1553static struct qcom_icc_node qhs_lpass_top = {
1554 .name = "qhs_lpass_top",
1555 .channels = 1,
1556 .buswidth = 4,
1557};
1558
1559static struct qcom_icc_node qns_sysnoc = {
1560 .name = "qns_sysnoc",
1561 .channels = 1,
1562 .buswidth = 16,
1563 .num_links = 1,
1564 .link_nodes = { &qnm_lpass_noc },
1565};
1566
1567static struct qcom_icc_node srvc_niu_aml_noc = {
1568 .name = "srvc_niu_aml_noc",
1569 .channels = 1,
1570 .buswidth = 4,
1571};
1572
1573static struct qcom_icc_node srvc_niu_lpass_agnoc = {
1574 .name = "srvc_niu_lpass_agnoc",
1575 .channels = 1,
1576 .buswidth = 4,
1577};
1578
1579static struct qcom_icc_node ebi = {
1580 .name = "ebi",
1581 .channels = 8,
1582 .buswidth = 4,
1583};
1584
1585static struct qcom_icc_node qns_mem_noc_hf = {
1586 .name = "qns_mem_noc_hf",
1587 .channels = 2,
1588 .buswidth = 32,
1589 .num_links = 1,
1590 .link_nodes = { &qnm_mnoc_hf },
1591};
1592
1593static struct qcom_icc_node qns_mem_noc_sf = {
1594 .name = "qns_mem_noc_sf",
1595 .channels = 2,
1596 .buswidth = 32,
1597 .num_links = 1,
1598 .link_nodes = { &qnm_mnoc_sf },
1599};
1600
1601static struct qcom_icc_node srvc_mnoc_hf = {
1602 .name = "srvc_mnoc_hf",
1603 .channels = 1,
1604 .buswidth = 4,
1605};
1606
1607static struct qcom_icc_node srvc_mnoc_sf = {
1608 .name = "srvc_mnoc_sf",
1609 .channels = 1,
1610 .buswidth = 4,
1611};
1612
1613static struct qcom_icc_node qns_hcp = {
1614 .name = "qns_hcp",
1615 .channels = 2,
1616 .buswidth = 32,
1617};
1618
1619static struct qcom_icc_node qns_nsp_gemnoc = {
1620 .name = "qns_nsp_gemnoc",
1621 .channels = 2,
1622 .buswidth = 32,
1623 .num_links = 1,
1624 .link_nodes = { &qnm_cmpnoc0 },
1625};
1626
1627static struct qcom_icc_node service_nsp_noc = {
1628 .name = "service_nsp_noc",
1629 .channels = 1,
1630 .buswidth = 4,
1631};
1632
1633static struct qcom_icc_node qns_pcie_mem_noc = {
1634 .name = "qns_pcie_mem_noc",
1635 .channels = 1,
1636 .buswidth = 32,
1637 .num_links = 1,
1638 .link_nodes = { &qnm_pcie },
1639};
1640
1641static struct qcom_icc_node qns_gemnoc_gc = {
1642 .name = "qns_gemnoc_gc",
1643 .channels = 1,
1644 .buswidth = 8,
1645 .num_links = 1,
1646 .link_nodes = { &qnm_snoc_gc },
1647};
1648
1649static struct qcom_icc_node qns_gemnoc_sf = {
1650 .name = "qns_gemnoc_sf",
1651 .channels = 1,
1652 .buswidth = 16,
1653 .num_links = 1,
1654 .link_nodes = { &qnm_snoc_sf },
1655};
1656
1657static struct qcom_icc_node srvc_snoc = {
1658 .name = "srvc_snoc",
1659 .channels = 1,
1660 .buswidth = 4,
1661};
1662
1663static struct qcom_icc_bcm bcm_acv = {
1664 .name = "ACV",
1665 .enable_mask = BIT(3),
1666 .num_nodes = 1,
1667 .nodes = { &ebi },
1668};
1669
1670static struct qcom_icc_bcm bcm_ce0 = {
1671 .name = "CE0",
1672 .num_nodes = 2,
1673 .nodes = { &qxm_crypto_0, &qxm_crypto_1 },
1674};
1675
1676static struct qcom_icc_bcm bcm_cn0 = {
1677 .name = "CN0",
1678 .keepalive = true,
1679 .num_nodes = 2,
1680 .nodes = { &qnm_gemnoc_cnoc, &qnm_gemnoc_pcie },
1681};
1682
1683static struct qcom_icc_bcm bcm_cn1 = {
1684 .name = "CN1",
1685 .num_nodes = 66,
1686 .nodes = { &qhs_ahb2phy2, &qhs_ahb2phy3,
1687 &qhs_anoc_throttle_cfg, &qhs_aoss,
1688 &qhs_apss, &qhs_boot_rom,
1689 &qhs_camera_cfg, &qhs_camera_nrt_throttle_cfg,
1690 &qhs_camera_rt_throttle_cfg, &qhs_clk_ctl,
1691 &qhs_compute0_cfg, &qhs_cpr_cx,
1692 &qhs_cpr_mmcx, &qhs_cpr_mx,
1693 &qhs_cpr_nspcx, &qhs_cpr_nsphmx,
1694 &qhs_crypto0_cfg, &qhs_cx_rdpm,
1695 &qhs_display0_cfg, &qhs_display0_rt_throttle_cfg,
1696 &qhs_emac0_cfg, &qhs_gp_dsp0_cfg,
1697 &qhs_gpdsp0_throttle_cfg, &qhs_gpu_tcu_throttle_cfg,
1698 &qhs_gpuss_cfg, &qhs_hwkm,
1699 &qhs_imem_cfg, &qhs_ipa,
1700 &qhs_ipc_router, &qhs_lpass_cfg,
1701 &qhs_lpass_throttle_cfg, &qhs_mx_rdpm,
1702 &qhs_mxc_rdpm, &qhs_pcie0_cfg,
1703 &qhs_pcie1_cfg, &qhs_pcie_tcu_throttle_cfg,
1704 &qhs_pcie_throttle_cfg, &qhs_pdm,
1705 &qhs_pimem_cfg, &qhs_pke_wrapper_cfg,
1706 &qhs_qdss_cfg, &qhs_qm_cfg,
1707 &qhs_qm_mpu_cfg, &qhs_sail_throttle_cfg,
1708 &qhs_sdc1, &qhs_security,
1709 &qhs_snoc_throttle_cfg, &qhs_tcsr,
1710 &qhs_tlmm, &qhs_tsc_cfg,
1711 &qhs_ufs_mem_cfg, &qhs_usb2_0,
1712 &qhs_usb3_0, &qhs_venus_cfg,
1713 &qhs_venus_cvp_throttle_cfg, &qhs_venus_v_cpu_throttle_cfg,
1714 &qhs_venus_vcodec_throttle_cfg, &qns_ddrss_cfg,
1715 &qns_gpdsp_noc_cfg, &qns_mnoc_hf_cfg,
1716 &qns_mnoc_sf_cfg, &qns_pcie_anoc_cfg,
1717 &qns_snoc_cfg, &qxs_boot_imem,
1718 &qxs_imem, &xs_sys_tcu_cfg },
1719};
1720
1721static struct qcom_icc_bcm bcm_cn2 = {
1722 .name = "CN2",
1723 .num_nodes = 3,
1724 .nodes = { &qhs_qup0, &qhs_qup1,
1725 &qhs_qup3 },
1726};
1727
1728static struct qcom_icc_bcm bcm_cn3 = {
1729 .name = "CN3",
1730 .num_nodes = 2,
1731 .nodes = { &xs_pcie_0, &xs_pcie_1 },
1732};
1733
1734static struct qcom_icc_bcm bcm_gna0 = {
1735 .name = "GNA0",
1736 .num_nodes = 1,
1737 .nodes = { &qxm_dsp0 },
1738};
1739
1740static struct qcom_icc_bcm bcm_mc0 = {
1741 .name = "MC0",
1742 .keepalive = true,
1743 .num_nodes = 1,
1744 .nodes = { &ebi },
1745};
1746
1747static struct qcom_icc_bcm bcm_mm0 = {
1748 .name = "MM0",
1749 .keepalive = true,
1750 .num_nodes = 4,
1751 .nodes = { &qnm_camnoc_hf, &qnm_mdp0_0,
1752 &qnm_mdp0_1, &qns_mem_noc_hf },
1753};
1754
1755static struct qcom_icc_bcm bcm_mm1 = {
1756 .name = "MM1",
1757 .num_nodes = 6,
1758 .nodes = { &qnm_camnoc_icp, &qnm_camnoc_sf,
1759 &qnm_video0, &qnm_video_cvp,
1760 &qnm_video_v_cpu, &qns_mem_noc_sf },
1761};
1762
1763static struct qcom_icc_bcm bcm_nsa0 = {
1764 .name = "NSA0",
1765 .num_nodes = 2,
1766 .nodes = { &qns_hcp, &qns_nsp_gemnoc },
1767};
1768
1769static struct qcom_icc_bcm bcm_nsa1 = {
1770 .name = "NSA1",
1771 .num_nodes = 1,
1772 .nodes = { &qxm_nsp },
1773};
1774
1775static struct qcom_icc_bcm bcm_pci0 = {
1776 .name = "PCI0",
1777 .num_nodes = 1,
1778 .nodes = { &qns_pcie_mem_noc },
1779};
1780
1781static struct qcom_icc_bcm bcm_qup0 = {
1782 .name = "QUP0",
1783 .vote_scale = 1,
1784 .keepalive = true,
1785 .num_nodes = 1,
1786 .nodes = { &qup0_core_slave },
1787};
1788
1789static struct qcom_icc_bcm bcm_qup1 = {
1790 .name = "QUP1",
1791 .vote_scale = 1,
1792 .keepalive = true,
1793 .num_nodes = 1,
1794 .nodes = { &qup1_core_slave },
1795};
1796
1797static struct qcom_icc_bcm bcm_qup2 = {
1798 .name = "QUP2",
1799 .vote_scale = 1,
1800 .keepalive = true,
1801 .num_nodes = 1,
1802 .nodes = { &qup3_core_slave },
1803};
1804
1805static struct qcom_icc_bcm bcm_sh0 = {
1806 .name = "SH0",
1807 .keepalive = true,
1808 .num_nodes = 1,
1809 .nodes = { &qns_llcc },
1810};
1811
1812static struct qcom_icc_bcm bcm_sh2 = {
1813 .name = "SH2",
1814 .num_nodes = 1,
1815 .nodes = { &chm_apps },
1816};
1817
1818static struct qcom_icc_bcm bcm_sn0 = {
1819 .name = "SN0",
1820 .keepalive = true,
1821 .num_nodes = 1,
1822 .nodes = { &qns_gemnoc_sf },
1823};
1824
1825static struct qcom_icc_bcm bcm_sn1 = {
1826 .name = "SN1",
1827 .num_nodes = 1,
1828 .nodes = { &qns_gemnoc_gc },
1829};
1830
1831static struct qcom_icc_bcm bcm_sn2 = {
1832 .name = "SN2",
1833 .num_nodes = 1,
1834 .nodes = { &qxs_pimem },
1835};
1836
1837static struct qcom_icc_bcm bcm_sn3 = {
1838 .name = "SN3",
1839 .num_nodes = 2,
1840 .nodes = { &qns_a1noc_snoc, &qnm_aggre1_noc },
1841};
1842
1843static struct qcom_icc_bcm bcm_sn4 = {
1844 .name = "SN4",
1845 .num_nodes = 2,
1846 .nodes = { &qns_a2noc_snoc, &qnm_aggre2_noc },
1847};
1848
1849static struct qcom_icc_bcm bcm_sn9 = {
1850 .name = "SN9",
1851 .num_nodes = 2,
1852 .nodes = { &qns_sysnoc, &qnm_lpass_noc },
1853};
1854
1855static struct qcom_icc_bcm bcm_sn10 = {
1856 .name = "SN10",
1857 .num_nodes = 1,
1858 .nodes = { &xs_qdss_stm },
1859};
1860
1861static struct qcom_icc_bcm * const aggre1_noc_bcms[] = {
1862 &bcm_sn3,
1863};
1864
1865static struct qcom_icc_node * const aggre1_noc_nodes[] = {
1866 [MASTER_QUP_3] = &qxm_qup3,
1867 [MASTER_EMAC] = &xm_emac_0,
1868 [MASTER_SDC] = &xm_sdc1,
1869 [MASTER_UFS_MEM] = &xm_ufs_mem,
1870 [MASTER_USB2] = &xm_usb2_2,
1871 [MASTER_USB3_0] = &xm_usb3_0,
1872 [SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc,
1873};
1874
1875static const struct regmap_config qcs8300_aggre1_noc_regmap_config = {
1876 .reg_bits = 32,
1877 .reg_stride = 4,
1878 .val_bits = 32,
1879 .max_register = 0x17080,
1880 .fast_io = true,
1881};
1882
1883static const struct qcom_icc_desc qcs8300_aggre1_noc = {
1884 .config = &qcs8300_aggre1_noc_regmap_config,
1885 .nodes = aggre1_noc_nodes,
1886 .num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
1887 .bcms = aggre1_noc_bcms,
1888 .num_bcms = ARRAY_SIZE(aggre1_noc_bcms),
1889 .qos_requires_clocks = true,
1890};
1891
1892static struct qcom_icc_bcm * const aggre2_noc_bcms[] = {
1893 &bcm_ce0,
1894 &bcm_sn4,
1895};
1896
1897static struct qcom_icc_node * const aggre2_noc_nodes[] = {
1898 [MASTER_QDSS_BAM] = &qhm_qdss_bam,
1899 [MASTER_QUP_0] = &qhm_qup0,
1900 [MASTER_QUP_1] = &qhm_qup1,
1901 [MASTER_CNOC_A2NOC] = &qnm_cnoc_datapath,
1902 [MASTER_CRYPTO_CORE0] = &qxm_crypto_0,
1903 [MASTER_CRYPTO_CORE1] = &qxm_crypto_1,
1904 [MASTER_IPA] = &qxm_ipa,
1905 [MASTER_QDSS_ETR_0] = &xm_qdss_etr_0,
1906 [MASTER_QDSS_ETR_1] = &xm_qdss_etr_1,
1907 [SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc,
1908};
1909
1910static const struct regmap_config qcs8300_aggre2_noc_regmap_config = {
1911 .reg_bits = 32,
1912 .reg_stride = 4,
1913 .val_bits = 32,
1914 .max_register = 0x1a080,
1915 .fast_io = true,
1916};
1917
1918static const struct qcom_icc_desc qcs8300_aggre2_noc = {
1919 .config = &qcs8300_aggre2_noc_regmap_config,
1920 .nodes = aggre2_noc_nodes,
1921 .num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
1922 .bcms = aggre2_noc_bcms,
1923 .num_bcms = ARRAY_SIZE(aggre2_noc_bcms),
1924 .qos_requires_clocks = true,
1925};
1926
1927static struct qcom_icc_bcm * const clk_virt_bcms[] = {
1928 &bcm_qup0,
1929 &bcm_qup1,
1930 &bcm_qup2,
1931};
1932
1933static struct qcom_icc_node * const clk_virt_nodes[] = {
1934 [MASTER_QUP_CORE_0] = &qup0_core_master,
1935 [MASTER_QUP_CORE_1] = &qup1_core_master,
1936 [MASTER_QUP_CORE_3] = &qup3_core_master,
1937 [SLAVE_QUP_CORE_0] = &qup0_core_slave,
1938 [SLAVE_QUP_CORE_1] = &qup1_core_slave,
1939 [SLAVE_QUP_CORE_3] = &qup3_core_slave,
1940};
1941
1942static const struct qcom_icc_desc qcs8300_clk_virt = {
1943 .nodes = clk_virt_nodes,
1944 .num_nodes = ARRAY_SIZE(clk_virt_nodes),
1945 .bcms = clk_virt_bcms,
1946 .num_bcms = ARRAY_SIZE(clk_virt_bcms),
1947};
1948
1949static struct qcom_icc_bcm * const config_noc_bcms[] = {
1950 &bcm_cn0,
1951 &bcm_cn1,
1952 &bcm_cn2,
1953 &bcm_cn3,
1954 &bcm_sn2,
1955 &bcm_sn10,
1956};
1957
1958static struct qcom_icc_node * const config_noc_nodes[] = {
1959 [MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc,
1960 [MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie,
1961 [SLAVE_AHB2PHY_2] = &qhs_ahb2phy2,
1962 [SLAVE_AHB2PHY_3] = &qhs_ahb2phy3,
1963 [SLAVE_ANOC_THROTTLE_CFG] = &qhs_anoc_throttle_cfg,
1964 [SLAVE_AOSS] = &qhs_aoss,
1965 [SLAVE_APPSS] = &qhs_apss,
1966 [SLAVE_BOOT_ROM] = &qhs_boot_rom,
1967 [SLAVE_CAMERA_CFG] = &qhs_camera_cfg,
1968 [SLAVE_CAMERA_NRT_THROTTLE_CFG] = &qhs_camera_nrt_throttle_cfg,
1969 [SLAVE_CAMERA_RT_THROTTLE_CFG] = &qhs_camera_rt_throttle_cfg,
1970 [SLAVE_CLK_CTL] = &qhs_clk_ctl,
1971 [SLAVE_CDSP_CFG] = &qhs_compute0_cfg,
1972 [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx,
1973 [SLAVE_RBCPR_MMCX_CFG] = &qhs_cpr_mmcx,
1974 [SLAVE_RBCPR_MX_CFG] = &qhs_cpr_mx,
1975 [SLAVE_CPR_NSPCX] = &qhs_cpr_nspcx,
1976 [SLAVE_CPR_NSPHMX] = &qhs_cpr_nsphmx,
1977 [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg,
1978 [SLAVE_CX_RDPM] = &qhs_cx_rdpm,
1979 [SLAVE_DISPLAY_CFG] = &qhs_display0_cfg,
1980 [SLAVE_DISPLAY_RT_THROTTLE_CFG] = &qhs_display0_rt_throttle_cfg,
1981 [SLAVE_EMAC_CFG] = &qhs_emac0_cfg,
1982 [SLAVE_GP_DSP0_CFG] = &qhs_gp_dsp0_cfg,
1983 [SLAVE_GPDSP0_THROTTLE_CFG] = &qhs_gpdsp0_throttle_cfg,
1984 [SLAVE_GPU_TCU_THROTTLE_CFG] = &qhs_gpu_tcu_throttle_cfg,
1985 [SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg,
1986 [SLAVE_HWKM] = &qhs_hwkm,
1987 [SLAVE_IMEM_CFG] = &qhs_imem_cfg,
1988 [SLAVE_IPA_CFG] = &qhs_ipa,
1989 [SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router,
1990 [SLAVE_LPASS] = &qhs_lpass_cfg,
1991 [SLAVE_LPASS_THROTTLE_CFG] = &qhs_lpass_throttle_cfg,
1992 [SLAVE_MX_RDPM] = &qhs_mx_rdpm,
1993 [SLAVE_MXC_RDPM] = &qhs_mxc_rdpm,
1994 [SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg,
1995 [SLAVE_PCIE_1_CFG] = &qhs_pcie1_cfg,
1996 [SLAVE_PCIE_TCU_THROTTLE_CFG] = &qhs_pcie_tcu_throttle_cfg,
1997 [SLAVE_PCIE_THROTTLE_CFG] = &qhs_pcie_throttle_cfg,
1998 [SLAVE_PDM] = &qhs_pdm,
1999 [SLAVE_PIMEM_CFG] = &qhs_pimem_cfg,
2000 [SLAVE_PKA_WRAPPER_CFG] = &qhs_pke_wrapper_cfg,
2001 [SLAVE_QDSS_CFG] = &qhs_qdss_cfg,
2002 [SLAVE_QM_CFG] = &qhs_qm_cfg,
2003 [SLAVE_QM_MPU_CFG] = &qhs_qm_mpu_cfg,
2004 [SLAVE_QUP_0] = &qhs_qup0,
2005 [SLAVE_QUP_1] = &qhs_qup1,
2006 [SLAVE_QUP_3] = &qhs_qup3,
2007 [SLAVE_SAIL_THROTTLE_CFG] = &qhs_sail_throttle_cfg,
2008 [SLAVE_SDC1] = &qhs_sdc1,
2009 [SLAVE_SECURITY] = &qhs_security,
2010 [SLAVE_SNOC_THROTTLE_CFG] = &qhs_snoc_throttle_cfg,
2011 [SLAVE_TCSR] = &qhs_tcsr,
2012 [SLAVE_TLMM] = &qhs_tlmm,
2013 [SLAVE_TSC_CFG] = &qhs_tsc_cfg,
2014 [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg,
2015 [SLAVE_USB2] = &qhs_usb2_0,
2016 [SLAVE_USB3_0] = &qhs_usb3_0,
2017 [SLAVE_VENUS_CFG] = &qhs_venus_cfg,
2018 [SLAVE_VENUS_CVP_THROTTLE_CFG] = &qhs_venus_cvp_throttle_cfg,
2019 [SLAVE_VENUS_V_CPU_THROTTLE_CFG] = &qhs_venus_v_cpu_throttle_cfg,
2020 [SLAVE_VENUS_VCODEC_THROTTLE_CFG] = &qhs_venus_vcodec_throttle_cfg,
2021 [SLAVE_DDRSS_CFG] = &qns_ddrss_cfg,
2022 [SLAVE_GPDSP_NOC_CFG] = &qns_gpdsp_noc_cfg,
2023 [SLAVE_CNOC_MNOC_HF_CFG] = &qns_mnoc_hf_cfg,
2024 [SLAVE_CNOC_MNOC_SF_CFG] = &qns_mnoc_sf_cfg,
2025 [SLAVE_PCIE_ANOC_CFG] = &qns_pcie_anoc_cfg,
2026 [SLAVE_SNOC_CFG] = &qns_snoc_cfg,
2027 [SLAVE_BOOT_IMEM] = &qxs_boot_imem,
2028 [SLAVE_IMEM] = &qxs_imem,
2029 [SLAVE_PIMEM] = &qxs_pimem,
2030 [SLAVE_PCIE_0] = &xs_pcie_0,
2031 [SLAVE_PCIE_1] = &xs_pcie_1,
2032 [SLAVE_QDSS_STM] = &xs_qdss_stm,
2033 [SLAVE_TCU] = &xs_sys_tcu_cfg,
2034};
2035
2036static const struct regmap_config qcs8300_config_noc_regmap_config = {
2037 .reg_bits = 32,
2038 .reg_stride = 4,
2039 .val_bits = 32,
2040 .max_register = 0x13080,
2041 .fast_io = true,
2042};
2043
2044static const struct qcom_icc_desc qcs8300_config_noc = {
2045 .config = &qcs8300_config_noc_regmap_config,
2046 .nodes = config_noc_nodes,
2047 .num_nodes = ARRAY_SIZE(config_noc_nodes),
2048 .bcms = config_noc_bcms,
2049 .num_bcms = ARRAY_SIZE(config_noc_bcms),
2050};
2051
2052static struct qcom_icc_node * const dc_noc_nodes[] = {
2053 [MASTER_CNOC_DC_NOC] = &qnm_cnoc_dc_noc,
2054 [SLAVE_LLCC_CFG] = &qhs_llcc,
2055 [SLAVE_GEM_NOC_CFG] = &qns_gemnoc,
2056};
2057
2058static const struct regmap_config qcs8300_dc_noc_regmap_config = {
2059 .reg_bits = 32,
2060 .reg_stride = 4,
2061 .val_bits = 32,
2062 .max_register = 0x5080,
2063 .fast_io = true,
2064};
2065
2066static const struct qcom_icc_desc qcs8300_dc_noc = {
2067 .config = &qcs8300_dc_noc_regmap_config,
2068 .nodes = dc_noc_nodes,
2069 .num_nodes = ARRAY_SIZE(dc_noc_nodes),
2070};
2071
2072static struct qcom_icc_bcm * const gem_noc_bcms[] = {
2073 &bcm_sh0,
2074 &bcm_sh2,
2075};
2076
2077static struct qcom_icc_node * const gem_noc_nodes[] = {
2078 [MASTER_GPU_TCU] = &alm_gpu_tcu,
2079 [MASTER_PCIE_TCU] = &alm_pcie_tcu,
2080 [MASTER_SYS_TCU] = &alm_sys_tcu,
2081 [MASTER_APPSS_PROC] = &chm_apps,
2082 [MASTER_COMPUTE_NOC] = &qnm_cmpnoc0,
2083 [MASTER_GEM_NOC_CFG] = &qnm_gemnoc_cfg,
2084 [MASTER_GPDSP_SAIL] = &qnm_gpdsp_sail,
2085 [MASTER_GFX3D] = &qnm_gpu,
2086 [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf,
2087 [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf,
2088 [MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie,
2089 [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc,
2090 [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf,
2091 [SLAVE_GEM_NOC_CNOC] = &qns_gem_noc_cnoc,
2092 [SLAVE_LLCC] = &qns_llcc,
2093 [SLAVE_GEM_NOC_PCIE_CNOC] = &qns_pcie,
2094 [SLAVE_SERVICE_GEM_NOC_1] = &srvc_even_gemnoc,
2095 [SLAVE_SERVICE_GEM_NOC_2] = &srvc_odd_gemnoc,
2096 [SLAVE_SERVICE_GEM_NOC] = &srvc_sys_gemnoc,
2097 [SLAVE_SERVICE_GEM_NOC2] = &srvc_sys_gemnoc_2,
2098};
2099
2100static const struct regmap_config qcs8300_gem_noc_regmap_config = {
2101 .reg_bits = 32,
2102 .reg_stride = 4,
2103 .val_bits = 32,
2104 .max_register = 0xf7080,
2105 .fast_io = true,
2106};
2107
2108static const struct qcom_icc_desc qcs8300_gem_noc = {
2109 .config = &qcs8300_gem_noc_regmap_config,
2110 .nodes = gem_noc_nodes,
2111 .num_nodes = ARRAY_SIZE(gem_noc_nodes),
2112 .bcms = gem_noc_bcms,
2113 .num_bcms = ARRAY_SIZE(gem_noc_bcms),
2114 .qos_requires_clocks = true,
2115};
2116
2117static struct qcom_icc_bcm * const gpdsp_anoc_bcms[] = {
2118 &bcm_gna0,
2119};
2120
2121static struct qcom_icc_node * const gpdsp_anoc_nodes[] = {
2122 [MASTER_SAILSS_MD0] = &qnm_sailss_md0,
2123 [MASTER_DSP0] = &qxm_dsp0,
2124 [SLAVE_GP_DSP_SAIL_NOC] = &qns_gp_dsp_sail_noc,
2125};
2126
2127static const struct regmap_config qcs8300_gpdsp_anoc_regmap_config = {
2128 .reg_bits = 32,
2129 .reg_stride = 4,
2130 .val_bits = 32,
2131 .max_register = 0xd080,
2132 .fast_io = true,
2133};
2134
2135static const struct qcom_icc_desc qcs8300_gpdsp_anoc = {
2136 .config = &qcs8300_gpdsp_anoc_regmap_config,
2137 .nodes = gpdsp_anoc_nodes,
2138 .num_nodes = ARRAY_SIZE(gpdsp_anoc_nodes),
2139 .bcms = gpdsp_anoc_bcms,
2140 .num_bcms = ARRAY_SIZE(gpdsp_anoc_bcms),
2141};
2142
2143static struct qcom_icc_bcm * const lpass_ag_noc_bcms[] = {
2144 &bcm_sn9,
2145};
2146
2147static struct qcom_icc_node * const lpass_ag_noc_nodes[] = {
2148 [MASTER_CNOC_LPASS_AG_NOC] = &qhm_config_noc,
2149 [MASTER_LPASS_PROC] = &qxm_lpass_dsp,
2150 [SLAVE_LPASS_CORE_CFG] = &qhs_lpass_core,
2151 [SLAVE_LPASS_LPI_CFG] = &qhs_lpass_lpi,
2152 [SLAVE_LPASS_MPU_CFG] = &qhs_lpass_mpu,
2153 [SLAVE_LPASS_TOP_CFG] = &qhs_lpass_top,
2154 [SLAVE_LPASS_SNOC] = &qns_sysnoc,
2155 [SLAVE_SERVICES_LPASS_AML_NOC] = &srvc_niu_aml_noc,
2156 [SLAVE_SERVICE_LPASS_AG_NOC] = &srvc_niu_lpass_agnoc,
2157};
2158
2159static const struct regmap_config qcs8300_lpass_ag_noc_regmap_config = {
2160 .reg_bits = 32,
2161 .reg_stride = 4,
2162 .val_bits = 32,
2163 .max_register = 0x17200,
2164 .fast_io = true,
2165};
2166
2167static const struct qcom_icc_desc qcs8300_lpass_ag_noc = {
2168 .config = &qcs8300_lpass_ag_noc_regmap_config,
2169 .nodes = lpass_ag_noc_nodes,
2170 .num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes),
2171 .bcms = lpass_ag_noc_bcms,
2172 .num_bcms = ARRAY_SIZE(lpass_ag_noc_bcms),
2173};
2174
2175static struct qcom_icc_bcm * const mc_virt_bcms[] = {
2176 &bcm_acv,
2177 &bcm_mc0,
2178};
2179
2180static struct qcom_icc_node * const mc_virt_nodes[] = {
2181 [MASTER_LLCC] = &llcc_mc,
2182 [SLAVE_EBI1] = &ebi,
2183};
2184
2185static const struct qcom_icc_desc qcs8300_mc_virt = {
2186 .nodes = mc_virt_nodes,
2187 .num_nodes = ARRAY_SIZE(mc_virt_nodes),
2188 .bcms = mc_virt_bcms,
2189 .num_bcms = ARRAY_SIZE(mc_virt_bcms),
2190};
2191
2192static struct qcom_icc_bcm * const mmss_noc_bcms[] = {
2193 &bcm_mm0,
2194 &bcm_mm1,
2195};
2196
2197static struct qcom_icc_node * const mmss_noc_nodes[] = {
2198 [MASTER_CAMNOC_HF] = &qnm_camnoc_hf,
2199 [MASTER_CAMNOC_ICP] = &qnm_camnoc_icp,
2200 [MASTER_CAMNOC_SF] = &qnm_camnoc_sf,
2201 [MASTER_MDP0] = &qnm_mdp0_0,
2202 [MASTER_MDP1] = &qnm_mdp0_1,
2203 [MASTER_CNOC_MNOC_HF_CFG] = &qnm_mnoc_hf_cfg,
2204 [MASTER_CNOC_MNOC_SF_CFG] = &qnm_mnoc_sf_cfg,
2205 [MASTER_VIDEO_P0] = &qnm_video0,
2206 [MASTER_VIDEO_PROC] = &qnm_video_cvp,
2207 [MASTER_VIDEO_V_PROC] = &qnm_video_v_cpu,
2208 [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf,
2209 [SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf,
2210 [SLAVE_SERVICE_MNOC_HF] = &srvc_mnoc_hf,
2211 [SLAVE_SERVICE_MNOC_SF] = &srvc_mnoc_sf,
2212};
2213
2214static const struct regmap_config qcs8300_mmss_noc_regmap_config = {
2215 .reg_bits = 32,
2216 .reg_stride = 4,
2217 .val_bits = 32,
2218 .max_register = 0x40000,
2219 .fast_io = true,
2220};
2221
2222static const struct qcom_icc_desc qcs8300_mmss_noc = {
2223 .config = &qcs8300_mmss_noc_regmap_config,
2224 .nodes = mmss_noc_nodes,
2225 .num_nodes = ARRAY_SIZE(mmss_noc_nodes),
2226 .bcms = mmss_noc_bcms,
2227 .num_bcms = ARRAY_SIZE(mmss_noc_bcms),
2228};
2229
2230static struct qcom_icc_bcm * const nspa_noc_bcms[] = {
2231 &bcm_nsa0,
2232 &bcm_nsa1,
2233};
2234
2235static struct qcom_icc_node * const nspa_noc_nodes[] = {
2236 [MASTER_CDSP_NOC_CFG] = &qhm_nsp_noc_config,
2237 [MASTER_CDSP_PROC] = &qxm_nsp,
2238 [SLAVE_HCP_A] = &qns_hcp,
2239 [SLAVE_CDSP_MEM_NOC] = &qns_nsp_gemnoc,
2240 [SLAVE_SERVICE_NSP_NOC] = &service_nsp_noc,
2241};
2242
2243static const struct regmap_config qcs8300_nspa_noc_regmap_config = {
2244 .reg_bits = 32,
2245 .reg_stride = 4,
2246 .val_bits = 32,
2247 .max_register = 0x16080,
2248 .fast_io = true,
2249};
2250
2251static const struct qcom_icc_desc qcs8300_nspa_noc = {
2252 .config = &qcs8300_nspa_noc_regmap_config,
2253 .nodes = nspa_noc_nodes,
2254 .num_nodes = ARRAY_SIZE(nspa_noc_nodes),
2255 .bcms = nspa_noc_bcms,
2256 .num_bcms = ARRAY_SIZE(nspa_noc_bcms),
2257};
2258
2259static struct qcom_icc_bcm * const pcie_anoc_bcms[] = {
2260 &bcm_pci0,
2261};
2262
2263static struct qcom_icc_node * const pcie_anoc_nodes[] = {
2264 [MASTER_PCIE_0] = &xm_pcie3_0,
2265 [MASTER_PCIE_1] = &xm_pcie3_1,
2266 [SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_mem_noc,
2267};
2268
2269static const struct regmap_config qcs8300_pcie_anoc_regmap_config = {
2270 .reg_bits = 32,
2271 .reg_stride = 4,
2272 .val_bits = 32,
2273 .max_register = 0xc080,
2274 .fast_io = true,
2275};
2276
2277static const struct qcom_icc_desc qcs8300_pcie_anoc = {
2278 .config = &qcs8300_pcie_anoc_regmap_config,
2279 .nodes = pcie_anoc_nodes,
2280 .num_nodes = ARRAY_SIZE(pcie_anoc_nodes),
2281 .bcms = pcie_anoc_bcms,
2282 .num_bcms = ARRAY_SIZE(pcie_anoc_bcms),
2283};
2284
2285static struct qcom_icc_bcm * const system_noc_bcms[] = {
2286 &bcm_sn0,
2287 &bcm_sn1,
2288 &bcm_sn3,
2289 &bcm_sn4,
2290 &bcm_sn9,
2291};
2292
2293static struct qcom_icc_node * const system_noc_nodes[] = {
2294 [MASTER_GIC_AHB] = &qhm_gic,
2295 [MASTER_A1NOC_SNOC] = &qnm_aggre1_noc,
2296 [MASTER_A2NOC_SNOC] = &qnm_aggre2_noc,
2297 [MASTER_LPASS_ANOC] = &qnm_lpass_noc,
2298 [MASTER_SNOC_CFG] = &qnm_snoc_cfg,
2299 [MASTER_PIMEM] = &qxm_pimem,
2300 [MASTER_GIC] = &xm_gic,
2301 [SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc,
2302 [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf,
2303 [SLAVE_SERVICE_SNOC] = &srvc_snoc,
2304};
2305
2306static const struct regmap_config qcs8300_system_noc_regmap_config = {
2307 .reg_bits = 32,
2308 .reg_stride = 4,
2309 .val_bits = 32,
2310 .max_register = 0x15080,
2311 .fast_io = true,
2312};
2313
2314static const struct qcom_icc_desc qcs8300_system_noc = {
2315 .config = &qcs8300_system_noc_regmap_config,
2316 .nodes = system_noc_nodes,
2317 .num_nodes = ARRAY_SIZE(system_noc_nodes),
2318 .bcms = system_noc_bcms,
2319 .num_bcms = ARRAY_SIZE(system_noc_bcms),
2320};
2321
2322static const struct of_device_id qnoc_of_match[] = {
2323 { .compatible = "qcom,qcs8300-aggre1-noc",
2324 .data = &qcs8300_aggre1_noc},
2325 { .compatible = "qcom,qcs8300-aggre2-noc",
2326 .data = &qcs8300_aggre2_noc},
2327 { .compatible = "qcom,qcs8300-clk-virt",
2328 .data = &qcs8300_clk_virt},
2329 { .compatible = "qcom,qcs8300-config-noc",
2330 .data = &qcs8300_config_noc},
2331 { .compatible = "qcom,qcs8300-dc-noc",
2332 .data = &qcs8300_dc_noc},
2333 { .compatible = "qcom,qcs8300-gem-noc",
2334 .data = &qcs8300_gem_noc},
2335 { .compatible = "qcom,qcs8300-gpdsp-anoc",
2336 .data = &qcs8300_gpdsp_anoc},
2337 { .compatible = "qcom,qcs8300-lpass-ag-noc",
2338 .data = &qcs8300_lpass_ag_noc},
2339 { .compatible = "qcom,qcs8300-mc-virt",
2340 .data = &qcs8300_mc_virt},
2341 { .compatible = "qcom,qcs8300-mmss-noc",
2342 .data = &qcs8300_mmss_noc},
2343 { .compatible = "qcom,qcs8300-nspa-noc",
2344 .data = &qcs8300_nspa_noc},
2345 { .compatible = "qcom,qcs8300-pcie-anoc",
2346 .data = &qcs8300_pcie_anoc},
2347 { .compatible = "qcom,qcs8300-system-noc",
2348 .data = &qcs8300_system_noc},
2349 { }
2350};
2351MODULE_DEVICE_TABLE(of, qnoc_of_match);
2352
2353static struct platform_driver qnoc_driver = {
2354 .probe = qcom_icc_rpmh_probe,
2355 .remove = qcom_icc_rpmh_remove,
2356 .driver = {
2357 .name = "qnoc-qcs8300",
2358 .of_match_table = qnoc_of_match,
2359 .sync_state = icc_sync_state,
2360 },
2361};
2362
2363static int __init qnoc_driver_init(void)
2364{
2365 return platform_driver_register(&qnoc_driver);
2366}
2367core_initcall(qnoc_driver_init);
2368
2369static void __exit qnoc_driver_exit(void)
2370{
2371 platform_driver_unregister(&qnoc_driver);
2372}
2373module_exit(qnoc_driver_exit);
2374
2375MODULE_DESCRIPTION("QCS8300 NoC driver");
2376MODULE_LICENSE("GPL");