Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
4 *
5 */
6
7#include <linux/device.h>
8#include <linux/interconnect.h>
9#include <linux/interconnect-provider.h>
10#include <linux/module.h>
11#include <linux/of_platform.h>
12#include <dt-bindings/interconnect/qcom,sm8750-rpmh.h>
13
14#include "bcm-voter.h"
15#include "icc-rpmh.h"
16
17static struct qcom_icc_node qhm_qspi;
18static struct qcom_icc_node qhm_qup1;
19static struct qcom_icc_node qxm_qup02;
20static struct qcom_icc_node xm_sdc4;
21static struct qcom_icc_node xm_ufs_mem;
22static struct qcom_icc_node xm_usb3_0;
23static struct qcom_icc_node qhm_qdss_bam;
24static struct qcom_icc_node qhm_qup2;
25static struct qcom_icc_node qxm_crypto;
26static struct qcom_icc_node qxm_ipa;
27static struct qcom_icc_node qxm_soccp;
28static struct qcom_icc_node qxm_sp;
29static struct qcom_icc_node xm_qdss_etr_0;
30static struct qcom_icc_node xm_qdss_etr_1;
31static struct qcom_icc_node xm_sdc2;
32static struct qcom_icc_node qup0_core_master;
33static struct qcom_icc_node qup1_core_master;
34static struct qcom_icc_node qup2_core_master;
35static struct qcom_icc_node qsm_cfg;
36static struct qcom_icc_node qnm_gemnoc_cnoc;
37static struct qcom_icc_node qnm_gemnoc_pcie;
38static struct qcom_icc_node alm_gpu_tcu;
39static struct qcom_icc_node alm_sys_tcu;
40static struct qcom_icc_node chm_apps;
41static struct qcom_icc_node qnm_gpu;
42static struct qcom_icc_node qnm_lpass_gemnoc;
43static struct qcom_icc_node qnm_mdsp;
44static struct qcom_icc_node qnm_mnoc_hf;
45static struct qcom_icc_node qnm_mnoc_sf;
46static struct qcom_icc_node qnm_nsp_gemnoc;
47static struct qcom_icc_node qnm_pcie;
48static struct qcom_icc_node qnm_snoc_sf;
49static struct qcom_icc_node qnm_ubwc_p;
50static struct qcom_icc_node xm_gic;
51static struct qcom_icc_node qnm_lpiaon_noc;
52static struct qcom_icc_node qnm_lpass_lpinoc;
53static struct qcom_icc_node qnm_lpinoc_dsp_qns4m;
54static struct qcom_icc_node llcc_mc;
55static struct qcom_icc_node qnm_camnoc_hf;
56static struct qcom_icc_node qnm_camnoc_nrt_icp_sf;
57static struct qcom_icc_node qnm_camnoc_rt_cdm_sf;
58static struct qcom_icc_node qnm_camnoc_sf;
59static struct qcom_icc_node qnm_mdp;
60static struct qcom_icc_node qnm_vapss_hcp;
61static struct qcom_icc_node qnm_video_cv_cpu;
62static struct qcom_icc_node qnm_video_eva;
63static struct qcom_icc_node qnm_video_mvp;
64static struct qcom_icc_node qnm_video_v_cpu;
65static struct qcom_icc_node qsm_mnoc_cfg;
66static struct qcom_icc_node qnm_nsp;
67static struct qcom_icc_node qsm_pcie_anoc_cfg;
68static struct qcom_icc_node xm_pcie3;
69static struct qcom_icc_node qnm_aggre1_noc;
70static struct qcom_icc_node qnm_aggre2_noc;
71static struct qcom_icc_node qns_a1noc_snoc;
72static struct qcom_icc_node qns_a2noc_snoc;
73static struct qcom_icc_node qup0_core_slave;
74static struct qcom_icc_node qup1_core_slave;
75static struct qcom_icc_node qup2_core_slave;
76static struct qcom_icc_node qhs_ahb2phy0;
77static struct qcom_icc_node qhs_ahb2phy1;
78static struct qcom_icc_node qhs_camera_cfg;
79static struct qcom_icc_node qhs_clk_ctl;
80static struct qcom_icc_node qhs_crypto0_cfg;
81static struct qcom_icc_node qhs_display_cfg;
82static struct qcom_icc_node qhs_eva_cfg;
83static struct qcom_icc_node qhs_gpuss_cfg;
84static struct qcom_icc_node qhs_i2c;
85static struct qcom_icc_node qhs_i3c_ibi0_cfg;
86static struct qcom_icc_node qhs_i3c_ibi1_cfg;
87static struct qcom_icc_node qhs_imem_cfg;
88static struct qcom_icc_node qhs_mss_cfg;
89static struct qcom_icc_node qhs_pcie_cfg;
90static struct qcom_icc_node qhs_prng;
91static struct qcom_icc_node qhs_qdss_cfg;
92static struct qcom_icc_node qhs_qspi;
93static struct qcom_icc_node qhs_qup02;
94static struct qcom_icc_node qhs_qup1;
95static struct qcom_icc_node qhs_qup2;
96static struct qcom_icc_node qhs_sdc2;
97static struct qcom_icc_node qhs_sdc4;
98static struct qcom_icc_node qhs_spss_cfg;
99static struct qcom_icc_node qhs_tcsr;
100static struct qcom_icc_node qhs_tlmm;
101static struct qcom_icc_node qhs_ufs_mem_cfg;
102static struct qcom_icc_node qhs_usb3_0;
103static struct qcom_icc_node qhs_venus_cfg;
104static struct qcom_icc_node qhs_vsense_ctrl_cfg;
105static struct qcom_icc_node qss_mnoc_cfg;
106static struct qcom_icc_node qss_pcie_anoc_cfg;
107static struct qcom_icc_node xs_qdss_stm;
108static struct qcom_icc_node xs_sys_tcu_cfg;
109static struct qcom_icc_node qhs_aoss;
110static struct qcom_icc_node qhs_ipa;
111static struct qcom_icc_node qhs_ipc_router;
112static struct qcom_icc_node qhs_soccp;
113static struct qcom_icc_node qhs_tme_cfg;
114static struct qcom_icc_node qns_apss;
115static struct qcom_icc_node qss_cfg;
116static struct qcom_icc_node qss_ddrss_cfg;
117static struct qcom_icc_node qxs_boot_imem;
118static struct qcom_icc_node qxs_imem;
119static struct qcom_icc_node qxs_modem_boot_imem;
120static struct qcom_icc_node srvc_cnoc_main;
121static struct qcom_icc_node xs_pcie;
122static struct qcom_icc_node chs_ubwc_p;
123static struct qcom_icc_node qns_gem_noc_cnoc;
124static struct qcom_icc_node qns_llcc;
125static struct qcom_icc_node qns_pcie;
126static struct qcom_icc_node qns_lpass_ag_noc_gemnoc;
127static struct qcom_icc_node qns_lpass_aggnoc;
128static struct qcom_icc_node qns_lpi_aon_noc;
129static struct qcom_icc_node ebi;
130static struct qcom_icc_node qns_mem_noc_hf;
131static struct qcom_icc_node qns_mem_noc_sf;
132static struct qcom_icc_node srvc_mnoc;
133static struct qcom_icc_node qns_nsp_gemnoc;
134static struct qcom_icc_node qns_pcie_mem_noc;
135static struct qcom_icc_node srvc_pcie_aggre_noc;
136static struct qcom_icc_node qns_gemnoc_sf;
137
138static struct qcom_icc_node qhm_qspi = {
139 .name = "qhm_qspi",
140 .channels = 1,
141 .buswidth = 4,
142 .num_links = 1,
143 .link_nodes = { &qns_a1noc_snoc },
144};
145
146static struct qcom_icc_node qhm_qup1 = {
147 .name = "qhm_qup1",
148 .channels = 1,
149 .buswidth = 4,
150 .num_links = 1,
151 .link_nodes = { &qns_a1noc_snoc },
152};
153
154static struct qcom_icc_node qxm_qup02 = {
155 .name = "qxm_qup02",
156 .channels = 1,
157 .buswidth = 8,
158 .num_links = 1,
159 .link_nodes = { &qns_a1noc_snoc },
160};
161
162static struct qcom_icc_node xm_sdc4 = {
163 .name = "xm_sdc4",
164 .channels = 1,
165 .buswidth = 8,
166 .num_links = 1,
167 .link_nodes = { &qns_a1noc_snoc },
168};
169
170static struct qcom_icc_node xm_ufs_mem = {
171 .name = "xm_ufs_mem",
172 .channels = 1,
173 .buswidth = 16,
174 .num_links = 1,
175 .link_nodes = { &qns_a1noc_snoc },
176};
177
178static struct qcom_icc_node xm_usb3_0 = {
179 .name = "xm_usb3_0",
180 .channels = 1,
181 .buswidth = 8,
182 .num_links = 1,
183 .link_nodes = { &qns_a1noc_snoc },
184};
185
186static struct qcom_icc_node qhm_qdss_bam = {
187 .name = "qhm_qdss_bam",
188 .channels = 1,
189 .buswidth = 4,
190 .num_links = 1,
191 .link_nodes = { &qns_a2noc_snoc },
192};
193
194static struct qcom_icc_node qhm_qup2 = {
195 .name = "qhm_qup2",
196 .channels = 1,
197 .buswidth = 4,
198 .num_links = 1,
199 .link_nodes = { &qns_a2noc_snoc },
200};
201
202static struct qcom_icc_node qxm_crypto = {
203 .name = "qxm_crypto",
204 .channels = 1,
205 .buswidth = 8,
206 .num_links = 1,
207 .link_nodes = { &qns_a2noc_snoc },
208};
209
210static struct qcom_icc_node qxm_ipa = {
211 .name = "qxm_ipa",
212 .channels = 1,
213 .buswidth = 8,
214 .num_links = 1,
215 .link_nodes = { &qns_a2noc_snoc },
216};
217
218static struct qcom_icc_node qxm_soccp = {
219 .name = "qxm_soccp",
220 .channels = 1,
221 .buswidth = 8,
222 .num_links = 1,
223 .link_nodes = { &qns_a2noc_snoc },
224};
225
226static struct qcom_icc_node qxm_sp = {
227 .name = "qxm_sp",
228 .channels = 1,
229 .buswidth = 8,
230 .num_links = 1,
231 .link_nodes = { &qns_a2noc_snoc },
232};
233
234static struct qcom_icc_node xm_qdss_etr_0 = {
235 .name = "xm_qdss_etr_0",
236 .channels = 1,
237 .buswidth = 8,
238 .num_links = 1,
239 .link_nodes = { &qns_a2noc_snoc },
240};
241
242static struct qcom_icc_node xm_qdss_etr_1 = {
243 .name = "xm_qdss_etr_1",
244 .channels = 1,
245 .buswidth = 8,
246 .num_links = 1,
247 .link_nodes = { &qns_a2noc_snoc },
248};
249
250static struct qcom_icc_node xm_sdc2 = {
251 .name = "xm_sdc2",
252 .channels = 1,
253 .buswidth = 8,
254 .num_links = 1,
255 .link_nodes = { &qns_a2noc_snoc },
256};
257
258static struct qcom_icc_node qup0_core_master = {
259 .name = "qup0_core_master",
260 .channels = 1,
261 .buswidth = 4,
262 .num_links = 1,
263 .link_nodes = { &qup0_core_slave },
264};
265
266static struct qcom_icc_node qup1_core_master = {
267 .name = "qup1_core_master",
268 .channels = 1,
269 .buswidth = 4,
270 .num_links = 1,
271 .link_nodes = { &qup1_core_slave },
272};
273
274static struct qcom_icc_node qup2_core_master = {
275 .name = "qup2_core_master",
276 .channels = 1,
277 .buswidth = 4,
278 .num_links = 1,
279 .link_nodes = { &qup2_core_slave },
280};
281
282static struct qcom_icc_node qsm_cfg = {
283 .name = "qsm_cfg",
284 .channels = 1,
285 .buswidth = 4,
286 .num_links = 33,
287 .link_nodes = { &qhs_ahb2phy0, &qhs_ahb2phy1,
288 &qhs_camera_cfg, &qhs_clk_ctl,
289 &qhs_crypto0_cfg, &qhs_display_cfg,
290 &qhs_eva_cfg, &qhs_gpuss_cfg,
291 &qhs_i2c, &qhs_i3c_ibi0_cfg,
292 &qhs_i3c_ibi1_cfg, &qhs_imem_cfg,
293 &qhs_mss_cfg, &qhs_pcie_cfg,
294 &qhs_prng, &qhs_qdss_cfg,
295 &qhs_qspi, &qhs_qup02,
296 &qhs_qup1, &qhs_qup2,
297 &qhs_sdc2, &qhs_sdc4,
298 &qhs_spss_cfg, &qhs_tcsr,
299 &qhs_tlmm, &qhs_ufs_mem_cfg,
300 &qhs_usb3_0, &qhs_venus_cfg,
301 &qhs_vsense_ctrl_cfg, &qss_mnoc_cfg,
302 &qss_pcie_anoc_cfg, &xs_qdss_stm,
303 &xs_sys_tcu_cfg },
304};
305
306static struct qcom_icc_node qnm_gemnoc_cnoc = {
307 .name = "qnm_gemnoc_cnoc",
308 .channels = 1,
309 .buswidth = 16,
310 .num_links = 12,
311 .link_nodes = { &qhs_aoss, &qhs_ipa,
312 &qhs_ipc_router, &qhs_soccp,
313 &qhs_tme_cfg, &qns_apss,
314 &qss_cfg, &qss_ddrss_cfg,
315 &qxs_boot_imem, &qxs_imem,
316 &qxs_modem_boot_imem, &srvc_cnoc_main },
317};
318
319static struct qcom_icc_node qnm_gemnoc_pcie = {
320 .name = "qnm_gemnoc_pcie",
321 .channels = 1,
322 .buswidth = 8,
323 .num_links = 1,
324 .link_nodes = { &xs_pcie },
325};
326
327static struct qcom_icc_node alm_gpu_tcu = {
328 .name = "alm_gpu_tcu",
329 .channels = 1,
330 .buswidth = 8,
331 .num_links = 2,
332 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
333};
334
335static struct qcom_icc_node alm_sys_tcu = {
336 .name = "alm_sys_tcu",
337 .channels = 1,
338 .buswidth = 8,
339 .num_links = 2,
340 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
341};
342
343static struct qcom_icc_node chm_apps = {
344 .name = "chm_apps",
345 .channels = 4,
346 .buswidth = 32,
347 .num_links = 4,
348 .link_nodes = { &chs_ubwc_p, &qns_gem_noc_cnoc,
349 &qns_llcc, &qns_pcie },
350};
351
352static struct qcom_icc_node qnm_gpu = {
353 .name = "qnm_gpu",
354 .channels = 2,
355 .buswidth = 32,
356 .num_links = 2,
357 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
358};
359
360static struct qcom_icc_node qnm_lpass_gemnoc = {
361 .name = "qnm_lpass_gemnoc",
362 .channels = 1,
363 .buswidth = 16,
364 .num_links = 3,
365 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
366 &qns_pcie },
367};
368
369static struct qcom_icc_node qnm_mdsp = {
370 .name = "qnm_mdsp",
371 .channels = 1,
372 .buswidth = 16,
373 .num_links = 3,
374 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
375 &qns_pcie },
376};
377
378static struct qcom_icc_node qnm_mnoc_hf = {
379 .name = "qnm_mnoc_hf",
380 .channels = 2,
381 .buswidth = 32,
382 .num_links = 2,
383 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
384};
385
386static struct qcom_icc_node qnm_mnoc_sf = {
387 .name = "qnm_mnoc_sf",
388 .channels = 2,
389 .buswidth = 32,
390 .num_links = 2,
391 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
392};
393
394static struct qcom_icc_node qnm_nsp_gemnoc = {
395 .name = "qnm_nsp_gemnoc",
396 .channels = 2,
397 .buswidth = 32,
398 .num_links = 3,
399 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
400 &qns_pcie },
401};
402
403static struct qcom_icc_node qnm_pcie = {
404 .name = "qnm_pcie",
405 .channels = 1,
406 .buswidth = 8,
407 .num_links = 2,
408 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
409};
410
411static struct qcom_icc_node qnm_snoc_sf = {
412 .name = "qnm_snoc_sf",
413 .channels = 1,
414 .buswidth = 16,
415 .num_links = 3,
416 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
417 &qns_pcie },
418};
419
420static struct qcom_icc_node qnm_ubwc_p = {
421 .name = "qnm_ubwc_p",
422 .channels = 1,
423 .buswidth = 32,
424 .num_links = 1,
425 .link_nodes = { &qns_llcc },
426};
427
428static struct qcom_icc_node xm_gic = {
429 .name = "xm_gic",
430 .channels = 1,
431 .buswidth = 8,
432 .num_links = 1,
433 .link_nodes = { &qns_llcc },
434};
435
436static struct qcom_icc_node qnm_lpiaon_noc = {
437 .name = "qnm_lpiaon_noc",
438 .channels = 1,
439 .buswidth = 16,
440 .num_links = 1,
441 .link_nodes = { &qns_lpass_ag_noc_gemnoc },
442};
443
444static struct qcom_icc_node qnm_lpass_lpinoc = {
445 .name = "qnm_lpass_lpinoc",
446 .channels = 1,
447 .buswidth = 16,
448 .num_links = 1,
449 .link_nodes = { &qns_lpass_aggnoc },
450};
451
452static struct qcom_icc_node qnm_lpinoc_dsp_qns4m = {
453 .name = "qnm_lpinoc_dsp_qns4m",
454 .channels = 1,
455 .buswidth = 16,
456 .num_links = 1,
457 .link_nodes = { &qns_lpi_aon_noc },
458};
459
460static struct qcom_icc_node llcc_mc = {
461 .name = "llcc_mc",
462 .channels = 4,
463 .buswidth = 4,
464 .num_links = 1,
465 .link_nodes = { &ebi },
466};
467
468static struct qcom_icc_node qnm_camnoc_hf = {
469 .name = "qnm_camnoc_hf",
470 .channels = 2,
471 .buswidth = 32,
472 .num_links = 1,
473 .link_nodes = { &qns_mem_noc_hf },
474};
475
476static struct qcom_icc_node qnm_camnoc_nrt_icp_sf = {
477 .name = "qnm_camnoc_nrt_icp_sf",
478 .channels = 1,
479 .buswidth = 8,
480 .num_links = 1,
481 .link_nodes = { &qns_mem_noc_sf },
482};
483
484static struct qcom_icc_node qnm_camnoc_rt_cdm_sf = {
485 .name = "qnm_camnoc_rt_cdm_sf",
486 .channels = 1,
487 .buswidth = 8,
488 .num_links = 1,
489 .link_nodes = { &qns_mem_noc_sf },
490};
491
492static struct qcom_icc_node qnm_camnoc_sf = {
493 .name = "qnm_camnoc_sf",
494 .channels = 2,
495 .buswidth = 32,
496 .num_links = 1,
497 .link_nodes = { &qns_mem_noc_sf },
498};
499
500static struct qcom_icc_node qnm_mdp = {
501 .name = "qnm_mdp",
502 .channels = 2,
503 .buswidth = 32,
504 .num_links = 1,
505 .link_nodes = { &qns_mem_noc_hf },
506};
507
508static struct qcom_icc_node qnm_vapss_hcp = {
509 .name = "qnm_vapss_hcp",
510 .channels = 1,
511 .buswidth = 32,
512 .num_links = 1,
513 .link_nodes = { &qns_mem_noc_sf },
514};
515
516static struct qcom_icc_node qnm_video_cv_cpu = {
517 .name = "qnm_video_cv_cpu",
518 .channels = 1,
519 .buswidth = 8,
520 .num_links = 1,
521 .link_nodes = { &qns_mem_noc_sf },
522};
523
524static struct qcom_icc_node qnm_video_eva = {
525 .name = "qnm_video_eva",
526 .channels = 2,
527 .buswidth = 32,
528 .num_links = 1,
529 .link_nodes = { &qns_mem_noc_sf },
530};
531
532static struct qcom_icc_node qnm_video_mvp = {
533 .name = "qnm_video_mvp",
534 .channels = 2,
535 .buswidth = 32,
536 .num_links = 1,
537 .link_nodes = { &qns_mem_noc_sf },
538};
539
540static struct qcom_icc_node qnm_video_v_cpu = {
541 .name = "qnm_video_v_cpu",
542 .channels = 1,
543 .buswidth = 8,
544 .num_links = 1,
545 .link_nodes = { &qns_mem_noc_sf },
546};
547
548static struct qcom_icc_node qsm_mnoc_cfg = {
549 .name = "qsm_mnoc_cfg",
550 .channels = 1,
551 .buswidth = 4,
552 .num_links = 1,
553 .link_nodes = { &srvc_mnoc },
554};
555
556static struct qcom_icc_node qnm_nsp = {
557 .name = "qnm_nsp",
558 .channels = 2,
559 .buswidth = 32,
560 .num_links = 1,
561 .link_nodes = { &qns_nsp_gemnoc },
562};
563
564static struct qcom_icc_node qsm_pcie_anoc_cfg = {
565 .name = "qsm_pcie_anoc_cfg",
566 .channels = 1,
567 .buswidth = 4,
568 .num_links = 1,
569 .link_nodes = { &srvc_pcie_aggre_noc },
570};
571
572static struct qcom_icc_node xm_pcie3 = {
573 .name = "xm_pcie3",
574 .channels = 1,
575 .buswidth = 8,
576 .num_links = 1,
577 .link_nodes = { &qns_pcie_mem_noc },
578};
579
580static struct qcom_icc_node qnm_aggre1_noc = {
581 .name = "qnm_aggre1_noc",
582 .channels = 1,
583 .buswidth = 16,
584 .num_links = 1,
585 .link_nodes = { &qns_gemnoc_sf },
586};
587
588static struct qcom_icc_node qnm_aggre2_noc = {
589 .name = "qnm_aggre2_noc",
590 .channels = 1,
591 .buswidth = 16,
592 .num_links = 1,
593 .link_nodes = { &qns_gemnoc_sf },
594};
595
596static struct qcom_icc_node qns_a1noc_snoc = {
597 .name = "qns_a1noc_snoc",
598 .channels = 1,
599 .buswidth = 16,
600 .num_links = 1,
601 .link_nodes = { &qnm_aggre1_noc },
602};
603
604static struct qcom_icc_node qns_a2noc_snoc = {
605 .name = "qns_a2noc_snoc",
606 .channels = 1,
607 .buswidth = 16,
608 .num_links = 1,
609 .link_nodes = { &qnm_aggre2_noc },
610};
611
612static struct qcom_icc_node qup0_core_slave = {
613 .name = "qup0_core_slave",
614 .channels = 1,
615 .buswidth = 4,
616};
617
618static struct qcom_icc_node qup1_core_slave = {
619 .name = "qup1_core_slave",
620 .channels = 1,
621 .buswidth = 4,
622};
623
624static struct qcom_icc_node qup2_core_slave = {
625 .name = "qup2_core_slave",
626 .channels = 1,
627 .buswidth = 4,
628};
629
630static struct qcom_icc_node qhs_ahb2phy0 = {
631 .name = "qhs_ahb2phy0",
632 .channels = 1,
633 .buswidth = 4,
634};
635
636static struct qcom_icc_node qhs_ahb2phy1 = {
637 .name = "qhs_ahb2phy1",
638 .channels = 1,
639 .buswidth = 4,
640};
641
642static struct qcom_icc_node qhs_camera_cfg = {
643 .name = "qhs_camera_cfg",
644 .channels = 1,
645 .buswidth = 4,
646};
647
648static struct qcom_icc_node qhs_clk_ctl = {
649 .name = "qhs_clk_ctl",
650 .channels = 1,
651 .buswidth = 4,
652};
653
654static struct qcom_icc_node qhs_crypto0_cfg = {
655 .name = "qhs_crypto0_cfg",
656 .channels = 1,
657 .buswidth = 4,
658};
659
660static struct qcom_icc_node qhs_display_cfg = {
661 .name = "qhs_display_cfg",
662 .channels = 1,
663 .buswidth = 4,
664};
665
666static struct qcom_icc_node qhs_eva_cfg = {
667 .name = "qhs_eva_cfg",
668 .channels = 1,
669 .buswidth = 4,
670};
671
672static struct qcom_icc_node qhs_gpuss_cfg = {
673 .name = "qhs_gpuss_cfg",
674 .channels = 1,
675 .buswidth = 8,
676};
677
678static struct qcom_icc_node qhs_i2c = {
679 .name = "qhs_i2c",
680 .channels = 1,
681 .buswidth = 4,
682};
683
684static struct qcom_icc_node qhs_i3c_ibi0_cfg = {
685 .name = "qhs_i3c_ibi0_cfg",
686 .channels = 1,
687 .buswidth = 4,
688};
689
690static struct qcom_icc_node qhs_i3c_ibi1_cfg = {
691 .name = "qhs_i3c_ibi1_cfg",
692 .channels = 1,
693 .buswidth = 4,
694};
695
696static struct qcom_icc_node qhs_imem_cfg = {
697 .name = "qhs_imem_cfg",
698 .channels = 1,
699 .buswidth = 4,
700};
701
702static struct qcom_icc_node qhs_mss_cfg = {
703 .name = "qhs_mss_cfg",
704 .channels = 1,
705 .buswidth = 4,
706};
707
708static struct qcom_icc_node qhs_pcie_cfg = {
709 .name = "qhs_pcie_cfg",
710 .channels = 1,
711 .buswidth = 4,
712};
713
714static struct qcom_icc_node qhs_prng = {
715 .name = "qhs_prng",
716 .channels = 1,
717 .buswidth = 4,
718};
719
720static struct qcom_icc_node qhs_qdss_cfg = {
721 .name = "qhs_qdss_cfg",
722 .channels = 1,
723 .buswidth = 4,
724};
725
726static struct qcom_icc_node qhs_qspi = {
727 .name = "qhs_qspi",
728 .channels = 1,
729 .buswidth = 4,
730};
731
732static struct qcom_icc_node qhs_qup02 = {
733 .name = "qhs_qup02",
734 .channels = 1,
735 .buswidth = 4,
736};
737
738static struct qcom_icc_node qhs_qup1 = {
739 .name = "qhs_qup1",
740 .channels = 1,
741 .buswidth = 4,
742};
743
744static struct qcom_icc_node qhs_qup2 = {
745 .name = "qhs_qup2",
746 .channels = 1,
747 .buswidth = 4,
748};
749
750static struct qcom_icc_node qhs_sdc2 = {
751 .name = "qhs_sdc2",
752 .channels = 1,
753 .buswidth = 4,
754};
755
756static struct qcom_icc_node qhs_sdc4 = {
757 .name = "qhs_sdc4",
758 .channels = 1,
759 .buswidth = 4,
760};
761
762static struct qcom_icc_node qhs_spss_cfg = {
763 .name = "qhs_spss_cfg",
764 .channels = 1,
765 .buswidth = 4,
766};
767
768static struct qcom_icc_node qhs_tcsr = {
769 .name = "qhs_tcsr",
770 .channels = 1,
771 .buswidth = 4,
772};
773
774static struct qcom_icc_node qhs_tlmm = {
775 .name = "qhs_tlmm",
776 .channels = 1,
777 .buswidth = 4,
778};
779
780static struct qcom_icc_node qhs_ufs_mem_cfg = {
781 .name = "qhs_ufs_mem_cfg",
782 .channels = 1,
783 .buswidth = 4,
784};
785
786static struct qcom_icc_node qhs_usb3_0 = {
787 .name = "qhs_usb3_0",
788 .channels = 1,
789 .buswidth = 4,
790};
791
792static struct qcom_icc_node qhs_venus_cfg = {
793 .name = "qhs_venus_cfg",
794 .channels = 1,
795 .buswidth = 4,
796};
797
798static struct qcom_icc_node qhs_vsense_ctrl_cfg = {
799 .name = "qhs_vsense_ctrl_cfg",
800 .channels = 1,
801 .buswidth = 4,
802};
803
804static struct qcom_icc_node qss_mnoc_cfg = {
805 .name = "qss_mnoc_cfg",
806 .channels = 1,
807 .buswidth = 4,
808 .num_links = 1,
809 .link_nodes = { &qsm_mnoc_cfg },
810};
811
812static struct qcom_icc_node qss_pcie_anoc_cfg = {
813 .name = "qss_pcie_anoc_cfg",
814 .channels = 1,
815 .buswidth = 4,
816 .num_links = 1,
817 .link_nodes = { &qsm_pcie_anoc_cfg },
818};
819
820static struct qcom_icc_node xs_qdss_stm = {
821 .name = "xs_qdss_stm",
822 .channels = 1,
823 .buswidth = 4,
824};
825
826static struct qcom_icc_node xs_sys_tcu_cfg = {
827 .name = "xs_sys_tcu_cfg",
828 .channels = 1,
829 .buswidth = 8,
830};
831
832static struct qcom_icc_node qhs_aoss = {
833 .name = "qhs_aoss",
834 .channels = 1,
835 .buswidth = 4,
836};
837
838static struct qcom_icc_node qhs_ipa = {
839 .name = "qhs_ipa",
840 .channels = 1,
841 .buswidth = 4,
842};
843
844static struct qcom_icc_node qhs_ipc_router = {
845 .name = "qhs_ipc_router",
846 .channels = 1,
847 .buswidth = 4,
848};
849
850static struct qcom_icc_node qhs_soccp = {
851 .name = "qhs_soccp",
852 .channels = 1,
853 .buswidth = 4,
854};
855
856static struct qcom_icc_node qhs_tme_cfg = {
857 .name = "qhs_tme_cfg",
858 .channels = 1,
859 .buswidth = 4,
860};
861
862static struct qcom_icc_node qns_apss = {
863 .name = "qns_apss",
864 .channels = 1,
865 .buswidth = 8,
866};
867
868static struct qcom_icc_node qss_cfg = {
869 .name = "qss_cfg",
870 .channels = 1,
871 .buswidth = 4,
872 .num_links = 1,
873 .link_nodes = { &qsm_cfg },
874};
875
876static struct qcom_icc_node qss_ddrss_cfg = {
877 .name = "qss_ddrss_cfg",
878 .channels = 1,
879 .buswidth = 4,
880};
881
882static struct qcom_icc_node qxs_boot_imem = {
883 .name = "qxs_boot_imem",
884 .channels = 1,
885 .buswidth = 16,
886};
887
888static struct qcom_icc_node qxs_imem = {
889 .name = "qxs_imem",
890 .channels = 1,
891 .buswidth = 8,
892};
893
894static struct qcom_icc_node qxs_modem_boot_imem = {
895 .name = "qxs_modem_boot_imem",
896 .channels = 1,
897 .buswidth = 8,
898};
899
900static struct qcom_icc_node srvc_cnoc_main = {
901 .name = "srvc_cnoc_main",
902 .channels = 1,
903 .buswidth = 4,
904};
905
906static struct qcom_icc_node xs_pcie = {
907 .name = "xs_pcie",
908 .channels = 1,
909 .buswidth = 8,
910};
911
912static struct qcom_icc_node chs_ubwc_p = {
913 .name = "chs_ubwc_p",
914 .channels = 1,
915 .buswidth = 32,
916};
917
918static struct qcom_icc_node qns_gem_noc_cnoc = {
919 .name = "qns_gem_noc_cnoc",
920 .channels = 1,
921 .buswidth = 16,
922 .num_links = 1,
923 .link_nodes = { &qnm_gemnoc_cnoc },
924};
925
926static struct qcom_icc_node qns_llcc = {
927 .name = "qns_llcc",
928 .channels = 4,
929 .buswidth = 16,
930 .num_links = 1,
931 .link_nodes = { &llcc_mc },
932};
933
934static struct qcom_icc_node qns_pcie = {
935 .name = "qns_pcie",
936 .channels = 1,
937 .buswidth = 8,
938 .num_links = 1,
939 .link_nodes = { &qnm_gemnoc_pcie },
940};
941
942static struct qcom_icc_node qns_lpass_ag_noc_gemnoc = {
943 .name = "qns_lpass_ag_noc_gemnoc",
944 .channels = 1,
945 .buswidth = 16,
946 .num_links = 1,
947 .link_nodes = { &qnm_lpass_gemnoc },
948};
949
950static struct qcom_icc_node qns_lpass_aggnoc = {
951 .name = "qns_lpass_aggnoc",
952 .channels = 1,
953 .buswidth = 16,
954 .num_links = 1,
955 .link_nodes = { &qnm_lpiaon_noc },
956};
957
958static struct qcom_icc_node qns_lpi_aon_noc = {
959 .name = "qns_lpi_aon_noc",
960 .channels = 1,
961 .buswidth = 16,
962 .num_links = 1,
963 .link_nodes = { &qnm_lpass_lpinoc },
964};
965
966static struct qcom_icc_node ebi = {
967 .name = "ebi",
968 .channels = 4,
969 .buswidth = 4,
970};
971
972static struct qcom_icc_node qns_mem_noc_hf = {
973 .name = "qns_mem_noc_hf",
974 .channels = 2,
975 .buswidth = 32,
976 .num_links = 1,
977 .link_nodes = { &qnm_mnoc_hf },
978};
979
980static struct qcom_icc_node qns_mem_noc_sf = {
981 .name = "qns_mem_noc_sf",
982 .channels = 2,
983 .buswidth = 32,
984 .num_links = 1,
985 .link_nodes = { &qnm_mnoc_sf },
986};
987
988static struct qcom_icc_node srvc_mnoc = {
989 .name = "srvc_mnoc",
990 .channels = 1,
991 .buswidth = 4,
992};
993
994static struct qcom_icc_node qns_nsp_gemnoc = {
995 .name = "qns_nsp_gemnoc",
996 .channels = 2,
997 .buswidth = 32,
998 .num_links = 1,
999 .link_nodes = { &qnm_nsp_gemnoc },
1000};
1001
1002static struct qcom_icc_node qns_pcie_mem_noc = {
1003 .name = "qns_pcie_mem_noc",
1004 .channels = 1,
1005 .buswidth = 8,
1006 .num_links = 1,
1007 .link_nodes = { &qnm_pcie },
1008};
1009
1010static struct qcom_icc_node srvc_pcie_aggre_noc = {
1011 .name = "srvc_pcie_aggre_noc",
1012 .channels = 1,
1013 .buswidth = 4,
1014};
1015
1016static struct qcom_icc_node qns_gemnoc_sf = {
1017 .name = "qns_gemnoc_sf",
1018 .channels = 1,
1019 .buswidth = 16,
1020 .num_links = 1,
1021 .link_nodes = { &qnm_snoc_sf },
1022};
1023
1024static struct qcom_icc_bcm bcm_acv = {
1025 .name = "ACV",
1026 .enable_mask = BIT(0),
1027 .num_nodes = 1,
1028 .nodes = { &ebi },
1029};
1030
1031static struct qcom_icc_bcm bcm_ce0 = {
1032 .name = "CE0",
1033 .num_nodes = 1,
1034 .nodes = { &qxm_crypto },
1035};
1036
1037static struct qcom_icc_bcm bcm_cn0 = {
1038 .name = "CN0",
1039 .enable_mask = BIT(0),
1040 .keepalive = true,
1041 .num_nodes = 44,
1042 .nodes = { &qsm_cfg, &qhs_ahb2phy0,
1043 &qhs_ahb2phy1, &qhs_camera_cfg,
1044 &qhs_clk_ctl, &qhs_crypto0_cfg,
1045 &qhs_eva_cfg, &qhs_gpuss_cfg,
1046 &qhs_i3c_ibi0_cfg, &qhs_i3c_ibi1_cfg,
1047 &qhs_imem_cfg, &qhs_mss_cfg,
1048 &qhs_pcie_cfg, &qhs_prng,
1049 &qhs_qdss_cfg, &qhs_qspi,
1050 &qhs_sdc2, &qhs_sdc4,
1051 &qhs_spss_cfg, &qhs_tcsr,
1052 &qhs_tlmm, &qhs_ufs_mem_cfg,
1053 &qhs_usb3_0, &qhs_venus_cfg,
1054 &qhs_vsense_ctrl_cfg, &qss_mnoc_cfg,
1055 &qss_pcie_anoc_cfg, &xs_qdss_stm,
1056 &xs_sys_tcu_cfg, &qnm_gemnoc_cnoc,
1057 &qnm_gemnoc_pcie, &qhs_aoss,
1058 &qhs_ipa, &qhs_ipc_router,
1059 &qhs_soccp, &qhs_tme_cfg,
1060 &qns_apss, &qss_cfg,
1061 &qss_ddrss_cfg, &qxs_boot_imem,
1062 &qxs_imem, &qxs_modem_boot_imem,
1063 &srvc_cnoc_main, &xs_pcie },
1064};
1065
1066static struct qcom_icc_bcm bcm_cn1 = {
1067 .name = "CN1",
1068 .num_nodes = 5,
1069 .nodes = { &qhs_display_cfg, &qhs_i2c,
1070 &qhs_qup02, &qhs_qup1,
1071 &qhs_qup2 },
1072};
1073
1074static struct qcom_icc_bcm bcm_co0 = {
1075 .name = "CO0",
1076 .enable_mask = BIT(0),
1077 .num_nodes = 2,
1078 .nodes = { &qnm_nsp, &qns_nsp_gemnoc },
1079};
1080
1081static struct qcom_icc_bcm bcm_lp0 = {
1082 .name = "LP0",
1083 .num_nodes = 2,
1084 .nodes = { &qnm_lpass_lpinoc, &qns_lpass_aggnoc },
1085};
1086
1087static struct qcom_icc_bcm bcm_mc0 = {
1088 .name = "MC0",
1089 .keepalive = true,
1090 .num_nodes = 1,
1091 .nodes = { &ebi },
1092};
1093
1094static struct qcom_icc_bcm bcm_mm0 = {
1095 .name = "MM0",
1096 .num_nodes = 1,
1097 .nodes = { &qns_mem_noc_hf },
1098};
1099
1100static struct qcom_icc_bcm bcm_mm1 = {
1101 .name = "MM1",
1102 .enable_mask = BIT(0),
1103 .num_nodes = 9,
1104 .nodes = { &qnm_camnoc_hf, &qnm_camnoc_nrt_icp_sf,
1105 &qnm_camnoc_rt_cdm_sf, &qnm_camnoc_sf,
1106 &qnm_vapss_hcp, &qnm_video_cv_cpu,
1107 &qnm_video_mvp, &qnm_video_v_cpu,
1108 &qns_mem_noc_sf },
1109};
1110
1111static struct qcom_icc_bcm bcm_qup0 = {
1112 .name = "QUP0",
1113 .keepalive = true,
1114 .vote_scale = 1,
1115 .num_nodes = 1,
1116 .nodes = { &qup0_core_slave },
1117};
1118
1119static struct qcom_icc_bcm bcm_qup1 = {
1120 .name = "QUP1",
1121 .keepalive = true,
1122 .vote_scale = 1,
1123 .num_nodes = 1,
1124 .nodes = { &qup1_core_slave },
1125};
1126
1127static struct qcom_icc_bcm bcm_qup2 = {
1128 .name = "QUP2",
1129 .keepalive = true,
1130 .vote_scale = 1,
1131 .num_nodes = 1,
1132 .nodes = { &qup2_core_slave },
1133};
1134
1135static struct qcom_icc_bcm bcm_sh0 = {
1136 .name = "SH0",
1137 .keepalive = true,
1138 .num_nodes = 1,
1139 .nodes = { &qns_llcc },
1140};
1141
1142static struct qcom_icc_bcm bcm_sh1 = {
1143 .name = "SH1",
1144 .enable_mask = BIT(0),
1145 .num_nodes = 14,
1146 .nodes = { &alm_gpu_tcu, &alm_sys_tcu,
1147 &chm_apps, &qnm_gpu,
1148 &qnm_mdsp, &qnm_mnoc_hf,
1149 &qnm_mnoc_sf, &qnm_nsp_gemnoc,
1150 &qnm_pcie, &qnm_snoc_sf,
1151 &xm_gic, &chs_ubwc_p,
1152 &qns_gem_noc_cnoc, &qns_pcie },
1153};
1154
1155static struct qcom_icc_bcm bcm_sn0 = {
1156 .name = "SN0",
1157 .keepalive = true,
1158 .num_nodes = 1,
1159 .nodes = { &qns_gemnoc_sf },
1160};
1161
1162static struct qcom_icc_bcm bcm_sn2 = {
1163 .name = "SN2",
1164 .num_nodes = 1,
1165 .nodes = { &qnm_aggre1_noc },
1166};
1167
1168static struct qcom_icc_bcm bcm_sn3 = {
1169 .name = "SN3",
1170 .num_nodes = 1,
1171 .nodes = { &qnm_aggre2_noc },
1172};
1173
1174static struct qcom_icc_bcm bcm_sn4 = {
1175 .name = "SN4",
1176 .num_nodes = 1,
1177 .nodes = { &qns_pcie_mem_noc },
1178};
1179
1180static struct qcom_icc_bcm bcm_ubw0 = {
1181 .name = "UBW0",
1182 .num_nodes = 1,
1183 .nodes = { &qnm_ubwc_p },
1184};
1185
1186static struct qcom_icc_node * const aggre1_noc_nodes[] = {
1187 [MASTER_QSPI_0] = &qhm_qspi,
1188 [MASTER_QUP_1] = &qhm_qup1,
1189 [MASTER_QUP_3] = &qxm_qup02,
1190 [MASTER_SDCC_4] = &xm_sdc4,
1191 [MASTER_UFS_MEM] = &xm_ufs_mem,
1192 [MASTER_USB3_0] = &xm_usb3_0,
1193 [SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc,
1194};
1195
1196static const struct qcom_icc_desc sm8750_aggre1_noc = {
1197 .nodes = aggre1_noc_nodes,
1198 .num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
1199};
1200
1201static struct qcom_icc_bcm * const aggre2_noc_bcms[] = {
1202 &bcm_ce0,
1203};
1204
1205static struct qcom_icc_node * const aggre2_noc_nodes[] = {
1206 [MASTER_QDSS_BAM] = &qhm_qdss_bam,
1207 [MASTER_QUP_2] = &qhm_qup2,
1208 [MASTER_CRYPTO] = &qxm_crypto,
1209 [MASTER_IPA] = &qxm_ipa,
1210 [MASTER_SOCCP_AGGR_NOC] = &qxm_soccp,
1211 [MASTER_SP] = &qxm_sp,
1212 [MASTER_QDSS_ETR] = &xm_qdss_etr_0,
1213 [MASTER_QDSS_ETR_1] = &xm_qdss_etr_1,
1214 [MASTER_SDCC_2] = &xm_sdc2,
1215 [SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc,
1216};
1217
1218static const struct qcom_icc_desc sm8750_aggre2_noc = {
1219 .nodes = aggre2_noc_nodes,
1220 .num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
1221 .bcms = aggre2_noc_bcms,
1222 .num_bcms = ARRAY_SIZE(aggre2_noc_bcms),
1223};
1224
1225static struct qcom_icc_bcm * const clk_virt_bcms[] = {
1226 &bcm_qup0,
1227 &bcm_qup1,
1228 &bcm_qup2,
1229};
1230
1231static struct qcom_icc_node * const clk_virt_nodes[] = {
1232 [MASTER_QUP_CORE_0] = &qup0_core_master,
1233 [MASTER_QUP_CORE_1] = &qup1_core_master,
1234 [MASTER_QUP_CORE_2] = &qup2_core_master,
1235 [SLAVE_QUP_CORE_0] = &qup0_core_slave,
1236 [SLAVE_QUP_CORE_1] = &qup1_core_slave,
1237 [SLAVE_QUP_CORE_2] = &qup2_core_slave,
1238};
1239
1240static const struct qcom_icc_desc sm8750_clk_virt = {
1241 .nodes = clk_virt_nodes,
1242 .num_nodes = ARRAY_SIZE(clk_virt_nodes),
1243 .bcms = clk_virt_bcms,
1244 .num_bcms = ARRAY_SIZE(clk_virt_bcms),
1245};
1246
1247static struct qcom_icc_bcm * const config_noc_bcms[] = {
1248 &bcm_cn0,
1249 &bcm_cn1,
1250};
1251
1252static struct qcom_icc_node * const config_noc_nodes[] = {
1253 [MASTER_CNOC_CFG] = &qsm_cfg,
1254 [SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy0,
1255 [SLAVE_AHB2PHY_NORTH] = &qhs_ahb2phy1,
1256 [SLAVE_CAMERA_CFG] = &qhs_camera_cfg,
1257 [SLAVE_CLK_CTL] = &qhs_clk_ctl,
1258 [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg,
1259 [SLAVE_DISPLAY_CFG] = &qhs_display_cfg,
1260 [SLAVE_EVA_CFG] = &qhs_eva_cfg,
1261 [SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg,
1262 [SLAVE_I2C] = &qhs_i2c,
1263 [SLAVE_I3C_IBI0_CFG] = &qhs_i3c_ibi0_cfg,
1264 [SLAVE_I3C_IBI1_CFG] = &qhs_i3c_ibi1_cfg,
1265 [SLAVE_IMEM_CFG] = &qhs_imem_cfg,
1266 [SLAVE_CNOC_MSS] = &qhs_mss_cfg,
1267 [SLAVE_PCIE_CFG] = &qhs_pcie_cfg,
1268 [SLAVE_PRNG] = &qhs_prng,
1269 [SLAVE_QDSS_CFG] = &qhs_qdss_cfg,
1270 [SLAVE_QSPI_0] = &qhs_qspi,
1271 [SLAVE_QUP_3] = &qhs_qup02,
1272 [SLAVE_QUP_1] = &qhs_qup1,
1273 [SLAVE_QUP_2] = &qhs_qup2,
1274 [SLAVE_SDCC_2] = &qhs_sdc2,
1275 [SLAVE_SDCC_4] = &qhs_sdc4,
1276 [SLAVE_SPSS_CFG] = &qhs_spss_cfg,
1277 [SLAVE_TCSR] = &qhs_tcsr,
1278 [SLAVE_TLMM] = &qhs_tlmm,
1279 [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg,
1280 [SLAVE_USB3_0] = &qhs_usb3_0,
1281 [SLAVE_VENUS_CFG] = &qhs_venus_cfg,
1282 [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg,
1283 [SLAVE_CNOC_MNOC_CFG] = &qss_mnoc_cfg,
1284 [SLAVE_PCIE_ANOC_CFG] = &qss_pcie_anoc_cfg,
1285 [SLAVE_QDSS_STM] = &xs_qdss_stm,
1286 [SLAVE_TCU] = &xs_sys_tcu_cfg,
1287};
1288
1289static const struct qcom_icc_desc sm8750_config_noc = {
1290 .nodes = config_noc_nodes,
1291 .num_nodes = ARRAY_SIZE(config_noc_nodes),
1292 .bcms = config_noc_bcms,
1293 .num_bcms = ARRAY_SIZE(config_noc_bcms),
1294};
1295
1296static struct qcom_icc_bcm * const cnoc_main_bcms[] = {
1297 &bcm_cn0,
1298};
1299
1300static struct qcom_icc_node * const cnoc_main_nodes[] = {
1301 [MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc,
1302 [MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie,
1303 [SLAVE_AOSS] = &qhs_aoss,
1304 [SLAVE_IPA_CFG] = &qhs_ipa,
1305 [SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router,
1306 [SLAVE_SOCCP] = &qhs_soccp,
1307 [SLAVE_TME_CFG] = &qhs_tme_cfg,
1308 [SLAVE_APPSS] = &qns_apss,
1309 [SLAVE_CNOC_CFG] = &qss_cfg,
1310 [SLAVE_DDRSS_CFG] = &qss_ddrss_cfg,
1311 [SLAVE_BOOT_IMEM] = &qxs_boot_imem,
1312 [SLAVE_IMEM] = &qxs_imem,
1313 [SLAVE_BOOT_IMEM_2] = &qxs_modem_boot_imem,
1314 [SLAVE_SERVICE_CNOC] = &srvc_cnoc_main,
1315 [SLAVE_PCIE_0] = &xs_pcie,
1316};
1317
1318static const struct qcom_icc_desc sm8750_cnoc_main = {
1319 .nodes = cnoc_main_nodes,
1320 .num_nodes = ARRAY_SIZE(cnoc_main_nodes),
1321 .bcms = cnoc_main_bcms,
1322 .num_bcms = ARRAY_SIZE(cnoc_main_bcms),
1323};
1324
1325static struct qcom_icc_bcm * const gem_noc_bcms[] = {
1326 &bcm_sh0,
1327 &bcm_sh1,
1328 &bcm_ubw0,
1329};
1330
1331static struct qcom_icc_node * const gem_noc_nodes[] = {
1332 [MASTER_GPU_TCU] = &alm_gpu_tcu,
1333 [MASTER_SYS_TCU] = &alm_sys_tcu,
1334 [MASTER_APPSS_PROC] = &chm_apps,
1335 [MASTER_GFX3D] = &qnm_gpu,
1336 [MASTER_LPASS_GEM_NOC] = &qnm_lpass_gemnoc,
1337 [MASTER_MSS_PROC] = &qnm_mdsp,
1338 [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf,
1339 [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf,
1340 [MASTER_COMPUTE_NOC] = &qnm_nsp_gemnoc,
1341 [MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie,
1342 [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf,
1343 [MASTER_UBWC_P] = &qnm_ubwc_p,
1344 [MASTER_GIC] = &xm_gic,
1345 [SLAVE_UBWC_P] = &chs_ubwc_p,
1346 [SLAVE_GEM_NOC_CNOC] = &qns_gem_noc_cnoc,
1347 [SLAVE_LLCC] = &qns_llcc,
1348 [SLAVE_MEM_NOC_PCIE_SNOC] = &qns_pcie,
1349};
1350
1351static const struct qcom_icc_desc sm8750_gem_noc = {
1352 .nodes = gem_noc_nodes,
1353 .num_nodes = ARRAY_SIZE(gem_noc_nodes),
1354 .bcms = gem_noc_bcms,
1355 .num_bcms = ARRAY_SIZE(gem_noc_bcms),
1356};
1357
1358static struct qcom_icc_node * const lpass_ag_noc_nodes[] = {
1359 [MASTER_LPIAON_NOC] = &qnm_lpiaon_noc,
1360 [SLAVE_LPASS_GEM_NOC] = &qns_lpass_ag_noc_gemnoc,
1361};
1362
1363static const struct qcom_icc_desc sm8750_lpass_ag_noc = {
1364 .nodes = lpass_ag_noc_nodes,
1365 .num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes),
1366};
1367
1368static struct qcom_icc_bcm * const lpass_lpiaon_noc_bcms[] = {
1369 &bcm_lp0,
1370};
1371
1372static struct qcom_icc_node * const lpass_lpiaon_noc_nodes[] = {
1373 [MASTER_LPASS_LPINOC] = &qnm_lpass_lpinoc,
1374 [SLAVE_LPIAON_NOC_LPASS_AG_NOC] = &qns_lpass_aggnoc,
1375};
1376
1377static const struct qcom_icc_desc sm8750_lpass_lpiaon_noc = {
1378 .nodes = lpass_lpiaon_noc_nodes,
1379 .num_nodes = ARRAY_SIZE(lpass_lpiaon_noc_nodes),
1380 .bcms = lpass_lpiaon_noc_bcms,
1381 .num_bcms = ARRAY_SIZE(lpass_lpiaon_noc_bcms),
1382};
1383
1384static struct qcom_icc_node * const lpass_lpicx_noc_nodes[] = {
1385 [MASTER_LPASS_PROC] = &qnm_lpinoc_dsp_qns4m,
1386 [SLAVE_LPICX_NOC_LPIAON_NOC] = &qns_lpi_aon_noc,
1387};
1388
1389static const struct qcom_icc_desc sm8750_lpass_lpicx_noc = {
1390 .nodes = lpass_lpicx_noc_nodes,
1391 .num_nodes = ARRAY_SIZE(lpass_lpicx_noc_nodes),
1392};
1393
1394static struct qcom_icc_bcm * const mc_virt_bcms[] = {
1395 &bcm_acv,
1396 &bcm_mc0,
1397};
1398
1399static struct qcom_icc_node * const mc_virt_nodes[] = {
1400 [MASTER_LLCC] = &llcc_mc,
1401 [SLAVE_EBI1] = &ebi,
1402};
1403
1404static const struct qcom_icc_desc sm8750_mc_virt = {
1405 .nodes = mc_virt_nodes,
1406 .num_nodes = ARRAY_SIZE(mc_virt_nodes),
1407 .bcms = mc_virt_bcms,
1408 .num_bcms = ARRAY_SIZE(mc_virt_bcms),
1409};
1410
1411static struct qcom_icc_bcm * const mmss_noc_bcms[] = {
1412 &bcm_mm0,
1413 &bcm_mm1,
1414};
1415
1416static struct qcom_icc_node * const mmss_noc_nodes[] = {
1417 [MASTER_CAMNOC_HF] = &qnm_camnoc_hf,
1418 [MASTER_CAMNOC_NRT_ICP_SF] = &qnm_camnoc_nrt_icp_sf,
1419 [MASTER_CAMNOC_RT_CDM_SF] = &qnm_camnoc_rt_cdm_sf,
1420 [MASTER_CAMNOC_SF] = &qnm_camnoc_sf,
1421 [MASTER_MDP] = &qnm_mdp,
1422 [MASTER_CDSP_HCP] = &qnm_vapss_hcp,
1423 [MASTER_VIDEO_CV_PROC] = &qnm_video_cv_cpu,
1424 [MASTER_VIDEO_EVA] = &qnm_video_eva,
1425 [MASTER_VIDEO_MVP] = &qnm_video_mvp,
1426 [MASTER_VIDEO_V_PROC] = &qnm_video_v_cpu,
1427 [MASTER_CNOC_MNOC_CFG] = &qsm_mnoc_cfg,
1428 [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf,
1429 [SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf,
1430 [SLAVE_SERVICE_MNOC] = &srvc_mnoc,
1431};
1432
1433static const struct qcom_icc_desc sm8750_mmss_noc = {
1434 .nodes = mmss_noc_nodes,
1435 .num_nodes = ARRAY_SIZE(mmss_noc_nodes),
1436 .bcms = mmss_noc_bcms,
1437 .num_bcms = ARRAY_SIZE(mmss_noc_bcms),
1438};
1439
1440static struct qcom_icc_bcm * const nsp_noc_bcms[] = {
1441 &bcm_co0,
1442};
1443
1444static struct qcom_icc_node * const nsp_noc_nodes[] = {
1445 [MASTER_CDSP_PROC] = &qnm_nsp,
1446 [SLAVE_CDSP_MEM_NOC] = &qns_nsp_gemnoc,
1447};
1448
1449static const struct qcom_icc_desc sm8750_nsp_noc = {
1450 .nodes = nsp_noc_nodes,
1451 .num_nodes = ARRAY_SIZE(nsp_noc_nodes),
1452 .bcms = nsp_noc_bcms,
1453 .num_bcms = ARRAY_SIZE(nsp_noc_bcms),
1454};
1455
1456static struct qcom_icc_bcm * const pcie_anoc_bcms[] = {
1457 &bcm_sn4,
1458};
1459
1460static struct qcom_icc_node * const pcie_anoc_nodes[] = {
1461 [MASTER_PCIE_ANOC_CFG] = &qsm_pcie_anoc_cfg,
1462 [MASTER_PCIE_0] = &xm_pcie3,
1463 [SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_mem_noc,
1464 [SLAVE_SERVICE_PCIE_ANOC] = &srvc_pcie_aggre_noc,
1465};
1466
1467static const struct qcom_icc_desc sm8750_pcie_anoc = {
1468 .nodes = pcie_anoc_nodes,
1469 .num_nodes = ARRAY_SIZE(pcie_anoc_nodes),
1470 .bcms = pcie_anoc_bcms,
1471 .num_bcms = ARRAY_SIZE(pcie_anoc_bcms),
1472};
1473
1474static struct qcom_icc_bcm * const system_noc_bcms[] = {
1475 &bcm_sn0,
1476 &bcm_sn2,
1477 &bcm_sn3,
1478};
1479
1480static struct qcom_icc_node * const system_noc_nodes[] = {
1481 [MASTER_A1NOC_SNOC] = &qnm_aggre1_noc,
1482 [MASTER_A2NOC_SNOC] = &qnm_aggre2_noc,
1483 [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf,
1484};
1485
1486static const struct qcom_icc_desc sm8750_system_noc = {
1487 .nodes = system_noc_nodes,
1488 .num_nodes = ARRAY_SIZE(system_noc_nodes),
1489 .bcms = system_noc_bcms,
1490 .num_bcms = ARRAY_SIZE(system_noc_bcms),
1491};
1492
1493static const struct of_device_id qnoc_of_match[] = {
1494 { .compatible = "qcom,sm8750-aggre1-noc", .data = &sm8750_aggre1_noc},
1495 { .compatible = "qcom,sm8750-aggre2-noc", .data = &sm8750_aggre2_noc},
1496 { .compatible = "qcom,sm8750-clk-virt", .data = &sm8750_clk_virt},
1497 { .compatible = "qcom,sm8750-config-noc", .data = &sm8750_config_noc},
1498 { .compatible = "qcom,sm8750-cnoc-main", .data = &sm8750_cnoc_main},
1499 { .compatible = "qcom,sm8750-gem-noc", .data = &sm8750_gem_noc},
1500 { .compatible = "qcom,sm8750-lpass-ag-noc", .data = &sm8750_lpass_ag_noc},
1501 { .compatible = "qcom,sm8750-lpass-lpiaon-noc", .data = &sm8750_lpass_lpiaon_noc},
1502 { .compatible = "qcom,sm8750-lpass-lpicx-noc", .data = &sm8750_lpass_lpicx_noc},
1503 { .compatible = "qcom,sm8750-mc-virt", .data = &sm8750_mc_virt},
1504 { .compatible = "qcom,sm8750-mmss-noc", .data = &sm8750_mmss_noc},
1505 { .compatible = "qcom,sm8750-nsp-noc", .data = &sm8750_nsp_noc},
1506 { .compatible = "qcom,sm8750-pcie-anoc", .data = &sm8750_pcie_anoc},
1507 { .compatible = "qcom,sm8750-system-noc", .data = &sm8750_system_noc},
1508 { }
1509};
1510MODULE_DEVICE_TABLE(of, qnoc_of_match);
1511
1512static struct platform_driver qnoc_driver = {
1513 .probe = qcom_icc_rpmh_probe,
1514 .remove = qcom_icc_rpmh_remove,
1515 .driver = {
1516 .name = "qnoc-sm8750",
1517 .of_match_table = qnoc_of_match,
1518 .sync_state = icc_sync_state,
1519 },
1520};
1521
1522static int __init qnoc_driver_init(void)
1523{
1524 return platform_driver_register(&qnoc_driver);
1525}
1526core_initcall(qnoc_driver_init);
1527
1528static void __exit qnoc_driver_exit(void)
1529{
1530 platform_driver_unregister(&qnoc_driver);
1531}
1532module_exit(qnoc_driver_exit);
1533
1534MODULE_DESCRIPTION("SM8750 NoC driver");
1535MODULE_LICENSE("GPL");