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1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright © 2006-2015, Intel Corporation.
4 *
5 * Authors: Ashok Raj <ashok.raj@intel.com>
6 * Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
7 * David Woodhouse <David.Woodhouse@intel.com>
8 */
9
10#ifndef _INTEL_IOMMU_H_
11#define _INTEL_IOMMU_H_
12
13#include <linux/types.h>
14#include <linux/iova.h>
15#include <linux/io.h>
16#include <linux/idr.h>
17#include <linux/mmu_notifier.h>
18#include <linux/list.h>
19#include <linux/iommu.h>
20#include <linux/io-64-nonatomic-lo-hi.h>
21#include <linux/dmar.h>
22#include <linux/bitfield.h>
23#include <linux/xarray.h>
24#include <linux/perf_event.h>
25#include <linux/pci.h>
26#include <linux/generic_pt/iommu.h>
27
28#include <asm/iommu.h>
29#include <uapi/linux/iommufd.h>
30
31/*
32 * VT-d hardware uses 4KiB page size regardless of host page size.
33 */
34#define VTD_PAGE_SHIFT (12)
35#define VTD_PAGE_SIZE (1UL << VTD_PAGE_SHIFT)
36#define VTD_PAGE_MASK (((u64)-1) << VTD_PAGE_SHIFT)
37#define VTD_PAGE_ALIGN(addr) (((addr) + VTD_PAGE_SIZE - 1) & VTD_PAGE_MASK)
38
39#define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT)
40
41#define VTD_STRIDE_SHIFT (9)
42#define VTD_STRIDE_MASK (((u64)-1) << VTD_STRIDE_SHIFT)
43
44#define DMA_PTE_READ BIT_ULL(0)
45#define DMA_PTE_WRITE BIT_ULL(1)
46#define DMA_PTE_LARGE_PAGE BIT_ULL(7)
47#define DMA_PTE_SNP BIT_ULL(11)
48
49#define DMA_FL_PTE_PRESENT BIT_ULL(0)
50#define DMA_FL_PTE_US BIT_ULL(2)
51#define DMA_FL_PTE_ACCESS BIT_ULL(5)
52#define DMA_FL_PTE_DIRTY BIT_ULL(6)
53
54#define DMA_SL_PTE_DIRTY_BIT 9
55#define DMA_SL_PTE_DIRTY BIT_ULL(DMA_SL_PTE_DIRTY_BIT)
56
57#define ADDR_WIDTH_5LEVEL (57)
58#define ADDR_WIDTH_4LEVEL (48)
59
60#define CONTEXT_TT_MULTI_LEVEL 0
61#define CONTEXT_TT_DEV_IOTLB 1
62#define CONTEXT_TT_PASS_THROUGH 2
63#define CONTEXT_PASIDE BIT_ULL(3)
64
65/*
66 * Intel IOMMU register specification per version 1.0 public spec.
67 */
68#define DMAR_VER_REG 0x0 /* Arch version supported by this IOMMU */
69#define DMAR_CAP_REG 0x8 /* Hardware supported capabilities */
70#define DMAR_ECAP_REG 0x10 /* Extended capabilities supported */
71#define DMAR_GCMD_REG 0x18 /* Global command register */
72#define DMAR_GSTS_REG 0x1c /* Global status register */
73#define DMAR_RTADDR_REG 0x20 /* Root entry table */
74#define DMAR_CCMD_REG 0x28 /* Context command reg */
75#define DMAR_FSTS_REG 0x34 /* Fault Status register */
76#define DMAR_FECTL_REG 0x38 /* Fault control register */
77#define DMAR_FEDATA_REG 0x3c /* Fault event interrupt data register */
78#define DMAR_FEADDR_REG 0x40 /* Fault event interrupt addr register */
79#define DMAR_FEUADDR_REG 0x44 /* Upper address register */
80#define DMAR_PMEN_REG 0x64 /* Enable Protected Memory Region */
81#define DMAR_PLMBASE_REG 0x68 /* PMRR Low addr */
82#define DMAR_PLMLIMIT_REG 0x6c /* PMRR low limit */
83#define DMAR_PHMBASE_REG 0x70 /* pmrr high base addr */
84#define DMAR_PHMLIMIT_REG 0x78 /* pmrr high limit */
85#define DMAR_IQH_REG 0x80 /* Invalidation queue head register */
86#define DMAR_IQT_REG 0x88 /* Invalidation queue tail register */
87#define DMAR_IQ_SHIFT 4 /* Invalidation queue head/tail shift */
88#define DMAR_IQA_REG 0x90 /* Invalidation queue addr register */
89#define DMAR_ICS_REG 0x9c /* Invalidation complete status register */
90#define DMAR_IQER_REG 0xb0 /* Invalidation queue error record register */
91#define DMAR_IRTA_REG 0xb8 /* Interrupt remapping table addr register */
92#define DMAR_PQH_REG 0xc0 /* Page request queue head register */
93#define DMAR_PQT_REG 0xc8 /* Page request queue tail register */
94#define DMAR_PQA_REG 0xd0 /* Page request queue address register */
95#define DMAR_PRS_REG 0xdc /* Page request status register */
96#define DMAR_PECTL_REG 0xe0 /* Page request event control register */
97#define DMAR_PEDATA_REG 0xe4 /* Page request event interrupt data register */
98#define DMAR_PEADDR_REG 0xe8 /* Page request event interrupt addr register */
99#define DMAR_PEUADDR_REG 0xec /* Page request event Upper address register */
100#define DMAR_MTRRCAP_REG 0x100 /* MTRR capability register */
101#define DMAR_MTRRDEF_REG 0x108 /* MTRR default type register */
102#define DMAR_MTRR_FIX64K_00000_REG 0x120 /* MTRR Fixed range registers */
103#define DMAR_MTRR_FIX16K_80000_REG 0x128
104#define DMAR_MTRR_FIX16K_A0000_REG 0x130
105#define DMAR_MTRR_FIX4K_C0000_REG 0x138
106#define DMAR_MTRR_FIX4K_C8000_REG 0x140
107#define DMAR_MTRR_FIX4K_D0000_REG 0x148
108#define DMAR_MTRR_FIX4K_D8000_REG 0x150
109#define DMAR_MTRR_FIX4K_E0000_REG 0x158
110#define DMAR_MTRR_FIX4K_E8000_REG 0x160
111#define DMAR_MTRR_FIX4K_F0000_REG 0x168
112#define DMAR_MTRR_FIX4K_F8000_REG 0x170
113#define DMAR_MTRR_PHYSBASE0_REG 0x180 /* MTRR Variable range registers */
114#define DMAR_MTRR_PHYSMASK0_REG 0x188
115#define DMAR_MTRR_PHYSBASE1_REG 0x190
116#define DMAR_MTRR_PHYSMASK1_REG 0x198
117#define DMAR_MTRR_PHYSBASE2_REG 0x1a0
118#define DMAR_MTRR_PHYSMASK2_REG 0x1a8
119#define DMAR_MTRR_PHYSBASE3_REG 0x1b0
120#define DMAR_MTRR_PHYSMASK3_REG 0x1b8
121#define DMAR_MTRR_PHYSBASE4_REG 0x1c0
122#define DMAR_MTRR_PHYSMASK4_REG 0x1c8
123#define DMAR_MTRR_PHYSBASE5_REG 0x1d0
124#define DMAR_MTRR_PHYSMASK5_REG 0x1d8
125#define DMAR_MTRR_PHYSBASE6_REG 0x1e0
126#define DMAR_MTRR_PHYSMASK6_REG 0x1e8
127#define DMAR_MTRR_PHYSBASE7_REG 0x1f0
128#define DMAR_MTRR_PHYSMASK7_REG 0x1f8
129#define DMAR_MTRR_PHYSBASE8_REG 0x200
130#define DMAR_MTRR_PHYSMASK8_REG 0x208
131#define DMAR_MTRR_PHYSBASE9_REG 0x210
132#define DMAR_MTRR_PHYSMASK9_REG 0x218
133#define DMAR_PERFCAP_REG 0x300
134#define DMAR_PERFCFGOFF_REG 0x310
135#define DMAR_PERFOVFOFF_REG 0x318
136#define DMAR_PERFCNTROFF_REG 0x31c
137#define DMAR_PERFINTRSTS_REG 0x324
138#define DMAR_PERFINTRCTL_REG 0x328
139#define DMAR_PERFEVNTCAP_REG 0x380
140#define DMAR_ECMD_REG 0x400
141#define DMAR_ECEO_REG 0x408
142#define DMAR_ECRSP_REG 0x410
143#define DMAR_ECCAP_REG 0x430
144
145#define DMAR_IQER_REG_IQEI(reg) FIELD_GET(GENMASK_ULL(3, 0), reg)
146#define DMAR_IQER_REG_ITESID(reg) FIELD_GET(GENMASK_ULL(47, 32), reg)
147#define DMAR_IQER_REG_ICESID(reg) FIELD_GET(GENMASK_ULL(63, 48), reg)
148
149#define OFFSET_STRIDE (9)
150
151#define DMAR_VER_MAJOR(v) (((v) & 0xf0) >> 4)
152#define DMAR_VER_MINOR(v) ((v) & 0x0f)
153
154/*
155 * Decoding Capability Register
156 */
157#define cap_esrtps(c) (((c) >> 63) & 1)
158#define cap_esirtps(c) (((c) >> 62) & 1)
159#define cap_ecmds(c) (((c) >> 61) & 1)
160#define cap_fl5lp_support(c) (((c) >> 60) & 1)
161#define cap_pi_support(c) (((c) >> 59) & 1)
162#define cap_fl1gp_support(c) (((c) >> 56) & 1)
163#define cap_read_drain(c) (((c) >> 55) & 1)
164#define cap_write_drain(c) (((c) >> 54) & 1)
165#define cap_max_amask_val(c) (((c) >> 48) & 0x3f)
166#define cap_num_fault_regs(c) ((((c) >> 40) & 0xff) + 1)
167#define cap_pgsel_inv(c) (((c) >> 39) & 1)
168
169#define cap_super_page_val(c) (((c) >> 34) & 0xf)
170
171#define cap_fault_reg_offset(c) ((((c) >> 24) & 0x3ff) * 16)
172#define cap_max_fault_reg_offset(c) \
173 (cap_fault_reg_offset(c) + cap_num_fault_regs(c) * 16)
174
175#define cap_zlr(c) (((c) >> 22) & 1)
176#define cap_isoch(c) (((c) >> 23) & 1)
177#define cap_mgaw(c) ((((c) >> 16) & 0x3f) + 1)
178#define cap_sagaw(c) (((c) >> 8) & 0x1f)
179#define cap_caching_mode(c) (((c) >> 7) & 1)
180#define cap_phmr(c) (((c) >> 6) & 1)
181#define cap_plmr(c) (((c) >> 5) & 1)
182#define cap_rwbf(c) (((c) >> 4) & 1)
183#define cap_afl(c) (((c) >> 3) & 1)
184#define cap_ndoms(c) (((unsigned long)1) << (4 + 2 * ((c) & 0x7)))
185/*
186 * Extended Capability Register
187 */
188
189#define ecap_pms(e) (((e) >> 51) & 0x1)
190#define ecap_rps(e) (((e) >> 49) & 0x1)
191#define ecap_smpwc(e) (((e) >> 48) & 0x1)
192#define ecap_flts(e) (((e) >> 47) & 0x1)
193#define ecap_slts(e) (((e) >> 46) & 0x1)
194#define ecap_slads(e) (((e) >> 45) & 0x1)
195#define ecap_smts(e) (((e) >> 43) & 0x1)
196#define ecap_dit(e) (((e) >> 41) & 0x1)
197#define ecap_pds(e) (((e) >> 42) & 0x1)
198#define ecap_pasid(e) (((e) >> 40) & 0x1)
199#define ecap_pss(e) (((e) >> 35) & 0x1f)
200#define ecap_eafs(e) (((e) >> 34) & 0x1)
201#define ecap_nwfs(e) (((e) >> 33) & 0x1)
202#define ecap_srs(e) (((e) >> 31) & 0x1)
203#define ecap_ers(e) (((e) >> 30) & 0x1)
204#define ecap_prs(e) (((e) >> 29) & 0x1)
205#define ecap_broken_pasid(e) (((e) >> 28) & 0x1)
206#define ecap_dis(e) (((e) >> 27) & 0x1)
207#define ecap_nest(e) (((e) >> 26) & 0x1)
208#define ecap_mts(e) (((e) >> 25) & 0x1)
209#define ecap_iotlb_offset(e) ((((e) >> 8) & 0x3ff) * 16)
210#define ecap_max_iotlb_offset(e) (ecap_iotlb_offset(e) + 16)
211#define ecap_coherent(e) ((e) & 0x1)
212#define ecap_qis(e) ((e) & 0x2)
213#define ecap_pass_through(e) (((e) >> 6) & 0x1)
214#define ecap_eim_support(e) (((e) >> 4) & 0x1)
215#define ecap_ir_support(e) (((e) >> 3) & 0x1)
216#define ecap_dev_iotlb_support(e) (((e) >> 2) & 0x1)
217#define ecap_max_handle_mask(e) (((e) >> 20) & 0xf)
218#define ecap_sc_support(e) (((e) >> 7) & 0x1) /* Snooping Control */
219
220/*
221 * Decoding Perf Capability Register
222 */
223#define pcap_num_cntr(p) ((p) & 0xffff)
224#define pcap_cntr_width(p) (((p) >> 16) & 0x7f)
225#define pcap_num_event_group(p) (((p) >> 24) & 0x1f)
226#define pcap_filters_mask(p) (((p) >> 32) & 0x1f)
227#define pcap_interrupt(p) (((p) >> 50) & 0x1)
228/* The counter stride is calculated as 2 ^ (x+10) bytes */
229#define pcap_cntr_stride(p) (1ULL << ((((p) >> 52) & 0x7) + 10))
230
231/*
232 * Decoding Perf Event Capability Register
233 */
234#define pecap_es(p) ((p) & 0xfffffff)
235
236/* Virtual command interface capability */
237#define vccap_pasid(v) (((v) & DMA_VCS_PAS)) /* PASID allocation */
238
239/* IOTLB_REG */
240#define DMA_TLB_FLUSH_GRANU_OFFSET 60
241#define DMA_TLB_GLOBAL_FLUSH (((u64)1) << 60)
242#define DMA_TLB_DSI_FLUSH (((u64)2) << 60)
243#define DMA_TLB_PSI_FLUSH (((u64)3) << 60)
244#define DMA_TLB_IIRG(type) ((type >> 60) & 3)
245#define DMA_TLB_IAIG(val) (((val) >> 57) & 3)
246#define DMA_TLB_READ_DRAIN (((u64)1) << 49)
247#define DMA_TLB_WRITE_DRAIN (((u64)1) << 48)
248#define DMA_TLB_DID(id) (((u64)((id) & 0xffff)) << 32)
249#define DMA_TLB_IVT (((u64)1) << 63)
250#define DMA_TLB_IH_NONLEAF (((u64)1) << 6)
251#define DMA_TLB_MAX_SIZE (0x3f)
252
253/* INVALID_DESC */
254#define DMA_CCMD_INVL_GRANU_OFFSET 61
255#define DMA_ID_TLB_GLOBAL_FLUSH (((u64)1) << 4)
256#define DMA_ID_TLB_DSI_FLUSH (((u64)2) << 4)
257#define DMA_ID_TLB_PSI_FLUSH (((u64)3) << 4)
258#define DMA_ID_TLB_READ_DRAIN (((u64)1) << 7)
259#define DMA_ID_TLB_WRITE_DRAIN (((u64)1) << 6)
260#define DMA_ID_TLB_DID(id) (((u64)((id & 0xffff) << 16)))
261#define DMA_ID_TLB_IH_NONLEAF (((u64)1) << 6)
262#define DMA_ID_TLB_ADDR(addr) (addr)
263#define DMA_ID_TLB_ADDR_MASK(mask) (mask)
264
265/* PMEN_REG */
266#define DMA_PMEN_EPM (((u32)1)<<31)
267#define DMA_PMEN_PRS (((u32)1)<<0)
268
269/* GCMD_REG */
270#define DMA_GCMD_TE (((u32)1) << 31)
271#define DMA_GCMD_SRTP (((u32)1) << 30)
272#define DMA_GCMD_SFL (((u32)1) << 29)
273#define DMA_GCMD_EAFL (((u32)1) << 28)
274#define DMA_GCMD_WBF (((u32)1) << 27)
275#define DMA_GCMD_QIE (((u32)1) << 26)
276#define DMA_GCMD_SIRTP (((u32)1) << 24)
277#define DMA_GCMD_IRE (((u32) 1) << 25)
278#define DMA_GCMD_CFI (((u32) 1) << 23)
279
280/* GSTS_REG */
281#define DMA_GSTS_TES (((u32)1) << 31)
282#define DMA_GSTS_RTPS (((u32)1) << 30)
283#define DMA_GSTS_FLS (((u32)1) << 29)
284#define DMA_GSTS_AFLS (((u32)1) << 28)
285#define DMA_GSTS_WBFS (((u32)1) << 27)
286#define DMA_GSTS_QIES (((u32)1) << 26)
287#define DMA_GSTS_IRTPS (((u32)1) << 24)
288#define DMA_GSTS_IRES (((u32)1) << 25)
289#define DMA_GSTS_CFIS (((u32)1) << 23)
290
291/* DMA_RTADDR_REG */
292#define DMA_RTADDR_SMT (((u64)1) << 10)
293
294/* CCMD_REG */
295#define DMA_CCMD_ICC (((u64)1) << 63)
296#define DMA_CCMD_GLOBAL_INVL (((u64)1) << 61)
297#define DMA_CCMD_DOMAIN_INVL (((u64)2) << 61)
298#define DMA_CCMD_DEVICE_INVL (((u64)3) << 61)
299#define DMA_CCMD_FM(m) (((u64)((m) & 0x3)) << 32)
300#define DMA_CCMD_MASK_NOBIT 0
301#define DMA_CCMD_MASK_1BIT 1
302#define DMA_CCMD_MASK_2BIT 2
303#define DMA_CCMD_MASK_3BIT 3
304#define DMA_CCMD_SID(s) (((u64)((s) & 0xffff)) << 16)
305#define DMA_CCMD_DID(d) ((u64)((d) & 0xffff))
306
307/* ECMD_REG */
308#define DMA_MAX_NUM_ECMD 256
309#define DMA_MAX_NUM_ECMDCAP (DMA_MAX_NUM_ECMD / 64)
310#define DMA_ECMD_REG_STEP 8
311#define DMA_ECMD_ENABLE 0xf0
312#define DMA_ECMD_DISABLE 0xf1
313#define DMA_ECMD_FREEZE 0xf4
314#define DMA_ECMD_UNFREEZE 0xf5
315#define DMA_ECMD_OA_SHIFT 16
316#define DMA_ECMD_ECRSP_IP 0x1
317#define DMA_ECMD_ECCAP3 3
318#define DMA_ECMD_ECCAP3_ECNTS BIT_ULL(48)
319#define DMA_ECMD_ECCAP3_DCNTS BIT_ULL(49)
320#define DMA_ECMD_ECCAP3_FCNTS BIT_ULL(52)
321#define DMA_ECMD_ECCAP3_UFCNTS BIT_ULL(53)
322#define DMA_ECMD_ECCAP3_ESSENTIAL (DMA_ECMD_ECCAP3_ECNTS | \
323 DMA_ECMD_ECCAP3_DCNTS | \
324 DMA_ECMD_ECCAP3_FCNTS | \
325 DMA_ECMD_ECCAP3_UFCNTS)
326
327/* FECTL_REG */
328#define DMA_FECTL_IM (((u32)1) << 31)
329
330/* FSTS_REG */
331#define DMA_FSTS_PFO (1 << 0) /* Primary Fault Overflow */
332#define DMA_FSTS_PPF (1 << 1) /* Primary Pending Fault */
333#define DMA_FSTS_IQE (1 << 4) /* Invalidation Queue Error */
334#define DMA_FSTS_ICE (1 << 5) /* Invalidation Completion Error */
335#define DMA_FSTS_ITE (1 << 6) /* Invalidation Time-out Error */
336#define DMA_FSTS_PRO (1 << 7) /* Page Request Overflow */
337#define dma_fsts_fault_record_index(s) (((s) >> 8) & 0xff)
338
339/* FRCD_REG, 32 bits access */
340#define DMA_FRCD_F (((u32)1) << 31)
341#define dma_frcd_type(d) ((d >> 30) & 1)
342#define dma_frcd_fault_reason(c) (c & 0xff)
343#define dma_frcd_source_id(c) (c & 0xffff)
344#define dma_frcd_pasid_value(c) (((c) >> 8) & 0xfffff)
345#define dma_frcd_pasid_present(c) (((c) >> 31) & 1)
346/* low 64 bit */
347#define dma_frcd_page_addr(d) (d & (((u64)-1) << PAGE_SHIFT))
348
349/* PRS_REG */
350#define DMA_PRS_PPR ((u32)1)
351#define DMA_PRS_PRO ((u32)2)
352
353#define DMA_VCS_PAS ((u64)1)
354
355/* PERFINTRSTS_REG */
356#define DMA_PERFINTRSTS_PIS ((u32)1)
357
358#define IOMMU_WAIT_OP(iommu, offset, op, cond, sts) \
359do { \
360 cycles_t start_time = get_cycles(); \
361 while (1) { \
362 sts = op(iommu->reg + offset); \
363 if (cond) \
364 break; \
365 if (DMAR_OPERATION_TIMEOUT < (get_cycles() - start_time))\
366 panic("DMAR hardware is malfunctioning\n"); \
367 cpu_relax(); \
368 } \
369} while (0)
370
371#define QI_LENGTH 256 /* queue length */
372
373enum {
374 QI_FREE,
375 QI_IN_USE,
376 QI_DONE,
377 QI_ABORT
378};
379
380#define QI_CC_TYPE 0x1
381#define QI_IOTLB_TYPE 0x2
382#define QI_DIOTLB_TYPE 0x3
383#define QI_IEC_TYPE 0x4
384#define QI_IWD_TYPE 0x5
385#define QI_EIOTLB_TYPE 0x6
386#define QI_PC_TYPE 0x7
387#define QI_DEIOTLB_TYPE 0x8
388#define QI_PGRP_RESP_TYPE 0x9
389#define QI_PSTRM_RESP_TYPE 0xa
390
391#define QI_IEC_SELECTIVE (((u64)1) << 4)
392#define QI_IEC_IIDEX(idx) (((u64)(idx & 0xffff) << 32))
393#define QI_IEC_IM(m) (((u64)(m & 0x1f) << 27))
394
395#define QI_IWD_STATUS_DATA(d) (((u64)d) << 32)
396#define QI_IWD_STATUS_WRITE (((u64)1) << 5)
397#define QI_IWD_FENCE (((u64)1) << 6)
398#define QI_IWD_PRQ_DRAIN (((u64)1) << 7)
399
400#define QI_IOTLB_DID(did) (((u64)did) << 16)
401#define QI_IOTLB_DR(dr) (((u64)dr) << 7)
402#define QI_IOTLB_DW(dw) (((u64)dw) << 6)
403#define QI_IOTLB_GRAN(gran) (((u64)gran) >> (DMA_TLB_FLUSH_GRANU_OFFSET-4))
404#define QI_IOTLB_ADDR(addr) (((u64)addr) & VTD_PAGE_MASK)
405#define QI_IOTLB_IH(ih) (((u64)ih) << 6)
406#define QI_IOTLB_AM(am) (((u8)am) & 0x3f)
407
408#define QI_CC_FM(fm) (((u64)fm) << 48)
409#define QI_CC_SID(sid) (((u64)sid) << 32)
410#define QI_CC_DID(did) (((u64)did) << 16)
411#define QI_CC_GRAN(gran) (((u64)gran) >> (DMA_CCMD_INVL_GRANU_OFFSET-4))
412
413#define QI_DEV_IOTLB_SID(sid) ((u64)((sid) & 0xffff) << 32)
414#define QI_DEV_IOTLB_QDEP(qdep) (((qdep) & 0x1f) << 16)
415#define QI_DEV_IOTLB_ADDR(addr) ((u64)(addr) & VTD_PAGE_MASK)
416#define QI_DEV_IOTLB_PFSID(pfsid) (((u64)(pfsid & 0xf) << 12) | \
417 ((u64)((pfsid >> 4) & 0xfff) << 52))
418#define QI_DEV_IOTLB_SIZE 1
419#define QI_DEV_IOTLB_MAX_INVS 32
420
421#define QI_PC_PASID(pasid) (((u64)pasid) << 32)
422#define QI_PC_DID(did) (((u64)did) << 16)
423#define QI_PC_GRAN(gran) (((u64)gran) << 4)
424
425/* PASID cache invalidation granu */
426#define QI_PC_ALL_PASIDS 0
427#define QI_PC_PASID_SEL 1
428#define QI_PC_GLOBAL 3
429
430#define QI_EIOTLB_ADDR(addr) ((u64)(addr) & VTD_PAGE_MASK)
431#define QI_EIOTLB_IH(ih) (((u64)ih) << 6)
432#define QI_EIOTLB_AM(am) (((u64)am) & 0x3f)
433#define QI_EIOTLB_PASID(pasid) (((u64)pasid) << 32)
434#define QI_EIOTLB_DID(did) (((u64)did) << 16)
435#define QI_EIOTLB_GRAN(gran) (((u64)gran) << 4)
436
437/* QI Dev-IOTLB inv granu */
438#define QI_DEV_IOTLB_GRAN_ALL 1
439#define QI_DEV_IOTLB_GRAN_PASID_SEL 0
440
441#define QI_DEV_EIOTLB_ADDR(a) ((u64)(a) & VTD_PAGE_MASK)
442#define QI_DEV_EIOTLB_SIZE (((u64)1) << 11)
443#define QI_DEV_EIOTLB_PASID(p) ((u64)((p) & 0xfffff) << 32)
444#define QI_DEV_EIOTLB_SID(sid) ((u64)((sid) & 0xffff) << 16)
445#define QI_DEV_EIOTLB_QDEP(qd) ((u64)((qd) & 0x1f) << 4)
446#define QI_DEV_EIOTLB_PFSID(pfsid) (((u64)(pfsid & 0xf) << 12) | \
447 ((u64)((pfsid >> 4) & 0xfff) << 52))
448#define QI_DEV_EIOTLB_MAX_INVS 32
449
450/* Page group response descriptor QW0 */
451#define QI_PGRP_PASID_P(p) (((u64)(p)) << 4)
452#define QI_PGRP_RESP_CODE(res) (((u64)(res)) << 12)
453#define QI_PGRP_DID(rid) (((u64)(rid)) << 16)
454#define QI_PGRP_PASID(pasid) (((u64)(pasid)) << 32)
455
456/* Page group response descriptor QW1 */
457#define QI_PGRP_IDX(idx) (((u64)(idx)) << 3)
458
459
460#define QI_RESP_SUCCESS 0x0
461#define QI_RESP_INVALID 0x1
462#define QI_RESP_FAILURE 0xf
463
464#define QI_GRAN_NONG_PASID 2
465#define QI_GRAN_PSI_PASID 3
466
467#define qi_shift(iommu) (DMAR_IQ_SHIFT + !!ecap_smts((iommu)->ecap))
468
469struct qi_desc {
470 u64 qw0;
471 u64 qw1;
472 u64 qw2;
473 u64 qw3;
474};
475
476struct q_inval {
477 raw_spinlock_t q_lock;
478 void *desc; /* invalidation queue */
479 int *desc_status; /* desc status */
480 int free_head; /* first free entry */
481 int free_tail; /* last free entry */
482 int free_cnt;
483};
484
485/* Page Request Queue depth */
486#define PRQ_ORDER 4
487#define PRQ_SIZE (SZ_4K << PRQ_ORDER)
488#define PRQ_RING_MASK (PRQ_SIZE - 0x20)
489#define PRQ_DEPTH (PRQ_SIZE >> 5)
490
491struct dmar_pci_notify_info;
492
493#ifdef CONFIG_IRQ_REMAP
494#define INTR_REMAP_TABLE_REG_SIZE 0xf
495#define INTR_REMAP_TABLE_REG_SIZE_MASK 0xf
496
497#define INTR_REMAP_TABLE_ENTRIES 65536
498
499struct irq_domain;
500
501struct ir_table {
502 struct irte *base;
503 unsigned long *bitmap;
504};
505
506void intel_irq_remap_add_device(struct dmar_pci_notify_info *info);
507#else
508static inline void
509intel_irq_remap_add_device(struct dmar_pci_notify_info *info) { }
510#endif
511
512struct iommu_flush {
513 void (*flush_context)(struct intel_iommu *iommu, u16 did, u16 sid,
514 u8 fm, u64 type);
515 void (*flush_iotlb)(struct intel_iommu *iommu, u16 did, u64 addr,
516 unsigned int size_order, u64 type);
517};
518
519enum {
520 SR_DMAR_FECTL_REG,
521 SR_DMAR_FEDATA_REG,
522 SR_DMAR_FEADDR_REG,
523 SR_DMAR_FEUADDR_REG,
524 MAX_SR_DMAR_REGS
525};
526
527#define VTD_FLAG_TRANS_PRE_ENABLED (1 << 0)
528#define VTD_FLAG_IRQ_REMAP_PRE_ENABLED (1 << 1)
529#define VTD_FLAG_SVM_CAPABLE (1 << 2)
530
531#define sm_supported(iommu) (intel_iommu_sm && ecap_smts((iommu)->ecap))
532#define pasid_supported(iommu) (sm_supported(iommu) && \
533 ecap_pasid((iommu)->ecap))
534#define ssads_supported(iommu) (sm_supported(iommu) && \
535 ecap_slads((iommu)->ecap) && \
536 ecap_smpwc(iommu->ecap))
537#define nested_supported(iommu) (sm_supported(iommu) && \
538 ecap_nest((iommu)->ecap))
539
540struct pasid_entry;
541struct pasid_state_entry;
542struct page_req_dsc;
543
544/*
545 * 0: Present
546 * 1-11: Reserved
547 * 12-63: Context Ptr (12 - (haw-1))
548 * 64-127: Reserved
549 */
550struct root_entry {
551 u64 lo;
552 u64 hi;
553};
554
555/*
556 * low 64 bits:
557 * 0: present
558 * 1: fault processing disable
559 * 2-3: translation type
560 * 12-63: address space root
561 * high 64 bits:
562 * 0-2: address width
563 * 3-6: aval
564 * 8-23: domain id
565 */
566struct context_entry {
567 u64 lo;
568 u64 hi;
569};
570
571struct iommu_domain_info {
572 struct intel_iommu *iommu;
573 unsigned int refcnt; /* Refcount of devices per iommu */
574 u16 did; /* Domain ids per IOMMU. Use u16 since
575 * domain ids are 16 bit wide according
576 * to VT-d spec, section 9.3 */
577};
578
579/*
580 * We start simply by using a fixed size for the batched descriptors. This
581 * size is currently sufficient for our needs. Future improvements could
582 * involve dynamically allocating the batch buffer based on actual demand,
583 * allowing us to adjust the batch size for optimal performance in different
584 * scenarios.
585 */
586#define QI_MAX_BATCHED_DESC_COUNT 16
587struct qi_batch {
588 struct qi_desc descs[QI_MAX_BATCHED_DESC_COUNT];
589 unsigned int index;
590};
591
592struct dmar_domain {
593 union {
594 struct iommu_domain domain;
595 struct pt_iommu iommu;
596 /* First stage page table */
597 struct pt_iommu_x86_64 fspt;
598 /* Second stage page table */
599 struct pt_iommu_vtdss sspt;
600 };
601
602 struct xarray iommu_array; /* Attached IOMMU array */
603
604 u8 force_snooping:1; /* Create PASID entry with snoop control */
605 u8 dirty_tracking:1; /* Dirty tracking is enabled */
606 u8 nested_parent:1; /* Has other domains nested on it */
607 u8 iotlb_sync_map:1; /* Need to flush IOTLB cache or write
608 * buffer when creating mappings.
609 */
610
611 spinlock_t lock; /* Protect device tracking lists */
612 struct list_head devices; /* all devices' list */
613 struct list_head dev_pasids; /* all attached pasids */
614
615 spinlock_t cache_lock; /* Protect the cache tag list */
616 struct list_head cache_tags; /* Cache tag list */
617 struct qi_batch *qi_batch; /* Batched QI descriptors */
618
619 union {
620 /* DMA remapping domain */
621 struct {
622 /* Protect the s1_domains list */
623 spinlock_t s1_lock;
624 /* Track s1_domains nested on this domain */
625 struct list_head s1_domains;
626 };
627
628 /* Nested user domain */
629 struct {
630 /* parent page table which the user domain is nested on */
631 struct dmar_domain *s2_domain;
632 /* page table attributes */
633 struct iommu_hwpt_vtd_s1 s1_cfg;
634 /* link to parent domain siblings */
635 struct list_head s2_link;
636 };
637
638 /* SVA domain */
639 struct {
640 struct mmu_notifier notifier;
641 };
642 };
643};
644PT_IOMMU_CHECK_DOMAIN(struct dmar_domain, iommu, domain);
645PT_IOMMU_CHECK_DOMAIN(struct dmar_domain, sspt.iommu, domain);
646PT_IOMMU_CHECK_DOMAIN(struct dmar_domain, fspt.iommu, domain);
647
648/*
649 * In theory, the VT-d 4.0 spec can support up to 2 ^ 16 counters.
650 * But in practice, there are only 14 counters for the existing
651 * platform. Setting the max number of counters to 64 should be good
652 * enough for a long time. Also, supporting more than 64 counters
653 * requires more extras, e.g., extra freeze and overflow registers,
654 * which is not necessary for now.
655 */
656#define IOMMU_PMU_IDX_MAX 64
657
658struct iommu_pmu {
659 struct intel_iommu *iommu;
660 u32 num_cntr; /* Number of counters */
661 u32 num_eg; /* Number of event group */
662 u32 cntr_width; /* Counter width */
663 u32 cntr_stride; /* Counter Stride */
664 u32 filter; /* Bitmask of filter support */
665 void __iomem *base; /* the PerfMon base address */
666 void __iomem *cfg_reg; /* counter configuration base address */
667 void __iomem *cntr_reg; /* counter 0 address*/
668 void __iomem *overflow; /* overflow status register */
669
670 u64 *evcap; /* Indicates all supported events */
671 u32 **cntr_evcap; /* Supported events of each counter. */
672
673 struct pmu pmu;
674 DECLARE_BITMAP(used_mask, IOMMU_PMU_IDX_MAX);
675 struct perf_event *event_list[IOMMU_PMU_IDX_MAX];
676 unsigned char irq_name[16];
677};
678
679#define IOMMU_IRQ_ID_OFFSET_PRQ (DMAR_UNITS_SUPPORTED)
680#define IOMMU_IRQ_ID_OFFSET_PERF (2 * DMAR_UNITS_SUPPORTED)
681
682struct intel_iommu {
683 void __iomem *reg; /* Pointer to hardware regs, virtual addr */
684 u64 reg_phys; /* physical address of hw register set */
685 u64 reg_size; /* size of hw register set */
686 u64 cap;
687 u64 ecap;
688 u64 vccap;
689 u64 ecmdcap[DMA_MAX_NUM_ECMDCAP];
690 u32 gcmd; /* Holds TE, EAFL. Don't need SRTP, SFL, WBF */
691 raw_spinlock_t register_lock; /* protect register handling */
692 int seq_id; /* sequence id of the iommu */
693 int agaw; /* agaw of this iommu */
694 int msagaw; /* max sagaw of this iommu */
695 unsigned int irq, pr_irq, perf_irq;
696 u16 segment; /* PCI segment# */
697 unsigned char name[16]; /* Device Name */
698
699#ifdef CONFIG_INTEL_IOMMU
700 /* mutex to protect domain_ida */
701 struct mutex did_lock;
702 struct ida domain_ida; /* domain id allocator */
703 unsigned long *copied_tables; /* bitmap of copied tables */
704 spinlock_t lock; /* protect context, domain ids */
705 struct root_entry *root_entry; /* virtual address */
706
707 struct iommu_flush flush;
708#endif
709 struct page_req_dsc *prq;
710 unsigned char prq_name[16]; /* Name for PRQ interrupt */
711 unsigned long prq_seq_number;
712 struct completion prq_complete;
713 struct iopf_queue *iopf_queue;
714 unsigned char iopfq_name[16];
715 /* Synchronization between fault report and iommu device release. */
716 struct mutex iopf_lock;
717 struct q_inval *qi; /* Queued invalidation info */
718 u32 iommu_state[MAX_SR_DMAR_REGS]; /* Store iommu states between suspend and resume.*/
719
720 /* rb tree for all probed devices */
721 struct rb_root device_rbtree;
722 /* protect the device_rbtree */
723 spinlock_t device_rbtree_lock;
724
725#ifdef CONFIG_IRQ_REMAP
726 struct ir_table *ir_table; /* Interrupt remapping info */
727 struct irq_domain *ir_domain;
728#endif
729 struct iommu_device iommu; /* IOMMU core code handle */
730 int node;
731 u32 flags; /* Software defined flags */
732
733 struct dmar_drhd_unit *drhd;
734 void *perf_statistic;
735
736 struct iommu_pmu *pmu;
737};
738
739/* PCI domain-device relationship */
740struct device_domain_info {
741 struct list_head link; /* link to domain siblings */
742 u32 segment; /* PCI segment number */
743 u8 bus; /* PCI bus number */
744 u8 devfn; /* PCI devfn number */
745 u16 pfsid; /* SRIOV physical function source ID */
746 u8 pasid_supported:3;
747 u8 pasid_enabled:1;
748 u8 pri_supported:1;
749 u8 pri_enabled:1;
750 u8 ats_supported:1;
751 u8 ats_enabled:1;
752 u8 dtlb_extra_inval:1; /* Quirk for devices need extra flush */
753 u8 domain_attached:1; /* Device has domain attached */
754 u8 ats_qdep;
755 unsigned int iopf_refcount;
756 struct device *dev; /* it's NULL for PCIe-to-PCI bridge */
757 struct intel_iommu *iommu; /* IOMMU used by this device */
758 struct dmar_domain *domain; /* pointer to domain */
759 struct pasid_table *pasid_table; /* pasid table */
760 /* device tracking node(lookup by PCI RID) */
761 struct rb_node node;
762#ifdef CONFIG_INTEL_IOMMU_DEBUGFS
763 struct dentry *debugfs_dentry; /* pointer to device directory dentry */
764#endif
765};
766
767struct dev_pasid_info {
768 struct list_head link_domain; /* link to domain siblings */
769 struct device *dev;
770 ioasid_t pasid;
771#ifdef CONFIG_INTEL_IOMMU_DEBUGFS
772 struct dentry *debugfs_dentry; /* pointer to pasid directory dentry */
773#endif
774};
775
776static inline void __iommu_flush_cache(
777 struct intel_iommu *iommu, void *addr, int size)
778{
779 if (!ecap_coherent(iommu->ecap))
780 clflush_cache_range(addr, size);
781}
782
783/* Convert generic struct iommu_domain to private struct dmar_domain */
784static inline struct dmar_domain *to_dmar_domain(struct iommu_domain *dom)
785{
786 return container_of(dom, struct dmar_domain, domain);
787}
788
789/*
790 * Domain ID 0 and 1 are reserved:
791 *
792 * If Caching mode is set, then invalid translations are tagged
793 * with domain-id 0, hence we need to pre-allocate it. We also
794 * use domain-id 0 as a marker for non-allocated domain-id, so
795 * make sure it is not used for a real domain.
796 *
797 * Vt-d spec rev3.0 (section 6.2.3.1) requires that each pasid
798 * entry for first-level or pass-through translation modes should
799 * be programmed with a domain id different from those used for
800 * second-level or nested translation. We reserve a domain id for
801 * this purpose. This domain id is also used for identity domain
802 * in legacy mode.
803 */
804#define FLPT_DEFAULT_DID 1
805#define IDA_START_DID 2
806
807/* Retrieve the domain ID which has allocated to the domain */
808static inline u16
809domain_id_iommu(struct dmar_domain *domain, struct intel_iommu *iommu)
810{
811 struct iommu_domain_info *info =
812 xa_load(&domain->iommu_array, iommu->seq_id);
813
814 return info->did;
815}
816
817static inline u16
818iommu_domain_did(struct iommu_domain *domain, struct intel_iommu *iommu)
819{
820 if (domain->type == IOMMU_DOMAIN_SVA ||
821 domain->type == IOMMU_DOMAIN_IDENTITY)
822 return FLPT_DEFAULT_DID;
823 return domain_id_iommu(to_dmar_domain(domain), iommu);
824}
825
826static inline bool dev_is_real_dma_subdevice(struct device *dev)
827{
828 return dev && dev_is_pci(dev) &&
829 pci_real_dma_dev(to_pci_dev(dev)) != to_pci_dev(dev);
830}
831
832/*
833 * 0: readable
834 * 1: writable
835 * 2-6: reserved
836 * 7: super page
837 * 8-10: available
838 * 11: snoop behavior
839 * 12-63: Host physical address
840 */
841struct dma_pte {
842 u64 val;
843};
844
845static inline u64 dma_pte_addr(struct dma_pte *pte)
846{
847#ifdef CONFIG_64BIT
848 return pte->val & VTD_PAGE_MASK;
849#else
850 /* Must have a full atomic 64-bit read */
851 return __cmpxchg64(&pte->val, 0ULL, 0ULL) & VTD_PAGE_MASK;
852#endif
853}
854
855static inline bool dma_pte_present(struct dma_pte *pte)
856{
857 return (pte->val & 3) != 0;
858}
859
860static inline bool dma_pte_superpage(struct dma_pte *pte)
861{
862 return (pte->val & DMA_PTE_LARGE_PAGE);
863}
864
865static inline bool context_present(struct context_entry *context)
866{
867 return (context->lo & 1);
868}
869
870#define LEVEL_STRIDE (9)
871#define LEVEL_MASK (((u64)1 << LEVEL_STRIDE) - 1)
872#define MAX_AGAW_WIDTH (64)
873#define MAX_AGAW_PFN_WIDTH (MAX_AGAW_WIDTH - VTD_PAGE_SHIFT)
874
875static inline int agaw_to_level(int agaw)
876{
877 return agaw + 2;
878}
879
880static inline int width_to_agaw(int width)
881{
882 return DIV_ROUND_UP(width - 30, LEVEL_STRIDE);
883}
884
885static inline unsigned int level_to_offset_bits(int level)
886{
887 return (level - 1) * LEVEL_STRIDE;
888}
889
890static inline int pfn_level_offset(u64 pfn, int level)
891{
892 return (pfn >> level_to_offset_bits(level)) & LEVEL_MASK;
893}
894
895
896static inline void context_set_present(struct context_entry *context)
897{
898 u64 val;
899
900 dma_wmb();
901 val = READ_ONCE(context->lo) | 1;
902 WRITE_ONCE(context->lo, val);
903}
904
905/*
906 * Clear the Present (P) bit (bit 0) of a context table entry. This initiates
907 * the transition of the entry's ownership from hardware to software. The
908 * caller is responsible for fulfilling the invalidation handshake recommended
909 * by the VT-d spec, Section 6.5.3.3 (Guidance to Software for Invalidations).
910 */
911static inline void context_clear_present(struct context_entry *context)
912{
913 u64 val;
914
915 val = READ_ONCE(context->lo) & GENMASK_ULL(63, 1);
916 WRITE_ONCE(context->lo, val);
917 dma_wmb();
918}
919
920static inline void context_set_fault_enable(struct context_entry *context)
921{
922 context->lo &= (((u64)-1) << 2) | 1;
923}
924
925static inline void context_set_translation_type(struct context_entry *context,
926 unsigned long value)
927{
928 context->lo &= (((u64)-1) << 4) | 3;
929 context->lo |= (value & 3) << 2;
930}
931
932static inline void context_set_address_root(struct context_entry *context,
933 unsigned long value)
934{
935 context->lo &= ~VTD_PAGE_MASK;
936 context->lo |= value & VTD_PAGE_MASK;
937}
938
939static inline void context_set_address_width(struct context_entry *context,
940 unsigned long value)
941{
942 context->hi |= value & 7;
943}
944
945static inline void context_set_domain_id(struct context_entry *context,
946 unsigned long value)
947{
948 context->hi |= (value & ((1 << 16) - 1)) << 8;
949}
950
951static inline void context_set_pasid(struct context_entry *context)
952{
953 context->lo |= CONTEXT_PASIDE;
954}
955
956static inline int context_domain_id(struct context_entry *c)
957{
958 return((c->hi >> 8) & 0xffff);
959}
960
961static inline void context_clear_entry(struct context_entry *context)
962{
963 context->lo = 0;
964 context->hi = 0;
965}
966
967#ifdef CONFIG_INTEL_IOMMU
968static inline bool context_copied(struct intel_iommu *iommu, u8 bus, u8 devfn)
969{
970 if (!iommu->copied_tables)
971 return false;
972
973 return test_bit(((long)bus << 8) | devfn, iommu->copied_tables);
974}
975
976static inline void
977set_context_copied(struct intel_iommu *iommu, u8 bus, u8 devfn)
978{
979 set_bit(((long)bus << 8) | devfn, iommu->copied_tables);
980}
981
982static inline void
983clear_context_copied(struct intel_iommu *iommu, u8 bus, u8 devfn)
984{
985 clear_bit(((long)bus << 8) | devfn, iommu->copied_tables);
986}
987#endif /* CONFIG_INTEL_IOMMU */
988
989/*
990 * Set the RID_PASID field of a scalable mode context entry. The
991 * IOMMU hardware will use the PASID value set in this field for
992 * DMA translations of DMA requests without PASID.
993 */
994static inline void
995context_set_sm_rid2pasid(struct context_entry *context, unsigned long pasid)
996{
997 context->hi |= pasid & ((1 << 20) - 1);
998}
999
1000/*
1001 * Set the DTE(Device-TLB Enable) field of a scalable mode context
1002 * entry.
1003 */
1004static inline void context_set_sm_dte(struct context_entry *context)
1005{
1006 context->lo |= BIT_ULL(2);
1007}
1008
1009/*
1010 * Set the PRE(Page Request Enable) field of a scalable mode context
1011 * entry.
1012 */
1013static inline void context_set_sm_pre(struct context_entry *context)
1014{
1015 context->lo |= BIT_ULL(4);
1016}
1017
1018/*
1019 * Clear the PRE(Page Request Enable) field of a scalable mode context
1020 * entry.
1021 */
1022static inline void context_clear_sm_pre(struct context_entry *context)
1023{
1024 context->lo &= ~BIT_ULL(4);
1025}
1026
1027/* Returns a number of VTD pages, but aligned to MM page size */
1028static inline unsigned long aligned_nrpages(unsigned long host_addr, size_t size)
1029{
1030 host_addr &= ~PAGE_MASK;
1031 return PAGE_ALIGN(host_addr + size) >> VTD_PAGE_SHIFT;
1032}
1033
1034/* Return a size from number of VTD pages. */
1035static inline unsigned long nrpages_to_size(unsigned long npages)
1036{
1037 return npages << VTD_PAGE_SHIFT;
1038}
1039
1040static inline void qi_desc_iotlb(struct intel_iommu *iommu, u16 did, u64 addr,
1041 unsigned int size_order, u64 type,
1042 struct qi_desc *desc)
1043{
1044 u8 dw = 0, dr = 0;
1045 int ih = addr & 1;
1046
1047 if (cap_write_drain(iommu->cap))
1048 dw = 1;
1049
1050 if (cap_read_drain(iommu->cap))
1051 dr = 1;
1052
1053 desc->qw0 = QI_IOTLB_DID(did) | QI_IOTLB_DR(dr) | QI_IOTLB_DW(dw)
1054 | QI_IOTLB_GRAN(type) | QI_IOTLB_TYPE;
1055 desc->qw1 = QI_IOTLB_ADDR(addr) | QI_IOTLB_IH(ih)
1056 | QI_IOTLB_AM(size_order);
1057 desc->qw2 = 0;
1058 desc->qw3 = 0;
1059}
1060
1061static inline void qi_desc_dev_iotlb(u16 sid, u16 pfsid, u16 qdep, u64 addr,
1062 unsigned int mask, struct qi_desc *desc)
1063{
1064 if (mask) {
1065 addr |= (1ULL << (VTD_PAGE_SHIFT + mask - 1)) - 1;
1066 desc->qw1 = QI_DEV_IOTLB_ADDR(addr) | QI_DEV_IOTLB_SIZE;
1067 } else {
1068 desc->qw1 = QI_DEV_IOTLB_ADDR(addr);
1069 }
1070
1071 if (qdep >= QI_DEV_IOTLB_MAX_INVS)
1072 qdep = 0;
1073
1074 desc->qw0 = QI_DEV_IOTLB_SID(sid) | QI_DEV_IOTLB_QDEP(qdep) |
1075 QI_DIOTLB_TYPE | QI_DEV_IOTLB_PFSID(pfsid);
1076 desc->qw2 = 0;
1077 desc->qw3 = 0;
1078}
1079
1080/* PASID-selective IOTLB invalidation */
1081static inline void qi_desc_piotlb_all(u16 did, u32 pasid, struct qi_desc *desc)
1082{
1083 desc->qw0 = QI_EIOTLB_PASID(pasid) | QI_EIOTLB_DID(did) |
1084 QI_EIOTLB_GRAN(QI_GRAN_NONG_PASID) | QI_EIOTLB_TYPE;
1085 desc->qw1 = 0;
1086}
1087
1088/* Page-selective-within-PASID IOTLB invalidation */
1089static inline void qi_desc_piotlb(u16 did, u32 pasid, u64 addr,
1090 unsigned int size_order, bool ih,
1091 struct qi_desc *desc)
1092{
1093 /*
1094 * calculate_psi_aligned_address() must be used for addr and size_order
1095 */
1096 desc->qw0 = QI_EIOTLB_PASID(pasid) | QI_EIOTLB_DID(did) |
1097 QI_EIOTLB_GRAN(QI_GRAN_PSI_PASID) | QI_EIOTLB_TYPE;
1098 desc->qw1 = QI_EIOTLB_ADDR(addr) | QI_EIOTLB_IH(ih) |
1099 QI_EIOTLB_AM(size_order);
1100}
1101
1102static inline void qi_desc_dev_iotlb_pasid(u16 sid, u16 pfsid, u32 pasid,
1103 u16 qdep, u64 addr,
1104 unsigned int size_order,
1105 struct qi_desc *desc)
1106{
1107 unsigned long mask = 1UL << (VTD_PAGE_SHIFT + size_order - 1);
1108
1109 desc->qw0 = QI_DEV_EIOTLB_PASID(pasid) | QI_DEV_EIOTLB_SID(sid) |
1110 QI_DEV_EIOTLB_QDEP(qdep) | QI_DEIOTLB_TYPE |
1111 QI_DEV_IOTLB_PFSID(pfsid);
1112
1113 /*
1114 * If S bit is 0, we only flush a single page. If S bit is set,
1115 * The least significant zero bit indicates the invalidation address
1116 * range. VT-d spec 6.5.2.6.
1117 * e.g. address bit 12[0] indicates 8KB, 13[0] indicates 16KB.
1118 * size order = 0 is PAGE_SIZE 4KB
1119 * Max Invs Pending (MIP) is set to 0 for now until we have DIT in
1120 * ECAP.
1121 */
1122 if (!IS_ALIGNED(addr, VTD_PAGE_SIZE << size_order))
1123 pr_warn_ratelimited("Invalidate non-aligned address %llx, order %d\n",
1124 addr, size_order);
1125
1126 /* Take page address */
1127 desc->qw1 = QI_DEV_EIOTLB_ADDR(addr);
1128
1129 if (size_order) {
1130 /*
1131 * Existing 0s in address below size_order may be the least
1132 * significant bit, we must set them to 1s to avoid having
1133 * smaller size than desired.
1134 */
1135 desc->qw1 |= GENMASK_ULL(size_order + VTD_PAGE_SHIFT - 1,
1136 VTD_PAGE_SHIFT);
1137 /* Clear size_order bit to indicate size */
1138 desc->qw1 &= ~mask;
1139 /* Set the S bit to indicate flushing more than 1 page */
1140 desc->qw1 |= QI_DEV_EIOTLB_SIZE;
1141 }
1142}
1143
1144/* Convert value to context PASID directory size field coding. */
1145#define context_pdts(pds) (((pds) & 0x7) << 9)
1146
1147struct dmar_drhd_unit *dmar_find_matched_drhd_unit(struct pci_dev *dev);
1148
1149int dmar_enable_qi(struct intel_iommu *iommu);
1150void dmar_disable_qi(struct intel_iommu *iommu);
1151int dmar_reenable_qi(struct intel_iommu *iommu);
1152void qi_global_iec(struct intel_iommu *iommu);
1153
1154void qi_flush_context(struct intel_iommu *iommu, u16 did,
1155 u16 sid, u8 fm, u64 type);
1156void qi_flush_iotlb(struct intel_iommu *iommu, u16 did, u64 addr,
1157 unsigned int size_order, u64 type);
1158void qi_flush_dev_iotlb(struct intel_iommu *iommu, u16 sid, u16 pfsid,
1159 u16 qdep, u64 addr, unsigned mask);
1160
1161void qi_flush_piotlb_all(struct intel_iommu *iommu, u16 did, u32 pasid);
1162
1163void qi_flush_dev_iotlb_pasid(struct intel_iommu *iommu, u16 sid, u16 pfsid,
1164 u32 pasid, u16 qdep, u64 addr,
1165 unsigned int size_order);
1166void quirk_extra_dev_tlb_flush(struct device_domain_info *info,
1167 unsigned long address, unsigned long pages,
1168 u32 pasid, u16 qdep);
1169void qi_flush_pasid_cache(struct intel_iommu *iommu, u16 did, u64 granu,
1170 u32 pasid);
1171
1172int qi_submit_sync(struct intel_iommu *iommu, struct qi_desc *desc,
1173 unsigned int count, unsigned long options);
1174
1175void __iommu_flush_iotlb(struct intel_iommu *iommu, u16 did, u64 addr,
1176 unsigned int size_order, u64 type);
1177/*
1178 * Options used in qi_submit_sync:
1179 * QI_OPT_WAIT_DRAIN - Wait for PRQ drain completion, spec 6.5.2.8.
1180 */
1181#define QI_OPT_WAIT_DRAIN BIT(0)
1182
1183int domain_attach_iommu(struct dmar_domain *domain, struct intel_iommu *iommu);
1184void domain_detach_iommu(struct dmar_domain *domain, struct intel_iommu *iommu);
1185void device_block_translation(struct device *dev);
1186int paging_domain_compatible(struct iommu_domain *domain, struct device *dev);
1187
1188struct dev_pasid_info *
1189domain_add_dev_pasid(struct iommu_domain *domain,
1190 struct device *dev, ioasid_t pasid);
1191void domain_remove_dev_pasid(struct iommu_domain *domain,
1192 struct device *dev, ioasid_t pasid);
1193
1194int __domain_setup_first_level(struct intel_iommu *iommu, struct device *dev,
1195 ioasid_t pasid, u16 did, phys_addr_t fsptptr,
1196 int flags, struct iommu_domain *old);
1197
1198int dmar_ir_support(void);
1199
1200void iommu_flush_write_buffer(struct intel_iommu *iommu);
1201struct iommu_domain *
1202intel_iommu_domain_alloc_nested(struct device *dev, struct iommu_domain *parent,
1203 u32 flags,
1204 const struct iommu_user_data *user_data);
1205struct device *device_rbtree_find(struct intel_iommu *iommu, u16 rid);
1206
1207enum cache_tag_type {
1208 CACHE_TAG_IOTLB,
1209 CACHE_TAG_DEVTLB,
1210 CACHE_TAG_NESTING_IOTLB,
1211 CACHE_TAG_NESTING_DEVTLB,
1212};
1213
1214struct cache_tag {
1215 struct list_head node;
1216 enum cache_tag_type type;
1217 struct intel_iommu *iommu;
1218 /*
1219 * The @dev field represents the location of the cache. For IOTLB, it
1220 * resides on the IOMMU hardware. @dev stores the device pointer to
1221 * the IOMMU hardware. For DevTLB, it locates in the PCIe endpoint.
1222 * @dev stores the device pointer to that endpoint.
1223 */
1224 struct device *dev;
1225 u16 domain_id;
1226 ioasid_t pasid;
1227 unsigned int users;
1228};
1229
1230int cache_tag_assign(struct dmar_domain *domain, u16 did, struct device *dev,
1231 ioasid_t pasid, enum cache_tag_type type);
1232int cache_tag_assign_domain(struct dmar_domain *domain,
1233 struct device *dev, ioasid_t pasid);
1234void cache_tag_unassign_domain(struct dmar_domain *domain,
1235 struct device *dev, ioasid_t pasid);
1236void cache_tag_flush_range(struct dmar_domain *domain, unsigned long start,
1237 unsigned long end, int ih);
1238void cache_tag_flush_all(struct dmar_domain *domain);
1239void cache_tag_flush_range_np(struct dmar_domain *domain, unsigned long start,
1240 unsigned long end);
1241
1242void intel_context_flush_no_pasid(struct device_domain_info *info,
1243 struct context_entry *context, u16 did);
1244
1245int intel_iommu_enable_prq(struct intel_iommu *iommu);
1246int intel_iommu_finish_prq(struct intel_iommu *iommu);
1247void intel_iommu_page_response(struct device *dev, struct iopf_fault *evt,
1248 struct iommu_page_response *msg);
1249void intel_iommu_drain_pasid_prq(struct device *dev, u32 pasid);
1250
1251int intel_iommu_enable_iopf(struct device *dev);
1252void intel_iommu_disable_iopf(struct device *dev);
1253
1254static inline int iopf_for_domain_set(struct iommu_domain *domain,
1255 struct device *dev)
1256{
1257 if (!domain || !domain->iopf_handler)
1258 return 0;
1259
1260 return intel_iommu_enable_iopf(dev);
1261}
1262
1263static inline void iopf_for_domain_remove(struct iommu_domain *domain,
1264 struct device *dev)
1265{
1266 if (!domain || !domain->iopf_handler)
1267 return;
1268
1269 intel_iommu_disable_iopf(dev);
1270}
1271
1272static inline int iopf_for_domain_replace(struct iommu_domain *new,
1273 struct iommu_domain *old,
1274 struct device *dev)
1275{
1276 int ret;
1277
1278 ret = iopf_for_domain_set(new, dev);
1279 if (ret)
1280 return ret;
1281
1282 iopf_for_domain_remove(old, dev);
1283
1284 return 0;
1285}
1286
1287#ifdef CONFIG_INTEL_IOMMU_SVM
1288void intel_svm_check(struct intel_iommu *iommu);
1289struct iommu_domain *intel_svm_domain_alloc(struct device *dev,
1290 struct mm_struct *mm);
1291#else
1292static inline void intel_svm_check(struct intel_iommu *iommu) {}
1293static inline struct iommu_domain *intel_svm_domain_alloc(struct device *dev,
1294 struct mm_struct *mm)
1295{
1296 return ERR_PTR(-ENODEV);
1297}
1298#endif
1299
1300#ifdef CONFIG_INTEL_IOMMU_DEBUGFS
1301void intel_iommu_debugfs_init(void);
1302void intel_iommu_debugfs_create_dev(struct device_domain_info *info);
1303void intel_iommu_debugfs_remove_dev(struct device_domain_info *info);
1304void intel_iommu_debugfs_create_dev_pasid(struct dev_pasid_info *dev_pasid);
1305void intel_iommu_debugfs_remove_dev_pasid(struct dev_pasid_info *dev_pasid);
1306#else
1307static inline void intel_iommu_debugfs_init(void) {}
1308static inline void intel_iommu_debugfs_create_dev(struct device_domain_info *info) {}
1309static inline void intel_iommu_debugfs_remove_dev(struct device_domain_info *info) {}
1310static inline void intel_iommu_debugfs_create_dev_pasid(struct dev_pasid_info *dev_pasid) {}
1311static inline void intel_iommu_debugfs_remove_dev_pasid(struct dev_pasid_info *dev_pasid) {}
1312#endif /* CONFIG_INTEL_IOMMU_DEBUGFS */
1313
1314extern const struct attribute_group *intel_iommu_groups[];
1315struct context_entry *iommu_context_addr(struct intel_iommu *iommu, u8 bus,
1316 u8 devfn, int alloc);
1317
1318extern const struct iommu_ops intel_iommu_ops;
1319extern const struct iommu_domain_ops intel_fs_paging_domain_ops;
1320extern const struct iommu_domain_ops intel_ss_paging_domain_ops;
1321
1322static inline bool intel_domain_is_fs_paging(struct dmar_domain *domain)
1323{
1324 return domain->domain.ops == &intel_fs_paging_domain_ops;
1325}
1326
1327static inline bool intel_domain_is_ss_paging(struct dmar_domain *domain)
1328{
1329 return domain->domain.ops == &intel_ss_paging_domain_ops;
1330}
1331
1332#ifdef CONFIG_INTEL_IOMMU
1333extern int intel_iommu_sm;
1334int iommu_calculate_agaw(struct intel_iommu *iommu);
1335int iommu_calculate_max_sagaw(struct intel_iommu *iommu);
1336int ecmd_submit_sync(struct intel_iommu *iommu, u8 ecmd, u64 oa, u64 ob);
1337
1338static inline bool ecmd_has_pmu_essential(struct intel_iommu *iommu)
1339{
1340 return (iommu->ecmdcap[DMA_ECMD_ECCAP3] & DMA_ECMD_ECCAP3_ESSENTIAL) ==
1341 DMA_ECMD_ECCAP3_ESSENTIAL;
1342}
1343
1344extern int dmar_disabled;
1345extern int intel_iommu_enabled;
1346#else
1347static inline int iommu_calculate_agaw(struct intel_iommu *iommu)
1348{
1349 return 0;
1350}
1351static inline int iommu_calculate_max_sagaw(struct intel_iommu *iommu)
1352{
1353 return 0;
1354}
1355#define dmar_disabled (1)
1356#define intel_iommu_enabled (0)
1357#define intel_iommu_sm (0)
1358#endif
1359
1360static inline const char *decode_prq_descriptor(char *str, size_t size,
1361 u64 dw0, u64 dw1, u64 dw2, u64 dw3)
1362{
1363 char *buf = str;
1364 int bytes;
1365
1366 bytes = snprintf(buf, size,
1367 "rid=0x%llx addr=0x%llx %c%c%c%c%c pasid=0x%llx index=0x%llx",
1368 FIELD_GET(GENMASK_ULL(31, 16), dw0),
1369 FIELD_GET(GENMASK_ULL(63, 12), dw1),
1370 dw1 & BIT_ULL(0) ? 'r' : '-',
1371 dw1 & BIT_ULL(1) ? 'w' : '-',
1372 dw0 & BIT_ULL(52) ? 'x' : '-',
1373 dw0 & BIT_ULL(53) ? 'p' : '-',
1374 dw1 & BIT_ULL(2) ? 'l' : '-',
1375 FIELD_GET(GENMASK_ULL(51, 32), dw0),
1376 FIELD_GET(GENMASK_ULL(11, 3), dw1));
1377
1378 /* Private Data */
1379 if (dw0 & BIT_ULL(9)) {
1380 size -= bytes;
1381 buf += bytes;
1382 snprintf(buf, size, " private=0x%llx/0x%llx\n", dw2, dw3);
1383 }
1384
1385 return str;
1386}
1387
1388#endif